ADA4099-2HRZ

Data Sheet ADA4099-1/ADA4099-2 50 V, 8 MHz, 1.5 mA per Channel, Robust, Over-The-Top, Precision Op Amps FEATURES ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► GENERAL DESCRIPTION Ultrawide common-mode range: −VS − 0.1 V to −VS + 70 V Wide power supply voltage range: (VSY): +3.15 V to +50 V (±25 V for PSRR) Low supply current: 1.5 mA per channel (typical) Low input offset voltage: ±40 µV maximum Low input offset voltage drift: ±0.4 μV/°C maximum Low voltage noise: ► 1/f noise corner: 6 Hz typical ► 150 nV p-p typical at 0.1 Hz to 10 Hz ► 7 nV/√Hz typical at 100 Hz (en) High speed ► GBP: 8 MHz typical ► Slew rate: 5.5 V/µs typical at ΔVOUT = 25 V Low power shutdown: 20 µA maximum Low input bias current: ±10 nA maximum Large signal voltage gain: 120 dB minimum CMRR: 118 dB, minimum PSRR: 123 dB, minimum Input overdrive tolerant with no phase reversal ±2 kV HBM and ±1.25 kV FICDM Wide temperature range: −55°C to +150°C (H grade) The ADA4099-1 and ADA4099-2 are single/dual robust, precision, rail-to-rail input/output operational amplifiers (op amps) with inputs that operate from −VS to +VS and beyond, which is referred to in this data sheet as Over-The-Top™. The devices feature offset voltages of 5 V f = 100 Hz f = 100 Hz, VCM > 5 V ΔVOUT = 2 V TMIN < TA < TMAX Test frequency (fTEST) = 25 kHz TMIN < TA < TMAX ΔVOUT = ±2 V H Grade Typ Max ±40 ±90 ±10 ±40 ±90 µV µV ±65 ±125 ±70 ±125 ±0.4 ±10 ±15 98 125 10 25 ±4 ±10 ±2 ±5 ±25 ±65 ±140 ±70 ±200 ±0.8 ±10 ±30 98 125 10 25 ±4 ±20 ±2 ±5 µV µV µV µV µV/°C nA nA µA µA µA µA nA nA µA µA dB 136 −VS + 70 130 ±25 ±0.1 ±4 70 40 ±2 ±0.5 108 114 108 −VS − 0.1 126 110 120 102 150 6 7 8 0.5 5 2.7 1.75 7.5 6.75 4 8 47 1.15 82.5 0.001 118 132 140 Min Unit 2.7 1.75 7.5 6.5 136 132 −VS + 70 140 130 dB dB dB V dB dB dB dB 150 6 7 8 0.5 5 nV p-p Hz nV/√Hz nV/√Hz pA/√Hz pA/√Hz 4 V/μs V/μs MHz MHz Degrees μs 8 47 1.15 Rev. A | 3 of 34 Data Sheet ADA4099-1/ADA4099-2 SPECIFICATIONS Table 1. Parameter Test Conditions/Comments B Grade Min 0.1% Settling Time Total Harmonic Distortion Plus Noise (THD + N) Channel Separation INPUT CHARACTERISTICS Input Resistance Over-The-Top Input Capacitance SHDN AND SHDNx PINS Input Logic Low Input Logic High Response Time Pull-Down Current H Grade Max Min Typ Unit Max ΔVOUT = ±2 V f = 10 kHz, VOUT = 2 V p-p, RL = 10 kΩ, bandwidth = 80 kHz f = 1 kHz, RL = 2 kΩ 1.5 0.001 1.5 0.001 μs % 115 115 dB Differential mode Common mode Differential mode, VCM > 5 V Common mode, VCM > 5 V Differential mode Common mode 100 >1 600 >100 9 3 100 >1 600 >100 9 3 kΩ GΩ Ω MΩ pF pF Amplifier active, SHDN and SHDNx voltage (VSHDN) < −VS + 0.5 V, TMIN < TA < TMAX Amplifier shutdown, VSHDN > −VS + 1.5 −VS + 1.5 V, TMIN < TA < TMAX Amplifier active to shutdown Amplifier shutdown to active VSHDN = −VS + 0.5 V, TMIN < TA < TMAX VSHDN = −VS + 1.5 V, TMIN < TA < TMAX OUTPUT CHARACTERISTICS Output Voltage Swing Low Overdrive voltage (VOD4) = 30 mV, no load TMIN < TA < TMAX VOD = 30 mV, sink current, (ISINK) = 10 mA TMIN < TA < TMAX Output Voltage Swing High VOD = 30 mV, no load TMIN < TA < TMAX VOD = 30 mV, source current, (ISOURCE) = 10 mA TMIN < TA < TMAX Short-Circuit Current ISOURCE TMIN< TA < TMAX ISINK TMIN < TA < TMAX Output Pin Leakage During Shutdown VSHDN = −VS + 1.5 V TMIN < TA < TMAX POWER SUPPLY Maximum Operating Voltage5 Voltage Range Guaranteed by power supply rejection ratio (PSRR) Supply Current/Channel Amplifier active TMIN < TA < TMAX Amplifier shutdown VSHDN = −VS + 1.5 V TMIN < TA < TMAX analog.com Typ −VS + 0.5 −VS + 0.5 −VS + 1.5 2.5 10 0.6 0.3 V 3 2.5 2.5 10 0.6 0.3 3 2.5 μs μs µA µA 45 60 45 60 mV 260 105 325 260 120 325 mV mV 450 55 140 1100 mV mV mV mV 1650 ±100 ±10 mV mA mA mA mA nA µA 50 50 V V 1.6 2.35 20 mA mA µA 22.5 µA 45 900 435 55 110 1100 45 900 1500 20 15 40 20 V 30 20 15 40 20 50 ±0.01 ±100 ±10 50 50 3.15 1.5 12 1.6 2.2 20 22.5 30 50 ±0.01 3.15 1.5 12 Rev. A | 4 of 34 Data Sheet ADA4099-1/ADA4099-2 SPECIFICATIONS Table 1. Parameter PSRR THERMAL SHUTDOWN6 Temperature Hysteresis Operating Temperature Test Conditions/Comments VSY = 3.15 V to ±25 V TMIN < TA < TMAX B Grade Min Typ 123 119 136 Junction temperature (TJ) Ambient temperature (TA) H Grade Max Typ 123 120 136 dB dB 175 20 °C °C °C 175 20 −40 +125 Unit Min −55 Max +150 1 Thermoelectric voltages present in the high speed production test limit the measurement accuracy of this parameter. The limits shown in Table 1 are determined by test capability and are not necessarily indicative of actual device performance. 2 Offset voltage drift is guaranteed through lab characterization and is not production tested. 3 Test accuracy is limited by high speed production test equipment repeatability. Bench measurements indicate that the input offset current in Over-The-Top configuration is typically controlled to under 250 nA at +25°C and 1000 nA over the −55°C < TA < +150°C temperature range. 4 VOD is +30 mV for VOUT high and −30 mV for VOUT low. 5 Maximum operating voltage is limited by the time-dependent dielectric breakdown (TDDB) of on-chip capacitor oxides. The amplifier tolerates temporary transient overshoot up to the specified absolute maximum rating, but the dc supply voltage must be limited to the maximum operating voltage. 6 Thermal shutdown is lab characterized only and is not tested in production. ±15 V SUPPLY VCM = 0 V, SHDN pin (ADA4099-1) and SHDNx pins (ADA4099-2 10-lead LFCSP) are open, RL = 499 kΩ to ground, and TA = 25°C, unless otherwise noted. Table 2. B Grade Parameter Test Conditions/Comments Min DC PERFORMANCE Input Offset Voltage (VOS)1 TMIN < TA < TMAX VSY = ±25 V TMIN < TA < TMAX Input Offset Voltage Drift2 Input Bias Current analog.com ±12 ±4 Input Offset Current Common-Mode Input Range Max ±0.1 ±4 TMIN < TA < TMAX VSY = ±25 V TMIN < TA < TMAX CMRR Typ ±15 TMIN < TA < TMAX ±2 TMIN < TA < TMAX VSY = ±25 V TMIN < TA < TMAX VCM = −14.75 V to +13.25 V TMIN < TA < TMAX VCM = −15.1 V to +13.25 V TMIN < TA < TMAX VCM = −15.1 V to +55 V TMIN < TA < TMAX Guaranteed by CMRR tests ±4 118 112 115 105 117 110 −15.1 H Grade Typ Max Unit ±40 ±95 ±40 ±105 ±12 ±40 ±90 ±40 ±90 µV µV µV µV ±0.4 ±10 ±25 ±10 ±35 ±5 ±15 ±5 ±20 ±0.1 ±4 ±0.9 ±10 ±60 ±10 ±100 ±5 ±30 ±5 ±35 µV/°C nA nA nA nA nA nA nA nA dB dB dB dB dB dB V 130 126 126 +55 Min ±15 ±4 ±2 ±4 118 114 115 101 117 107 −15.1 130 126 126 +55 Rev. A | 5 of 34 Data Sheet ADA4099-1/ADA4099-2 SPECIFICATIONS Table 2. B Grade Parameter AOL NOISE PERFORMANCE Input Voltage Noise Over-The-Top Input Current Noise Over-The-Top DYNAMIC PERFORMANCE Slew Rate GBP Phase Margin 1% Settling Time 0.1% Settling Time THD + N Channel Separation INPUT CHARACTERISTICS Input Resistance Input Capacitance SHDN AND SHDNx PINS Input Logic Low Input Logic High Response Time Pull-Down Current OUTPUT CHARACTERISTICS Output Voltage Swing Low Output Voltage Swing High analog.com Test Conditions/Comments Min Typ ΔVOUT = 25 V TMIN < TA < TMAX ΔVOUT = 25 V, RL =10 kΩ TMIN < TA < TMAX 134 120 120 114 154 f = 0.1 Hz to 10 Hz 1/f noise corner f = 100 Hz f = 100 Hz, VCM > +VS f = 100 Hz f = 100 Hz, VCM > +VS ΔVOUT = 25 V TMIN < TA < TMAX fTEST = 25 kHz TMIN < TA < TMAX 134 Min Typ 134 116 120 110 154 150 6 7 8 0.5 5 3.5 2.0 7.5 6.75 ΔVOUT = ±2 V ΔVOUT = ±2 V f = 10 kHz, VOUT = 5.6 V p-p, RL = 10 kΩ, bandwidth = 80 kHz f = 1 kHz, RL = 2 kΩ Differential mode Common mode Differential mode Common mode Amplifier active, VSHDN < −VS + 0.5 V Amplifier shutdown, VSHDN > −VS + 1.5 V −VS + 1.5 Amplifier active to shutdown Amplifier shutdown to active VSHDN = −VS + 0.5 V, TMIN < TA < TMAX VSHDN = −VS + 1.5 V, TMIN < TA < TMAX VOD3 = 30 mV, no load TMIN < TA < TMAX VOD = 30 mV, ISINK = 10 mA TMIN < TA < TMAX VOD = 30 mV, no load TMIN < TA < TMAX VOD = 30 mV, ISOURCE = 10 mA TMIN < TA < TMAX H Grade Max 5.5 3.5 2.0 7.5 6.5 Max Unit dB dB dB dB 134 150 6 7 8 0.5 5 nV p-p Hz nV/√Hz nV/√Hz pA/√Hz pA/√Hz 5.5 57 1.15 1.5 0.001 57 1.15 1.5 0.001 V/μs V/μs MHz MHz Degrees μs μs % 115 115 dB 100 >1 9 3 100 >1 9 3 kΩ GΩ pF pF 8 8 −VS + 0.5 −VS + 0.5 3 2.5 V V μs μs µA µA 60 125 325 450 55 165 1100 1650 mV mV mV mV mV mV mV mV −VS + 1.5 2.5 10 0.6 0.3 45 260 45 900 3 2.5 60 115 325 435 55 140 1100 1500 2.5 10 0.6 0.3 45 260 45 900 Rev. A | 6 of 34 Data Sheet ADA4099-1/ADA4099-2 SPECIFICATIONS Table 2. B Grade Parameter Short-Circuit Current POWER SUPPLY Maximum Operating Voltage4 Voltage Range Supply Current/Channel PSRR THERMAL SHUTDOWN5 Temperature Hysteresis Operating Temperature Test Conditions/Comments Min Typ ISOURCE TMIN < TA < TMAX ISINK TMIN < TA < TMAX 25 20 40 20 34 Guaranteed by PSRR 3.15 Amplifier active TMIN < TA < TMAX VSY = ±25 V TMIN < TA < TMAX Amplifier shutdown, VSHDN = −VS + 1.5 V TMIN < TA < TMAX VSY = 3.15 V to 50 V 123 TMIN < TA < TMAX 119 TJ TA H Grade Max 50 1.65 1.75 17 50 50 1.8 2.45 2 2.7 24 27 136 Min Typ 25 20 40 20 34 1.65 1.75 17 175 20 −40 50 50 1.8 2.6 2 2.85 24 27 136 175 20 +125 −55 Unit mA mA mA mA 50 3.15 123 120 Max +150 V V mA mA mA mA µA µA dB dB °C °C °C 1 Thermoelectric voltages present in the high speed production test limit the measurement accuracy of this parameter. The limits shown in Table 2 are determined by test capability and are not necessarily indicative of actual device performance. 2 Offset voltage drift is guaranteed through lab characterization and is not production tested. 3 VOD is +30 mV for VOUT high and −30 mV for VOUT low. 4 Maximum operating voltage is limited by the TDDB of on-chip capacitor oxides. The amplifier tolerates temporary transient overshoot up to the specified absolute maximum rating and the dc supply voltage must be limited to the maximum operating voltage. 5 Thermal shutdown is lab characterized only and is not tested in production. analog.com Rev. A | 7 of 34 Data Sheet ADA4099-1/ADA4099-2 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage1 Transient Continuous Power Dissipation (PD) Differential Input Voltage ±IN Pin Voltage Continuous Survival ±IN Pin Current SHDN and SHDNx Voltage2 Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature (TJ) Rating 60 V 50 V See Figure 3 ±80 V −5 V to +80 V −10 V to +80 V 20 mA −0.3 V to +60 V −65°C to +150°C −55°C to +150°C 300°C 175°C 1 Maximum supply voltage is limited by the TDDB of on-chip capacitor oxides. The amplifiers tolerate temporary transient overshoot up to the specified transient maximum rating. The continuous operating supply voltage must be limited to no more than 50 V. 2 SHDN is Pin 5 on the ADA4099-1. SHDNx refers to SHDN1 and SHDN2 (Pin 5 and Pin 6, respectively) on the ADA4099-2 10-lead LFCSP). Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Junction temperatures (TJ) exceeding 125°C promote accelerated aging. The ADA4099-1 and ADA4099-2 demonstrates ±25 V supply operation beyond 1400 hours at TA = 140°C. The PD due to the load drive depends on the application. The PD due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing θJA. Additional metal that is directly in contact with the package leads from metal traces through vias, ground, and power planes reduces θJA. Figure 3 shows the maximum PD vs. TA for the single and dual 6-lead TSOT packages on a JEDEC standard, 4‑layer board, with −VS connected to a pad that is thermally connected to a printed circuit board (PCB) plane. θJA values are approximations. Figure 3. Maximum Power Dissipation vs. Ambient Temperature THERMAL RESISTANCE Thermal performance is directly linked to PCB design and operating environment. Careful attention to PCB thermal design is required. MAXIMUM POWER DISSIPATION θJA is the junction to ambient thermal resistance. The maximum safe power dissipation (PD) on the device is limited by the associated rise in either case temperature (TC) or TJ on the die. At approximately TC = 150°C, which is the glass transition temperature, the properties of the plastic changes. Exceeding this temperature limit, even temporarily, may change the stresses that the package exerts on the die, which permanently shifts the parametric performance of the ADA4099-1 and ADA4099-2. Exceeding TJ = 175°C for an extended period may result in changes in the silicon devices and may cause failure of the device. Table 4. Thermal Resistance The PD on the package is the sum of the quiescent power dissipation and the power dissipated in the package due to the output load drive. The quiescent power is expressed in the following equation: VSY × ISY Package Type θJA Unit UJ-6 R-8 RM-8 05-08-1699 192 120 163 43 °C/W °C/W °C/W °C/W ELECTROSTATIC DISCHARGE (ESD) RATINGS The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Field induced charged device model (FICDM) per ANSI/ESDA/JEDEC JS-002. where ISY is the quiescent current. analog.com Rev. A | 8 of 34 Data Sheet ADA4099-1/ADA4099-2 ABSOLUTE MAXIMUM RATINGS ESD Ratings for ADA4099-1 and ADA4099-2 Table 5. ADA4099-1 6-Lead TSOT, ADA4099-2 8-Lead SOIC_N, ADA4099-2 8-Lead MSOP, ADA4099-2 10-Lead LFCSP ESD Model Withstand Threshold (kV) Class HBM FICDM ±2 ±1.25 2 3 analog.com ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Rev. A | 9 of 34 Data Sheet ADA4099-1/ADA4099-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration for ADA4099-1 6-Lead TSOT Table 6. Pin Function Descriptions for ADA4099-1 6-Lead TSOT Pin No. Mnemonic Description 1 2 VOUT −VS 3 4 5 +IN −IN SHDN 6 +VS Amplifier Output. Negative Power Supply. In single-supply applications, this pin is normally soldered to a low impedance ground plane. In split supply applications, bypass this pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the pin as possible. Noninverting Input of the Amplifier. Inverting Input of the Amplifier. Op Amp Shutdown. The threshold for shutdown is approximately 1 V above the negative supply. If this pin is not connected or hard tied to −VS, the amplifier is active. If asserted high (VSHDN > −VS + 1.5 V), the amplifier is placed in a shutdown state, and the output of the amplifier goes to a high impedance state. If this pin is left unconnected, it is recommended to connect a small capacitor of 1 nF between SHDN and −VS to prevent signals from −IN from capacitively coupling to the SHDN pin. Positive Power Supply. Bypass this pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the pin as possible. Figure 5. Pin Configuration for ADA4099-2 8-Lead SOIC_N and 8-Lead MSOP Table 7. Pin Function Descriptions for ADA4099-2 8-Lead SOIC_N and 8-Lead MSOP Pin No. Mnemonic Description 1 2 3 4 VOUT1 −IN1 +IN1 −VS 5 6 7 8 +IN2 −IN2 VOUT2 +VS analog.com Amplifier Output, Channel 1. Inverting Input of the Amplifier, Channel 1. Noninverting Input of the Amplifier, Channel 1. Negative Power Supply. In single-supply applications, this pin is normally soldered to a low impedance ground plane. In split supply applications, bypass this pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the pin as possible. Inverting Input of the Amplifier, Channel 2. Noninverting Input of the Amplifier, Channel 2. Amplifier Output, Channel 2. Positive Power Supply. Bypass this pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the pin as possible. Rev. A | 10 of 34 Data Sheet ADA4099-1/ADA4099-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. Pin Configuration for ADA4099-2 10-Lead LFCSP Table 8. Pin Function Descriptions for ADA4099-2 10-Lead LFCSP Pin No. Mnemonic Description 1 2 3 4 VOUT1 −IN1 +IN1 −VS 5 SHDN1 6 SHDN2 7 8 9 10 +IN2 −IN2 VOUT2 +VS EPAD analog.com Amplifier Output, Channel 1. Inverting Input of the Amplifier, Channel 1. Noninverting Input of the Amplifier, Channel 1. Negative Power Supply. In single-supply applications, this pin is normally soldered to a low impedance ground plane. In split supply applications, bypass this pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the pin as possible. Op Amp Shutdown, Channel 1. The threshold for shutdown is approximately 1 V above the negative supply. If this pin is not connected or hard tied to −VS, the amplifier is active. If asserted high (VSHDN > −VS + 1.5 V), the amplifier is placed in a shutdown state, and the output of the amplifier goes to a high impedance state. If this pin is left unconnected, it is recommended to connect a small capacitor of 1 nF between SHDN1 and −VS to prevent signals from −IN from capacitively coupling to the SHDN1 pin. Op Amp Shutdown, Channel 2. The threshold for shutdown is approximately 1 V above the negative supply. If this pin is not connected or hard tied to −VS, the amplifier is active. If asserted high (VSHDN > −VS + 1.5 V), the amplifier is placed in a shutdown state, and the output of the amplifier goes to a high impedance state. If this pin is left unconnected, it is recommended to connect a small capacitor of 1 nF between SHDN2 and −VS to prevent signals from −IN from capacitively coupling to the SHDN2 pin. Inverting Input of the Amplifier, Channel 2. Noninverting Input of the Amplifier, Channel 2. Amplifier Output, Channel 2. Positive Power Supply. Bypass this pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the pin as possible. Exposed Pad. Connect the exposed pad to −VS. Rev. A | 11 of 34 Data Sheet ADA4099-1/ADA4099-2 TYPICAL PERFORMANCE CHARACTERISTICS Figure 7. Supply Current vs. Supply Voltage Figure 10. Shutdown Supply Current vs. Supply Voltage Figure 8. Supply Current vs. Temperature Across Various Supply Voltages Figure 11. Typical Distribution of Input Offset Voltage, VSY = 5 V Figure 9. Supply Current vs. VSHDN with Respect to −VS Figure 12. Typical Distribution of Input Offset Voltage with VSY = ±15 V analog.com Rev. A | 12 of 34 Data Sheet ADA4099-1/ADA4099-2 TYPICAL PERFORMANCE CHARACTERISTICS Figure 13. Typical Distribution of Input Offset Voltage with VSY = ±25 V Figure 16. Offset Voltage vs. Temperature with VSY = ±25 V Figure 14. Offset Voltage vs. Temperature with VSY = 5 V Figure 17. Midsupply Input Bias Current vs. Temperature with VSY = 5 V Figure 15. Offset Voltage vs. Temperature with VSY = ±15 V Figure 18. Midsupply Input Bias Current vs. Temperature with VSY = ±15 V analog.com Rev. A | 13 of 34 Data Sheet ADA4099-1/ADA4099-2 TYPICAL PERFORMANCE CHARACTERISTICS Figure 19. Offset Voltage vs. Temperature with VCM = 6 V, Over-The-Top Figure 22. Input Bias Current vs. Temperature with VSY = 5 V, Over-The-Top Figure 20. Offset Voltage vs. Temperature with VCM = 70 V Figure 23. Midsupply Input Bias Current vs. Temperature Across Various Supply Voltages Figure 21. Over-The-Top Input Bias Current vs. Temperature with VCM = 6 V analog.com Figure 24. Offset Voltage vs. Temperature Across Various Supply Voltages Rev. A | 14 of 34 Data Sheet ADA4099-1/ADA4099-2 TYPICAL PERFORMANCE CHARACTERISTICS Figure 25. Offset Voltage vs. Input Common-Mode Voltage over the Input Common-Mode Range Figure 28. Offset Voltage vs. Input Common-Mode Voltage for Ground Sensing Applications Figure 26. Offset Voltage vs. Input Common-Mode Voltage from Normal Operation to Over-The-Top Operation Figure 29. Input Bias Current vs. Input Common-Mode Voltage for Ground Sensing Applications Figure 27. Input Bias Current vs. Input Common-Mode Voltage from Normal Operation to Over-The-Top Operation Figure 30. Input Bias Current vs. Input Common-Mode Voltage analog.com Rev. A | 15 of 34 Data Sheet ADA4099-1/ADA4099-2 TYPICAL PERFORMANCE CHARACTERISTICS Figure 31. Supply Current vs. Minimum Supply Voltage Figure 34. Δ Offset Voltage vs. Output Voltage (VOUT) Figure 32. Offset Voltage vs. Minimum Supply Voltage Figure 35. Δ Offset Voltage vs. VOUT (2 kΩ Load) Figure 33. Offset Voltage vs. Supply Voltage Figure 36. SHDN Pin Current vs. VSHDN with Respect to −VS over Various Temperatures analog.com Rev. A | 16 of 34 Data Sheet ADA4099-1/ADA4099-2 TYPICAL PERFORMANCE CHARACTERISTICS Figure 37. Output Voltage Low (VOL) and Output Voltage High (VOH) vs. Temperature Figure 40. Noninverting Small Signal Frequency Response Figure 41. Inverting Small Signal Frequency Response Figure 38. Gain Bandwidth vs. Temperature Figure 39. Loop Gain and Phase vs. Frequency analog.com Figure 42. Unity-Gain Output Noise Density vs. Frequency Rev. A | 17 of 34 Data Sheet ADA4099-1/ADA4099-2 TYPICAL PERFORMANCE CHARACTERISTICS Figure 46. THD + N vs. Frequency over Load Figure 43. 0.1 Hz to 10 Hz Noise Figure 47. THD + N vs. Output Amplitude Figure 44. Unity-Gain Small Signal Step Response Figure 48. THD + N vs. Output Amplitude and Load Figure 45. Unity-Gain Large Signal Step Response analog.com Rev. A | 18 of 34 Data Sheet ADA4099-1/ADA4099-2 TYPICAL PERFORMANCE CHARACTERISTICS analog.com Figure 49. CMRR vs. Frequency Figure 51. Output Impedance vs. Frequency Figure 50. PSRR vs. Frequency Figure 52. Channel Separation vs. Frequency Rev. A | 19 of 34 Data Sheet ADA4099-1/ADA4099-2 THEORY OF OPERATION The ADA4099-1 and ADA4099-2 are single/dual robust, voltage feedback amplifiers that combine unity-gain stability with low offset, low offset drift, and 7 nV/√Hz of input noise. Figure 55 shows a simplified schematic of the device. The ADA4099-1 and ADA4099-2 have two input stages: a common emitter differential input stage consisting of the Q1 and Q2 PNP transistors that operate with the inputs biased between −VS and 1.5 V below +VS, and a common base input stage that consists of the Q3 to Q6 PNP transistors that operate when the common-mode input is biased >+VS − 1.5 V. These input stages result in two distinct operating regions, as shown in Figure 53. For common-mode input voltages that are approximately 1.5 V below the +VS supply, where Q1 and Q2 are active (see Figure 53), the common emitter PNP input stage is active and the input bias current is typically 10 V below −VS, at the cost of stability and added thermal noise. The input stage of the ADA4099-1 and ADA4099-2 incorporates phase reversal protection to prevent the output from phase reversing for inputs below −VS. The ADA4099-1 and ADA4099-2 op amps do not have clamping diodes between the inputs and can be differentially overdriven up to 80 V without damage, inducing parametric shifts, or drawing appreciable input current. Figure 57 summarizes the input fault types that can be applied to the ADA4099-1 and ADA4099-2 without compromising input integrity. Figure 57. ADA4099-1 and ADA4099-2 Fault Tolerant Conditions OVER-THE-TOP OPERATION CONSIDERATIONS When the ADA4099-1 and ADA4099-2 input common-modes are biased near or >+VS supply, the amplifiers operate in the Over-TheTop configuration. The differential input pair that controls amplifier operation is the common base pair, Q3 to Q6 (see Figure 55). Figure 56. ADA4099-1 and ADA4099-2 as Unity-Gain Buffers with Noninverting Inputs Driven Beyond the Supply (VSY = 5 V) Input bias currents change from