1:2 Single-Ended, Low Cost
Active RF Splitter
ADA4303-2
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
5V
Ideal for CATV applications
Excellent frequency response
1.7 GHz, −3 dB bandwidth
1 dB flatness to 1.2 GHz
Low noise figure: 4.4 dB
Low distortion
Composite second order (CSO): −62 dBc
Composite triple beat (CTB): −72 dBc
1 dB compression point of 8.5 dBm
3 dB of gain per output channel
24 dB isolation between output channels
75 Ω input and outputs
Small package size
12-lead, 3 mm × 3 mm lead frame chip scale package
5V
0.1µF
0.1µF
1µH
VCC
IL
VO1
VIN
0.01µF
ADA4303-2
0.01µF
VO2
0.01µF
249Ω
249Ω
06364-001
GND
APPLICATIONS
Figure 1.
Set-top boxes
Home gateways
CATV distribution systems
Splitter modules
Digital cable ready (DCR) TVs
GENERAL DESCRIPTION
TA = –40°C
3
2
TA = +25°C
1
0
TA = +85°C
–1
–2
–3
–4
–5
–6
–7
–8
50
100
1000
FREQUENCY (MHz)
4000
06364-010
The ADA4303-2 is a low cost alternative that simplifies designs
and improves system performance by integrating a signal splitter
element and a gain block into a single IC. The ADA4303-2 is
available in a 12-lead chip scale package (LFCSP) and operates
in the extended industrial temperature range of −40°C to +85°C.
4
GAIN (dB)
The ADA4303-2 is a 75 Ω, two-output active splitter for use
in applications where a lossless signal split is required. Typical
applications include multituner digital set-top boxes, cable splitter
modules, multituner/digital cable ready (DCR) televisions, and
home gateways where traditional solutions require discrete
passive splitter modules with separate fixed gain amplifiers.
Figure 2. Gain (S21) vs. Frequency
Rev. A
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Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADA4303-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................5
Applications ....................................................................................... 1
Typical Performance Characteristics ..............................................6
Functional Block Diagram .............................................................. 1
Applications Information .................................................................8
General Description ......................................................................... 1
Circuit Description .......................................................................8
Revision History ............................................................................... 2
Evaluation Board ...........................................................................8
Specifications..................................................................................... 3
RF Layout Considerations ............................................................8
Absolute Maximum Ratings ............................................................ 4
Power Supply..................................................................................8
Thermal Resistance ...................................................................... 4
Outline Dimensions ..........................................................................9
ESD Caution .................................................................................. 4
Ordering Guide .............................................................................9
REVISION HISTORY
5/2016—Rev. 0 to Rev. A
Changed LFCSP_VQ to LFCSP ................................... Throughout
Changes to Figure 4 and Table 4 ..................................................... 5
Changes to Figure 17 ........................................................................ 8
Updated Outline Dimensions ......................................................... 9
Changes to Ordering Guide ............................................................ 9
10/2006—Revision 0: Initial Version
Rev. A | Page 2 of 12
Data Sheet
ADA4303-2
SPECIFICATIONS
VCC = 5 V, RIN = RL = 75 Ω, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Bandwidth (−3 dB)
Specified Frequency Range
Gain (S21)
1 dB Gain Flatness
NOISE/DISTORTION PERFORMANCE
Noise Figure
Output IP3
Output IP2
Composite Triple Beat (CTB)
Composite Second-Order (CSO)
Cross Modulation (CXM)
INPUT CHARACTERISTICS
Input Return Loss (S11)
Output-to-Input Isolation (S12)
OUTPUT CHARACTERISTICS
Output Return Loss (S22)
Output-to-Output Isolation
1 dB Compression
POWER SUPPLY
Nominal Supply Voltage
Quiescent Supply Current
Test Conditions/Comments
Min
f = 100 MHz
54
2.0
Typ
Max
Unit
865
4.0
MHz
MHz
dB
MHz
1700
At 54 MHz
At 550 MHz
At 865 MHz
f1 = 97.25 MHz, f2 = 103.25 MHz
f1 = 97.25 MHz, f2 = 103.25 MHz
135 Channels, 15 dBmV/Channel, f = 865 MHz
135 Channels, 15 dBmV/Channel, f = 865 MHz
135 Channels, 15 dBmV/Channel, 100% modulation
at 15.75 kHz, f = 865 MHz
Referenced to 75 Ω
At 54 MHz
At 550 MHz
At 865 MHz
Any output, 54 MHz to 865 MHz
At 54 MHz
At 550 MHz
At 865 MHz
Referenced to 75 Ω
At 54 MHz
At 550 MHz
At 865 MHz
Between any two outputs, 54 MHz to 865 MHz
At 54 MHz
At 550 MHz
At 865 MHz
Output referred, f = 100 MHz
4.0
4.3
4.4
26.5
44.0
−72
−62
−68
4.3
4.9
5.1
−66
−60
−65
dB
dB
dB
dBm
dBm
dBc
dBc
dBc
−15.0
−19.5
−12.0
−11.5
−14.0
−7.5
dB
dB
dB
−31.8
−32.0
−32.5
−29.0
−29.5
−30.0
dB
dB
dB
−31.2
−19.4
−15.5
−23.0
−14.0
−11.0
dB
dB
dB
dB
dB
dB
dB
dBm
5.5
90
V
mA
−24.6
−24.0
−24.5
8.5
4.5
Rev. A | Page 3 of 12
3.0
1200
5.0
78
ADA4303-2
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Rating
5.5 V
See Figure 3
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This
is a stress rating only; functional operation of the product
at these or any other conditions above those indicated in
the operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package
leads/exposed pad from metal traces, through-holes, ground,
and power planes reduces the θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 12-lead LFCSP
(99.2°C/W) on a JEDEC standard 4-layer board.
2.5
θJA is specified for the worst-case conditions; that is, θJA is
specified for a device (including exposed pad) soldered to
the circuit board.
Table 3. Thermal Resistance
Package Type
12-Lead LFCSP (exposed pad)
θJA
99.2
Unit
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4303-2
package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the
glass transition temperature, the plastic changes the properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4303-2.
Exceeding a junction temperature of 150°C for an extended
period can result in changes in the silicon devices,
potentially causing failure.
MAXIMUM POWER DISSIPATION (W)
THERMAL RESISTANCE
2.0
1.5
1.0
0.5
0
–60
–40
–20
0
20
40
60
AMBIENT TEMPERATURE (°C)
80
100
120
06364-016
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the
voltage between the supply pins (VS) times the quiescent
current (IS). The power dissipated due to the load drive depends
upon the particular application. The power due to load drive is
calculated by multiplying the load current by the associated
voltage drop across the device. RMS voltages and currents must
be used in these calculations.
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. A | Page 4 of 12
Data Sheet
ADA4303-2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADA4303-2
10 NIC
11 IL
12 VCC
TOP VIEW
(Not to Scale)
VCC 1
9 VO1
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. CONNECT THE EPAD TO THE GROUND PLANE.
06364-002
NIC 6
GND 5
8 VO2
7 GND
GND 4
VIN 2
GND 3
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
Mnemonic
VCC
VIN
GND
GND
GND
NIC
GND
VO2
VO1
NC
IL
VCC
EPAD
Description
Supply Pin.
Input.
Ground.
Ground.
Ground.
Not Internal Connection.
Ground.
Output 2.
Output 1.
No Connection.
Bias Pin.
Supply Pin.
Exposed Pad. Connect the EPAD to the Ground Plane.
Rev. A | Page 5 of 12
ADA4303-2
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
–50
10
–53
–56
8
TA = +85°C
NOISE FIGURE (dB)
CSO (dBc)
–59
–62
TA = +25°C
–65
TA = –40°C
–68
–71
6
TA = +85°C
4
TA = +25°C
–74
TA = –40°C
2
100
1000
FREQUENCY (MHz)
0
50
06364-004
–80
50
100
1000
FREQUENCY (MHz)
Figure 5. Composite Second-Order (CSO) vs. Frequency
06364-007
–77
Figure 8. Noise Figure vs. Frequency
–60
60
–63
55
–66
50
OUTPUT IP2 (dBm)
–69
CTB (dBc)
TA = +85°C
–72
–75
–78
TA = +25°C
–81
TA = –40°C
45
40
35
30
–84
100
1000
FREQUENCY (MHz)
20
50
06364-005
–90
50
100
1000
FREQUENCY (MHz)
Figure 6. Composite Triple Beat (CTB) vs. Frequency
06364-008
25
–87
Figure 9. Output IP2 vs. Frequency
–60
40
–63
35
–66
30
OUTPUT IP3 (dBm)
–69
–72
–75
–78
–81
TA = +25°C
TA = –40°C
25
20
15
10
–84
–90
50
100
1000
FREQUENCY (MHz)
Figure 7. Cross Modulation (CXM) vs. Frequency
0
50
100
1000
FREQUENCY (MHz)
Figure 10. Output IP3 vs. Frequency
Rev. A | Page 6 of 12
06364-009
5
–87
06364-006
CXM (dBc)
TA = +85°C
Data Sheet
ADA4303-2
4
0
TA = –40°C
3
2
–5
GAIN (dB)
0
INPUT RETURN LOSS (dB)
TA = +25°C
1
TA = +85°C
–1
–2
–3
–4
–5
–6
–10
–15
–20
–25
100
1000
4000
FREQUENCY (MHz)
–30
50
06364-010
–8
50
Figure 14. Input Return Loss (S11) vs. Frequency
–30
0
–31
–5
OUTPUT RETURN LOSS (dB)
–32
–33
–34
–35
–36
–37
–38
–10
–15
–20
–25
–30
100
1000
4000
FREQUENCY (MHz)
–40
50
06364-011
–40
50
100
1000
FREQUENCY (MHz)
Figure 12. Output-to-Input Isolation (S12) vs. Frequency
06364-014
–35
–39
Figure 15. Output Return Loss (S22) vs. Frequency
0
90
QUIESCENT SUPPLY CURRENT (mA)
–5
–10
–15
–20
–25
–30
–35
85
80
75
70
–45
50
100
1000
FREQUENCY (MHz)
4000
06364-012
–40
Figure 13. Output-to-Output Isolation vs. Frequency
65
–60 –50 –40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
Figure 16. Quiescent Supply Current vs. Temperature
Rev. A | Page 7 of 12
06364-015
ISOLATION (dB)
1000
FREQUENCY (MHz)
Figure 11. Gain (S21) vs. Frequency
ISOLATION (dB)
100
06364-013
–7
ADA4303-2
Data Sheet
APPLICATIONS INFORMATION
EVALUATION BOARD
The ADA4303-2 active splitter is primarily intended for use
in the downstream path of television set-top boxes (STBs) that
contain multiple tuners. It is typically located directly after the
diplexer in a CATV customer premise unit. The ADA4303-2
provides a single-ended input and two single-ended outputs
that allow the delivery of the RF signal to two different signal
paths. These paths can include, but are not limited to, a main
picture tuner, a picture-in-picture (PIP) tuner, an out-of-band
(OOB) tuner, a digital video recorder (DVR), and a cable
modem (CM).
The ADA4303-2 evaluation board allows designers to assess the
performance of the device in particular applications. The board
includes 75 Ω coaxial connectors and 75 Ω controlled-impedance
signal traces that carry the input and output signals. Power (5 V)
is applied to the red VCC loop connector, and ground is connected
to the black GND loop connector.
The board has two 249 Ω resistors between each output and
ground that set the gain of the overall circuit to 3 dB and improve
output-to-output isolation. A schematic of the ADA4303-2
evaluation board is shown in Figure 17.
The ADA4303-2 exhibits composite second-order (CSO) and
composite triple beat (CTB) products that are −62 dBc and
−72 dBc, respectively. The use of the SiGe process also allows
the ADA4303-2 to achieve a noise figure (NF) of less than 4.5 dB.
RF LAYOUT CONSIDERATIONS
Appropriate impedance matching techniques are mandatory
when designing a circuit board for the ADA4303-2. Improper
characteristic impedances on traces can cause reflections that
can lead to poor linearity. The characteristic impedance of the
signal trace from each output should be 75 Ω.
CIRCUIT DESCRIPTION
The ADA4303-2 consists of a low noise buffer amplifier followed
by a resistive power divider. This arrangement provides 3 dB of
gain relative to the RF signal present at the input of the device.
The input and each output must be properly matched to a 75 Ω
environment for distortion and noise performance to match the
data sheet specifications. In addition, to achieve the specified gain,
a 1% 249 Ω resistor should be installed to ground on each output.
AC coupling capacitors of 0.01 µF are recommended for the
input and outputs.
POWER SUPPLY
The 5 V supply should be applied to each of the VCC pins and
RF choke via a low impedance power bus. The power bus should
be decoupled to ground using a 10 µF tantalum capacitor and
a 0.1 µF ceramic chip capacitor located close to the ADA4303-2.
In addition, the VCC pins should be decoupled to ground with
a 0.1 µF ceramic chip capacitor located as close to each of the
pins as possible.
A 1 µH RF choke (Coilcraft chip inductor 0805LS-102X) is
required to correctly bias internal nodes of the ADA4303-2.
It should be connected between the 5 V supply and IL (Pin 11).
VCC
C1
0.1µF
C6
0.1µF
11
VCC
12
1
8
VIN
VO2
GND
GND
GND
3
VO1
ADA4303-2
2
249Ω
9
VCC
J2
5
C4
0.01μF
249Ω
J3
6
06364-003
4
7
NIC
C2
0.01μF
C3
0.01μF
10
GND
J1
L1
1.0μH
NIC
+
IL
C5
10µF
GND
NIC = NO INTERNAL CONNECTION
Figure 17. ADA4303-2 Evaluation Board Schematic
Rev. A | Page 8 of 12
Data Sheet
ADA4303-2
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.30
0.23
0.18
10
0.50
BSC
PIN 1
INDICATOR
12
1
9
EXPOSED
PAD
1.65
1.50 SQ
1.35
7
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
3
6
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
4
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
111808-A
3.10
3.00 SQ
2.90
Figure 18. 12-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-12-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADA4303-2ACPZ-RL
ADA4303-2ACPZ-R7
ADA4303-2ACPZ-R2
ADA4303-2ACPZ-EB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
12-Lead LFCSP
12-Lead LFCSP
12-Lead LFCSP
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 9 of 12
Package Option
CP-12-5
CP-12-5
CP-12-5
Ordering Quantity
5000
1500
250
Branding
H0V
H0V
H0V
ADA4303-2
Data Sheet
NOTES
Rev. A | Page 10 of 12
Data Sheet
ADA4303-2
NOTES
Rev. A | Page 11 of 12
ADA4303-2
Data Sheet
NOTES
©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06364-0-5/16(A)
Rev. A | Page 12 of 12
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