Low Cost 6-Channel HD/SD Video Filter
ADA4420-6
FEATURES
FUNCTIONAL BLOCK DIAGRAM
INSD1
SD
×2
×1
SD
×2
×1
SD
×2
×1
HD
×2
×1
HD
×2
×1
HD
×2
OUTSD1
CLAMP
INSD2
OUTSD2
CLAMP
INSD3
DIS
OUTSD3
CLAMP
INHD1
APPLICATIONS
Set-top boxes
DVD players and recorders
HDTVs
Projectors
Personal video recorders
×1
OUTHD1
CLAMP
INHD2
OUTHD2
CLAMP
INHD3
CLAMP
ADA4420-6
OUTHD3
07532-001
Sixth-order filters
Transparent input sync tip clamp
−1 dB bandwidth of 26 MHz typical for HD
HD rejection @ 75 MHz: 48 dB typical
NTSC differential gain: 0.19%
NTSC differential phase: 0.76°
Rail-to-rail outputs
Low quiescent current: 32 mA typical
Disable feature
Output dc offset
Figure 1.
GENERAL DESCRIPTION
The ADA4420-6 is a low cost video reconstruction filter specifically
designed for consumer applications. It consists of six independent
sixth-order Butterworth filters/buffers, three for standard
definition (Y/C or CVBS) and three for high definition
component signals (YPrPb or RGB).
The ADA4420-6 operates from a single 5 V supply and has a
low quiescent current of 32 mA, making it ideal for applications
where power consumption is critical. A disable feature allows
for further power conservation by reducing the supply current
to less than 8 μA typical when the device is not in use.
Each channel features a transparent sync tip clamp, allowing ac
coupling of the inputs without requiring dc restoration.
The output drivers on the ADA4420-6 have rail-to-rail output
capabilities with 6 dB gain. A built-in offset of 250 mV allows
the outputs to be dc-coupled, eliminating the need for large
coupling capacitors. Each output is capable of driving two 75 Ω
doubly terminated cables.
The ADA4420-6 is available in either a 16-lead QSOP or a 20-lead
TSSOP, and operates in the extended industrial temperature
range of −40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved.
ADA4420-6
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications....................................................................................... 1
Test Circuits..................................................................................... 10
General Description ......................................................................... 1
Applications Information .............................................................. 11
Functional Block Diagram .............................................................. 1
Overview ..................................................................................... 11
Revision History ............................................................................... 2
Disable ......................................................................................... 11
Specifications..................................................................................... 3
Input and Output Coupling ...................................................... 11
Absolute Maximum Ratings............................................................ 4
Printed Circuit Board (PCB) Layout ....................................... 11
Thermal Resistance ...................................................................... 4
Video Encoder Reconstruction Filter...................................... 11
Maximum Power Dissipation ..................................................... 4
Outline Dimensions ....................................................................... 13
ESD Caution.................................................................................. 4
Ordering Guide .......................................................................... 14
Pin Configuration and Function Descriptions............................. 5
REVISION HISTORY
5/11—Rev. 0 to Rev. A
Added 20-Lead TSSOP Package .......................................Universal
Changes to General Description Section ...................................... 1
Changes to Disable Assert Voltage, Disable Assert Time, Disable
De-Assert Time Parameters ............................................................ 3
Changes to Table 3, Maximum Power Dissipation Section,
and Figure 2....................................................................................... 4
Added Figure 4 and Table 5............................................................. 6
Changes to Figure 18, Figure 19, and Figure 20 ......................... 10
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
8/08—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADA4420-6
SPECIFICATIONS
VS = 5 V, TA = 25°C, VO = 2.0 V p-p, RL = 150 Ω, dc-coupled inputs, ac-coupled outputs, unless otherwise noted. See Figure 18, Figure 19,
and Figure 20 for the test circuits.
Table 1.
Parameter
OVERALL PERFORMANCE
DC Voltage Gain
Input Voltage Range, All Inputs
Output Voltage Range, All Outputs
Linear Output Current per Channel
Filter Input Bias Current
SD CHANNEL DYNAMIC PERFORMANCE
−1 dB Bandwidth
−3 dB Bandwidth
Out-of-Band Rejection
Crosstalk
Total Harmonic Distortion
Signal-to-Noise Ratio
Propagation Delay
Group Delay Variation
Differential Gain
Differential Phase
HD CHANNEL DYNAMIC PERFORMANCE
−1 dB Bandwidth
−3 dB Bandwidth
Out-of-Band Rejection
Crosstalk
Total Harmonic Distortion
Signal-to-Noise Ratio
Propagation Delay
Group Delay Variation
DC CHARACTERISTICS
Operating Voltage
Quiescent Supply Current
PSRR
Output DC Offset
Disable Assert Voltage
Disable Assert Time
Disable De-Assert Time
Disable Input Bias Current
Input-to-Output Isolation
Test Conditions/Comments
Min
Typ
Max
Unit
All channels
5.8
6.0
0 to 2.1
0.25 to 4.6
30
1
6.2
dB
V
V
mA
μA
f = 27 MHz
f = 1 MHz
f = 1 MHz, VO = 1.4 V p-p, dc-coupled outputs
f = 100 kHz to 6 MHz, unweighted
8.5
42
f = 100 kHz to 5 MHz
NTSC; ac-coupled inputs, dc-coupled outputs;
see Figure 19
NTSC; ac-coupled inputs, dc-coupled outputs;
see Figure 19
f = 75 MHz
f = 1 MHz
f = 10 MHz, VO = 1.4 V p-p, dc-coupled outputs
f = 100 kHz to 30 MHz, unweighted
27
43
f = 100 kHz to 30 MHz
Active, DIS = 1
Disabled, DIS = 0
HD channel, referred to output
SD channel, referred to output
All channels
DIS = 0 to 1
DIS = 0 to 1
DIS = 1 to 0
Disabled, DIS = 0
Disabled, DIS = 0, f = 5 MHz
Rev. A | Page 3 of 16
35
40
135
8.6
10
45
−68
0.02
70
57
16
0.19
MHz
MHz
dB
dB
%
dB
ns
ns
%
0.76
Degrees
26
31
48
−68
0.57
66
15
11
MHz
MHz
dB
dB
%
dB
ns
ns
4.75 to 5.25
32
7
41
45
250
20
450
−6.8
−96
36
13
375
1.9
V
mA
μA
dB
dB
mV
V
ns
ns
μA
dB
ADA4420-6
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Rating
5.5 V
See Figure 2
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to load drive
depends on the particular application. For each output, the
power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to the loads is equal to the sum of the
power dissipations due to each individual load. RMS voltages
and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA.
Figure 2 shows the maximum power dissipation in the package
vs. the ambient temperature for the 16-lead QSOP (105°C/W)
and the 20-lead TSSOP (143°C/W) on a JEDEC standard 4-layer
board. θJA values are approximate.
2.0
THERMAL RESISTANCE
MAXIMUM POWER DISSIPATION (W)
1.8
θJA is specified for the device soldered to a high thermal
conductivity 4-layer (2s2p) circuit board, as described in
EIA/JESD 51-7.
Table 3.
θJA
105
143
θJC
23
45
Unit
°C/W
°C/W
1.4
16-LEAD QSOP
1.2
1.0
0.8
20-LEAD TSSOP
0.6
0.4
0.2
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4420-6
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4420-6. Exceeding a
junction temperature of 150°C for an extended time can result
in changes in the silicon devices, potentially causing failure.
0
0
10
20
30
40
50
60
70
80
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
ESD CAUTION
Rev. A | Page 4 of 16
90
100
07532-016
Package Type
16-Lead QSOP
20-Lead TSSOP
1.6
ADA4420-6
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INSD1
1
16 OUTSD1
INSD2
2
15 OUTSD2
INSD3
3
VCC
4
ADA4420-6
13 GND
DIS
5
TOP VIEW
(Not to Scale)
12 GND
INHD1
6
11 OUTHD1
INHD2
7
10 OUTHD2
INHD3
8
14 OUTSD3
OUTHD3
07532-002
9
Figure 3. 16-Lead QSOP Pin Configuration
Table 4. 16-Pin QSOP Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
INSD1
INSD2
INSD3
VCC
DIS
INHD1
INHD2
INHD3
OUTHD3
OUTHD2
OUTHD1
GND
GND
OUTSD3
OUTSD2
OUTSD1
Description
Standard Definition Input 1
Standard Definition Input 2
Standard Definition Input 3
Power Supply
Disable/Power-Down Input
High Definition Input 1
High Definition Input 2
High Definition Input 3
High Definition Output 3
High Definition Output 2
High Definition Output 1
Ground
Ground
Standard Definition Output 3
Standard Definition Output 2
Standard Definition Output 1
Rev. A | Page 5 of 16
ADA4420-6
INSD1 1
20 OUTSD1
INSD2 2
19
INSD3 3
18 OUTSD3
NC 4
DIS 6
17 GND
ADA4420-6
TOP VIEW
(Not to Scale)
16 GND
15 NC
INHD1 7
14 OUTHD1
INHD2 8
13 OUTHD2
INHD3 9
NC 10
12 OUTHD3
11
NC
NC = NO CONNECT.
DO NOT CONNECT TO THIS PIN.
07532-003
VCC 5
OUTSD2
Figure 4. 20-Lead TSSOP Pin Configuration
Table 5. 20-lead TSSOP Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Mnemonic
INSD1
INSD2
INSD3
NC
VCC
DIS
INHD1
INHD2
INHD3
NC
NC
OUTHD3
OUTHD2
OUTHD1
NC
GND
GND
OUTSD3
OUTSD2
OUTSD1
Description
Standard Definition Input 1.
Standard Definition Input 2.
Standard Definition Input 3.
Do not connect to this pin.
Power Supply.
Disable/Power Down Input.
High Definition Input 1.
High Definition Input 2.
High Definition Input 3.
Do not connect to this pin.
Do not connect to this pin.
High Definition Output 3.
High Definition Output 2.
High Definition Output 1.
No Connection.
Ground.
Ground.
Standard Definition Output 3.
Standard Definition Output 2.
Standard Definition Output 1.
Rev. A | Page 6 of 16
ADA4420-6
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, VO = 2.0 V p-p, RL = 150 Ω, dc-coupled inputs, ac-coupled outputs, unless otherwise noted. See Figure 18, Figure 19,
and Figure 20 for the test circuits.
10
NORMALIZED GAIN (dB)
SD CHANNELS,
RL = 75Ω
–20
–30
SD CHANNELS,
RL = 150Ω
–40
–50
–60
0
–1.0
–1.5
–2.0
–3.0
1
0
0.5
NORMALIZED GAIN (dB)
–10
–30
–40
–50
HD –40°C
HD +25°C
HD +85°C
SD –40°C
SD +25°C
SD +85°C
0
–0.5
–1.0
–1.5
HD –40°C
HD +25°C
HD +85°C
SD –40°C
SD +25°C
SD +85°C
–2.0
–2.5
100
FREQUENCY (MHz)
–3.0
07532-005
10
1
Figure 6. Frequency Response vs. Temperature
Figure 9. Flatness vs. Temperature
10
0
0
–10
–10
–20
–20
GAIN (dB)
10
–30
–40
HD DC-COUPLED
HD AC-COUPLED
–30
–40
–50
–50
–60
–60
SD VO = 100mV p-p
SD VO = 2.0V p-p
HD VO = 100mV p-p
HD VO = 2.0V p-p
–70
1
SD AC-COUPLED
–70
10
100
FREQUENCY (MHz)
07532-006
GAIN (dB)
10
FREQUENCY (MHz)
–80
SD DC-COUPLED
1
10
100
FREQUENCY (MHz)
Figure 10. Frequency Response vs. Output Coupling
Figure 7. Frequency Response vs. Amplitude
Rev. A | Page 7 of 16
07532-017
GAIN (dB)
–20
1
100
Figure 8. Flatness vs. Load (RL)
1.0
–70
100
FREQUENCY (MHz)
10
–60
10
07532-007
100
Figure 5. Frequency Response vs. Load (RL)
–80
HD CHANNELS,
RL = 150Ω
SD CHANNELS,
RL = 150Ω
–0.5
07532-008
10
07532-004
1
FREQUENCY (MHz)
–80
HD CHANNELS,
RL = 75Ω
–2.5
–70
–80
SD CHANNELS,
RL = 75Ω
0.5
HD CHANNELS,
RL = 150Ω
–10
GAIN (dB)
1.0
HD CHANNELS,
RL = 75Ω
0
ADA4420-6
6
100
90
5
SD CHANNELS
4
70
DIS VOLTAGE (V)
60
50
SD CHANNELS
40
30
2
HD CHANNELS
1
HD CHANNELS
20
3
1
10
100
FREQUENCY (MHz)
–1
–600
07532-009
0
0.1
–400
0
200
400
600
800
1000
1200
80
100
TIME (ns)
Figure 13. Enable Time
Figure 11. Group Delay vs. Frequency
10k
–200
07532-012
0
10
07532-013
GROUP DELAY (ns)
80
36
DIS = 0
SUPPLY CURRENT (mA)
1k
100
34
33
32
31
30
29
10
0.1
1
10
FREQUENCY (MHz)
100
07532-011
OUTPUT IMPEDANCE (Ω)
35
28
–60
–40
–20
0
20
40
60
TEMPERATURE (°C)
Figure 14. Supply Current vs. Temperature
Figure 12. Output Impedance vs. Frequency
Rev. A | Page 8 of 16
ADA4420-6
4.70
–10
4.68
OUTPUT SATURATION VOLTAGE (V)
0
–30
–40
–50
–60
SD CHANNELS
–70
HD CHANNELS
–90
0.1
1
10
100
1000
FREQUENCY (MHz)
6
5
HD CHANNELS
1
0
–1
–200 –160 –120
–80
–40
0
40
TIME (ns)
80
120
160
200
07532-015
DIS VOLTAGE (V)
SD CHANNELS
3
2
4.62
4.60
4.58
4.56
4.54
4.50
–60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 17. Output Saturation Voltage vs. Temperature
Figure 15. Crosstalk vs. Frequency
4
4.64
4.52
07532-014
–80
4.66
Figure 16. Disable Time
Rev. A | Page 9 of 16
100
07532-010
CROSSTALK (dB)
–20
ADA4420-6
TEST CIRCUITS
AGILENT E3631A POWER SUPPLY
+
±25V
COM
–
VCC
GND
DIS
+6V
+
–
ADA4420-6
TEST CIRCUIT
(SEE FIGURE 18)
VCC
0.1µF
INxDx
10µF
OUTxDx
50Ω
PORT 1
220µF
ADA4420-6
49.9Ω
VOUT
118Ω
07532-018
86.6Ω
GND
DIS
AGILENT 8753D VECTOR NETWORK ANALYZER
Figure 18. DC-Coupled Input, AC-Coupled Output
Figure 20. Test Circuit for Frequency Response and Group Delay
VCC
0.1µF
49.9Ω
0.1µF
10µF
ADA4420-6
VOUT
118Ω
86.6Ω
DIS
GND
07532-019
VIN
PORT 2
BIAS
CONNECT
PORT 1
07532-020
VIN
Figure 19. AC-Coupled Input, DC-Coupled Output
Rev. A | Page 10 of 16
ADA4420-6
APPLICATIONS INFORMATION
OVERVIEW
ADA4420-6
220µF
75Ω
CABLE
75Ω
220µF
75Ω
CABLE
75Ω
75Ω
07532-022
With its high impedance inputs and high output drive, the
ADA4420-6 is ideally suited to video reconstruction and antialias filtering applications. The high impedance inputs give
designers flexibility with regard to how the input signals are
terminated. Devices with DAC current source outputs that feed
the ADA4420-6 can be loaded in whatever resistance provides
the best performance, and devices with voltage outputs can be
optimally terminated as well. The ADA4420-6 outputs can each
drive up to two source-terminated, 75 Ω loads and; therefore, can
directly drive the outputs from set-top boxes and DVDs without
the need for a separate output buffer.
75Ω
Figure 21. Driving Two AC-Coupled Loads with Two Coupling Capacitors
ADA4420-6
75Ω
75Ω
CABLE
470µF
75Ω
75Ω
75Ω
CABLE
The ADA4420-6 includes a disable feature that can be used to
save power when a particular device is not in use. When disabled,
the ADA4420-6 typically draws only 7 μA from the supply. The
disable feature is asserted by pulling the DIS pin low.
Table 6 summarizes the operation of the disable feature.
Table 6. Disable Function
DIS Pin Connection
Status
VCC or Floating
GND
Enabled
Disabled
INPUT AND OUTPUT COUPLING
Inputs to the ADA4420-6 can be ac- or dc-coupled. For dc-coupled
inputs, the signal must be completely contained within the input
range of 0 V to 2.1 V. When using ac-coupled inputs, the lowest
point of the signal is clamped to approximately 0 V. The ADA4420-6
outputs can be either ac- or dc-coupled.
When driving single ac-coupled loads in standard 75 Ω video
distribution systems, a minimum capacitance of 220 μF is
recommended to avoid line and field droop. There are two ac
coupling options when driving two loads from one output. One
option simply uses the same value capacitor on the second load,
while the other option uses a common coupling capacitor that
is at least twice the value used for the single load (see Figure 21
and Figure 22).
When driving two parallel 150 Ω loads (75 Ω effective load), the
3 dB bandwidth of the filters typically varies from that of the filters
with a single 150 Ω load (see Figure 5).
75Ω
07532-023
DISABLE
Figure 22. Driving Two AC-Coupled Loads with One Common Coupling Capacitor
PRINTED CIRCUIT BOARD (PCB) LAYOUT
As with all high speed applications, attention to the PCB layout
is of paramount importance. When designing with the ADA4420-6,
adhere to standard high speed layout practices. A solid ground
plane is recommended, and surface-mount, ceramic power supply
decoupling capacitors should be placed as close as possible to the
supply pins. Connect all of the ADA4420-6 GND pins to the
ground plane with traces that are as short as possible. Controlled
impedance traces of the shortest length possible should be used
to connect to the signal I/O pins and should not pass over any
voids in the ground plane. A 75 Ω impedance level is typically
used in video applications. When driving transmission lines,
include series termination resistors on the signal outputs of the
ADA4420-6.
When the ADA4420-6 receives its inputs from a device with
current outputs, the required load resistor value for the output
current is often different from the characteristic impedance of
the signal traces. In this case, if the interconnections are short
(
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