ADA4930-1YCP-EBZ

Ultralow Noise Drivers for Low Voltage ADCs ADA4930-1/ADA4930-2 FEATURES Low input voltage noise: 1.2 nV/√Hz Low common-mode output: 0.9 V on single supply Extremely low harmonic distortion −104 dBc HD2 at 10 MHz −79 dBc HD2 at 70 MHz −73 dBc HD2 at 100 MHz −101 dBc HD3 at 10 MHz −82 dBc HD3 at 70 MHz −75 dBc HD3 at 100 MHz High speed −3 dB bandwidth of 1.35 GHz, G = 1 Slew rate: 3400 V/μs, 25% to 75% 0.1 dB gain flatness to 380 MHz Fast overdrive recovery of 1.5 ns 0.5 mV typical offset voltage Externally adjustable gain Differential-to-differential or single-ended-to-differential operation Adjustable output common-mode voltage Single-supply operation: 3.3 V or 5 V 100 FUNCTIONAL BLOCK DIAGRAMS 16 –VS 15 –VS 13 –VS 12 PD 11 –OUT 10 +OUT 9 VOCM –FB 1 +IN 2 –IN 3 +FB 4 ADA4930-1 14 –VS +VS 7 +VS 8 Figure 1. +IN1 –FB1 –VS1 –VS1 PD1 –OUT1 –IN1 +FB1 +VS1 +VS1 –FB2 +IN2 1 2 3 4 5 6 24 23 22 21 20 19 ADA4930-2 18 17 16 15 14 13 +OUT1 VOCM1 –VS2 –VS2 PD2 –OUT2 –IN2 +FB2 +VS2 +VS2 VOCM2 +OUT2 7 8 9 10 11 12 09209-001 +VS 5 +VS 6 Figure 2. APPLICATIONS ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Line drivers 10 VN (nV/√hz) 1 GENERAL DESCRIPTION The ADA4930-1/ADA4930-2 are very low noise, low distortion, high speed differential amplifiers. They are an ideal choice for driving 1.8 V high performance ADCs with resolutions up to 14 bits from dc to 70 MHz. The adjustable output common mode allows the ADA4930-1/ADA4930-2 to match the input of the ADC. The internal common-mode feedback loop provides exceptional output balance, suppression of even-order harmonic distortion products, and dc level translation. With the ADA4930-1/ADA4930-2, differential gain configurations are easily realized with a simple external feedback network of four resistors determining the closed-loop gain of the amplifier. The ADA4930-1/ADA4930-2 are fabricated using Analog Devices, Inc., proprietary silicon-germanium (SiGe), complementary bipolar process, enabling them to achieve very low levels of distortion with an input voltage noise of only 1.2 nV/√Hz. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 3. Voltage Noise Spectral Density The low dc offset and excellent dynamic performance of the ADA4930-1/ADA4930-2 make them well suited for a wide variety of data acquisition and signal processing applications. The ADA4930-1 is available in a Pb-free, 3 mm × 3 mm 16-lead LFCSP, and the ADA4930-2 is available in a Pb-free, 4 mm × 4 mm 24-lead LFCSP. The pinout has been optimized to facilitate printed circuit board (PCB) layout and minimize distortion. The ADA4930-1 is specified to operate over the −40°C to +105°C temperature range, and the ADA4930-2 is specified to operate over the −40°C to +105°C temperature range for 3.3 V or 5 V supply voltages. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. 09209-003 0 09209-002 ADA4930-1/ADA4930-2 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 3.3 V Operation ............................................................................ 3 3.3 V VOCM to VO, cm Performance ............................................... 4 3.3 V General Performance ......................................................... 4 5 V Operation ............................................................................... 5 5 V VOCM to VO, cm Performance .................................................. 6 5 V General Performance ............................................................ 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 Maximum Power Dissipation ..................................................... 7 ESD Caution .................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ............................................. 9 Test Circuits ..................................................................................... 15 Operational Description ................................................................ 16 Definition of Terms .................................................................... 16 Theory of Operation ...................................................................... 17 Analyzing an Application Circuit ............................................ 17 Setting the Closed-Loop Gain .................................................. 17 Estimating the Output Noise Voltage ...................................... 17 Impact of Mismatches in the Feedback Networks ................. 18 Input Common-Mode Voltage Range ..................................... 18 Minimum RG Value .................................................................... 19 Setting the Output Common-Mode Voltage .......................... 19 Calculating the Input Impedance for an Application Circuit ....................................................................................................... 19 Layout, Grounding, and Bypassing .............................................. 23 High Performance ADC Driving ................................................. 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25 REVISION HISTORY 10/10—Rev. 0 to Rev. A Changes to General Description .................................................... 1 10/10—Revision 0: Initial Version Rev. A | Page 2 of 28 ADA4930-1/ADA4930-2 SPECIFICATIONS 3.3 V OPERATION VS = 3.3 V, VICM = 0.9 V, VOCM = 0.9 V, RF = 301 Ω, RG = 301 Ω, RL, dm = 1 kΩ, single-ended input, differential output, TA = 25°C, TMIN to TMAX = −40°C to +105°C, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness ADA4930-1 ADA4930-2 Slew Rate Settling Time to 0.1% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE HD2/HD3 Test Conditions/Comments VO, dm = 0.1 V p-p VO, dm = 2 V p-p VO, dm = 0.1 V p-p Min Typ 1430 887 380 89 2877 6.3 1.5 −98/−97 −91/−88 −79/−79 −73/−73 91 86 1.15 3 −90 −3.1 −36 TMIN to TMAX −1.8 RF = RG = 10 kΩ, ΔVO = 0.5 V, RL = open circuit 0.3 Differential Common mode Common mode ΔVICM = 0.5 V dc; RF = RG = 10 kΩ, RL = open circuit Each single-ended output; RF = RG = 10 kΩ Each single-ended output; f = 1 MHz, TDH ≤ 60 dBc f = 1 MHz 0.11 30 55 150 3 1 −82 −0.5 2.75 −24 −0.05 +0.1 64 +3.1 −16 +1.8 Max Unit MHz MHz MHz MHz V/μs ns ns dB dB dB dB dBc dBc nV/√Hz pA/√Hz dB mV μV/°C μA μA/°C μA dB V kΩ MΩ pF dB V mA dB VO, dm = 2 V step, 25% to 75% VO, dm = 2 V step, RL = 200 Ω G = 3, VIN, dm = 0.7 V p-p pulse VO, dm = 2 V p-p, fC = 10 MHz VO, dm = 2 V p-p, fC = 30 MHz VO, dm = 2 V p-p, fC = 70 MHz VO, dm = 2 V p-p, fC = 100 MHz VO, dm = 1 V p-p/tone, fC = 70.05 MHz ± 0.05 MHz VO, dm = 1 V p-p/tone, fC = 140.05 MHz ± 0.05 MHz f = 100 kHz f = 100 kHz f = 100 MHz, ADA4930-2, RL = 200 Ω VIP = VIN = VOCM = 0 V, RL = open circuit TMIN to TMAX Third-Order IMD Input Voltage Noise Input Current Noise Crosstalk DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Common-Mode Voltage Range Input Resistance Input Capacitance CMRR OUTPUT CHARACTERISTICS Output Voltage Linear Output Current Output Balance Error 1.2 −77 1.74 Rev. A | Page 3 of 28 ADA4930-1/ADA4930-2 3.3 V VOCM TO VO, CM PERFORMANCE Table 2. Parameter VOCM DYNAMIC PERFORMANCE −3 dB Bandwidth Slew Rate VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage Input Voltage Noise Gain CMRR Test Conditions/Comments VO, cm = 0.1 V p-p VO, cm = 2 V p-p, 25% to 75% Min Typ 745 828 Max Unit MHz V/μs VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V f = 100 kHz ΔVOCM = 0.5 V dc; RF = RG = 10 kΩ, RL = open circuit 0.8 7.0 −25 0.99 8.3 +15.4 23.5 1 −83 1.1 10.3 +31 1.02 −77 V kΩ mV nV/√Hz V/V dB 3.3 V GENERAL PERFORMANCE Table 3. Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Test Conditions/Comments Min Typ 3.3 35 81 1.8 −74 −87 1.3 1 12 0.09 97 −40 +105 Max Unit V mA μA/°C mA dB dB V V μs ns μA μA °C +PSRR −PSRR POWER-DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Pin Bias Current Enabled Disabled OPERATING TEMPERATURE RANGE Enabled Enabled, TMIN to TMAX variation Disabled ΔVICM = 0.5 V; RF = RG = 10 kΩ, RL = open circuit ΔVICM = 0.5 V; RF = RG = 10 kΩ, RL = open circuit Disabled Enabled 32 0.44 40 2.35 −70 −76 PD = 3.3 V PD = 0 V Rev. A | Page 4 of 28 ADA4930-1/ADA4930-2 5 V OPERATION VS = 5 V, VICM = 0.9 V, VOCM = 0.9 V, RF = 301 Ω, RG = 301 Ω, RL, dm = 1 kΩ, single-ended input, differential output, TA= 25°C, TMIN to TMAX = −40°C to +105°C, unless otherwise noted. Table 4. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness ADA4930-1 ADA4930-2 Slew Rate Settling Time to 0.1% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE HD2/HD3 Test Conditions/Comments VO, dm = 0.1 V p-p VO, dm = 2 V p-p VO, dm = 0.1 V p-p Min Typ 1350 937 369 90 3400 6 1.5 −104/−101 −91/−93 −79/−82 −73/−75 94 90 1.2 2.8 −90 −3.1 −34 TMIN to TMAX −0.82 RF = RG = 10 kΩ, ΔVO = 1 V, RL = open circuit 0.3 Differential Common mode Common mode ΔVICM = 1 V dc; RF = RG = 10 kΩ, RL = open circuit Each single-ended output; RF = RG = 10 kΩ Each single-ended output; f = 1 MHz, TDH ≤ 60 dBc f = 1 MHz 0.18 30 55 150 3 1 −82 −0.15 1.8 −23 −0.05 +0.1 64 +3.1 −15 +0.82 Max Unit MHz MHz MHz MHz V/μs ns ns dB dB dB dB dBc dBc nV/√Hz pA/√Hz dB mV μV/°C μA μA/°C μA dB V kΩ MΩ pF dB V mA dB VO, dm = 2 V step, 25% to 75% VO, dm = 2 V step, RL = 200 Ω G = 3, VIN, dm = 0.7 V p-p pulse VO, dm = 2 V p-p, fC = 10 MHz VO, dm = 2 V p-p, fC = 30 MHz VO, dm = 2 V p-p, fC = 70 MHz VO, dm = 2 V p-p, fC = 100 MHz VO, dm = 1 V p-p/tone, fC = 70.05 MHz ± 0.05 MHz VO, dm = 1 V p-p/tone, fC = 140.05 MHz ± 0.05 MHz f = 100 kHz f = 100 kHz f = 100 MHz, ADA4930-2, RL = 200 Ω VIP = VIN = VOCM = 0 V, RL = open circuit TMIN to TMAX Third-Order IMD Input Voltage Noise Input Current Noise Crosstalk DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Common-Mode Voltage Range Input Resistance Input Capacitance CMRR OUTPUT CHARACTERISTICS Output Voltage Linear Output Current Output Balance Error 2.8 −77 3.38 Rev. A | Page 5 of 28 ADA4930-1/ADA4930-2 5 V VOCM TO VO, CM PERFORMANCE Table 5. Parameter VOCM DYNAMIC PERFORMANCE −3 dB Bandwidth Slew Rate VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage Input Voltage Noise Gain CMRR Test Conditions/Comments VO, cm = 0.1 V p-p VO, cm = 2 V p-p, 25% to 75% Min Typ 740 1224 Max Unit MHz V/μs VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V f = 100 kHz ΔVOCM = 1.5 V; RF = RG = 10 kΩ, RL = open circuit 0.5 7.0 −25 0.99 8.3 +0.35 23.5 1 −80 2.3 10.2 +15 1.02 −77 V kΩ mV nV/√Hz V/V dB 5 V GENERAL PERFORMANCE Table 6. Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Test Conditions/Comments Min Typ 5 34 74.5 1.8 −74 −91 3 1 12 0.09 97 −40 +105 Max Unit V mA μA/°C mA dB dB V V μs ns μA μA °C +PSRR −PSRR POWER-DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Pin Bias Current Enabled Disabled OPERATING TEMPERATURE RANGE Enabled Enabled, TMIN to TMAX variation Disabled ΔVICM = 1 V; RF = RG = 10 kΩ, RL = open circuit ΔVICM = 1 V; RF = RG = 10 kΩ, RL = open circuit Disabled Enabled 31.1 0.45 38.4 2.6 −71 −75 PD = 5 V PD = 0 V Rev. A | Page 6 of 28 ADA4930-1/ADA4930-2 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Supply Voltage Power Dissipation Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 5.5 V See Figure 4 −65°C to +125°C −40°C to +105°C 300°C 150°C The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. The power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads/ exposed pad from metal traces, through holes, ground, and power planes reduces θJA. Figure 4 shows the maximum safe power dissipation vs. the ambient temperature for the ADA4930-1 single 16-lead LFCSP (98°C/W) and the ADA4930-2 dual 24-lead LFCSP (67°C/W) on a JEDEC standard 4-layer board. 3.5 3.0 2.5 ADA4930-2 2.0 1.5 ADA4930-1 1.0 0.5 0 –40 –30 –20 –10 0 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the device (including exposed pad) soldered to a high thermal conductivity 2s2p circuit board, as described in EIA/JESD51-7. Table 8. Thermal Resistance Package Type 16-Lead LFCSP (Exposed Pad) 24-Lead LFCSP (Exposed Pad) θJA 98 67 Unit °C/W °C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the ADA4930-1/ADA4930-2 packages is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4930-1/ADA4930-2. Exceeding a junction temperature of 150°C for an extended period can result in changes in the silicon devices, potentially causing failure. MAXIMUM POWER DISSIPATION (W) 10 20 30 40 50 60 70 80 90 100 110 TEMPERATURE (°C) Figure 4. Maximum Power Dissipation vs. Ambient Temperature, 4-Layer Board ESD CAUTION Rev. A | Page 7 of 28 09209-004 ADA4930-1/ADA4930-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 16 –VS 15 –VS 14 –VS 13 –VS PIN 1 INDICATOR –FB 1 +IN 2 –IN 3 +FB 4 12 PD 11 –OUT 10 +OUT 9 VOCM ADA4930-1 TOP VIEW (Not to Scale) –IN1 +FB1 +VS1 +VS1 –FB2 +IN2 1 2 3 4 5 6 24 23 22 21 20 19 PIN 1 INDICATOR +IN1 –FB1 –VS1 –VS1 PD1 –OUT1 18 17 16 15 14 13 ADA4930-2 TOP VIEW (Not to Scale) +OUT1 VOCM1 –VS2 –VS2 PD2 –OUT2 +VS 5 +VS 6 +VS 7 +VS 8 09209-005 Figure 5. ADA4930-1 Pin Configuration Figure 6. ADA4930-2 Pin Configuration Table 9. ADA4930-1 Pin Function Descriptions Pin No. 1 2 3 4 5 to 8 9 10 11 12 13 to 16 Mnemonic −FB +IN −IN +FB +VS VOCM +OUT −OUT PD −VS EPAD Description Negative Output for Feedback Component Connection. Positive Input Summing Node. Negative Input Summing Node. Positive Output for Feedback Component Connection. Positive Supply Voltage. Output Common-Mode Voltage. Positive Output for Load Connection. Negative Output for Load Connection. Power-Down Pin. Negative Supply Voltage. Exposed Paddle. The exposed pad is not electrically connected to the device. It is typically soldered to ground or a power plane on the PCB that is thermally conductive. Table 10. ADA4930-2 Pin Function Descriptions Pin No. 1 2 3, 4 5 6 7 8 9, 10 11 12 13 14 15, 16 17 18 19 20 21, 22 23 24 Mnemonic −IN1 +FB1 +VS1 −FB2 +IN2 −IN2 +FB2 +VS2 VOCM2 +OUT2 −OUT2 PD2 −VS2 VOCM1 +OUT1 −OUT1 PD1 −VS1 −FB1 +IN1 EPAD Description Negative Input Summing Node 1. Positive Output Feedback Pin 1. Positive Supply Voltage 1. Negative Output Feedback Pin 2. Positive Input Summing Node 2. Negative Input Summing Node 2. Positive Output Feedback Pin 2. Positive Supply Voltage 2. Output Common-Mode Voltage 2. Positive Output 2. Negative Output 2. Power-Down Pin 2. Negative Supply Voltage 2. Output Common-Mode Voltage 1. Positive Output 1. Negative Output 1. Power-Down Pin 1. Negative Supply Voltage 1. Negative Output Feedback Pin 1. Positive Input Summing Node 1. Exposed Paddle. The exposed pad is not electrically connected to the device. It is typically soldered to ground or a power plane on the PCB that is thermally conductive. Rev. A | Page 8 of 28 09209-006 NOTES 1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO THE DEVICE. IT IS TYPICALLY SOLDERED TO GROUND OR A POWER PLANE ON THE PCB THAT IS THERMALLY CONDUCTIVE. NOTES 1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO THE DEVICE. IT IS TYPICALLY SOLDERED TO GROUND OR A POWER PLANE ON THE PCB THAT IS THERMALLY CONDUCTIVE. –IN2 +FB2 +VS2 +VS2 VOCM2 +OUT2 7 8 9 10 11 12 ADA4930-1/ADA4930-2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = 5 V, VICM = 0.9 V, VOCM = 0.9 V, RL, dm = 1 kΩ, unless otherwise noted. 3 VIN = 100mV 3 NORMALIZED CLOSED LOOP GAIN (dB) VIN = 2V p-p NORMALIZED CLOSED LOOP GAIN (dB) 0 –3 –6 –9 –12 –15 –18 –21 –24 1M 10M 100M FREQUENCY (Hz) 1G 10G 09209-007 0 –3 –6 –9 –12 –15 –18 –21 –24 1M 10M 100M FREQUENCY (Hz) 1G 10G 09209-010 09209-012 09209-011 G = 1, RG = 300Ω G = 2, RG = 150Ω G = 5, RG = 60Ω G = 1, RG = 300Ω G = 2, RG = 150Ω G = 5, RG = 60Ω –27 –27 Figure 7. Small Signal Frequency Response at Gain = 1, Gain = 2, and Gain = 5 3 0 –3 CLOSED LOOP GAIN (dB) Figure 10. Large Signal Frequency Response at Gain = 1, Gain = 2, and Gain = 5 6 3 0 VIN = 2V p-p VIN = 100mV –6 –9 –12 –15 –18 –21 –24 VS = 3.3V VS = 5.0V CLOSED LOOP GAIN (dB) –3 –6 –9 –12 –15 –18 –21 –24 VS = 3.3V VS = 5.0V 09209-008 –27 1M 10M 100M FREQUENCY (Hz) 1G 10G –27 1M 10M 100M FREQUENCY (Hz) 1G 10G Figure 8. Small Signal Frequency Response at VS = 3.3 V and VS = 5 V 3 0 –3 CLOSED LOOP GAIN (dB) CLOSED LOOP GAIN (dB) Figure 11. Large Signal Frequency Response at VS = 3.3 V and VS = 5 V 6 3 0 VIN = 2V p-p VIN = 100mV –6 –9 –12 –15 –18 –21 –24 TA = –40°C TA = +25°C TA = +105°C –3 –6 –9 –12 –15 –18 –21 –24 TA = –40°C TA = +25°C TA = +105°C 09209-009 –27 1M 10M 100M FREQUENCY (Hz) 1G 10G –27 1M 10M 100M FREQUENCY (Hz) 1G 10G Figure 9. Small Signal Frequency Response at TA = −40°C, TA = 25°C, and TA = 105°C Figure 12. Large Signal Frequency Response at TA = −40°C, TA = 25°C, and TA = 105°C Rev. A | Page 9 of 28 ADA4930-1/ADA4930-2 3 NORMALIZED CLOSED LOOP GAIN (dB) VIN = 100mV p-p 6 3 0 CLOSED-LOOP GAIN (dB) VIN = 2V p-p 0 –3 –6 –9 –12 –15 –18 –21 –24 09209-013 RL = 1kΩ RL = 200Ω –3 –6 –9 –12 –15 –18 –21 –24 RL = 1kΩ RL = 200Ω 1M 10M 100M FREQUENCY (Hz) 1G 10G 1M 10M 100M FREQUENCY (Hz) 1G 10G Figure 13. Small Signal Frequency Response for RL = 200 Ω and RL = 1 kΩ 3 2 1 VIN = 100mV Figure 16. Large Signal Frequency Response for RL = 200 Ω and RL = 1 kΩ 0.4 0.3 0.2 0.1 ADA4930-2, ADA4930-2, ADA4930-1, ADA4930-1, ADA4930-2, ADA4930-2, 200Ω, OUT 1 200Ω, OUT 2 200Ω 1kΩ 1kΩ, OUT 1 1kΩ, OUT 2 GAIN (dB) 0 –1 –2 –3 –4 –5 09209-014 GAIN (dB) 0 –0.1 –0.2 –0.3 –0.4 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 14. VOCM Small Signal Frequency Response –40 –50 –60 DISTORTION (dBc) –50 Figure 17. Small Signal 0.1 dB Flatness vs. Frequency for RL = 200 Ω and RL = 1 kΩ DISTORTION (dBc) –70 –80 –90 –100 –110 –120 1M HD2, HD3, HD2, HD3, HD2, HD3, GAIN = 1 GAIN = 1 GAIN = 2 GAIN = 2 GAIN = 5 GAIN = 5 –60 –70 HD2, HD3, HD2, HD3, RL = 200Ω RL = 200Ω RL = 1kΩ RL = 1kΩ –80 –90 –100 1M 10M FREQUENCY (Hz) 100M 200M FREQUENCY (Hz) Figure 15. Harmonic Distortion vs. Frequency for Gain = 1, Gain = 2, and Gain = 5 Figure 18. Harmonic Distortion vs. Frequency for RL = 200 Ω and RL = 1 kΩ Rev. A | Page 10 of 28 09209-018 10M 100M 200M 09209-015 –110 09209-017 –6 1M 09209-016 –27 –27 ADA4930-1/ADA4930-2 –60 –65 –70 –20 –40 DISTORTION (dBc) –80 –85 –90 –95 –100 –105 HD2, HD3, HD2, HD3, VS = 3.3V VS = 3.3V VS = 5.0V VS = 5.0V DISTORTON (dBc) –75 –60 HD2, HD3, HD2, HD3, 3.3V 3.3V 5.0V 5.0V –80 –100 –120 09209-019 10M FREQUENCY (Hz) 100M 200M 1.5 2.0 2.5 3.0 3.5 VOUT (V p-p) Figure 19. ADA4930-1 Harmonic Distortion vs. Frequency at VS = 3.3 V and VS = 5 V –40 –50 –60 10MHz, 10MHz, 70MHz, 70MHz, HD2 HD3 HD2 HD3 Figure 22. Harmonic Distortion vs. Output @ 10 MHz –40 –50 –60 –70 –80 –90 –100 –110 0.5 10MHz, 10MHz, 70MHz, 70MHz, HD2 HD3 HD2 HD3 DISTORTION (dBc) –70 –80 –90 –100 –110 –120 0.4 1.0 1.5 2.0 2.5 3.0 VOCM ABOVE – VS (V) VOCM ABOVE – VS (V) Figure 20. Harmonic Distortion vs. VOCM at VS = 3.3 V at 10 MHz and 70 MHz 0 –20 –40 HD2, HD3, HD2, HD3, VOUT = 1V p-p VOUT = 1V p-p VOUT = 2V p-p VOUT = 2V p-p 20 0 –20 –40 –60 –80 –100 –120 –140 69.8 Figure 23. Harmonic Distortion vs. VOCM at 10 MHz and 70 MHz –60 –80 –100 –120 –140 1M NORMALIZED SPECTRUM (dBc) DISTOTION (dBc) 10M FREQUENCY (Hz) 100M 200M 09209-021 69.9 70.0 70.1 FREQUENCY (MHz) 70.2 70.3 Figure 21. Distortion vs. VOUT at VS = 3.3 V Figure 24. 70 MHz Intermodulation Distortion Rev. A | Page 11 of 28 09209-024 09209-023 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 09209-020 DISTORTION (dBc) 09209-022 –110 1M –140 1.0 ADA4930-1/ADA4930-2 –40 –45 –50 CMRR (dB) –20 –30 –40 –50 –60 –70 –80 –90 09209-025 –55 –60 –65 –70 –75 100k PSRR (dB) 1M 10M FREQUENCY (Hz) 100M 1G 1M 10M FREQUENCY (Hz) 100M 1G Figure 25. CMRR vs. Frequency, RL = 200 Ω –60 –70 –80 CROSSTALK (dB) –20 Figure 28. PSRR vs. Frequency, RL = 200 Ω CHANNEL 1 TO CHANNEL 2 CHANNEL 2 TO CHANNEL 1 –25 –30 VIN = 1V p-p GAIN = 2 –90 –100 –110 –120 –130 –140 1M CROSSTALK (dB) –35 –40 –45 –50 –55 –60 10M 100M 1G 09209-026 1M FREQUENCY (Hz) 10M 100M FREQUENCY (Hz) 1G Figure 26. Crosstalk vs. Frequency, RL = 200 Ω 0 –10 –20 –30 –40 –50 –60 –70 1M 10M 100M FREQUENCY (Hz) 1G 10G S11 S22 –50 –55 –60 –65 DISTORTION (dBc) Figure 29. Output Balance vs. Frequency, RL = 200 Ω S PARAMETERS (dB) –70 –75 –80 –85 –90 –95 –100 RL = 200Ω RL = 1kΩ 09209-027 10M FREQUENCY (Hz) 100M 200M Figure 27. S11, S22, RL = 200 Ω Figure 30. SFDR Rev. A | Page 12 of 28 09209-030 –105 1M 09209-029 09209-028 –100 100k ADA4930-1/ADA4930-2 80 70 60 50 40 GAIN (dB) 60 30 0 GAIN 30 –60 PHASE PHASE (°) 100 10 30 20 10 0 –10 –20 –30 –40 10k 100k 1M –90 –120 –150 –180 –210 –240 –270 VN (nV/√hz) 1 09209-031 10M 100M 1G 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (MHz) FREQUENCY (Hz) Figure 31. Open Loop Gain and Phase 0.10 1.00 0.98 Figure 34. Voltage Noise Spectral Density 0.05 0.96 0.94 VOUT (V) 0 VOUT (V) 0.92 0.90 0.88 0.86 0.84 0.82 0 2 4 6 8 10 TIME (ns) 12 14 16 18 20 09209-035 09209-036 –0.05 0 2 4 TIME (ns) 6 8 10 Figure 32. Small Signal Pulse Response 2.0 1.5 1.0 0.5 2.0 VOUT (V) 09209-032 –0.10 0.80 Figure 35. Small Signal VOCM Pulse Response 3.0 VO = 2V p-p VO = 1V p-p 2.5 VOUT (V) 0 –0.5 –1.0 –1.5 –2.0 1.5 1.0 0.5 0 2 4 TIME (ns) 6 8 10 09209-033 0 0 2 4 6 8 10 TIME (ns) 12 14 16 18 20 Figure 33. Large Signal Pulse Response Figure 36. Large Signal VOCM Pulse Response Rev. A | Page 13 of 28 09209-034 –300 10G 0 ADA4930-1/ADA4930-2 2.25 2.00 1.75 1.50 VOLTAGE (V) 2.5 2.0 1.5 1.0 VIN × 3 VO, dm 1.25 1.00 0.75 0.50 0.25 0 09209-037 VOLTAGE (V) 0.5 0 –0.5 –1.0 –1.5 –2.0 PD +OUT –OUT 0 100 200 300 400 500 600 TIME (ns) 700 800 900 1000 0 5 10 15 20 25 30 TIME (ns) 35 40 45 50 Figure 37. PD Response vs. Time Figure 38. Vo, dm Overdrive Recovery Rev. A | Page 14 of 28 09209-038 –0.25 –2.5 ADA4930-1/ADA4930-2 TEST CIRCUITS 301Ω +VS 50Ω VIN 0.9V 57.6Ω 0.9V 301Ω VOCM 301Ω 09209-046 ADA4930 1kΩ 26.7Ω 0.9V 301Ω Figure 39. Equivalent Basic Test Circuit 301Ω +VS 50Ω VIN 0.9V 57.6Ω 0.9V 301Ω VOCM 301Ω 26.7Ω 0.9V 301Ω 50Ω ADA4930 50Ω 09209-047 Figure 40. Test Circuit for Output Balance 301Ω +VS 50Ω VIN 0.9V FILTER 57.6Ω 0.9V 301Ω 09209-048 301Ω VOCM 301Ω 26.7Ω 0.9V 0.1µF 412Ω FILTER ADA4930 0.1µF 261Ω 412Ω 0.9V Figure 41. Test Circuit for Distortion Measurements Rev. A | Page 15 of 28 ADA4930-1/ADA4930-2 OPERATIONAL DESCRIPTION DEFINITION OF TERMS –FB RG RF +IN –OUT +DIN VOCM –DIN +FB RG R F –IN Common-Mode Voltage Common-mode voltage refers to the average of two node voltages. The output common-mode voltage is defined as RL, dm VOUT, dm 09209-049 ADA4930 +OUT VOUT, cm = (V+OUT + V−OUT)/2 Balance Output balance is a measure of how close the differential signals are to being equal in amplitude and opposite in phase. Output balance is most easily determined by placing a well-matched resistor divider between the differential voltage nodes and comparing the magnitude of the signal at the divider midpoint with the magnitude of the differential signal (see Figure 39). By this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage. Figure 42. Circuit Definitions Differential Voltage Differential voltage refers to the difference between two node voltages. For example, the output differential voltage (or, equivalently, output differential-mode voltage) is defined as VOUT, dm = (V+OUT − V−OUT) where V+OUT and V−OUT refer to the voltages at the +OUT and −OUT terminals with respect to a common reference. Output Balance Error = VOUT , cm VOUT , dm Rev. A | Page 16 of 28 ADA4930-1/ADA4930-2 THEORY OF OPERATION The ADA4930-1/ADA4930-2 differ from conventional op amps in that they have two outputs whose voltages move in opposite directions and an additional input, VOCM. Like an op amp, they rely on high open-loop gain and negative feedback to force these outputs to the desired voltages. The ADA4930-1/ADA4930-2 behave much like standard voltage feedback op amps and facilitate single-ended-to-differential conversions, common-mode level shifting, and amplifications of differential signals. Like op amps, the ADA4930-1/ADA4930-2 have high input impedance and low output impedance. Two feedback loops control the differential and common-mode output voltages. The differential feedback, set with external resistors, controls the differential output voltage. The commonmode feedback controls the common-mode output voltage. This architecture makes it easy to set the output common-mode level to any arbitrary value within the specified limits. The output common-mode voltage is forced to be equal to the voltage applied to the VOCM input by the internal common-mode feedback loop. The internal common-mode feedback loop produces outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. This results in differential outputs that are very close to the ideal of being identical in amplitude and are exactly 180°◀apart in phase. ESTIMATING THE OUTPUT NOISE VOLTAGE The differential output noise of the ADA4930-1/ADA4930-2 can be estimated using the noise model in Figure 43. The input-referred noise voltage density, vnIN, is modeled as differential. The noise currents, inIN− and inIN+, appear between each input and ground. VnRG1 RG1 RF1 VnRF1 inIN+ + inIN– VnIN ADA4930 VOCM VnOD VnRG2 RG2 RF2 VnRF2 Figure 43. Noise Model Similar to the case of conventional op amps, the output noise voltage densities can be estimated by multiplying the inputreferred terms at +IN and −IN by an appropriate output factor. The output voltage due to vnIN is obtained by multiplying vnIN by the noise gain, GN. The circuit noise gain is ANALYZING AN APPLICATION CIRCUIT The ADA4930-1/ADA4930-2 use high open-loop gain and negative feedback to force their differential and common-mode output voltages to minimize the differential and common-mode error voltages. The differential error voltage is defined as the voltage between the differential inputs labeled +IN and −IN (see Figure 42). For most purposes, this voltage can be assumed to be zero. Similarly, the difference between the actual output common-mode voltage and the voltage applied to VOCM can also be assumed to be zero. Starting from these two assumptions, any application circuit can be analyzed. GN = (β1 + β2 ) RG1 RG2 and β2 = . RF1 + RG1 RF2 + RG2 2 where the feedback factors are β1 = When the feedback factors are matched, RF1/RG1 = RF2/RG2, R 1 β1 = β2 = β, and the noise gain becomes GN = = 1 + F . β RG The noise currents are uncorrelated with the same mean-square value, and each produces an output voltage that is equal to the noise current multiplied by the associated feedback resistance. The noise voltage density at the VOCM pin is vnCM. When the feedback networks have the same feedback factor, as in most cases, the output noise due to vnCM is common-mode and the output noise from VOCM is zero. Each of the four resistors contributes (4kTRxx)1/2. The noise from the feedback resistors appears directly at the output, and the noise from the gain resistors appears at the output multiplied by RF/RG. The total differential output noise density, vnOD, is the root-sumsquare of the individual output noise terms. vnOD = SETTING THE CLOSED-LOOP GAIN The differential-mode gain of the circuit in Figure 42 is determined by VOUT , dm VIN , dm = RF RG where the gain and feedback resistors, RG and RF, on each side are equal. ∑ (vnODi )2 i =1 8 Rev. A | Page 17 of 28 09209-050 VnCM ADA4930-1/ADA4930-2 Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks Input Noise Contribution Differential Input Inverting Input Noninverting Input VOCM Input Gain Resistor RG1 Gain Resistor RG2 Feedback Resistor RF1 Feedback Resistor RF2 Input Noise Term vnIN inIN+ inIN− vnCM vnRG1 vnRG2 vnRF1 vnRF2 Input Noise Voltage Density vnIN inIN+ × (RF2) inIN− × (RF1) vnCM (4kTRG1)1/2 (4kTRG2)1/2 (4kTRF1)1/2 (4kTRF2)1/2 Output Multiplication Factor GN 1 1 0 RF1/RG1 RF2/RG2 1 1 Differential Output Noise Voltage Density Terms vnOD1 = GN(vnIN) vnOD2 = (inIN+)(RF2) vnOD3 = (inIN−)(RF1) vnOD4 = 0 vnOD5 = (RF1/RG1)(4kTRG1)1/2 vnOD6 = (RF2/RG2)(4kTRG2)1/2 vnOD7 = (4kTRF1)1/2 vnOD8 = (4kTRF2)1/2 Table 12. Differential Input, DC-Coupled, VS = 5 V Nominal Gain (dB) 0 6 10 14 RF1, RF2 (Ω) 301 301 301 301 RG1, RG2 (Ω) 301 150 95.3 60.4 RIN, dm (Ω) 602 300 190.6 120.4 Differential Output Noise Density (nV/√Hz) 4.9 6.2 7.8 10.1 Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω, VS = 5 V Nominal Gain (dB) 0 6 10 14 1 RF1, RF2 (Ω) 301 301 301 301 RG1 (Ω) 142 63.4 33.2 10.2 RT (Ω) 64.2 84.5 1k 1.15 k RIN, cm (Ω) 190.67 95.06 53.54 17.5 RG2 (Ω)1 170 95 69.3 57.7 Differential Output Noise Density (nV/√Hz) 5.9 7.8 9.3 10.4 RG2 = RG1 + (RS||RT). Table 11 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms. Table 12 and Table 13 list several common gain settings, associated resistor values, input impedance, and output noise density for both balanced and unbalanced input configurations. IMPACT OF MISMATCHES IN THE FEEDBACK NETWORKS As previously mentioned, even if the external feedback networks (RF/RG) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. The amplitudes of the signals at each output remain equal and 180° out of phase. The input-to-output differential mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. The gain from the VOCM pin to VO, dm is equal to 2(β1 − β2)/(β1 + β2) When β1 = β2, this term goes to zero and there is no differential output voltage due to the voltage on the VOCM input (including noise). The extreme case occurs when one loop is open and the other has 100% feedback; in this case, the gain from VOCM input to VO, dm is either +2 or −2, depending on which loop is closed. The feedback loops are nominally matched to within 1% in most applications, and the output noise and offsets due to the VOCM input are negligible. If the loops are intentionally mismatched by a large amount, it is necessary to include the gain term from VOCM to VO, dm and account for the extra noise. For example, if β1 = 0.5 and β2 = 0.25, the gain from VOCM to VO, dm is 0.67. If the VOCM pin is set to 0.9 V, a differential offset voltage is present at the output of (0.9 V)(0.67) = 0.6 V. The differential output noise contribution is (5 nV/√Hz)(0.67) = 3.35 nV/√Hz. Both of these results are undesirable in most applications; therefore, it is best to use nominally matched feedback factors. Mismatched feedback networks also result in a degradation of the ability of the circuit to reject input common-mode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. As a practical summarization of the previous issues, resistors of 1% tolerance produce a worst-case input CMRR of approximately 40 dB, a worst-case differential-mode output offset of 9 mV due to a 0.9 V VOCM input, negligible VOCM noise contribution, and no significant degradation in output balance error. INPUT COMMON-MODE VOLTAGE RANGE The input common-mode range at the summing nodes of the ADA4930-1/ADA4930-2 is specified as 0.3 V to 1.5 V at VS = 3.3 V. To avoid nonlinearities, the voltage swing at the +IN and −IN terminals must be confined to these ranges. Rev. A | Page 18 of 28 ADA4930-1/ADA4930-2 MINIMUM RG VALUE Due to the wide bandwidth of the ADA4930-1/ADA4930-2, the value of RG must be greater than or equal to 301 Ω at unity gain to provide sufficient damping in the amplifier front end. In the terminated case, RG includes the Thevenin resistance of the source and load terminations. For an unbalanced single-ended input signal, as shown in Figure 45, the input impedance is RIN,SE = RG1 where: β1 = β2 = RG1 RG1 + R F1 RG 2 RG2 + R F 2 RF1 RIN, SE RG1 VOCM RG2 +VS β1 + β2 β1( β2 + 1) SETTING THE OUTPUT COMMON-MODE VOLTAGE The VOCM pin of the ADA4930-1/ADA4930-2 is biased at 3/10 of the total supply voltage above −VS with an internal voltage divider. The input impedance of the VOCM pin is 8.4 kΩ. When relying on the internal bias, the output common-mode voltage is within about 100 mV of the expected value. In cases where accurate control of the output common-mode level is required, it is recommended that an external source or resistor divider be used with source resistance less than 100 Ω. The output common-mode offset listed in the Specifications section assumes that the VOCM input is driven by a low impedance voltage source. It is also possible to connect the VOCM input to a common-mode voltage (VCM) output of an ADC. However, care must be taken to ensure that the output has sufficient drive capability. The input impedance of the VOCM pin is approximately 10 kΩ. If multiple ADA4930-1/ADA4930-2 devices share one reference output, it is recommended that a buffer be used. ADA4930 RL VOUT, dm RF2 Figure 45. ADA4930-1/ADA4930-2 with Unbalanced (Single-Ended) Input For a balanced system where RG1 = RG2 = RG and RF1 = RF2 = RF, the equations simplify to ⎞ ⎛ ⎟ ⎜ RG RG ⎟ β1 = β2 = and R IN,SE = ⎜ ⎟ ⎜ RF R G + RF ⎟ ⎜ 1− ⎝ 2(RG + R F ) ⎠ The input impedance of the circuit is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor RG1. The common-mode voltage at the amplifier input terminals can be easily determined by noting that the voltage at the inverting input is equal to the noninverting output voltage divided down by the voltage divider formed by RF2 and RG2. This voltage is present at both input terminals due to negative voltage feedback and is in phase with the input signal, thus reducing the effective voltage across RG1, partially bootstrapping it. CALCULATING THE INPUT IMPEDANCE FOR AN APPLICATION CIRCUIT The effective input impedance depends on whether the signal source is single-ended or differential. For a balanced differential input signal, as shown in Figure 44, the input impedance (RIN, dm) between the inputs (+DIN and −DIN) is RIN, dm = 2 × RG. RF ADA4930 +VS +DIN –DIN RG +IN VOCM –IN RF VOUT, dm 09209-051 RG Figure 44. ADA4930-1/ADA4930-2 Configured for Balanced (Differential) Inputs Rev. A | Page 19 of 28 09209-052 –VS ADA4930-1/ADA4930-2 Terminating a Single-Ended Input This section describes the five steps that properly terminate a single-ended input to the ADA4930-1/ADA4930-2. Assume a system gain of 1, RF1 = RF2 = 301 Ω, an input source with an opencircuit output voltage of 2 V p-p, and a source resistance of 50 Ω. Figure 46 shows this circuit. 1. Calculate the input impedance. β1 = β2 = 301/602 = 0.5 and RIN = 401.333 Ω RF1 RIN 401.333Ω RS VS 2V p-p 50Ω RG1 301Ω VOCM RG2 301Ω –VS 301Ω 09209-053 4. Set RF1 = RF2 = RF to maintain a balanced system. Compensate the imbalance caused by RTH. There are two methods available to compensate, which follow: • Add RTH to RG2 to maintain balanced gain resistances V and increase RF1 and RF2 to RF = S Gain(RG + RTH) to VTH • maintain the system gain. R × VTH Decrease RG2 to RG2 = F to maintain system VS × Gain gain and decrease RG1 to (RG2 − RTH) to maintain balanced gain resistances. 301Ω +VS ADA4930 RL VOUT, dm The first compensation method is used in the Diff Amp Calculator™ tool. Using the second compensation method, RG2 = 160.498 Ω and RG1 = 160.498 − 26.66 = 133.837 Ω. The modified circuit is shown in Figure 49. RF1 301Ω +VS RTH VTH 1.066V p-p 26.661Ω RG1 133.837Ω VOCM RG2 160.498Ω –VS 301Ω 09209-056 RF2 Figure 46. Single-Ended Input Impedance RIN 2. Add a termination resistor, RT. To match the 50 Ω source resistance, RT is added. Because RT||401.33 Ω = 50 Ω, RT = 57.116 Ω. RF1 RIN 50Ω RS VS 2V p-p 50Ω RT 57.116 Ω RG1 301Ω VOCM RG2 301Ω –VS 301Ω 09209-054 ADA4930 RL VOUT, dm 301Ω +VS RF2 Figure 49. Thevenin Equivalent with Matched Gain Resistors ADA4930 RL VOUT, dm 5. RF2 Figure 47. Adding Termination Resistor RT 3. Replace the source-termination resistor combination with its Thevenin equivalent. The Thevenin equivalent of the source resistance RS and the termination resistance RT is RTH = RS||RT = 26.66 Ω. TheThevenin equivalent of the source voltage is RT VTH = VS = 1.066 V p-p RS + RT RS VS 2V p-p 50Ω RT 57.116 Ω VTH 1.066V p-p RTH 26.661Ω 09209-055 Figure 49 presents an easily manageable circuit with matched feedback loops that can be easily evaluated. The modified gain resistor, RG1, changes the input impedance. Repeat Step 1 through Step 4 several times using the modified value of RG1 from the previous iteration until the value of RT does not change from the previous iteration. After three additional iterations, the change in RG1 is less than 0.1%. The final circuit is shown in Figure 50 with the closest 0.5% resistor values. RF1 301Ω +VS RG RT 64.2Ω 142Ω VOCM RG2 169Ω 09209-057 0.998V p-p RS VS 2V p-p 50Ω VP ADA4930 VN RL VOUT, dm 1.990V p-p –VS RF2 301Ω Figure 48. Thevenin Equivalent Circuit Figure 50. Terminated Single-Ended-to-Differential System with G = 1 Rev. A | Page 20 of 28 ADA4930-1/ADA4930-2 Terminating a Single-Ended Input in a Single-Supply Applications When the application circuit of Figure 50 is powered by a single supply, the common-mode voltage at the amplifier inputs, VP and VN, may have to be raised to comply with the specified input common-mode range. Two methods are available: a dc bias on the source, as shown in Figure 51, or by connecting resistors RCM between each input and the supply, as shown on Figure 54. 3. To comply with the minimum specified input common-mode voltage of 0.3 V at VS = 3.3 V, set the minimum value of VP and VN to 0.3 V. Recognize that VP and VN are at their minimum values when VOP and VS are at their minimum (and therefore VON is at its maximum). Let VP min = VN min = 0.3 V, VOCM = VCM = 1 V, VTH min = −VTH/2 VON max = VOCM + VOUT, dm/4 and VOP min = VOCM − VOUT, dm/4 Substitute conditions into the nodal equation for VP and solve for VDC-TH. 0.3 = −1.124/2 + VDC-TH + 0.361 × (1 + 1.99/4 = 1.124/2 – VDC-TH) 0.3 + 0.562 − 0.361 − 0.18 − 0.203 = 0.639 VDC-TH VDC-TH = 0.186 V Or Substitute conditions into the nodal equation for VN and solve for VDC-TH. 0.3 = VDC-TH + 0.361 × (1 − 1.99/4 − VDC-TH) 0.3 – 0.361 + 0.18 = 0.639 × VDC-TH 09209-151 4. Input Common-Mode Adjustment with DC Biased Source To drive a 1.8 V ADC with VCM = 1 V, a 3.3 V single supply minimizes the power dissipation of the ADA4930-1/ADA4930-2. The application circuit of Figure 50 on a 3.3 V single supply with a dc bias added to the source is shown in Figure 51. RF1 301Ω 3.3V RS VS 2V p-p 50Ω RT 64.2Ω RG1 142Ω VOCM RG2 50Ω 64.2Ω 142Ω VN VP ADA4930 RL VOUT, dm 1.990V p-p VDC RF2 301Ω VDC-TH = 0.186 V 5. Converting VDC-TH from its Thevenin equivalent results in V DC = R S + RTH RTH × 0.186 = 0.33 V Figure 51. Single-Supply, Terminated Single-Ended-to-Differential System with G = 1 To determine the minimum required dc bias, the following steps must be taken: 1. Convert the terminated inputs to their Thevenin equivalents, as shown in the Figure 52 circuit. RF1 301Ω 3.3V RTH 28.11Ω VTH 1.124V p-p RG1 142Ω VOCM RTH 28.11Ω VDC-TH RG2 142Ω VN VOP VP VON The final application circuit is shown in Figure 53. The additional dc bias of 0.33 V at the inputs ensures that the minimum input common-mode requirements are met when the source signal is bipolar with a 2 V p-p amplitude and VOCM is at 1 V. RF1 301Ω ADA4930 RL VOUT, dm 1.99V p-p 3.3V RS VS 2V p-p 09209-159 RG1 RT 64.2Ω 142Ω VOCM RG2 VP 50Ω ADA4930 VN RL VOUT, dm 1.990V p-p RF2 301Ω 50Ω VDC 0.33V 64.2Ω 142Ω Figure 52. Thevenin Equivalent of Single-Supply Application Circuit RF2 09209-160 2. Write a nodal equation for VP or VN. V P = VTH + V DC −TH + 301 (VON − VTH − VDC −TH ) 301 + 142 + 28.11 301Ω Figure 53. Single-Supply Application Circuit with DC Source Bias V N = V DC −TH + 301 VOP 301 + 142 + 28.11 Recognize that while the ADA4930-1/ADA4930-2 is in its linear operating region, VP and VN are equal. Therefore, both equations in Step 2 give equal results. Rev. A | Page 21 of 28 ADA4930-1/ADA4930-2 Input Common-Mode Adjustment with Resistors The circuit shown in Figure 54 shows an alternate method to bias the amplifier inputs, eliminating the dc source. 3.3V VS RCM RF1 301Ω +VS RS VSOURCE 2V p-p 50Ω RT VIN RG1 301Ω VOCM RG2 301Ω –VS RCM VS 3.3V RF2 09209-152 Calculate the following: 1. 2. 3. 4. β1 and β2. For the circuit shown in Figure 54, β1 = 0.5 and β2 = 0.5. RCM for VP min = 0.3 V and VIN min = −0.5 V. RCM = 9933 Ω. The new values for β1 and β2. β1 = 0.4925 and β2 = 0.4925. The input impedance using the following: ADA4930 RL VOUT, dm RIN − SE ⎛ ⎜ 1 = RG1 ⎜ ⎜ 1 − VP ⎜V INP ⎝ ⎛ ⎞ ⎞ ⎜ ⎟ ⎟ β1 + β2 ⎜ ⎟ ⎟=R G1 ⎜ β1 + β2 − RF1 β1β2 ⎟ ⎟ ⎟ ⎜ ⎟ RG1 ⎠ ⎝ ⎠ 5. 6. 7. 8. 9. 301Ω Figure 54. Single-Supply Biasing Scheme with Resistors Define β1 = RP/RF1 and β2 = RN/RF2, where RP = RG1||RCM||RF1 and RN = RG2||RCM||RF2. Set RF1 = RF2 = RF to maintain a balanced system, as shown. Write a nodal equation at VP and solve for VP. VP = β1β2 ⎛ RF 2R ⎜ VIN + 2VOCM + VS F β1 + β2 ⎜ RG1 RCM ⎝ RIN-SE = 399.35 Ω. RT, RTH, and VTH. RT = 57.16 Ω, RTH = 26.67 Ω, and VTH = 1.067 V. The new values for RG1 and RG2. RG2 = 160.55 Ω and RG1 = 133.88 Ω. The new values for β1 and β2. β1 = 0.284 and β2 = 0.317. The new value of RCM. RCM = 4759.63 Ω. Repeat Step 3 through Step 8 until the values of RG1 and RG2 remain constant between iterations. After four iterations, the final circuit is shown in Figure 55. +VS RCM 1.87kΩ RF1 301Ω +VS RS VS 2V p-p 50Ω RT 65.1Ω RG1 142Ω VOCM RG2 170Ω –VS RCM 1.87kΩ +VS RF2 09209-153 ⎞ ⎟ ⎟ ⎠ Determine VP min. This is the minimum input common-mode voltage from the Specifications section. For a 3.3 V supply, VP min = 0.3 V. Determine the minimum input voltage, VIN min at the output of the source. Recognize that once properly terminated, the source voltage is ½ of its open circuit value. Therefore, VIN min = −0.5 V. Rearrange the VP equation for RCM 1 1 = RCM 2VS RF ADA4930 RL VOUT, dm 301Ω ⎛ β1 + β2 ⎞ RF ⎜ ⎟ ⎜ β1β2 VP min − R VIN min − 2VOCM ⎟ G1 ⎝ ⎠ Figure 55. Single-Supply, Single-Ended Input System with Bias Resistors Rev. A | Page 22 of 28 ADA4930-1/ADA4930-2 LAYOUT, GROUNDING, AND BYPASSING The ADA4930-1/ADA4930-2 are high speed devices. Realizing their superior performance requires attention to the details of high speed PCB design. The first requirement is to use a multilayer PCB with solid ground and power planes that cover as much of the board area as possible. Bypass each power supply pin directly to a nearby ground plane, as close to the device as possible. Use 0.1 μF high frequency ceramic chip capacitors. Provide low frequency bulk bypassing, using 10 μF tantalum capacitors from each supply to ground. Stray transmission line capacitance in combination with package parasitics can potentially form a resonant circuit at high frequencies, resulting in excessive gain peaking or possible oscillation. Signal routing should be short and direct to avoid such parasitic effects. Provide symmetrical layout for complementary signals to maximize balanced performance. Use radio frequency transmission lines to connect the driver and receiver to the amplifier. Minimize stray capacitance at the input/output pins by clearing the underlying ground and low impedance planes near these pins (see Figure 56). If the driver/receiver is more than one-eighth of the wavelength from the amplifier, the signal trace widths should be minimal. This nontransmission line configuration requires the underlying and adjacent ground and low impedance planes to be cleared near the signal lines. The exposed thermal paddle is internally connected to the ground pin of the amplifier. Solder the paddle to the low impedance ground plane on the PCB to ensure the specified electrical performance and to provide thermal relief. To reduce thermal impedance further, it is recommended that the ground planes on all layers under the paddle be connected together with vias. 1.30 0.80 1.30 0.80 09209-058 Figure 56. ADA4930-1 Ground and Power Plane Voiding in the Vicinity of RF and RG Figure 57. Recommended PCB Thermal Attach Pad Dimensions (Millimeters) 1.3 mm 0.8 mm TOP METAL GROUND PLANE POWER PLANE BOTTOM METAL Figure 58. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters) Rev. A | Page 23 of 28 09209-060 09209-059 ADA4930-1/ADA4930-2 HIGH PERFORMANCE ADC DRIVING The ADA4930-1/ADA4930-2 provide excellent performance in 3.3 V single-supply applications. The circuit shown in Figure 59 is an example of the ADA4930-1 driving an AD9255, 14-bit, 80 MSPS ADC that is specified to operate with a single 1.8 V supply. The performance of the ADC is optimized when it is driven differentially, making the best use of the signal swing available within the 1.8 V supply. The ADA4930-1 performs the single-ended-to-differential conversion, commonmode level shifting, and buffering of the driving signal. The ADA4930-1 is configured for a single-ended input to differential output with a gain of 2 V/V. The 84.5 Ω termination resistor, in parallel with the single-ended input impedance of 95.1 Ω, provides a 50 Ω termination for the source. The additional 31.6 Ω (95 Ω total) at the inverting input balances the parallel impedance of the 50 Ω source and the termination resistor that drives the noninverting input. The VOCM pin is connected to the VCM output of the AD9255 and sets the output common mode of the ADA4930-1 at 1 V. Note that a dc bias must be added to the signal source and its Thevenin equivalent to the gain resistor on the inverting side to ensure that the inputs of the ADA4930-1 are kept at or above the specified minimum input common-mode voltage at all times. The 0.5 V dc bias at the signal source and the 0.314 V dc bias on the gain resistor at the inverting input set the inputs of the ADA4930-1 to ~0.48 V dc. With 1 V p-p maximum signal swing at the input, the ADA4930-1 inputs swing between 0.36 V and 0.6 V. For a common-mode voltage of 1 V, each ADA4930-1 output swings between 0.501 V and 1.498 V, providing a 1.994 V p-p differential output. 301Ω 3.3V 50Ω VIN 1V p-p 0.5V 84.5Ω 63.4Ω VOCM 95Ω 0.314V 301Ω + 33Ω 30pF 33Ω 168nH 90pF VIN+ 168nH AGND VCM 09209-157 A third-order, 40 MHz, low-pass filter between the ADA4930-1 and the AD9255 reduces the noise bandwidth of the amplifier and isolates the driver outputs from the ADC inputs. The circuit shown in Figure 60 is an example of ½ of an ADA4930-2 driving ½ of an AD9640, a 14-bit, 80 MSPS ADC that is specified to operate with a single 1.8 V supply. The performance of the ADC is optimized when it is driven differentially, making the best use of the signal swing available within the 1.8 V supply. The ADA4930-2 performs the singleended-to-differential conversion, common-mode level shifting, and buffering of the driving signal. The ADA4930-2 is configured for a single-ended input to differential output with a gain of 2 V/V. The 88.5 Ω termination resistor, in parallel with the single-ended input impedance of 114.75 Ω, provides a 50 Ω termination for the source. The increased gain resistance at the inverting input balances the 50 Ω source resistance and the termination resistor that drives the noninverting input. The VOCM pin is connected to the CML output of the AD9640 and sets the output common mode of the ADA4930-2 at 1 V. The 739 Ω resistors between each input and the 3.3 V supply provide the necessary dc bias to guarantee compliance with the input common-mode range of the ADA4930-2. For a common-mode voltage of 1 V, each ADA4930-2 output swings between 0.501 V and 1.498 V, providing a 1.994 V p-p differential output. A third-order, 40 MHz, low-pass filter between the ADA4930-2 and the AD9640 reduces the noise bandwidth of the amplifier and isolates the driver outputs from the ADC inputs. 1.8V AVDD VIN– DRVDD D11 TO D0 ADA4930-1 AD9255 Figure 59. Driving an AD9255, 14-Bit, 80 MSPS ADC 3.3V 739Ω + 64.2Ω VOCM 96.2Ω 739Ω 3.3V 301Ω 168nH 301Ω 3.3V 50Ω 88.5Ω VIN 1V p-p 168nH AVDD VIN– VIN+ AGND CML 09209-158 1.8V DRVDD D11 TO D0 ADA4930-2 30pF 90pF AD9640 VOCM Figure 60. Driving an AD9640, 14-Bit, 80 MSPS ADC Rev. A | Page 24 of 28 ADA4930-1/ADA4930-2 OUTLINE DIMENSIONS 3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12° MAX 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 072208-A 24 1 0.60 MAX 0.50 0.40 0.30 PIN 1 INDICATOR *1.45 1.30 SQ 1.15 13 16 12 (BOTTOM VIEW) 1 EXPOSED PAD 9 8 5 4 0.25 MIN 1.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 61. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-2) Dimensions shown in millimeters 4.10 4.00 SQ 3.90 0.60 MAX 0.60 MAX 18 19 PIN 1 INDICATOR PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 13 6 7 2.44 2.34 SQ 2.24 TOP VIEW 0.70 MAX 0.65 TYP 0.50 0.40 0.30 12 0.20 MIN 2.50 BCS FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 08-18-2010-A 0.90 0.85 0.80 SEATING PLANE 12° MAX 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.05 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8 Figure 62. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-24-13) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADA4930-1YCPZ-R2 ADA4930-1YCPZ-RL ADA4930-1YCPZ-R7 ADA4930-1YCP-EBZ ADA4930-2YCPZ-R2 ADA4930-2YCPZ-RL ADA4930-2YCPZ-R7 ADA4930-2YCP-EBZ 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ Evaluation Board 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ Evaluation Board Package Option CP-16-2 CP-16-2 CP-16-2 CP-24-13 CP-24-13 CP-24-13 Ordering Quantity 250 5,000 1,500 250 5,000 1,500 Branding H1G H1G H1G Z = RoHS Compliant Part. Rev. A | Page 25 of 28 ADA4930-1/ADA4930-2 NOTES Rev. A | Page 26 of 28 ADA4930-1/ADA4930-2 NOTES Rev. A | Page 27 of 28 ADA4930-1/ADA4930-2 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09209-0-10/10(A) Rev. A | Page 28 of 28