16-Bit, 1 MSPS, 8-Channel
Data Acquisition System
ADAS3022-EP
Enhanced Product
FEATURES
Ease of use—16-bit, 1 MSPS complete data acquisition system
High impedance, 8-channel input: >500 MΩ
Differential input voltage range: ±24.576 V maximum
High input common-mode rejection: >100 dB
User-programmable input ranges
Channel sequencer with individual channel gains
On-chip 4.096 V reference and buffer
Auxiliary input—direct interface to PulSAR® ADC inputs
No latency or pipeline delay (SAR architecture)
Serial 4-wire, 1.8 V to 5 V SPI-/SPORT-compatible interface
40-Lead LFCSP package (6 mm × 6 mm)
ENHANCED FEATURES
Supports defense and aerospace applications (AQEC
standard)
Military temperature range (such as −55°C to +105°C)
Controlled manufacturing baseline
One assembly/test site
Enhanced product change notification
Qualification data available on request
an 8-channel, low leakage multiplexer; a high impedance
programmable gain instrumentation amplifier (PGIA) stage with
high common-mode rejection; a precision, low drift 4.096 V
reference and buffer; and a 16-bit charge redistribution analogto-digital converter (ADC) with a successive approximation
register (SAR) architecture. The ADAS3022-EP can resolve eight
single-ended inputs or four fully differential inputs up to
±24.576 V when using ±15 V supplies. In addition, the device
can accept the commonly used bipolar differential, bipolar
single-ended, pseudo bipolar, or pseudo unipolar input signals,
as shown in Table 1, thus enabling the use of almost any direct
sensor interface.
The ADAS3022-EP simplifies design challenges by eliminating
signal buffering, level shifting, amplification/attenuation,
common-mode rejection, settling time, and any other analog
signal conditioning challenge while allowing a smaller form
factor, faster time to market, and lower cost.
Additional application and technical information can be found
in the ADAS3022 data sheet.
APPLICATIONS
Table 1. Typical Input Range Selection
Multichannel data acquisition and system monitoring
Process controls
Power line monitoring
Automated test equipment
Instrumentation
Signal (V)
Differential
±1
±2.5
±5
±10
Single Ended
0 to 1
0 to 2.5
0 to 5
0 to 10
GENERAL DESCRIPTION
The ADAS3022-EP is a complete 16-bit, 1 MSPS, successive
approximation–based, analog-to-digital data acquisition system
that is manufactured on Analog Devices, Inc., proprietary iCMOS®
high voltage industrial process technology. The device integrates
Rev. 0
Input Range, VIN (V)
±1.28
±2.56
±5.12
±10.24
±1.28
±2.56
±5.12
±10.24
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADAS3022-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ......................................................... 10
Enhanced Features............................................................................ 1
ESD Caution................................................................................ 10
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions........................... 11
General Description ......................................................................... 1
Typical Performance Characteristics ........................................... 13
Revision History ........................................................................... 2
Outline Dimensions ....................................................................... 21
Functional Block Diagram .............................................................. 3
Ordering Guide .......................................................................... 21
Specifications..................................................................................... 4
Timing Specifications .................................................................. 8
REVISION HISTORY
6/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 21
Enhanced Product
ADAS3022-EP
FUNCTIONAL BLOCK DIAGRAM
VDDH
DIFF
PAIR
IN0/IN1
DIFF TO
COM
AVDD
DVDD
VIO
RESET
ADAS3022-EP
PD
CNV
LOGIC/
INTERFACE
IN0
BUSY
IN1
CS
IN2
IN3
IN4/IN5
IN4
PulSAR®
PGIA
MUX
DIN
IN5
IN6/IN7
SDO
IN6
IN7
COM
SCK
ADC
TEMP
SENSOR
REFIN
BUF
AUX+
REF
AUX–
VSSH
AGND
DGND
REFx
Figure 1.
Rev. 0 | Page 3 of 21
15983-001
IN2/IN3
ADAS3022-EP
Enhanced Product
SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%, VIO = 1.8 V to AVDD, internal voltage reference (VREF) =
4.096 V, sampling frequency (fS) = 1 MSPS unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUTS—IN[7:0], COM
Operating Input Voltage Range
Differential Input Voltage Range, VIN
Input Impedance, ZIN
Channel Off Leakage
Channel On Leakage
Common-Mode Voltage Range
(VCM) 2
Test Conditions/Comments
Min
16
VIN
VIN+ − VIN−
PGIA gain = 0.16, VIN = 49.15 V p-p
PGIA gain = 0.2, VIN = 40.96 V p-p
PGIA gain = 0.4, VIN = 20.48 V p-p
PGIA gain = 0.8, VIN = 10.24 V p-p
PGIA gain = 1.6, VIN = 5.12 V p-p
PGIA gain = 3.2, VIN = 2.56 V p-p
PGIA gain = 6.4, VIN = 1.28 V p-p
Transient Response
DC ACCURACY
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Transition Noise
Gain Error
Gain Error Temperature Drift
Max
Unit 1
Bits
−VSSH + 2.5
VDDH − 2.5
V
−6 × VREF
−5 × VREF
−2.5 × VREF
−1.25 × VREF
−0.625 × VREF
−0.3125 × VREF
−0.1563 × VREF
500
+6 × VREF
+5 × VREF
+2.5 × VREF
+1.25 × VREF
+0.625 × VREF
+0.3125 × VREF
+0.1563 × VREF
V
V
V
V
V
V
V
MΩ
nA
nA
−5.12
−7.68
−8.96
−9.60
−9.92
+5.12
+7.68
+8.96
+9.60
+9.92
V
V
V
V
V
−VREF
+VREF
V
0
0
0
0
1000
500
250
125
520
kSPS
kSPS
kSPS
kSPS
ns
+2
+3
+5
+1.0
+1.25
+1.25
Bits
LSB
LSB
LSB
LSB
LSB
LSB
+9
0.1
LSB
LSB
LSB
LSB
ppm/°C
±0.6
±0.02
VIN+, VIN−; full-scale differential inputs
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
ANALOG INPUTS—AUX+, AUX−
Differential Input Voltage Range
THROUGHPUT
Conversion Rate
Typ
One channel and one pair
Two channels and two pairs
Four channels and four pairs
Eight channels
Full-scale step
PGIA gain = 0.16, 0.2, 0.4, 0.8, and 1.6
PGIA gain = 3.2
PGIA gain = 6.4
PGIA gain = 0.16, 0.2, 0.4, 0.8, and 1.6
PGIA gain = 3.2
PGIA gain = 6.4
External reference
PGIA gain = 0.16, 0.2, 0.4, 0.8, and 1.6
PGIA gain = 3.2
PGIA gain = 6.4
External reference, all PGIA gains, TA = 25°C
External reference, all PGIA gains
Rev. 0 | Page 4 of 21
16
−2
−3
−5
−0.9
−0.9
−0.9
±0.6
±1.0
±1.5
±0.6
±0.75
±0.75
5
7
11
−9
Enhanced Product
Parameter
Offset Error
Offset Error Temperature Drift
Total Unadjusted Error
AC ACCURACY 3
Signal-to-Noise Ratio (SNR)
Signal-to-Noise-and-Distortion
(SINAD)
Dynamic Range
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range
(SFDR)
Channel to Channel Crosstalk
Common-Mode Rejection Ratio
(CMRR)
−3 dB Input Bandwidth
ADAS3022-EP
Test Conditions/Comments
External reference, TA = 25°C
PGIA gain = 0.16, 0.2, 0.4, and 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
External reference
PGIA gain = 0.16, 0.2, 0.4, and 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
External reference, ambient temperature
(TA) = 25°C
PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6, and 3.2
PGIA gain = 6.4
fIN = 10 kHz
PGIA gain = 0.16
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
Input frequency (fIN) = 10 kHz
PGIA gain = 0.16
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
fIN = 10 kHz, −60 dB input
PGIA gain = 0.16
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
fIN = 10 kHz, all PGIA gains
fIN = 10 kHz, all PGIA gains
Min
Typ
Max
Unit 1
−3.0
−4.0
−7.5
−12.5
+0.2
+0.2
+0.2
+0.2
+3.0
+4.0
+7.5
+12.5
LSB
LSB
LSB
LSB
0.1
0.2
0.4
0.8
0.5
1.0
2.0
4.0
ppm/°C
ppm/°C
ppm/°C
ppm/°C
+9
+15
LSB
LSB
−9
−15
90.0
90.0
89.5
89.0
88.0
86.0
83.0
91.5
91.5
91.5
91.0
89.7
86.8
84.5
dB
dB
dB
dB
dB
dB
dB
88.0
88.0
88.5
88.5
87.5
85.5
82.5
90.0
90.0
91.0
90.5
89.5
86.5
84.0
dB
dB
dB
dB
dB
dB
dB
91.0
91.0
90.5
90.0
89.0
86.0
83.5
92.0
92.0
91.5
91.0
90.0
87.0
85.0
−100
101
dB
dB
dB
dB
dB
dB
dB
dB
dB
−120
dB
110.0
105.0
98.0
98.0
8
dB
dB
dB
dB
MHz
fIN = 10 kHz, all channels inactive
fIN = 2 kHz
PGIA gain = 0.16, 0.2, 0.4, and 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
−40 dBFS
Rev. 0 | Page 5 of 21
90.0
90.0
90.0
90.0
ADAS3022-EP
Parameter
AUXILIARY ADC INPUT CHANNEL
DC Accuracy
Integral Nonlinearity Error
Differential Nonlinearity Error
Gain Error
Offset Error
AC Performance
SNR
SINAD
THD
SFDR
INTERNAL REFERENCE
REF1 and REF2 Output Voltage
REF1 and REF2 Output Current
REF1 and REF2 Temperature Drift
REF1 and REF2 Line Regulation
Internal Reference
Buffer Only
REFIN Output Voltage4
Turn-On Settling Time
EXTERNAL REFERENCE
Voltage Range
Current Drain
TEMPERATURE SENSOR
Output Voltage
Temperature Sensitivity
DIGITAL INPUTS
Logic Levels
Input Voltage Low, VIL
Input Voltage High, VIH
Input Low Current, IIL
Input High Current, IIH
DIGITAL OUTPUTS5
Data Format
Output Low Voltage, VOL
Output High Voltage, VOH
POWER SUPPLIES
VIO
AVDD
DVDD
VDDH6
VSSH6
Enhanced Product
Test Conditions/Comments
Min
Typ
Max
Unit1
−1.5
−0.8
−2.5
−5
±0.5
±0.6
±0.2
±0.2
+1.5
+1.0
+2.5
+5
LSB
LSB
LSB
LSB
90.0
89.5
93.0
92.5
−105
110
4.088
4.096
250
±5
±1
External reference
Internal reference
TA = 25°C
TA = 25°C
REFEN = 1
REFEN = 0
AVDD = 5 V ± 5%
TA = 25°C
CREFIN, CREF1, CREF2 = 10 μF and 0.1 μF
2.495
REFx input
REFIN input (buffered)
VREF = 4.096 V
4.000
TA = 25 °C
20
4
2.500
100
4.096
2.5
100
dB
dB
dB
dB
4.104
2.505
4.104
2.505
275
800
VIO > 3 V
VIO ≤ 3 V
VIO > 3 V
VIO ≤ 3 V
−0.3
−0.3
0.7 × VIO
0.9 × VIO
−1
−1
+0.3 × VIO
+0.1 × VIO
VIO + 0.3
VIO + 0.3
+1
+1
VIO − 0.3
VDDH > input voltage + 2.5 V
VSSH < input voltage − 2.5 V
Rev. 0 | Page 6 of 21
1.8
4.75
4.75
14.25
−15.75
5
5
15
−15
μV/V
μV/V
V
ms
V
V
μA
mV
μV/°C
Twos complement
0.4
ISINK = +500 μA
ISOURCE = −500 μA
PD = 0
V
μA
ppm/°C
ppm/°C
AVDD + 0.3
5.25
5.25
15.75
−14.25
V
V
V
V
μA
μA
V
V
V
V
V
V
V
Enhanced Product
Parameter
VDDH Capacitance, IVDDH
Current at VSSH Supply, IVSSH
Current at AVDD, IAVDD
Current at DVDD, IDVDD
Current at VIO, IVIO
Power Supply Sensitivity
At TA = 25°C
TEMPERATURE RANGE
Specified Performance
ADAS3022-EP
Test Conditions/Comments
PGIA gain = 0.16
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
All PGIA gains, PD = 1
PGIA gain = 0.16
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
All PGIA gains, PD = 1
PGIA gain = 6.4, reference buffer enabled
All other PGIA gains, reference buffer
enabled
PGIA gain = 6.4, reference buffer disabled
All other PGIA gains, reference buffer
disabled
All PGIA gains, PD = 1
All PGIA gains, PD = 0
All PGIA gains, PD = 1
VIO = 3.3 V, PD = 0
PD = 1
Min
−3.0
−3.0
−3.5
−5.5
−9.5
−17.5
−17.5
−55
1
Max
3.5
3.5
4.0
5.5
9.5
17.5
17.5
21.0
19.0
Unit1
mA
mA
mA
mA
mA
mA
mA
μA
mA
mA
mA
mA
mA
mA
mA
μA
mA
mA
14
12
17.5
16.0
mA
mA
100
2.5
10
0.30
10
External reference
PGIA gain = 0.16, 0.2, 0.4, and 0.8;
VDDH/VSSH ± 5%
PGIA gain = 3.2, VDDH/VSSH ± 5%
PGIA gain = 6.4, VDDH/VSSH ± 5%
PGIA gain = 0.16, AVDD/DVDD ± 5%
PGIA gain = 0.2, AVDD/DVDD ± 5%
PGIA gain = 0.4, AVDD/DVDD ± 5%
PGIA gain = 0.8, AVDD/DVDD ± 5%
PGIA gain = 1.6, AVDD/DVDD ± 5%
PGIA gain = 3.2, AVDD/DVDD ± 5%
PGIA gain = 6.4, AVDD/DVDD ± 5%
TMIN to TMAX
Typ
3.0
3.0
3.5
5.0
8.5
15.5
15.5
100
−2.5
−2.5
−3.0
−4.5
−8.0
−15
−15
10
18
16
3.5
1.2
μA
mA
μA
mA
μA
±0.5
LSB
±1.0
±2.0
±0.6
±0.8
±1.0
±1.5
±2.0
±3.5
±7.0
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
+105
°C
LSB means least significant bit and changes depending on the voltage range.
The common-mode voltage (VCM) for a PGIA gain of 0.16 or 0.2 is 0 V.
3
All ac accuracy specifications expressed in decibels are referred to a full-scale range (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise noted.
4
This is the output from the internal band gap reference.
5
There is no pipeline delay. Conversion results are available immediately after a conversion is complete.
6
The differential input common-mode voltage (VCM) range changes according to the maximum input range selected and the high voltage power supplies (VDDH and
VSSH). Note that the specified operating input voltage of any input pin requires 2.5 V of headroom from the VDDH and VSSH supplies; therefore, (VSSH + 2.5 V) ≤
INx/COM ≤ (VDDH − 2.5 V).
2
Rev. 0 | Page 7 of 21
ADAS3022-EP
Enhanced Product
TIMING SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%, VIO = 1.8 V to AVDD, internal reference, VREF = 4.096 V,
fS = 1 MSPS unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Time Between Conversions
Warp Mode, 1 CMS = 0
Normal Mode (Default), CMS = 1
Conversion Time: CNV Rising Edge to Data Available
Warp Mode, CMS = 0
Normal Mode (Default), CMS = 1
Auxiliary ADC Input Channel Acquisition Time
CNV Pulse Width
CNV High to Hold Time (Aperture Delay)
CNV High to Busy Delay
Safe Data Access Time During Conversion
Quiet Conversion Time (BUSY High)
Warp Mode, CMS = 0
Normal Mode (Default), CMS = 1
Data Access During Quiet Conversion Time
Warp Mode, CMS = 0
Normal Mode (Default), CMS = 1
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Valid
SCK Falling Edge to Data Valid Delay
VIO > 4.5 V
VIO > 3.0 V
VIO > 2.7 V
VIO > 2.3 V
VIO > 1.8 V
CS/RESET/PD Low to SDO
VIO > 4.5 V
VIO > 3.0 V
VIO > 2.7 V
VIO > 2.3 V
VIO > 1.8 V
CS/RESET/PD High to SDO High Impedance
DIN Valid Setup Time from SCK Rising Edge
DIN Valid Hold Time from SCK Rising Edge
CNV Rising to CS
RESET/PD High Pulse
1
Symbol
tCYC
Min
Typ
1
1.1
Max
Unit
1000
µs
µs
tCONV
825
925
tACQ
tCH
tAD
tCBD
tDDC
tQUIET
520
500
ns
ns
ns
ns
ns
ns
ns
400
500
ns
ns
200
300
ns
ns
ns
ns
ns
ns
12
18
24
25
37
ns
ns
ns
ns
ns
15
16
18
23
28
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1000
600
10
2
tDDCA
tSCK
tSCKL
tSCKH
tSDOH
tSDOD
15
5
5
4
tEN
tDIS
tDINS
tDINH
tCCS
tRH
Exceeding the maximum time has an effect on the accuracy of the conversion.
Rev. 0 | Page 8 of 21
4
4
5
5
Enhanced Product
ADAS3022-EP
Timing Diagrams
500µA
IOL
70% VIO
30% VIO
tDELAY
tDELAY
500µA
15983-002
CL
50pF
IOH
tCYC
EOC
EOC
SOC
POWER
UP
CONVERSION (n – 1)
UNDEFINED
0.8V OR 0.5V2
Figure 3. Voltage Levels for Timing
tACQ
PHASE
2V OR VIO – 0.5V1
0.8V OR 0.5V2
12V IF VIO > 2.5V; VIO – 0.5V IF VIO < 2.5V.
20.8V IF VIO > 2.5V; 0.5V IF VIO < 2.5V.
Figure 2. Load Circuit for Digital Interface Timing
SOC
2V OR VIO – 0.5V1
15983-003
1.4V
TO SDO
ACQUISITION (n)
UNDEFINED
tDDC
tQUIET
tDAC
NOTE 1
NOTE 2
NOTE 1
ACQUISITION (n + 1)
UNDEFINED
CONVERSION (n)
UNDEFINED
CONVERSION (n + 1)
UNDEFINED
CNV
BUSY
tDDCA
NOTE 5
NOTE 2
tAD
NOTE 4
CS
X
1
16/32
NOTE 3
SCK
1
16
DIN
CFG
INVALID
CFG (n + 2)
CFG (n + 2)
CFG (n + 3)
SDO
DATA
INVALID
DATA (n – 1)
INVALID
DATA (n – 1)
INVALID
DATA (n)
INVALID
EOC
EOC
ACQUISITION
(n + 2)
PHASE
DATA (n)
INVALID
EOC
ACQUISITION
(n + 3)
CONVERSION
(n + 2)
CFG (n + 3)
ACQUISITION
(n + 4)
CONVERSION
(n + 3)
CONVERSION
(n + 4)
CNV
BUSY
CS
1
16
1
16
1
DIN
CFG (n + 4)
CFG (n + 4)
CFG (n + 5)
CFG (n + 5)
CFG (n + 6)
CFG (n + 6)
SDO
DATA (n + 1)
INVALID
DATA (n + 1)
INVALID
DATA (n + 2)
DATA (n + 2)
DATA (n + 3)
DATA (n + 3)
NOTES
1. DATA ACCESS CAN OCCUR DURING A CONVERSION ( tDDC ), AFTER A CONVERSION (tDAC ), OR BOTH DURING AND AFTER A CONVERSION.
THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC).
2. DATA ACCESS CAN ALSO OCCUR UP TO tDDCA WHILE BUSY IS ACTIVE (SEE THE ADAS3022 DATA SHEET FOR DETAILS). ALL OF THE BUSY
TIME CAN BE USED TO ACQUIRE DATA.
3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO
READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION.
4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE.
5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME
OF THE APERTURE DELAY (tAD) SHOULD ELAPSE PRIOR TO DATA ACCESS.
Figure 4. General Timing Diagram
Rev. 0 | Page 9 of 21
15983-028
SCK
ADAS3022-EP
Enhanced Product
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Analog Inputs/Outputs
INx, COM to AGND
AUX+, AUX− to AGND
REFx to AGND
REFIN to AGND
REFN to AGND
Ground Voltage Differences
AGND, RGND, DGND
Supply Voltages
VDDH to AGND
VSSH to AGND
AVDD, DVDD, VIO to AGND
ACAP, DCAP, RCAP to GND
Digital Inputs/Outputs
CNV, DIN, SCK, RESET, PD, CS
to DGND
SDO, BUSY to DGND
Internal Power Dissipation
Junction Temperature
Storage Temperature Range
Thermal Impedance
θJA
θJC
Rating
VSSH − 0.3 V to VDDH + 0.3 V
−0.3 V to AVDD + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V
AGND − 0.3 V to +2.7 V
±0.3 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
±0.3 V
−0.3 V to +16.5 V
+0.3 V to −16.5 V
−0.3 V to +7 V
−0.3 V to +2.7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
2W
125°C
−65°C to +125°C
44.1°C/W
0.28°C/W
Rev. 0 | Page 10 of 21
Enhanced Product
ADAS3022-EP
40
39
38
37
36
35
34
33
32
31
AUX–
VDDH
VSSH
REFN
REFN
RGND
REF2
REF1
REFIN
RCAP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADAS3022-EP
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
NC
NC
AVDD
DVDD
ACAP
DCAP
AGND
AGND
DGND
DGND
NOTES
1. NC = NO CONNECT. THIS PIN IS NOT INTERNALLY CONNECTED.
2. CONNECT THE EXPOSED PADDLE TO VSSH.
15983-004
CS
DIN
RESET
NC
PD
SCK
VIO
SDO
BUSY
CNV
11
12
13
14
15
16
17
18
19
20
IN0 1
IN1 2
IN2 3
IN3 4
AUX+ 5
IN4 6
IN5 7
IN6 8
IN7 9
COM 10
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1 to 4
5
6 to 9
10
Mnemonic
IN0 to IN3
AUX+
IN4 to IN7
COM
Type1
AI
AI
AI
AI
11
CS
DI
12
DIN
DI
13
RESET
DI
14, 29, 30
15
NC
PD
N/A
DI
16
SCK
DI
17
VIO
P
18
SDO
DO
19
BUSY
DO
20
21, 22
23, 24
25
CNV
DGND
AGND
DCAP
DI
P
P
P
26
ACAP
P
Description
Input Channel 0 to Input Channel 3.
Auxiliary Input Channel Positive Input.
Input Channel 4 to Input Channel 7.
IN[7:0] Common Channel Input. The IN[7:0] input channels can be referenced to a common point. The
maximum voltage on this pin is ±10.24 V for all PGIA gains except for a PGIA gain of 0.16, in which case,
the maximum voltage on this pin is ±12.228 V. AUX+ and AUX− are not referenced to COM.
Chip Select. Active low signal. Enables the digital interface for writing and reading data. Use this pin
when sharing the serial bus. For a dedicated ADAS3022-EP serial interface, CS can be tied to DGND or
CNV to simplify the interface.
Data Input. Serial data input used for writing the 16-bit configuration word (CFG) that is latched on SCK
rising edges. CFG is an internal register that is updated on the rising edge of the end of a conversion, which is
the falling edge of BUSY. The configuration register can be written to during and after a conversion.
Asynchronous Reset. A low to high transition resets the ADAS3022-EP. The current conversion, if active,
is aborted and CFG is reset to the default state.
No Connect. This pin is not connected internally.
Power-Down. A low to high transition powers down the ADAS3022-EP, minimizing the bias current.
Note that this pin must be held high until the user is ready to power on the device; after powering on
the device, the user must wait 100 ms until the reference is enabled and then wait for the completion of
two dummy conversions before the device is ready to convert.
Serial Clock Input. The DIN and SDO data sent to and from the ADAS3022-EP are synchronized with
SCK.
Digital Interface Supply. Nominally, this supply is at the same voltage as the supply of the host
interface: 1.8 V, 2.5 V, 3.3 V, or 5 V.
Serial Data Output. The conversion result is output on this pin and is synchronized to SCK falling edges.
The conversion result is output in twos complement format.
Busy Output. An active high signal on this pin indicates that a conversion is in process. Reading or
writing data during the quiet conversion phase (tQUIET) may cause incorrect bit decisions.
Convert Input. A conversion is initiated on the rising edge of this pin.
Digital Ground. Connect these pins to the system digital ground plane.
Analog Ground. Connect these pins to the system analog ground plane.
Internal 2.5 V Digital Regulator Output. Decouple this internally regulated output using a 10 μF
capacitor and a 0.1 μF local capacitor.
Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal ADC core and all
of the supporting analog circuits with the exception of the internal reference. Decouple this internally
regulated output using a 10 μF capacitor and a 0.1 μF local capacitor.
Rev. 0 | Page 11 of 21
ADAS3022-EP
Enhanced Product
Pin No.
27
28
31
Mnemonic
DVDD
AVDD
RCAP
Type1
P
P
P
32
REFIN
AI/O
33, 34
REF1, REF2
AI/O
35
36, 37
RGND
REFN
P
P
38
VSSH
P
39
VDDH
P
40
AUX−
EPAD
AI
Description
Digital 5 V Supply. Decouple this supply using a 10 μF capacitor and a 0.1 μF local capacitor.
Analog 5 V Supply. Decouple this supply using a 10 μF capacitor and a 0.1 μF local capacitor.
Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal reference.
Decouple this pin using a 1 μF capacitor connected to RCAP and a 0.1 μF local capacitor.
Internal 2.5 V Band Gap Reference Output, Reference Buffer Input, or Reference Power-Down Input. See
the Voltage Reference Input/Output section of the ADAS3022 data sheet for more information.
Reference Input/Output. Regardless of the reference method, these pins need individual decoupling
using external 10 μF ceramic capacitors connected as close to REF1, REF2, and REFN as possible. REF1
and REF2 must be tied together externally.
Reference Supply Ground. Connect this pin to the system analog ground plane.
Reference Input/Output Ground. Connect the 10 μF capacitors on REF1 and REF2 to these pins, and
connect these pins to the system analog ground plane.
High Voltage Analog Negative Supply. Nominally, the supply of this pin should be −15 V. Decouple this
pin using a 10 μF capacitor and a 0.1 μF local capacitor.
High Voltage Analog Positive Supply. Nominally, the supply of this pin should be +15 V. Decouple this
pin using a 10 μF capacitor and a 0.1 μF local capacitor.
Auxiliary Input Channel Negative Input.
Exposed Paddle. Connect the exposed paddle to VSSH.
1
AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, N/A = not applicable, and P = power.
Rev. 0 | Page 12 of 21
Enhanced Product
ADAS3022-EP
TYPICAL PERFORMANCE CHARACTERISTICS
VDDH = 15 V, VSSH = −15 V, AVDD = DVDD = 5 V, VIO = 1.8 V to AVDD, unless otherwise noted.
2.0
1.00
GAIN = 0.16, 0.2, 0.4, 0.8, AND 1.6
INL MAX = +0.649
INL MIN = –0.592
FOR ALL GAINS
0.75
0.50
0.5
0.25
0
–0.5
–0.25
–1.0
–0.50
–1.5
–0.75
–2.0
0
8192
16384
24576
32768
40960
49152
57344 65536
CODE
–1.00
0
8192
16384
24576
32768
40960
49152
57344 65536
CODE
Figure 9. Differential Nonlinearity (DNL) vs. Code for All PGIA Gains
Figure 6. Integral Nonlinearity (INL) vs. Code,
PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6
400,000
2.0
GAIN = 3.2
INL MAX = +1.026
INL MIN = –0.948
1.5
GAIN = 0.16, 0.2, 0.4, 0.8, 1.6
350,000
300,000
0.5
250,000
COUNT
1.0
0
300,200
200,000
152,600
CODE
0
6,400
600
CODE IN HEX
Figure 10. Histogram of a DC Input at Code Center,
PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6
Figure 7. Integral Nonlinearity vs. Code, PGIA Gain = 3.2
400,000
2.0
GAIN = 6.4
INL MAX = +0.558
INL MIN = –1.319
GAIN = 3.2
350,000
300,000
0.5
250,000
213,200
200,000
50,000
–2.0
0
25,500
CODE
1,600
8003
57344 65536
8002
49152
8001
40960
8000
32768
7FFF
24576
7FFE
16384
7FFD
8192
7FFC
0
15983-106
22,700
1,400
CODE IN HEX
Figure 11. Histogram of a DC Input at Code Center, PGIA Gain = 3.2
Figure 8. Integral Nonlinearity vs. Code, PGIA Gain = 6.4
Rev. 0 | Page 13 of 21
15983-119
–1.5
129,000
118,400
8009
–1.0
100,000
8008
150,000
8007
–0.5
8006
0
8005
COUNT
1.0
8004
1.5
INL (LSB)
15983-117
57344 65536
8009
49152
8008
40960
8007
32768
8006
24576
8005
16384
8004
8192
8003
0
8002
–2.0
52,300
8001
50,000
8000
–1.5
7FFF
100,000
7FFE
–1.0
7FFD
150,000
7FFC
–0.5
15983-105
INL (LSB)
0
15983-108
DNL (LSB)
1.0
15983-101
INL (LSB)
1.5
ADAS3022-EP
Enhanced Product
400,000
100
EXTERNAL REFERENCE
GAIN = 6.4
fS = 1000kSPS
GAIN = 6.4
90
350,000
80
300,000
70
COUNT
COUNT
250,000
200,000
157,300
151,900
150,000
60
50
40
30
82,000
75,100
20
50,000
21,700
0
0
15983-120
8009
8008
8007
8006
8005
8004
8003
8002
8001
8000
7FFF
7FFE
7FFD
7FFC
10
18,400
2,400 100
200 300
0
CODE IN HEX
0.4
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
OFFSET DRIFT (ppm/°C)
Figure 15. Offset Drift, PGIA Gain = 6.4
Figure 12. Histogram of a DC Input at Code Center, PGIA Gain = 6.4
100
120
112
EXTERNAL REFERENCE
GAIN = 0.16, 0.2, 0.4, 0.8, AND 1.6
fS = 1000kSPS
90
fS = 1000kSPS
EXTERNAL 2.5V REFERENCE
INTERNAL BUFFER
100
80
70
80
60
COUNT
COUNT
0.8
15983-157
100,000
50
72
60
40
40
30
23
20
20
10
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
OFFSET DRIFT (ppm/°C)
0
15983-155
0
0
1
2
3
4
5
6
7
8
REFERENCE BUFFER DRIFT (ppm/°C)
9
10
15983-140
2
0
Figure 16. Reference Buffer Drift, External 2.5 V Reference
Figure 13. Offset Drift, PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6
120
100
fS = 1000kSPS
EXTERNAL REFERENCE
GAIN = 3.2
fS = 1000kSPS
90
INTERNAL 2.5V REFERENCE
INTERNAL BUFFER
100
80
80
COUNT
60
50
60
46
40
38
40
35
30
30
20
20
15
15
11
10
10
6
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
OFFSET DRIFT (ppm/°C)
1.8
2.0
0
0
1
2
3
4
5
6
7
8
9
1
10 11 12 13 14 15
REFERENCE BUFFER DRIFT (ppm/°C)
Figure 17. Reference Buffer Drift, Internal 2.5 V Reference
Figure 14. Offset Drift, PGIA Gain = 3.2
Rev. 0 | Page 14 of 21
15983-141
2
0
15983-156
COUNT
70
Enhanced Product
ADAS3022-EP
0
0
–60
–40
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
–180
0
100
200
300
400
500
FREQUENCY (kHz)
–180
15983-121
0
300
400
500
Figure 21. 10 kHz FFT, PGIA Gain = 0.8
0
GAIN = 0.2
fS = 1000kSPS
fIN = 10.1kHz
SNR = 91.4dB
SINAD = 89.9dB
THD = –94.7dB
SFDR = 94.8dB
–40
–60
–40
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
100
200
300
400
500
FREQUENCY (kHz)
–180
15983-122
–180
0
GAIN = 1.6
fS = 1000kSPS
fIN = 10.1kHz
SNR = 89.8dB
SINAD = 89.7dB
THD = –106dB
SFDR = 107dB
–20
AMPLITUDE (dBFS)
–20
0
100
200
300
400
500
FREQUENCY (kHz)
Figure 19. 10 kHz FFT, PGIA Gain = 0.2
15983-125
0
AMPLITUDE (dBFS)
200
FREQUENCY (kHz)
Figure 18. 10 kHz FFT, PGIA Gain = 0.16
Figure 22. 10 kHz FFT, PGIA Gain = 1.6
0
0
GAIN = 0.4
fS = 1000kSPS
fIN = 10.1kHz
SNR = 91.2dB
SINAD = 91.0dB
THD = –103dB
SFDR = 104dB
–40
–60
–40
–80
–100
–120
–60
–80
–100
–120
–140
–160
–160
–180
100
200
300
400
FREQUENCY (kHz)
500
15983-123
–140
0
GAIN = 3.2
fS = 1000kSPS
fIN = 10.1kHz
SNR = 87.6dB
SINAD = 87.5dB
THD = –105dB
SFDR = 106dB
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
100
Figure 20. 10 kHz FFT, PGIA Gain = 0.4
–180
0
100
200
300
400
FREQUENCY (kHz)
Figure 23. 10 kHz FFT, PGIA Gain = 3.2
Rev. 0 | Page 15 of 21
500
15983-126
AMPLITUDE (dBFS)
–40
GAIN = 0.8
fS = 1000kSPS
fIN = 10.1kHz
SNR = 90.7dB
SINAD = 90.6dB
THD = –107dB
SFDR = 106dB
–20
AMPLITUDE (dBFS)
–20
15983-124
GAIN = 0.16
fS = 1000kSPS
fIN = 10.1kHz
SNR = 91.7dB
SINAD = 89.2dB
THD = –92.5dB
SFDR = 92.5dB
ADAS3022-EP
Enhanced Product
–55
0
–20
–60
–65
–70
–75
–80
THD (dB)
AMPLITUDE (dBFS)
–40
GAIN = 0.4,
GAIN = 0.8,
GAIN = 1.6,
GAIN = 3.2,
GAIN = 0.4,
GAIN = 0.8,
GAIN = 1.6,
GAIN = 3.2,
–60
GAIN = 6.4
fS = 1000kSPS
fIN = 10.1kHz
SNR = 85.7dB
SINAD = 85.6dB
THD = –101dB
SFDR = 103dB
–80
–100
–0.5dBFS
–0.5dBFS
–0.5dBFS
–0.5dBFS
–10dBFS
–10dBFS
–10dBFS
–10dBFS
–85
–90
–95
–100
–120
–105
–140
–110
–115
–160
100
200
400
300
500
FREQUENCY (kHz)
–125
15983-127
0
10
1
100
1000
FREQUENCY (kHz)
Figure 24. 10 kHz FFT, PGIA Gain = 6.4
15983-304
–120
–180
Figure 27. THD vs. Frequency
–60
100
INTERNAL REFERENCE
CHANNEL 4 TO COM, SEQUENCER DISABLED
VIN = –0.5dBFS ON CHANNEL 0 TO CHANNEL 3,
CHANNEL 5 TO CHANNEL 7
fS = 1000kSPS
–70
95
–80
CROSSTALK (dB)
85
80
75
70
1
–0.5dBFS
–0.5dBFS
–0.5dBFS
–0.5dBFS
–10dBFS
–10dBFS
–10dBFS
–10dBFS
10
–90
–100
–110
–120
–130
100
1000
FREQUENCY (kHz)
–140
0
20
40
60
80
100
120
180
200
Figure 28. Crosstalk vs. Frequency
Figure 25. SNR vs. Frequency
100
130
GAIN = 0.16
GAIN = 0.20
GAIN = 0.40
GAIN = 0.80
GAIN = 1.60
GAIN = 3.20
GAIN = 6.40
95
120
90
110
CMRR (dB)
80
75
70
GAIN = 0.4, –0.5dBFS
GAIN = 0.8, –0.5dBFS
GAIN = 1.6, –0.5dBFS
GAIN = 3.2, –0.5dBFS
GAIN = 0.4, –10dBFS
GAIN = 0.8, –10dBFS
GAIN = 1.6, –10dBFS
GAIN = 3.2, –10dBFS
60
55
50
1
10
90
80
COMMON-MODE AMPLITUDE = 20.48V p-p
INTERNAL REFERENCE
fS = 1000kSPS
70
100
FREQUENCY (kHz)
1000
15983-302
65
100
60
1
10
100
1k
FREQUENCY (Hz)
Figure 29. CMRR vs. Frequency
Figure 26. SINAD vs. Frequency
Rev. 0 | Page 16 of 21
10k
100k
15983-139
85
SINAD (dB)
160
140
FREQUENCY (kHz)
15983-300
GAIN = 0.4,
GAIN = 0.8,
GAIN = 1.6,
GAIN = 3.2,
GAIN = 0.4,
GAIN = 0.8,
GAIN = 1.6,
GAIN = 3.2,
15983-303
SNR (dB)
90
Enhanced Product
ADAS3022-EP
–55
PSRR VDDH
AVDD, GAIN = 0.2
AVDD, GAIN = 3.2
20
PSRR VSSH
AVDD, GAIN = 1.6
AVDD, GAIN = 6.4
GAIN = 0.2
GAIN = 1.6
–60
AVDD CURRENT (mA)
–65
–70
–75
–80
–85
–90
GAIN = 0.8
GAIN = 6.4
16
14
12
0.1
1
10
100
FREQUENCY (kHz)
10
10
Figure 30. Power Supply Rejection Ration (PSRR) vs. Frequency
GAIN = 0.2
GAIN = 1.6
Figure 33. AVDD Current vs. Throughput, Internal Reference
15
GAIN = 0.8
GAIN = 6.4
GAIN = 0.4
GAIN = 3.2
GAIN = 0.2
GAIN = 1.6
18
GAIN = 0.8
GAIN = 6.4
GAIN = 0.4
GAIN = 3.2
AVDD CURRENT (mA)
14
17
16
15
14
13
12
11
10
4.8
4.9
5.0
5.1
5.2
5.3
AVDD SUPPLY (V)
9
15983-130
13
4.7
1000
10
100
1000
THROUGHPUT (kSPS)
Figure 31. AVDD Current vs. AVDD Supply, Internal Reference
15983-135
19
100
THROUGHPUT (kSPS)
15983-134
–95
–100
0.01
AVDD CURRENT (mA)
GAIN = 0.4
GAIN = 3.2
18
15983-301
POWER SUPPLY REJECTION RATIO (dB)
–50
Figure 34. AVDD Current vs. Throughput, External Reference
15
4.5
GAIN = 0.2
GAIN = 1.6
4.0
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
14
DVDD CURRENT (mA)
13
12
3.0
2.5
2.0
1.5
11
10
4.7
4.8
GAIN = 0.4
GAIN = 3.2
4.9
GAIN = 0.8
GAIN = 6.4
5.0
5.1
1.0
5.2
5.3
AVDD SUPPLY (V)
Figure 32. AVDD Current vs. AVDD Supply, External Reference
0.5
10
100
THROUGHPUT (kSPS)
Figure 35. DVDD Current vs. Throughput
Rev. 0 | Page 17 of 21
1000
15983-136
GAIN = 0.2
GAIN = 1.6
15983-131
AVDD CURRENT (mA)
3.5
ADAS3022-EP
Enhanced Product
0
18
GAIN = 0.2
GAIN = 1.6
fS = 1000kSPS
GAIN = 0.8
GAIN = 6.4
GAIN = 0.4
GAIN = 3.2
–2
–4
VSSH CURRENT (mA)
VDDH CURRENT (mA)
15
12
9
6
–6
–8
–10
–12
–14
–16
3
100
1000
THROUGHPUT (kSPS)
15983-137
10
–20
–50 –40 –30 –20 –10
10
20
30
40
50
GAIN = 0.8
GAIN = 6.4
70
60
90
80
Figure 39. VSSH Current vs. Temperature
19.5
0
fS = 1000kSPS
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
19.0
AVDD CURRENT (mA)
–3
–6
–9
–12
–15
17.5
17.0
16.5
GAIN = 0.8
GAIN = 6.4
–18
10
18.0
100
1000
THROUGHPUT (kSPS)
16.0
–50 –40 –30 –20 –10
18
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
10
20
30
40
50
70
60
80
90
Figure 40. AVDD Current vs. Temperature
Figure 37. VSSH Current vs. Throughput
20
0
TEMPERATURE (°C)
15983-144
GAIN = 0.4
GAIN = 3.2
15983-138
GAIN = 0.2
GAIN = 1.6
18.5
1.0
GAIN = 0.8
GAIN = 6.4
0.9
fS = 1000kSPS
VIO = 3.3V
fS = 1000kSPS
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
0.8
DVDD CURRENT (mA)
16
14
12
10
8
6
0.7
0.6
0.5
0.4
0.3
0.2
2
0.1
0
–50 –40 –30 –20 –10
0
10
20
30
40
50
60
TEMPERATURE (°C)
70 80
90
15983-142
4
0
–50 –40 –30 –20 –10
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
Figure 41. DVDD Current vs. Temperature
Figure 38. VDDH Current vs. Temperature
Rev. 0 | Page 18 of 21
80
90
15983-146
VSSH CURRENT (mA)
0
GAIN = 0.4
GAIN = 3.2
TEMPERATURE (°C)
Figure 36. VDDH Current vs. Throughput
VDDH CURRENT (mA)
GAIN = 0.2
GAIN = 1.6
15983-143
–18
0
Enhanced Product
ADAS3022-EP
5
4.00
fS = 1000kSPS
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
4
3.75
3
GAIN ERROR (LSB)
VIO CURRENT (mA)
3.50
3.25
3.00
2.75
2
GAIN = 0.16
GAIN = 0.2
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
fS = 1000kSPS
EXTERNAL REFERENCE
1
0
–1
–2
2.50
–3
2.25
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
–5
–50 –40 –30 –20 –10
15983-145
0
50
60
70
80
90
70
80
90
70
80
90
Figure 45. Gain Error vs. Temperature
Figure 42. VIO Current vs. Temperature
12
100
fS = 1000kSPS
GAIN = 0.16
GAIN = 0.2
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
96
94
8
OFFSET ERROR (LSB)
98
SNR (dB)
0 10 20 30 40
TEMPERATURE (°C)
15983-149
–4
2.00
–50 –40 –30 –20 –10
92
90
88
86
84
GAIN = 0.16
GAIN = 0.2
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
fS = 1000kSPS
EXTERNAL REFERENCE
4
0
–4
–8
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
–12
–50 –40 –30 –20 –10
15983-147
80
–50 –40 –30 –20 –10
Figure 43. SNR vs. Temperature
–85
–90
20
30
40
50
60
5
GAIN = 0.16
GAIN = 0.2
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
fS = 1000kSPS
4
EXTERNAL REFERENCE
3
2
–95
–100
–105
GAIN ERROR
1
0
–1
OFFSET ERROR
–2
–110
–3
–115
0
10
20
30
40
50
TEMPERATURE (°C)
Figure 44. THD vs. Temperature
60
70
80
90
–5
–50 –40 –30 –20 –10
0
10
20
30
40
TEMPERATURE (°C)
50
60
15983-151
–4
–120
–50 –40 –30 –20 –10
15983-148
THD (dB)
10
Figure 46. Offset Error vs. Temperature
ERROR (LSB)
–80
0
TEMPERATURE (°C)
15983-150
82
Figure 47. Offset and Gain Errors of the AUX +/AUX− ADC Channel Pair vs.
Temperature
Rev. 0 | Page 19 of 21
ADAS3022-EP
Enhanced Product
5200
5000
4800
4600
4400
4200
4000
3800
3400
–50 –40 –30 –20 –10
0
10
20
30
40
50
60
70
90
80
TEMPERATURE (°C)
20
16
10
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.5dBFS
–3.5
–4.5
10k
GAIN = 0.4
GAIN = 1.6
GAIN = 6.4
100k
1M
FREQUENCY (Hz)
10M
15983-153
NORMALIZED CLOSED-LOOP GAIN (dB)
fS = 1000kSPS
GAIN = 0.2
GAIN = 0.8
GAIN = 3.2
12
8
5
4
0
0
100
200
300
400
500
600
700
800
900
0
1000
THROUGHPUT (kSPS)
Figure 50. Temperature Sensor Output Error vs. Throughput
0
–4.0
24
15
Figure 48. Temperature Sensor Output Code vs. Temperature
0.5
28
20
15983-152
3600
TA = 25°C
INTERNAL REFERENCE
Figure 49. Large Signal Frequency Response vs. Gain
Rev. 0 | Page 20 of 21
TEMPERATURE SENSOR OUTPUT ERROR (°C)
TEMP SENSOR OUTPUT CODE (LSB)
5400
32
25
15983-154
TEMPERATURE SENSOR OUTPUT ERROR (mV)
5600
Enhanced Product
ADAS3022-EP
OUTLINE DIMENSIONS
0.30
0.25
0.18
40
31
30
1
0.50
BSC
TOP VIEW
1.00
0.95
0.85
0.45
0.40
0.35
11
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*4.70
4.60 SQ
4.50
EXPOSED
PAD
21
PIN 1
INDICATOR
10
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5
WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.
11-22-2013-B
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.95 mm Package Height
(CP-40-15)
Dimensions shown in millimeters
(See the ADAS3022 Data Sheet for Additional Information)
ORDERING GUIDE
Model1
ADAS3022SCPZ-EP
ADAS3022SCPZ-EP-RL
EVAL-ADAS3022EDZ
1
Temperature Range
−55°C to +105°C
−55°C to +105°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15983-0-6/17(0)
Rev. 0 | Page 21 of 21
Package Option
CP-40-15
CP-40-15
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