ADATE205

250 MHz Dual DCL ADATE205 FEATURES Driver, comparator, and active load 250 MHz toggle rate Inhibit mode function Dynamic clamps Operating voltage range: −1.5 V to +6.5 V Output voltage swing: 200 mV to 8 V Four range adjustable slew rate True/complement data mode bit 100-lead thin quad flat package, exposed pad Low per channel power 1.15 W with load off 1.50 W with load programmed at 20 mA nominal Low leakage ( 1.0 V, IOL = 0 mA to 35 mA Slope of line between 5 mA and 30 mA IOH and IOL programmed at 20 mV (200 μA) Relative to a line from 5 mA to 30 mA; IOL, IOH from 200 μA to 35 mA Measured at IOH, IOL = 30 mA IOL, IOH = 20 mA, VCOM = 0 V VCOM = −1.5 V to +6.5 V IOL, IOH = 20 mA, VCOM = −1.5 V to +6.5 V IOL, IOH = 20 mA, VCOM = −1.5 V to +6.5 V, relative to a line at 0 V and 5 V V TT = 2 V, VCOM = 4 V/0 V, IOL = 20 mA, IOH = 20 mA V TT = 2 V, VCOM = 4 V/0 V, IOL = 20 mA, IOH = 20 mA Driver = INH, VDUT swept from −1.5 V to +6.5 V Driver = INH, VDUT swept from −1.5 V to +6.5 V 9.5 −200 −50 10 10.5 +200 +50 mA/V μA μA Output Current Tempco, IOH, IOLT VCOM Buffer (Through Bridge) VCOM Buffer Offset VCOM Buffer Bias Current VCOM Buffer Gain VCOM Buffer Linearity Error ±3 10 −10 0.99 −10 3 +1 1 +1 10 +10 1.01 +10 μA/C mV μA V/V mV Dynamic Performance Propagation Delay—IMAX to INHIBIT INHIBIT to IMAX TOTAL FUNCTION Output Leakage Current Output Leakage Current, Low Leakage Mode Output Capacitance Power Supplies 5 Total Supply Range Positive Supply, VCC Negative Supply, VEE Positive Supply Current, VCC Negative Supply Current, VEE Total Power Dissipation Positive Supply Current Load Disabled, VCC Negative Supply Current Load Disabled, VEE Total Power Dissipation Temperature Sensor Gain Factor 1 2 2.3 2.3 ns ns −1.5 −200 +0.28 +10 2 +1.5 +200 μA nA pF 9.75 −5.25 160 210 2 115 160 1.3 10.0 −5.0 180 240 3 135 190 2.3 10 15.5 10.25 −4.75 205 270 4 170 220 2.8 V V V mA mA W mA mA W mV/°C Load enabled at 20 mA, driver is set to VIL = 0 V Load enabled at 20 mA, driver is set to VIL = 0 V Load enabled at 20 mA, driver is set to VIL = 0 V Load enabled at 0 mA, driver is set to VIL = 0 V Load enabled at 0 mA, driver is set to VIL = 0 V Load enabled at 0 mA, driver is set to VIL = 0 V Five diodes in series 1 μs period, pulse width = 50 ns to 500 ps, pulse width measured when amplitude drops 10%. Measured at 50% of input amp to 50% of output amp. 3 tPD measured from the 50% of enable signal to 50% of output. 4 The low leakage mode of the comparator, controlled by VLLM input, reduces the leakage due to the comparator input. The comparator operates in this mode, but its bandwidth is compromised and is not guaranteed. 5 Under no circumstances should the input voltages exceed the supply voltages. Rev. 0 | Page 7 of 16 ADATE205 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Current for VCC Maximum Current for VEE Positive Supply Voltage (VCC to GND) Negative Supply Voltage (VEE to GND) Operating Temperature (Junction) Storage Temperature Range ESD (Human Body Model) Rating 205 mA 270 mA +10.5 V −5.5 V +150°C −65°C to +150°C ±1500 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 8 of 16 ADATE205 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND/SHIELDS GND/SHIELDS GND/SHIELDS GND/SHIELDS CVH_1 CVH_2 DUT_1 DUT_2 CVL_1 CVL_2 TEMP GND GND GND GND GND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VCOM_1 GNDREF_1 VIOH_1 VIOL_1 GND D_INV_1 VIT_1 VIL_1 VIH_1 GND VCC VCC VCC VCC VCC VEE VEE VEE 1 2 3 4 5 6 7 8 9 PIN 1 75 74 73 72 71 70 69 68 VCOM_2 GNDREF_2 VIOH_2 VIOL_2 GND D_INV_2 VIT_2 VIL_2 VIH_2 CLAMPH_2 CLAMPL_2 GND CLLM_2 LDEN_2 VTEN_2 VEE VEE VCC VCC GND GND DR_DATA_P_2 DR_DATA_P_T_2 DR_DATA_N_T_2 DR_DATA_N_2 CLAMPL_1 10 CLAMPH_1 11 GND 12 CLLM_1 13 LDEN_1 14 VTEN_1 15 VEE 16 VEE 17 VCC 18 VCC 19 GND 20 GND 21 DR_DATA_P_1 22 DR_DATA_P_T_1 23 DR_DATA_N_T_1 24 DR_DATA_N_1 25 ADATE205 TOP VIEW (Not to Scale) 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SLEW1 SLEW0 VEE GND GND VEE NC COMP_L_P_1 COMP_L_N_1 COMP_H_P_1 COMP_L_N_2 COMP_L_P_2 CMOS_VDD COMP_H_N_1 COMP_H_N_2 COMP_H_P_2 DR_EN_P_1 NC DR_EN_P_T_1 DR_EN_N_T_1 DR_EN_N_T_2 DR_EN_P_T_2 DR_EN_N_1 DR_EN_N_2 DR_EN_P_2 Figure 2. Pin Configuration Rev. 0 | Page 9 of 16 05737-002 ADATE205 Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5, 12, 20, 21, 36, 40, 55, 56, 64, 71, 76, 79, 83, 93, 97, 100 6 7 8 9 10 11 13 14 15 16, 17, 33, 43, 59, 60, 84, 87, 92 18 19, 57, 58, 77, 78, 89, 98, 99 22 23 24 25 26 Mnemonic VCOM_1 GNDREF_1 VIOH_1 VIOL_1 GND Description Commutation Reference Voltage. Reference GND for VIOL, VIOH. Program Voltage for IOH (Sink). Program Voltage for IOL (Source). Device Ground. D_INV_1 VIT_1 VIL_1 VIH_1 CLAMPL_1 CLAMPH_1 CLLM_1 LDEN_1 V TEN_1 VEE VCC DR_DATA_P_1 DR_DATA_P_T_1 DR_DATA_N_T_1 DR_DATA_N_1 DR_EN_P_1 Driver Invert. Driver Term Voltage Reference. Driver Low Voltage Reference. Driver High Voltage Reference. Low Clamp. High Clamp. Comparator Low Leakage Mode. Determines Whether LD Responds to DR_EN_1 or is Disabled (see Table 4). Low Speed Control Signal. When high, DR_EN_1 forces driver output to VIT. Otherwise, DR_EN_1 forces driver to High Impedance (see Table 4). Negative Power Supply. Positive Power Supply. High Speed Data Inputs. Sets high/low state of driver output (see Table 4). Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the appropriate signal. Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the appropriate signal. Complement of DR_DATA_P_1. High Speed Enable Inputs. Multifunction depending on status of VTEN_1 and LDEN_1. Causes driver to enter/leave inhibit; driver to enter/leave termination mode; load to leave/enter inhibit (see Table 4). Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the appropriate signal. Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the appropriate signal. Complement of DR_EN_P_1. No Connect. High Comparator Outputs. Complement of COMP_H_P_1. Low Comparator Outputs. Complement of COMP_L_P_1. Logic Signals Controlling Driver Slew Rates for Both Drivers. 00 codes for maximum slew voltage; 11 codes for minimum slew voltage. CMOS Supply ( Internal ÷ 2 = Single-Ended Logic Reference). Complement of COMP_L_P_1. Low Comparator Outputs. Complement of COMP_H_P_1. High Comparator Outputs. 27 28 29 30, 46 31 32 34 35 37, 39 38 41 42 44 45 DR_EN_P_T_1 DR_EN_N_T_1 DR_EN_N_1 NC COMP_H_P_1 COMP_H_N_1 COMP_L_P_1 COMP_L_N_1 SLEW1, SLEW0 CMOS_VDD COMP_L_N_2 COMP_L_P_2 COMP_H_N_2 COMP_H_P_2 Rev. 0 | Page 10 of 16 ADATE205 Pin No. 47 48 49 50 Mnemonic DR_EN_N_2 DR_EN_N_T_2 DR_EN_P_T_2 DR_EN_P_2 Description Complement of DR_EN_P_2. Complement of DR_EN_N_T_2. Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the appropriate signal. High Speed Enable Inputs. Multifunction depending on status of VTEN_2 and LDEN_2. Causes driver to enter/leave inhibit; driver to enter/leave termination mode; load to leave/enter inhibit (see Table 4). Complement of DR_DATA_P_2. Complement of DR_DATA_P_T_2. Termination Resistors for HS Inputs. Opposite end of each 50 Ω termination resistor goes to the appropriate signal. High Speed Data Inputs. Sets high/low state of driver output (see Table 4). Low Speed Control Signal. When high, DR_EN_2 forces driver output to VT; otherwise, DR_EN_2 forces driver to high impedance (see Table 4). Determines Whether LD Responds to DR_EN_2 or is Disabled (see Table 4). Comp Low Leakage Mode. Low Clamp. High Clamp. Driver High Voltage Reference. Driver Low Voltage Reference. Driver Term Voltage Reference. Driver Invert. Program Voltage for IOL (Source). Program Voltage for IOH (Sink). Reference GND for VIOL, VIOH. Commutation Reference Voltage. Device Ground or Pin Shield. Output/Input Pin. Window High Reference Level. Window Low Reference Level. Temperature Sense, Five Diode String, Reference to GND. Window Low Reference Level. Window High Reference Level. Output/Input pin. 51 52 53 54 61 62 63 65 66 67 68 69 70 72 73 74 75 80, 82, 94, 96 81 85 86 88 90 91 95 DR_DATA_N_2 DR_DATA_N_T_2 DR_DATA_P_T_2 DR_DATA_P_2 V TEN_2 LDEN_2 CLLM_2 CLAMPL_2 CLAMPH_2 VIH_2 VIL_2 VIT_2 D_INV_2 VIOL_2 VIOH_2 GNDREF_2 VCOM_2 GND/SHIELDS DUT_2 CVH_2 CVL_2 TEMP CVL_1 CVH_1 DUT_1 Rev. 0 | Page 11 of 16 ADATE205 TYPICAL PERFORMACE CHARACTERISTICS 2400 2200 2000 VIH = 5V 5 4 3 DRIVER = VIH 1600 LINEARITY ERROR (mV) 1800 VIL = 0V TERMINATION = 50Ω 2 1 0 –1 –2 –3 –4 200mV/DIV 1400 1200 1000 800 600 400 200 0 0 2 4 6 8 VIH = 3V 05737-003 –5 –6 –2 –1 0 1 2 3 4 5 6 7 10 2ns/DIV 12 14 16 18 VDUT (V) Figure 3. Driver Large Signal Response 240 220 200 VIH = 500mV VIL = 0V TERMINATION = 50Ω 6 5 4 Figure 6. Driver VIH Linearity vs. Output DRIVER = VIL 160 LINEARITY ERROR (mV) 180 3 2 1 0 –1 –2 –3 20mV/DIV 140 120 100 80 60 40 20 0 0 2 4 6 8 10 2ns/DIV 12 14 16 18 05737-004 VIH = 200mV –4 –5 –2 –1 0 1 2 3 4 5 6 7 VDUT (V) Figure 4. Driver Small Signal Response 10 0 –10 TRAILING FALL EDGE Figure 7. Driver VIL Linearity vs. Output 8 6 DRIVER = VTERM –30 LINEARITY ERROR (mV) –20 TRAILING RISE EDGE 4 2 0 –2 –4 05737-008 10ps/DIV –40 –50 –60 –70 –80 –90 –100 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 05737-005 –6 –8 –2 25.0 –1 0 1 2 3 4 5 6 7 2.5ns/DIV VDUT (V) Figure 5. Driver Trailing Edge Timing Error vs. Pulse Width Figure 8. Driver VTERM Linearity vs. Output Rev. 0 | Page 12 of 16 05737-007 VIH = 100mV 05737-006 VIH = 1V ADATE205 1.0004 1.0003 1.0002 1.0001 1.0000 0.9999 0.9998 0.9997 05737-009 4.0 3.5 3.0 OFFSET (mV) GAIN (V/V) 2.5 2.0 1.5 1.0 05737-012 0.9996 0.9995 60 70 80 90 100 0.5 0 –2 110 –1 0 1 2 3 4 5 6 7 TEMPERATURE (°C) COMMON-MODE VOLTAGE (V) Figure 9. Driver Gain vs. Temperature 2.0 1.5 1.0 Figure 12. Comparator Offset vs. Common-Mode Voltage 1100 1050 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 –50 –100 OFFSET (mV) 0 –0.5 –1.0 –1.5 60 50mV/DIV 0.5 05737-010 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500 8000 7500 8000 8500 9000 9000 TEMPERATURE (°C) 500ps/DIV Figure 10. Driver Offset vs. Temperature Figure 13. Comparator Schmoo at 1 ns Rise and Fall Time 240 220 200 180 160 20mV/DIV 140 120 100 80 60 40 20 0 2 4 6 8 10 12 14 16 18 20 05737-011 0 500 1100 1050 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 –50 –100 VIN = 0V TO 1V CVH >CVL