Data Sheet
200 MHz Dual Integrated DCL with Level
Setting DACs, Per Pin PMU, and Per Chip VHH
ADATE304
FEATURES
GENERAL DESCRIPTION
Driver
3-level driver with high-Z mode and built-in clamps
Precision trimmed output resistance
Low leakage mode (typically VCL.
Table 3.
Min
Typ
Max
Unit
Test
Level
−1.0
−200
±50
+6.75
+200
V
mV
D
P
Resolution
0.6
0.75
mV
PF
DNL
±1
mV
CT
mV
P
mV/°C
CT
Parameter
VCH
Range
Uncalibrated Accuracy
INL
−40
Tempco
VCL
Range
Uncalibrated Accuracy
±2
+40
−0.3
−1.25
−200
±50
+5.75
+200
V
mV
D
P
Resolution
0.6
0.75
mV
PF
DNL
±1
mV
CT
mV
P
mV/°C
CT
mA
mA
mV
P
P
P
INL
−40
Tempco
DC CLAMP CURRENT LIMIT
VCH
VCL
DUTGND VOLTAGE ACCURACY
±2
+40
0.5
−120
60
−7
−85
85
±1
−60
120
+7
Test Conditions/Comments
Driver high-Z, sinking 1 mA; VCH error measured at the
calibration points of 0.0 V and 5.0 V
Driver high-Z, sinking 1 mA; after two-point gain/offset
calibration; range/number of DAC bits as measured at
the calibration points of 0.0 V and 5.0 V
Driver high-Z, sinking 1 mA; after two-point gain/offset
calibration
Driver high-Z, sinking 1 mA; after two-point gain/offset
calibration; measured over VCH range of −1.0 V to +6.75 V
Measured at calibration points
Driver high-Z, sourcing 1 mA; VCL error measured at the
calibration points of 0.0 V and 5.0 V
Driver high-Z, sourcing 1 mA; after two-point gain/offset
calibration; range/number of DAC bits as measured at
the calibration points of 0.0 V and 5.0 V
Driver high-Z, sourcing 1 mA; after two-point gain/offset
calibration
Driver high-Z, sourcing 1 mA; after two-point gain/offset
calibration; measured over VCL range of −1.0 V to +5.75 V
Measured at calibration points
Driver high-Z, VCH = 0 V, VCL = −1.0 V, VDUTx = +5 V
Driver high-Z, VCH = 6.75 V, VCL = 5.0 V, VDUTx = 0.0 V
Over ±0.1 V range; measured at the endpoints of VCH
and VCL functional range
NORMAL WINDOW COMPARATOR
VOH tests done with VOL = −1.25 V; VOL tests done with VOH = +6.75 V, unless otherwise specified.
Table 4.
Parameter
DC SPECIFICATIONS
Input Voltage Range
Differential Voltage Range
Comparator Input Offset Voltage
Accuracy, Uncalibrated
Comparator Threshold Resolution
Comparator Threshold DNL
Comparator Threshold INL
Comparator Input Offset Voltage
Tempco
DUTGND Voltage Accuracy
Min
−1.25
±0.1
−150
−7
Typ
Max
Unit
Test
Level
±30
+6.75
±8.0
+150
V
V
mV
D
D
P
0.6
1
mV
PF
±1
±1.3
+7
mV
mV
CT
P
µV/°C
CT
mV
P
±100
−7
±0.5
+7
Rev. C | Page 7 of 51
Test Conditions/Comments
Offset measured at the calibration points
of 0.0 V and 5.0 V
After two-point gain/offset calibration;
range/number of DAC bits as measured at
the calibration points of 0 V and 5 V
After two-point gain/offset calibration
After two-point gain/offset calibration;
measured over VOH, VOL range of −1.25 V
to +6.75 V
Measured at calibration points
Over ±0.1 V range; measured at endpoints
of VOH and VOL functional range
ADATE304
Parameter
Comparator Uncertainty Range
DC Hysteresis
DC PSRR
Digital Output Characteristics
Internal Pull-Up Resistance to
Comparator, COMP_VTT Pin
VCOMP_VTT Range
Common-Mode Voltage
Data Sheet
Min
Typ
6.0
Test
Level
CB
mV
mV/V
CB
CT
60
Ω
P
5.0
V
V
V
mV
mV
ps
D
CT
P
CT
P
CB
0.5
±5
40
50
3.3
VCOMP_VTT − 1.88
VCOMP_VTT − 2.075
Differential Voltage
400
Rise/Fall Time, 20% to 80%
Unit
mV
Max
VCOMP_VTT − 1.675
250
500
450
600
AC SPECIFICATIONS
Propagation Delay, Input to
Output
1.75
ns
CB
Propagation Delay Tempco
5
ps/°C
CT
200
ps
CB
50
ps
CB
50
ps
CB
Overdrive, 250 mV and 1.0 V
75
ps
CB
Pulse Width, Sweep 1.6 ns to
10 ns
75
ps
CB
Duty Cycle, 5% to 95%
50
ps
CB
Minimum Pulse Width
2.0
ns
CB
Input Equivalent Bandwidth,
Terminated
ERT High-Z Mode, 3 V, 20%
to 80%
500
MHz
CB
2.5
ns
CB
Propagation Delay Matching
High Transition to Low
Transition
High to Low Comparator
Propagation Delay Change (with
Respect To)
Slew Rate, 800 ps, 1 ns, 1.2 ns,
and 2.2 ns (10% to 90%)
Rev. C | Page 8 of 51
Test Conditions/Comments
VDUTx = 0 V, sweep comparator threshold to
determine uncertainty region
VDUTx = 0 V
Measured at calibration points
Pull 1 mA and 10 mA from Logic 1 leg and
measure ΔV to calculate resistance; measured
ΔV/9 mA; done for both comparator logic
states
Measured with 100 Ω differential termination
Measured with no external termination
Measured with 100 Ω differential termination
Measured with no external termination
Measured with each comparator leg
terminated 50 Ω to GND
Input transition time = 800 ps, 10% to 90%;
measured with each comparator leg
terminated 50 Ω to GND, unless otherwise
specified
VDUTx = 0 V to 1.0 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement:
VOH = +0.50 V, VOL = −1.25 V; low-side
measurement: VOH = +6.75 V, VOL = +0.50 V
VDUTx = 0 V to 1.0 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement:
VOH = +0.50 V, VOL = −1.25 V; low-side
measurement: VOH = +6.75 V, VOL = +0.50 V
VDUTx = 0 V to 1.0 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement:
VOH = +0.50 V, VOL = −1.25 V; low-side
measurement: VOH = +6.75 V, VOL = +0.50 V
VDUTx = 0 V to 1.0 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement:
VOH = +0.50 V, VOL = −1.25 V; low-side
measurement: VOH = +6.75V, VOL = +0.50 V
For 250 mV: VDUTx = 0 V to 0.5 V swing; for
1.0 V: VDUTx = 0 V to 1.25 V swing; Driver
VTERM mode, VT = 0.0 V; high-side
measurement: VOH = +0.25 V, VOL = −1.25
V; low-side measurement: VOH = +6.75 V,
VOL = +0.25 V
VDUTx = 0 V to 1.0 V swing @ 32.0 MHz,
Driver VTERM mode, VT = 0.0 V; high-side
measurement: VOH = +0.5 V, VOL = −1.25 V;
low-side measurement: VOH = +6.75 V,
VOL = +0.5 V
VDUTx = 0 V to 1.0 V swing @ 1.0 MHz, Driver
VTERM mode, VT =0.0 V; high-side
measurement: VOH = +0.50 V, VOL = −1.25
V; low-side measurement: VOH = +6.75 V,
VOL = +0.50 V
VDUTx = 0 V to 1.0 V swing, Driver VTERM
mode, VT = 0.0 V; less than 12% amplitude
degradation measured by shmoo
VDUTx = 0 V to 1.0 V swing, Driver VTERM
mode, VT = 0.0 V; as measured by shmoo
VDUTx = 0 V to 3.0 V swing, driver high-Z; as
measured by shmoo; input transition time of
~2000 ps, 10% to 90%
Data Sheet
ADATE304
DIFFERENTIAL COMPARATOR
VOH tests done with VOL = −1.1 V, VOL tests done with VOH = +1.1 V, unless otherwise specified.
Table 5.
Parameter
DC SPECIFICATIONS
Input Voltage Range
Operational Differential Voltage
Range
Maximum Differential Voltage Range
Comparator Input Offset Voltage
Accuracy, Uncalibrated
VOH, VOL Resolution
Min
Unit
Test
Level
+4.5
±1.1
V
V
D
D
±35
±8
+150
V
mV
D
P/CT
0.6
1
mV
PF
mV
CT
mV
P
µV/°C
mV
CT
CB
mV
mV/V
CB
P
−1.25
±0.05
−150
VOH, VOL DNL
VOH, VOL INL
Max
Typ
±1
−15
±2.0
+15
VOH, VOL Offset Voltage Tempco
Comparator Uncertainty Range
±200
18
DC Hysteresis
CMRR
0.5
0.15
DC PSRR
AC SPECIFICATIONS
±1.5
mV/V
CT
Propagation Delay, Input to Output
1.7
ns
CB
Propagation Delay Tempco
5
ps/°C
CT
100
50
ps
ps
CB
CB
1
Propagation Delay Matching
High Transition to Low Transition
High-to-Low Comparator
Propagation Delay Change (with
Respect To)
Slew Rate, 800 ps, 1 ns, 1.2 ns, and
2.2 ns (10% to 90%)
60
ps
CB
Overdrive, 250 mV and 750 mV
100
ps
CB
Pulse Width, Sweep from 1.6 ns to
10 ns
75
ps
CB
Duty Cycle, 5% to 95%
60
ps
CB
Rev. C | Page 9 of 51
Test Conditions/Comments
Offset measured at differential calibration points +1.0 V
and −1.0 V, with common mode = 0.0 V
After two-point gain/offset calibration; range/number of
DAC bits as measured at differential calibration points
+1.0 V and −1.0 V, with common mode = 0.0 V
After two-point gain/offset calibration; common
mode = 0.0 V
After two-point gain/offset calibration; measured over VOH,
VOL range of −1.1 V to +1.1 V, common mode = 0.0 V
Measured at calibration points
VDUTx = 0 V, sweep comparator threshold to determine
uncertainty region
VDUTx = 0 V
Offset measured at common-mode voltage points of
−1.5 V and +4.5 V, with differential voltage = 0.0 V
Measured at calibration points
Input transition time = 800 ps, 10% to 90%, measured
with each comparator leg terminated 50 Ω to GND
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
VDUT0 = 0 V, for 250 mV: VDUT1 = 0 V to 0.5 V swing; for
750 mV: VDUT1 = 0 V to 1.0 V swing, Driver VTERM mode,
VT = 0.0 V; VOH = −0.25 V; repeat for other DUT channel
with comparator threshold = +0.25 V
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing @ 32 MHz, Driver
VTERM mode, VT = 0.0 V; high-side measurement: VOH =
0.0 V, VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing @ 1 MHz, Driver
VTERM mode, VT = 0.0 V; high-side measurement: VOH =
0.0 V, VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
ADATE304
Data Sheet
Parameter
Minimum Pulse Width
Min
Typ
2.5
Input Equivalent Bandwidth,
Terminated
Max
400
Unit
ns
Test
Level
CB
MHz
CB
Test Conditions/Comments
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V, VOL
= 0.0 V; less than 10% amplitude degradation measured
by shmoo; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V, VOL
= 0.0 V; less than 22% amplitude degradation measured
by shmoo; repeat for other DUT channel
ACTIVE LOAD
See the Truth Tables section and Table 29 for load control information.
Table 6.
Parameter
DC SPECIFICATIONS
Input Characteristics
VCOM Voltage Range
VDUT Range
VCOM Accuracy, Uncalibrated
Min
−1.00
−1.25
−200
VCOM Resolution
Typ
Max
Unit
Test
Level
±30
+6.50
+6.75
+200
V
V
mV
D
D
P
0.6
1
mV
PF
VCOM DNL
VCOM INL
−7
±1
±2
+7
mV
mV
CT
P
DUTGND Voltage Accuracy
−7
±1
+7
mV
P
Output Characteristics
IOL
Maximum Source Current
Uncalibrated Offset
12
−600
±100
+600
mA
µA
D
P
Uncalibrated Gain
−12
±4
+12
%
P
Resolution
1.5
2
µA
PF
DNL
±3.0
µA
CT
+80
µA
P
0.25
V
P
INL
−80
±20
90% Commutation Voltage
IOH
Maximum Sink Current
Uncalibrated Offset
12
−600
±100
+600
mA
µA
D
P
−12
±4
+12
%
P
Resolution
1.5
2
µA
PF
DNL
±3.0
µA
CT
Uncalibrated Gain
Test Conditions/Comments
Load active on, RCV active, unless otherwise noted
IOH = IOL = 6 mA, VCOM error measured at the calibration points
of 0.0 V and 5.0 V
IOH = IOL = 6 mA, after two-point gain/offset calibration;
range/number of DAC bits as measured at the calibration points
of 0.0 V and 5.0 V
IOH = IOL = 6 mA, after two-point gain/offset calibration
IOH = IOL = 6 mA, after two-point gain/offset calibration;
measured over VCOM range of −1.00 V to +6.50 V
Over ±0.1 V range; measured at end points of VCOM functional
range
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL offset calculated from
the calibration points of 1 mA and 11 mA
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL gain calculated from
the calibration points of 1 mA and 11 mA
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/
offset calibration; range/number of DAC bits as measured at the
calibration points of 1 mA and 11 mA
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point
gain/offset calibration
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/
offset calibration; measured over IOL range of 0 mA to 12 mA
IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOL reference at
VDUTx = −1.0 V, measure IOL current at VDUTx = +1.75 V, ensure > 90%
of reference current
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH offset calculated from
the calibration points of 1 mA and 11 mA
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH gain calculated from
the calibration points of 1 mA and 11 mA
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point
gain/offset calibration; range/number of DAC bits as measured at
the calibration points of 1 mA and 11 mA
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point
gain/offset calibration
Rev. C | Page 10 of 51
Data Sheet
Parameter
INL
ADATE304
Min
−80
Typ
±20
90% Commutation Voltage
Max
+80
Unit
µA
Test
Level
P
0.25
V
P
Output Current Tempco
AC SPECIFICATIONS
Dynamic Performance
Propagation Delay, Load Active
On to Load Active Off;
50%,90%
±1.5
µA/°C
CT
7.3
ns
CB
Propagation Delay, Load Active
Off to Load Active On;
50%, 90%
10.3
ns
CB
Propagation Delay Matching
3.0
ns
CB
Load Spike
190
mV
CB
Settling Time to 90%
1.9
ns
CB
Test Conditions/Comments
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point gain/
offset calibration; measured over IOH range of 0 mA to 12 mA
IOH = IOL =12 mA, VCOM = 2.0 V, measure IOH reference at VDUTx
= 5.0 V, measure IOH current at VDUTx = 2.25 V, ensure > 90% of
reference current
Measured at calibration points
Load active on, unless otherwise noted
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; measured from 50% point of RCVxP − RCVxN to 90% point of
final output, repeat for drive low and high
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; measured from 50% point of RCVxP − RCVxN to 90% point of
final output, repeat for drive low and high
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; active on vs. active off, repeat for drive low and high
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 0 mA, VH
= VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for IOH;
repeat for drive low and high
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for IOH;
measured at 90% of final value
PMU
FV is the force voltage, MV is the measure voltage, FI is the force current, MI is the measure current, FN is force nothing.
Table 7.
Parameter
FORCE VOLTAGE (FV)
Current Range A
Current Range B
Current Range C
Current Range D
Current Range E
Force Input Voltage Range at
Output for All Ranges
Force Voltage Uncalibrated
Accuracy for Range C
Force Voltage Uncalibrated
Accuracy for All Ranges
Force Voltage Offset Tempco
for All Ranges
Force Voltage Gain Tempco
for All Ranges
Forced Voltage INL
Min
Max
Unit
Test
Level
+6.75
mA
mA
µA
µA
µA
V
D
D
D
D
D
D
+100
mV
P
±25
mV
CT
±25
µV/°C
CT
PMU enabled, FV, Range C, PE disabled, error measured at
calibration points of 0.0 V and 5.0 V
PMU enabled, FV, PE disabled, error measured at calibration
points of 0.0 V and 5.0 V; repeat for each PMU current range
Measured at calibration points for each PMU current range
±10
ppm/°C
CT
Measured at calibration points for each PMU current range
mV
P
PMU enabled, FV, Range C, PE disabled, after two-point gain/offset
calibration; measured over output range of −1.25 V to +6.75 V
PMU enabled, FV, PE disabled, force −1.25 V, measure voltage
while PMU sinking zero and full-scale current; measure ∆V;
force 6.75 V, measure voltage while PMU sourcing zero and
full-scale current; measure ∆V; repeat for each PMU current
range
mV
mV
CT
CT
Typ
±32
±2
±200
±20
±2
−1.25
−100
−7
±25
±2
+7
Force Voltage Compliance vs.
Current Load
Range A
Range B to Range E
±4
±1
Rev. C | Page 11 of 51
Test Conditions/Comments
ADATE304
Parameter
Current Limit, Source, and Sink
Range A
Range B to Range E
DUTGND Voltage Accuracy
Data Sheet
Min
Typ
Max
Unit
Test
Level
108
140
180
%FS
P
120
145
180
%FS
P
−7
±1
+7
mV
P
+6.75
V
D
µA
CT
µA
P
MEASURE CURRENT (MI)
Measure Current, Pin DUTx
Voltage Range for All Ranges
Measure Current Uncalibrated
Accuracy
Range A
Range B
−1.25
±500
−400
±3.0
+400
Test Conditions/Comments
PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx
to 6.0 V; source: force 2.5 V, short DUTx to −1.0 V; Range A FS =
32 mA, 108% FS = 35 mA, 180% FS = 58 mA
PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx to
6.0 V; source: force 2.5 V, short DUTx to −1.0 V; repeat for each
PMU current range; example: Range B FS = 2 mA, 120 % FS =
2.4 mA, 180% FS = 3.6 mA
Over ±0.1 V range; measured at endpoints of FV functional
range
VDUTx externally forced to 0.0V, unless otherwise specified; ideal
MEASOUT transfer functions: VMEASOUT01 [V] = (IMEASOUT01 × 5/FSR) +
2.5 + VDUTGND I(VMEASOUT01) [A] = (VMEASOUT01 − VDUTGND − 2.5) × FSR/5
PMU enabled, FIMI, Range A, PE disabled, error at calibration
points −25 mA and +25 mA, error = (I(VMEASOUT01) − IDUTx)
PMU enabled, FIMI, Range B, PE disabled, error at calibration
points −1.6 mA and +1.6 mA, error = (I(VMEASOUT01) − IDUTx)
PMU enabled, FIMI, PE disabled, error at calibration points of
±80% FS, error = (I(VMEASOUT01)1 − IDUTx)
PMU enabled, FIMI, PE disabled, error at calibration points of
±80% FS, error = (I(VMEASOUT01) − IDUTx)
PMU enabled, FIMI, PE disabled, error at calibration points of
±80% FS, error = (I(VMEASOUT01) − IDUTx)
Range C
± 2.00
µA
CT
Range D
±0.30
µA
CT
Range E
±0.08
µA
CT
±2
±25
±5
±1
µA/°C
nA/°C
nA/°C
nA/°C
CT
CT
CT
CT
Measured at calibration points
Measured at calibration points
Measured at calibration points
Measured at calibration points
±2.5
%
CT
%
P
±4
%
CT
PMU enabled, FIMI, PE disabled, gain error from calibration
points ±80% FS
PMU enabled, FIMI, Range B, PE disabled, gain error from
calibration points ±1.6 mA
PMU enabled, FIMI, PE disabled, gain error from calibration
points ±80% FS
Measured at calibration points
±300
±50
ppm/°C
ppm/°C
CT
CT
±0.05
%FSR
CT
%FSR
P
%FSR
CT
%FSR/V
P
mV
CT
Measure Current Offset Tempco
Range A
Range B
Range C
Range D and Range E
Measure Current Gain Error,
Nominal Gain = 1
Range A
Range B
−20
Range C to Range E
Measure Current Gain Tempco
Range A
Range B to Range E
Measure Current INL
Range A
Range B
−0.02
Range B to Range E
FVMI DUT Pin Voltage Rejection
DUTGND Voltage Accuracy
±2
+20
+0.02
±0.01
−0.01
+0.01
±2.5
Rev. C | Page 12 of 51
PMU enabled, FIMI, Range A, PE disabled, after two-point
gain/offset calibration, measured over FSR output of −32 mA
to +32 mA
PMU enabled, FIM,I Range B, PE disabled, after two-point gain/
offset calibration measured over FSR output of −2 mA to +2 mA
PMU enabled, FIMI, PE disabled, after two-point gain/offset
calibration; measured over FSR output
PMU enabled, FVMI, Range B, PE disabled, force −1 V and +5 V
into load of 1 mA; measure ∆I reported at MEASOUT01
Over ±0.1 V range; measured at endpoints of MI functional range
Data Sheet
Parameter
FORCE CURRENT (FI)
Force Current, DUTx Pin Voltage
Range for All Ranges
Force Current Uncalibrated
Accuracy
Range A
ADATE304
Min
Typ
−1.25
Max
Unit
Test
Level
+6.75
V
D
−5.0
±0.5
+5.0
mA
P
Range B
−400
±40
+400
µA
P
Range C
−40
±4
+40
µA
P
Range D
−4
±0.4
+4
µA
P
Range E
−400
±75
+400
nA
P
−20
±1
±80
±4
±4
+20
µA/°C
nA/°C
nA/°C
%
CT
CT
CT
P
ppm/°C
ppm/°C
CT
CT
Force Current Offset Tempco
Range A
Range B
Range C to Range E
Forced Current Gain Error,
Nominal Gain = 1
Forced Current Gain Tempco
Range A
Range B to Range E
Force Current INL
Range A
−500
±75
−0.3
±0.05
+0.3
%FSR
P
−0.2
±0.015
+0.2
%FSR
P
−0.6
−1.0
±0.06
±0.1
+0.6
+1.0
%FSR
%FSR
P
P
−1.25
−25
±2.0
+6.75
+25
V
mV
D
P
−0.2
±10
±0.01
+0.2
µV/°C
%
CT
P
Measure Voltage Gain Tempco
Measure Voltage INL
−7
25
±1
+7
ppm/°C
mV
CT
P
Rejection of Measure V vs. IDUTx
−1.5
±0.1
+1.5
mV
P
Range B to Range E
Force Current Compliance vs.
Voltage Load
Range A to Range D
Range E
MEASURE VOLTAGE
Measure Voltage Range
Measure Voltage Uncalibrated
Accuracy
Measure Voltage Offset Tempco
Measure Voltage Gain Error
Rev. C | Page 13 of 51
Test Conditions/Comments
VDUTx externally forced to 0.0V, unless otherwise specified, ideal
force current transfer function: IFORCE = (PMUDAC − 2.5) × (FSR/5)
PMU enabled, FIMI, Range A, PE disabled, error at calibration
points of −25 mA and +25 mA
PMU enabled, FIMI, Range B, PE disabled, error at calibration
points of −1.6 mA and 1.6 mA
PMU enabled, FIMI, Range C, PE disabled, error at calibration
points of ±80% FS
PMU enabled, FIMI, Range D, PE disabled, error at calibration
points of ±80% FS
PMU enabled, FIMI, Range E, PE disabled, error at calibration
points of ±80% FS
Measured at calibration points
Measured at calibration points
Measured at calibration points
PMU enabled, FIMI, PE disabled, gain error from calibration
points of ±80% FS
Measured at calibration points
PMU enabled, FIMI, Range A, PE disabled, after two-point
gain/offset calibration; measured over FSR output of −32 mA
to +32 mA
PMU enabled, FIMI, PE disabled, after two-point gain/offset
calibration; measured over FSR output
PMU enabled, FIMV, PE disabled; force positive full-scale
current driving −1.25 V and +6.75 V, measure ∆I @ DUTx pin;
force negative full-scale current driving −1.25 V and +6.75 V,
measure ∆I @ DUTx pin
PMU enabled, FVMV, Range B, PE disabled, error at calibration
points of 0 V and 5 V, error = (VMEASOUT01 − VDUTx)
Measured at calibration points
PMU enabled, FVMV, Range B, PE disabled, gain error from
calibration points of 0 V and 5 V
Measured at calibration points
PMU enabled, FVMV, Range B, PE disabled, after two-point
gain/offset calibration; measured over output range of −1.25 V
to +6.75 V
PMU enabled, FVMV, Range D, PE disabled, force 0 V into load
of −10 µA and +10 µA; measure ∆V reported at MEASOUT01
ADATE304
Data Sheet
Typ
Max
Unit
Test
Level
25
+6.75
4
200
V
mA
Ω
D
D
P
−1
+1
µA
P
−25
+25
mA
P
−1.25
0.75
−300
+10
+4.75
6.75
+300
V
V
mV
D
D
P
Negative Clamp Voltage Droop
−300
−10
+300
mV
P
Uncalibrated Accuracy
−250
±100
+250
mV
P
INL
−70
±5
+70
mV
P
±1
mV
CT
15
µs
S
20
µs
S
124
µs
S
1015
µs
S
3455
µs
S
Parameter
MEASOUT01 DC CHARACTERISTICS
MEASOUT01 Voltage Range
DC Output Current
MEASOUT01 Pin Output
Impedance
Output Leakage Current when
Tristated
Output Short-Circuit Current
VOLTAGE CLAMPS
Low Clamp Range (VCL)
High Clamp Range (VCH)
Positive Clamp Voltage Droop
DUTGND Voltage Accuracy
Min
−1.25
SETTLING/SWITCHING TIMES
Voltage Force Settling Time to
0.1% of Final Value
Range A, 200 pF and
2000 pF Load
Range B, 200 pF and
2000 pF Load
Range C, 200 pF and
2000 pF Load
Range D, 200 pF and
2000 pF Load
Range E, 200 pF and
2000 pF Load
Voltage Force Settling Time to
1.0% of Final Value
Range A, 200 pF and
2000 pF Load
Range B, 200 pF and
2000 pF Load
Range C, 200 pF and
2000 pF Load
Range D, 200 pF Load
Range D, 2000 pF Load
Range E, 200 pF Load
Range E, 2000 pF Load
Test Conditions/Comments
PMU enabled, FVMV, PE disabled; source resistance: PMU force
+6.75 V and load with 0 mA and +4 mA; sink resistance: PMU
force −1.25 V and load with 0 mA and −4 mA; resistance =
∆V/∆I at MEASOUT01 pin
Tested at −1.25 V and +6.75 V
PMU enabled, FVMV, PE disabled; source: PMU force +6.75 V,
short MEASOUT01 to −1.25 V; sink: PMU force −1.25 V, short
MEASOUT01 to +6.75 V
PMU enabled, FIMI, Range A, PE disabled, PMU clamps
enabled, VCH = +5.0 V, VCL = −1.0 V, PMU force 2.0 mA and
32 mA into open; ∆V seen at DUTx pin
PMU enabled, FIMI, Range A, PE disabled, PMU clamps
enabled, VCH = +5.0 V, VCL = −1.0 V, PMU force −2.0 mA and
−32 mA into open; ∆V seen at DUTx pin
PMU enabled, FIMI, Range B, PE disabled, PMU clamps enabled,
PMU force ±1 mA into open; VCH errors at calibration points
1.0 V and 5.0 V; VCL errors at the calibration points 0.0 V and
4.0 V
PMU enabled, FIMI, Range B, PE disabled, PMU clamps enabled,
PMU force ±1 mA into open; after two-point gain/offset
calibration; measured over PMU clamp range
Over ±0.1 V range; measured at endpoints of PMU clamp
functional range
SCAP = 330 pF, FFCAP = 220 pF
PMU enabled, FV, PE disabled, program PMUDAC steps of
500 mV and 5.0 V; simulation of worst case, 2000 pF load,
PMUDAC step of 5.0 V
PMU enabled, FV, PE disabled, start with PMUDAC
programmed to 0.0 V, program PMUDAC to 500 mV
14
µs
CB
14
µs
CB
14
µs
CB
45
45
45
225
µs
µs
µs
µs
CB
CB
CB
CB
Rev. C | Page 14 of 51
Data Sheet
Parameter
Voltage Force Settling Time to
1.0% of Final Value
Range A, 200 pF and
2000 pF Load
Range B, 200 pF Load
Range B, 2000 pF Load
Range C, 200 pF Load
Range C, 2000 pF Load
Range D, 200 pF Load
Range D, 2000 pF Load
Range E, 200 pF Load
Range E, 2000 pF Load
Current Force Settling Time to
0.1% of Final Value
Range A, 200 pF in Parallel
with 120 Ω
Range B, 200 pF in Parallel
with 1.5 kΩ
Range C, 200 pF in Parallel
with 15.0 kΩ
Range D, 200 pF in Parallel
with 150 kΩ
Range E, 200 pF in Parallel
with 1.5 MΩ
Current Force Settling Time to
1.0% of Final Value
Range A, 200 pF in Parallel
with 120 Ω
Range B, 200 pF in Parallel
with 1.5 kΩ
Range C, 200 pF in Parallel
with 15.0 kΩ
Range D, 200 pF in Parallel
with 150 kΩ
Range E, 200 pF in Parallel
with 1.5 MΩ
INTERACTION AND CROSSTALK
Measure Voltage Channel-toChannel Crosstalk
Measure Current Channel-toChannel Crosstalk
ADATE304
Min
Unit
Test
Level
4.0
µs
CB
4.2
4.2
5.8
19
50
210
360
610
µs
µs
µs
µs
µs
µs
µs
µs
CB
CB
CB
CB
CB
CB
CB
CB
Typ
Max
Test Conditions/Comments
PMU enabled, FV, PE disabled, start with PMUDAC
programmed to 0.0 V, program PMUDAC to 5.0 V
PMU enabled, FI, PE disabled, start with PMUDAC
programmed to 0 current, program PMUDAC to FS current
8.2
µs
S
9.4
µs
S
30
µs
S
281
µs
S
2668
µs
S
PMU enabled, FI, PE disabled, start with PMUDAC
programmed to 0 current, program PMUDAC to FS current
4.2
µs
CB
4.3
µs
CB
8.1
µs
CB
205
µs
CB
505
µs
CB
±0.125
%FSR
CT
±0.01
%FSR
CT
Rev. C | Page 15 of 51
PMU enabled, FIMV, PE disabled, Range B, forcing 0 mA into
0 V load; other channel: Range A, forcing a step of 0 mA to 25 mA
into 0 V load; report ∆V of MEASOUT01 pin under test;
0.125% × 8.0 V = 10 mV
PMU enabled, FVMI, PE disabled, Range E, forcing 0 V into
0 mA current load; other channel: Range E, forcing a step of 0 V
to 5 V into 0 mA current load; report ∆V of MEASOUT01 pin
under test; 0.01% × 5.0 V = 0.5 mV
ADATE304
Data Sheet
EXTERNAL SENSE (PMUS_CHx)
Table 8.
Parameter
EXTERNAL SENSE (PMUS_CHX)
Voltage Range
Input Leakage Current
Min
Max
Unit
Test
Level
Test Conditions/Comments
+6.75
+20
V
nA
D
P
Tested at −1.25 V and +6.75 V
Typ
Max
Unit
Test
Level
Test Conditions/Comments
1
+0.1
100
V
μA
D
P
Tested at −100 mV and +100 mV
Test Conditions/Comments
Typ
−1.25
−20
DUTGND INPUT
Table 9.
Parameter
DUTGND INPUT
Input Voltage Range, Referenced to GND
Input Bias Current
Min
−0.1
SERIAL PERIPHERAL INTERFACE
Table 10.
Parameter
SERIAL PERIPHERAL INTERFACE
Serial Input Logic High
Serial Input Logic Low
Input Bias Current
SCLK Clock Rate
SCLK Pulse Width
SCLK Crosstalk on DUTx Pin
Serial Output Logic High
Serial Output Logic Low
Update Time
Min
1.8
0
−10
Typ
1
50
9
8
VCC − 0.4
Max
Unit
Test
Level
VCC
0.7
+10
V
V
μA
MHz
ns
mV
V
PF
PF
P
PF
CT
CB
PF
V
μs
PF
D
VCC
0
0.8
10
Rev. C | Page 16 of 51
Tested at 0.0 V and 3.3 V
PE disabled, PMU FV enabled and forcing 0 V
Sourcing 2 mA
Sinking 2 mA
Maximum delay time required for the part to
enter a stable state after a serial bus
Data Sheet
ADATE304
HVOUT DRIVER
Table 11.
Parameter
VHH BUFFER
Voltage Range
Output High
Max
Unit
Test
Level
VPLUS − 3.25
V
V
D
P
5.9
V
P
±100
+500
mV
P
1
1.21
1.5
mV/°C
mV
CT
PF
±15
+30
mV
P
mV
CT
10
Ω
P
60
100
mA
P
−100
−60
mA
P
200
ns
CB
26
ns
CB
±125
mV
CB
Min
Typ
5.9
13.5
Output Low
Accuracy Uncalibrated
−500
Offset Tempco
Resolution
INL
−30
DUTGND Voltage Accuracy
±1
Output Resistance
1
DC Output Current Limit
Source
DC Output Current Limit Sink
Rise Time (From VL or VH to
VHH)
Fall Time (From VHH to VL or
VH)
Preshoot, Overshoot, and
Undershoot
VL/VH BUFFER
Voltage Range
Accuracy Uncalibrated
−0.1
−500
Offset Tempco
Resolution
INL
−20
DUTGND Voltage Accuracy
±100
+6.0
+500
V
mV
D
P
1
0.61
0.75
mV/°C
mV
CT
PF
±4
+20
mV
P
mV
CT
50
Ω
P
±2
Output Resistance
45
48
DC Output Current Limit
Source
DC Output Current Limit Sink
60
100
mA
P
−100
−60
mA
P
Rise Time (VL to VH)
11
ns
CB
Fall Time (VH to VL)
11.3
ns
CB
Preshoot, Overshoot, and
Undershoot
±54
mV
CB
Rev. C | Page 17 of 51
Test Conditions/Comments
VHH = (VT + 1 V) × 2 + DUTGND
VPLUS = 16.75 V nominal; in this condition, VHVOUT max = 13.5 V
VHH mode enabled, RCV active, VHH level = full scale,
sourcing 15 mA
VHH mode enabled, RCV active, VHH level = zero scale,
sinking 15 mA
VHH mode enabled, RCV active, VHVOUT error measured at
the calibration points of 7 V and 12 V
Measured at calibration points
VHH mode enabled, RCV active, after two-point gain/offset
calibration; range/number of DAC bits as measured at the
calibration points of 7 V and 12 V
VHH mode enabled, RCV active, after two-point gain/offset
calibration; measured over VHH range of 5.9 V to 13.5 V
Over ±0.1 V range; measured at endpoints of VHH
functional range
VHH mode enabled, RCV active, source: VHH = 10.0 V,
IHVOUT = 0 mA and 15 mA; sink: VHH = 6.5 V, IHVOUT = 0 mA and
−15 mA; ∆V/∆I
VHH mode enabled, RCV active, VHH = 10.0 V, short HVOUT
pin to 5.9 V, measure current
VHH mode enabled, RCV active, VHH = 6.5 V, short HVOUT
pin to 14.1 V, measure current
VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =
3.0 V; 20% to 80%, for DATA = high and DATA = low
VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =
3.0 V; 20% to 80%, for DATA = high and DATA = low
VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =
3.0 V; for DATA = high and DATA = low
VHH mode enabled, RCV inactive, error measured at the
calibration points 0 V and 5 V
Measured at calibration points
VHH mode enabled, RCV inactive, after two-point
gain/offset calibration; range/number of DAC bits as
measured at the calibration points 0 V and 5 V
VHH mode enabled, RCV inactive, after two-point
gain/offset calibration; measured over range of −0.1 V to
+6.0 V
Over ±0.1 V range; measured at endpoints of VH and VL,
functional range
VHH mode enabled, RCV inactive, source: VH = 3.0 V, IHVOUT
= +1 mA and +50 mA; sink: VL = 2.0 V, IHVOUT = −1 mA and
−50 mA; ∆V/∆I
VHH mode enabled, RCV inactive, VH = +6.0 V, short
HVOUT pin to −0.1 V, DATA high, measure current
VHH mode enabled, RCV inactive, VL = −0.1 V, short HVOUT
pin to +6.0 V, DATA low, measure current
VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,
toggle DATA; 20% to 80%
VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,
toggle DATA; 20% to 80%
VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,
toggle DATA
ADATE304
Data Sheet
OVERVOLTAGE DETECTOR (OVD)
Table 12.
Parameter
DC CHARACTERISTICS
Programmable Voltage Range
Accuracy Uncalibrated
Min
Typ
−2.25
−200
Max
Unit
Test
Level
+7.0
+200
V
mV
D
P
mV
CB
Test Conditions/Comments
OVD offset errors measured at programmed levels of +7.0 V
and −2.25 V
Hysteresis
LOGIC OUTPUT CHARACTERISTICS
Off State Leakage
112
10
1000
nA
P
Maximum On Voltage @ 100 μA
0.2
0.7
V
P
Propagation Delay
1.9
μs
CB
Max
Unit
Test
Level
Test Conditions/Comments
+7.5
V
kΩ
D
CT
PMUDAC = 0.0 V, FV, I = 0, 200 μA; ∆V/∆I
Disable OVD alarm, apply 3.3 V to OVD pin, measure
leakage current
Activate alarm, force 100 μA into OVD pin, measure active
alarm voltage
For OVD high: DUTx = 0 V to +6 V swing, OVD high = +3.0 V,
OVD low = −2.25 V; for OVD low: DUTx = 0 V to +6 V swing,
OVD high = +7.0 V, OVD low = +3.0 V
16-BIT DAC MONITOR MUX
Table 13.
Parameter
DC CHARACTERISTICS
Programmable Voltage Range
Output Resistance
Min
Typ
−2.5
16
Rev. C | Page 18 of 51
Data Sheet
ADATE304
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 14.
Parameter
Supply Voltages
Positive Supply Voltage (VDD to GND)
Positive VCC Supply Voltage (VCC to GND)
Negative Supply Voltage (VSS to GND)
Supply Voltage Difference (VDD to VSS)
Reference Ground (DUTGND to GND)
AGND to DGND
VPLUS Supply Voltage (VPLUS to GND)
Input Voltages
Input Common-Mode Voltage
Short-Circuit Voltage1
High Speed Input Voltage2
High Speed Differential Input Voltage3
VREF
DUTx I/O Pin Current
DCL Maximum Short-Circuit Current4
Temperature
Operating Temperature, Junction
Storage Temperature Range
Rating
Table 15. Thermal Resistance
−0.5 V to +11.5 V
−0.5 V to +4.0 V
−6.25 V to +0.5 V
−1.0 V to +16.5 V
−0.5 V to +0.5 V
−0.5 V to +0.5 V
−0.5 V to +17.5 V
VSS to VDD
−3.0 V to +8.0 V
0.0 V to VCC
0.0 V to VCC
−0.5 V to +5.5 V
±140 mA
Package Type
84-Ball CSP_BGA
θJA
31.1
EXPLANATION OF TEST LEVELS
D
Definition
S
Design verification simulation
P
100% production tested
PF
Functionally checked during production test
CT
Characterized on tester
CB
Characterized on bench
ESD CAUTION
125°C
−65°C to +150°C
1
RL = 0 Ω, VDUT continuous short-circuit condition (VH, VL, VT, high-Z, VCOM,
clamp modes).
2
DATAxP, DATAxN, RCVxP, RCVxN, under source RL = 0 Ω.
3
DATAxP to DATAxN, RCVxP, RCVxN.
4
RL = 0 Ω, VDUTx = –3 V to +8 V; DCL current limit. Continuous short-circuit
condition. ADATE304 must current limit and survive continuous short circuit.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 19 of 51
θJC
0.51
ADATE304
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10
9
8
7
6
5
4
3
2
1
A
HVOUT
PMUS_CH0
VSSO_0
(DRIVE)
DUT0
VDDO_0
(DRIVE)
VDDO_1
(DRIVE)
DUT1
VSSO_1
(DRIVE)
PMUS_CH1
TEMPSENSE
B
VPLUS
SCAP0
VSS
AGND
VDD
VDD
AGND
VSS
SCAP1
VDD/VDD_
TMPSNS
C
FFCAP_0B
AGND
DATA0N
VSS
VDD
VDD
VSS
DATA1N
AGND
FFCAP_1B
D
OVD_CH0
VDD
DATA0P
DATA1P
VDD
OVD_CH1
E
FFCAP_0A
VSS
RCV0N
RCV1N
VSS
FFCAP_1A
F
AGND
AGND
RCV0P
RCV1P
AGND
AGND
COMP_QL0P COMP_QL0N COMP_VTT0
H
COMP_QH0P COMP_QH0N
COMP_VTT1 COMP_QL1N COMP_QL1P
AGND
VSS
VDD
VDD
VSS
AGND
COMP_QH1N COMP_QH1P
J
AGND
AGND
AGND
RST
SDIN
DGND
DAC16_MON
AGND
AGND
AGND
K
VREF_GND
VREF
AGND
VCC
SCLK
SDOUT
CS
AGND
DUTGND
MEASOUT01/
TEMPSENSE
Figure 2. Pin Configuration
Rev. C | Page 20 of 51
07279-002
G
Data Sheet
ADATE304
Table 16. Pin Function Descriptions
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D8
D9
D10
E1
E2
E3
E8
E9
E10
F1
F2
F3
F8
F9
F10
G1
G2
G3
G8
Mnemonic
TEMPSENSE
PMUS_CH1
VSSO_1 (Drive)
DUT1
VDDO_1 (Drive)
VDDO_0 (Drive)
DUT0
VSSO_0 (Drive)
PMUS_CH0
HVOUT
VDD/VDD_TMPSNS
SCAP1
VSS
AGND
VDD
VDD
AGND
VSS
SCAP0
VPLUS
FFCAP_1B
AGND
DATA1N
VSS
VDD
VDD
VSS
DATA0N
AGND
FFCAP_0B
OVD_CH1
VDD
DATA1P
DATA0P
VDD
OVD_CH0
FFCAP_1A
VSS
RCV1N
RCV0N
VSS
FFCAP_0A
AGND
AGND
RCV1P
RCV0P
AGND
AGND
COMP_QL1P
COMP_QL1N
COMP_VTT1
COMP_VTT0
Description
Temperature Sense Output
PMU External Sense Path Channel 1
Driver Output Supply (−5.0 V) Channel 1
Device Under Test Channel 1
Driver Output Supply (+10.75 V) Channel 1
Driver Output Supply (+10.75 V) Channel 0
Device Under Test Channel 0
Driver Output Supply (−5.0 V) Channel 0
PMU External Sense Path Channel 0
High Voltage Driver Output
Temperature Sense Supply (+10.75 V)
PMU Stability Capacitor Connection Channel 1 (330 pF)
Supply (−5.0 V)
Analog Ground
Supply (+10.75 V)
Supply (+10.75 V)
Analog Ground
Supply (−5.0 V)
PMU Stability Capacitor Connection Channel 0 (330 pF)
Supply (+16.75 V)
PMU Feedforward Capacitor Connection B Channel 1 (220 pF)
Analog Ground
Driver Data Input (Negative) Channel 1
Supply (−5.0 V)
Supply (+10.75 V)
Supply (+10.75 V)
Supply (−5.0 V)
Driver Data Input (Negative) Channel 0
Analog Ground
PMU Feedforward Capacitor Connection B Channel 0 (220 pF)
Overvoltage Detection Flag Output Channel 1
Supply (+10.75 V)
Driver Data Input (Positive) Channel 1
Driver Data Input (Positive) Channel 0
Supply (+10.75 V)
Overvoltage Detection Flag Output Channel 0
PMU Feedforward Capacitor Connection A Channel 1 (220 pF)
Supply (−5.0 V)
Receive Data Input (Negative) Channel 1
Receive Data Input (Negative) Channel 0
Supply (−5.0 V)
PMU Feedforward Capacitor Connection A Channel 0 (220 pF)
Analog Ground
Analog Ground
Receive Data Input (Positive) Channel 1
Receive Data Input (Positive) Channel 0
Analog Ground
Analog Ground
Low-Side Comparator Output (Positive) Channel 1
Low-Side Comparator Output (Negative) Channel 1
Comparator Supply Termination Channel 1
Comparator Supply Termination Channel 0
Rev. C | Page 21 of 51
ADATE304
Data Sheet
Pin No.
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
Mnemonic
COMP_QL0N
COMP_QL0P
COMP_QH1P
COMP_QH1N
AGND
VSS
VDD
VDD
VSS
AGND
COMP_QH0N
COMP_QH0P
AGND
AGND
AGND
DAC16_MON
DGND
SDIN
RST
AGND
AGND
AGND
MEASOUT01/TEMPSENSE
K2
K3
K4
K5
K6
K7
K8
K9
K10
DUTGND
AGND
CS
SDOUT
SCLK
VCC
AGND
VREF
VREF_GND
Description
Low-Side Comparator Output (Negative) Channel 0
Low-Side Comparator Output (Positive) Channel 0
High-Side Comparator Output (Positive) Channel 1
High-Side Comparator Output (Negative) Channel 1
Analog Ground
Supply (−5.0 V)
Supply (+10.75 V)
Supply (+10.75 V)
Supply (−5.0 V)
Analog Ground
High-Side Comparator Output (Negative) Channel 0
High-Side Comparator Output (Positive) Channel 0
Analog Ground
Analog Ground
Analog Ground
16-Bit DAC Monitor Mux Output
Digital Ground
Serial Peripheral Interface (SPI) Data In
Serial Peripheral Interface (SPI) Reset
Analog Ground
Analog Ground
Analog Ground
Muxed Output Shared by PMU MEASOUT Channel 0, PMU MEASOUT Channel 1/
Temperature Sense and Temperature Sense GND Reference
DUT Ground Reference
Analog Ground
Serial Peripheral Interface (SPI) Chip Select
Serial Peripheral Interface (SPI) Data Out
Serial Peripheral Interface (SPI) Clock
Supply (+3.3 V)
Analog Ground
+5 V DAC Reference Voltage
DAC Ground Reference
Rev. C | Page 22 of 51
Data Sheet
ADATE304
TYPICAL PERFORMANCE CHARACTERISTICS
1.8
0.30
1.6
0.5V
0.25
3V
1.4
1.2
VOLTAGE (V)
VOLTAGE (V)
0.20
0.15
0.2V
0.10
2V
1.0
0.8
0.6
1V
0.4
0.05
0.2
0
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
–0.2
Figure 3. Driver Small Signal Response; VH = 0.2 V, 0.5 V;
VL = 0.0 V; 50 Ω Termination
1.0
1.5
2.0
3.0
2.5
TIME (ns)
3.5
4.0
4.5
5.0
1.8
1.6
3V
1.6
3V
1.4
1.4
1.2
1.2
0.8
0.6
1V
2V
1.0
0.8
0.6
0.4
0.4
0.2
0.2
0
0
2
4
6
8
10
12
TIME (ns)
14
16
18
20
–0.2
07279-004
0
1V
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TIME (ns)
Figure 4. Driver Large Signal Response; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
07279-007
VOLTAGE (V)
2V
1.0
–0.2
0.5
Figure 6. 50 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V, 50 Ω Termination
1.8
VOLTAGE (V)
0
07279-006
–0.05
07279-003
0
Figure 7. 100 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
6
1.6
5V
3V
1.4
5
1.2
VOLTAGE (V)
3V
3
2
2V
1.0
0.8
0.6
1V
1V
1
0.4
0
0
2
4
6
8
10
12
TIME (ns)
14
16
18
20
0
Figure 5. Driver Large Signal Response; VH = 1.0 V, 3.0 V, 5.0 V;
VL = 0.0 V; 500 Ω Termination
0
1
2
3
4
5
6
TIME (ns)
7
8
9
Figure 8. Response at 200 MH; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
Rev. C | Page 23 of 51
10
07279-008
–1
0.2
07279-005
VOLTAGE (V)
4
ADATE304
Data Sheet
1.6
0.6
3V
1.4
0.5
1.2
2V
VOLTAGE (V)
0.8
0.6
1V
0.2
0.1
0.4
0.5V
0
0.2
0
1
2
3
4
5
6
7
8
9
10
TIME (ns)
–0.1
07279-009
0
0.3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TIME (ns)
07279-012
VOLTAGE (V)
0.4
1.0
Figure 12. Driver Active (VH and VL) to and from VTERM Transition;
VH = 1.0 V, VT = 0.5 V, VL = 0.0 V
Figure 9. 300 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
1.2
1.0
2V
0.9
1.0
0.8
0.8
VOLTAGE (V)
VOLTAGE (V)
0.7
0.6
0.5
1V
0.4
0.3
0.6
0.4
0.2
0.5V
0.2
0
0.5
1.0
1.5
2.0
2.5
3.0
TIME (ns)
3.5
4.0
4.5
5.0
–0.2
07279-010
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TIME (ns)
07279-013
0
0.1
Figure 13. Driver Active (VH and VL) to and from VTERM Transition;
VH = 2.0 V, VT = 1.0 V, VL = 0.0 V
Figure 10. 400 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V,
VL = 0.0 V; 50 Ω Termination
1.6
1.2
1.4
1.0
1.2
1.0
VOLTAGE (V)
VOLTAGE (V)
0.8
0.6
0.4
0.8
0.6
0.4
0.2
0.2
250
300
FREQUENCY (MHz)
350
07279-011
200
–0.2
0
2
4
6
8
10
TIME (ns)
Figure 11. Driver Toggle Rate, VH = 2.0 V, VL = 0.0 V, 50 Ω Termination
Rev. C | Page 24 of 51
12
14
16
18
20
07279-014
0
0
Figure 14. Driver Active (VH and VL) to and from VTERM Transition;
VH = 3.0 V, VT = 1.5 V, VL = 0.0 V
Data Sheet
ADATE304
20
20
2V POS
0
TRAILING EDGE ERROR (ps)
0.2V POS
–20
–40
–60
–60
2
3
4
PULSEWIDTH (ns)
5
6
7
8 9 10
–100
1
2
3
4
PULSEWIDTH (ns)
5
6
7
8 9 10
07279-018
1
Figure 15. Driver Minimum Pulse Width; VH = 0.2 V, VL = 0.0 V
Figure 18. Driver Minimum Pulse Width; VH = 2.0 V, VL = 0.0 V
20
20
0.5V NEG
–20
0.5V POS
TRAILING EDGE ERROR (ps)
0
0
–40
–60
3V POS
–20
3V NEG
–40
–60
–80
–80
1
2
3
4
PULSEWIDTH (ns)
5
6
7
8 9 10
–100
07279-016
TRAILING EDGE ERROR (ps)
–40
1
Figure 16. Driver Minimum Pulse Width; VH = 0.5 V, VL = 0.0 V
2
3
4
PULSE WIDTH (ns)
5
6
7
8 9 10
07279-019
–80
2V NEG
–20
–80
07279-015
TRAILING EDGE ERROR (ps)
0.2V NEG
0
Figure 19. Driver Minimum Pulse Width; VH = 3.0 V, VL = 0.0 V
1.0
20
1V NEG
0.5
LINEARITY ERROR (mV)
1V POS
–20
–40
–60
0
–0.5
–1.0
–100
1
2
3
4
PULSEWIDTH (ns)
5
6
7
8 9 10
–2.0
–2
–1
0
1
2
3
4
5
DRIVER OUTPUT VOLTAGE (V)
Figure 20. Driver VH Linearity Error
Figure 17. Driver Minimum Pulse Width; VH = 1.0 V, VL = 0.0 V
Rev. C | Page 25 of 51
6
7
07279-020
–1.5
–80
07279-017
TRAILING EDGE ERROR (ps)
0
ADATE304
Data Sheet
120
1.0
100
0
–0.5
–1.0
–1
0
1
2
3
4
DRIVER OUTPUT VOLTAGE (V)
5
6
60
40
20
0
–20
–2
07279-021
–1.5
–2
80
–1
0
1
2
3
VDUTx (V)
4
5
6
7
07279-024
DRIVER OUTPUT CURRENT (mA)
LINEARITY ERROR (mV)
0.5
Figure 24. Driver Output Current Limit; Driver Programmed to −1.25 V;
VDUTx Swept from −1.25 V to +6.75 V
Figure 21. Driver VL Linearity Error
0.8
20
0.6
0
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
0
1
2
3
4
5
DRIVER OUTPUT VOLTAGE (V)
6
7
Figure 22. Driver VT Linearity Error
–60
–80
–100
–1
0
1
2
3
VDUTx (V)
4
5
6
7
Figure 25. Driver Output Current Limit; Driver Programmed to 6.75 V;
VDUTx Swept from −1.25 V to +6.75 V
8
48.0
7
47.8
6
LINEARITY ERROR (mV)
47.6
47.4
47.2
47.0
46.8
46.6
5
4
3
2
1
0
–1
46.4
–40
–20
0
20
DRIVER OUTPUT CURRENT (mA)
40
60
–3
–1
0
1
2
3
4
VL PROGRAMMED VOLTAGE (V)
Figure 26. HVOUT VL Linearity Error
Figure 23. Driver Output Resistance vs. Output Current
Rev. C | Page 26 of 51
5
6
07279-026
–2
46.2
–60
07279-023
DRIVER OUTPUT RESISTANCE (Ω)
–40
–120
–2
07279-022
–1.2
–2
–20
07279-025
DRIVER OUTPUT CURRENT (mA)
LINEARITY ERROR (mV)
0.4
Data Sheet
ADATE304
1.0
3
RISE INPUT
2
0.8
0
RISE SHMOO
VOLTAGE (V)
LINEARITY ERROR (mV)
1
–1
–2
–3
0.6
0.4
–4
FALL SHMOO
0.2
–5
–6
6
7
13
12
10
11
8
9
VL PROGRAMMED VOLTAGE (V)
14
07279-027
5
0
Figure 27. HVOUT VHH Linearity Error
0
0.6
1.2
1.8
2.4
3.0
TIME (ns)
07279-030
FALL INPUT
–7
Figure 30. Comparator Shmoo, 1.0 V Input, 0.7 ns (10% to 90%) Input,
50 Ω Terminated
1.0
80
RISE INPUT
0.8
60
50
VOLTAGE (V)
40
30
RISE SHMOO
0.6
0.4
20
FALL SHMOO
10
0.2
0
3
2
VHVOUT (V)
1
4
5
6
07279-028
0
0
0
0.6
2.4
1.8
3.0
TIME (ns)
Figure 31. Comparator Shmoo, 1.5 V Input, 1.0 ns (10% to 90%) Input,
50 Ω Terminated
Figure 28. HVOUT VH Current Limit; VH = −0.1 V;
VHVOUT Swept from −0.1 V to +6.0 V
80
1.6
RISE INPUT
60
40
1.2
VOLTAGE (V)
20
0
–20
RISE SHMOO
0.8
0.4
–40
FALL SHMOO
–60
FALL INPUT
–80
5
6
7
8
9
10
11
VHVOUT (V)
12
13
14
Figure 29. HVOUT VHH Current Limit; VHH = 10.0 V;
VHVOUT Swept from −5.9 V to +14.1 V
15
0
07279-029
HVOUT DRIVER CURRENT (mA)
1.2
07279-031
FALL INPUT
–10
–1
0
0.6
1.2
1.8
TIME (ns)
2.4
3.0
07279-032
HVOUT DRIVER CURRENT (mA)
70
Figure 32. Comparator Shmoo, 1.5 V Input, 1.0 ns (10% to 90%) Input,
50 Ω Terminated
Rev. C | Page 27 of 51
ADATE304
Data Sheet
10
0.6
0.4
0
LINEARITY ERROR (mV)
–20
–30
–40
1V POS
–50
1V NEG
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–60
2
3
4
PULSEWIDTH (ns)
5
6
7
–1.6
–2
07279-035
1
8 9 10
Figure 33. Comparator Minimum Pulse Width, 1.0 V
0
1
2
3
4
5
PROGRAMMED THRESHOLD VOLTAGE (V)
6
7
Figure 36. Comparator Threshold Linearity
–2.5
DIFFERENTIAL COMPARATOR OFFSET (mV)
100
TOTAL
75
50
25
RISING
0
FALLING
–25
–50
0.5
1.0
1.5
2.0
INPUT SLEWRATE (10%-90%) (ns)
2.5
–2.6
–2.7
–2.8
–2.9
–3.0
–3.1
–3.2
–2
07279-036
PROPAGATION DELAY VARIATION (ps)
–1
07279-038
–1.4
–70
Figure 34. Comparator Slew Rate Dispersion, Input Swing = 1.5 V,
Comparator Threshold = 0.75 V
–1
0
1
2
3
INPUT COMMON-MODE VOLTAGE (V)
4
07279-039
TRAILING EDGE ERROR (ps)
0.2
–10
5
Figure 37. Differential Comparator CMRR
15
1.8
1.6
10
LOAD CURRENT (mA)
1.4
VOLTAGE (V)
1.2
1.0
0.8
0.6
0.4
5
0
–5
–10
0
5
10
15
20
25
TIME (ns)
30
35
40
45
50
–15
–2
07279-037
0
Figure 35. Comparator Output Waveform, COMP_QH0P, COMP_QH0N
Rev. C | Page 28 of 51
–1
0
1
2
VDUTx (V)
3
4
5
6
Figure 38. Active Load Commutation Response; VCOM = 2.0 V;
IOH = IOL = 12 mA
07279-040
0.2
ADATE304
6
4
5
2
4
0
3
–2
2
–4
1
–6
0
2
4
6
8
ACTIVE LOAD CURRENT (mA)
10
12
0
–2
Figure 39. Active Load Current Linearity
–1
0
1
2
3
VDUTx (V)
4
5
6
7
30
40
07279-044
IDUTx (nA)
6
07279-041
LINEARITY ERROR (µA)
Data Sheet
Figure 42. DUTx Pin Leakage in High-Z Mode
0.8
40
0.6
20
0.2
LINEARITY ERROR (µA)
LINEARITY ERROR (mV)
0.4
0
–0.2
–0.4
–0.6
–0.8
0
–20
–40
–60
–80
–1.0
0
1
2
3
4
VCOM VOLTAGE (V)
5
6
7
–120
–40
07279-042
0.8
6.0
0.6
LINEARITY ERROR (µA)
5.5
5.0
4.5
4.0
3.5
0.4
0.2
0
–0.2
–0.4
–1
0
1
2
3
VDUTx (V)
4
5
6
7
–0.6
–2.0
07279-043
IDUTx (nA)
–20
–10
0
10
20
PMU OUTPUT CURRENT (mA)
Figure 43. PMU Force Current Range A Linearity
Figure 40. Active Load VCOM Linearity
3.0
–2
–30
–1.5
–1.0
–0.5
0
0.5
1.0
PMU OUTPUT CURRENT (mA)
1.5
Figure 44. PMU Force Current Range B Linearity
Figure 41. DUTx Pin Leakage in Low Leakage Mode
Rev. C | Page 29 of 51
2.0
07279-046
–1.4
–1
07279-045
–100
–1.2
ADATE304
Data Sheet
4
0.06
3
PMU VOLTAGE ERROR (mV)
0.02
0
–0.02
–0.04
1
0
–1
–2
–3
–0.15
–0.10 –0.05
0
0.05
0.10
PMU OUTPUT CURRENT (mA)
0.15
0.20
–4
–40
07279-047
–0.06
–0.20
2
Figure 45. PMU Force Current Range C Linearity
–30
–20
–10
0
10
IDUTx (mA)
20
30
40
07279-050
LINEARITY ERROR (µA)
0.04
Figure 48. PMU Force Voltage Range A Output Voltage Error at
6.75 V vs. Output Current
4
0.006
3
PMU VOLTAGE ERROR (mV)
0.002
0
–0.002
–0.004
1
0
–1
–2
0.020
–4
–40
07279-048
0.015
Figure 46. PMU Force Current Range D Linearity
–30
–20
–10
0
10
IDUTx (mA)
20
30
40
07279-051
–3
–0.006
–0.020 –0.015 –0.010 –0.005
0
0.005 0.010
PMU OUTPUT CURRENT (mA)
Figure 49. PMU FV Range A Output Voltage Error at −1.25 V
vs. Output Current
0.0006
0.6
0.0004
PMU VOLTAGE ERROR (mV)
0.4
0.0002
0
–0.0002
–0.0004
0.2
0
–0.2
–0.0006
–0.4
–0.0008
–0.0020 –0.0015 –0.0010 –0.0050 0
0.0050 0.0010 0.0015 0.0020
PMU OUTPUT CURRENT (mA)
–0.6
–2.0
Figure 47. PMU Force Current Range E Linearity
07279-049
LINEARITY ERROR (µA)
2
–1.5
–1.0
–0.5
0
0.5
IDUTx (mA)
1.0
1.5
2.0
07279-052
LINEARITY ERROR (µA)
0.004
Figure 50. PMU FV Range B Output Voltage Error at 6.75 V vs. Output Current
Rev. C | Page 30 of 51
Data Sheet
ADATE304
0.7
0.6
0.6
PMU CURRENT ERROR (µA)
0.2
0
–0.2
–0.4
0.4
0.3
0.2
0.1
0
–1.5
–1.0
–0.5
0
0.5
IDUTx (mA)
1.0
1.5
2.0
–0.1
–2
07279-053
–0.6
–2.0
0.5
Figure 51. PMU FV Range B Output Voltage Error at −1.25 V
vs. Output Current
–1
0
1
2
3
VDUTx (V)
4
5
6
07279-056
PMU VOLTAGE ERROR (mV)
0.4
7
Figure 54. PMU FI Range B Output Current Error at −2 mA vs. Output Voltage;
Output Voltage Is Pulled Externally
5
0.7
0.6
0
PMU CURRENT ERROR (µA)
–10
–15
–20
–25
0.3
0.2
0.1
0
–0.1
–0.2
–1
0
1
2
3
VDUTx (V)
4
5
6
7
–0.3
–2
07279-054
–30
–2
0.4
Figure 52. PMU FI Range A Output Current Error at −32 mA vs. Output
Voltage; Output Voltage Is Pulled Externally
–1
0
1
2
3
VDUTx (V)
4
5
6
07279-057
PMU CURRENT ERROR (µA)
0.5
–5
7
Figure 55. PMU FI Range B Output Current Error at +2 mA vs. Output Voltage;
Output Voltage Is Pulled Externally
10
0.0025
0
0.0020
PMU CURRENT ERROR (µA)
–20
–30
–40
–50
–60
–70
0.0010
0.0005
0
–0.0005
–80
–1
0
1
2
3
VDUTx (V)
4
5
6
7
–0.0010
–2
07279-055
–90
–2
0.0015
Figure 53. PMU FI Range A Output Current Error at +32 mA vs. Output
Voltage; Output Voltage Is Pulled Externally
–1
0
1
2
3
VDUTx (V)
4
5
6
7
07279-058
PMU CURRENT ERROR (µA)
–10
Figure 56. PMU FI Range E Output Current Error at −2 μA vs. Output Voltage;
Output Voltage Is Pulled Externally
Rev. C | Page 31 of 51
ADATE304
Data Sheet
0.0020
(100mV/DIV)
PMU CURRENT ERROR (µA)
0.0015
0.0010
0.0005
C1
–1
0
1
2
3
VDUTx (V)
4
5
6
7
Figure 57. PMU FI Range E Output Current Error at +2 μA vs. Output Voltage;
Output Voltage Is Pulled Externally
(500ps/DIV)
07279-062
–0.0005
–2
07279-059
0
Figure 60. Eye Diagram, 400 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
0.5
PMU VOLTAGE ERROR (mV)
0.4
(100mV/DIV)
0.3
0.2
C1
0.1
0
1
2
VDUTx (V)
3
4
5
Figure 61. Eye Diagram, 600 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
(200mV/DIV)
Figure 58. PMU Measure Current Range B CMRR,
Externally Pulling 1 mA, FVMI
C1
(1ns/DIV)
07279-061
(100mV/DIV)
(200ps/DIV)
07279-063
–1
C1
(500ps/DIV)
Figure 59. Eye Diagram, 200 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
07279-065
–0.1
–2
07279-060
0
Figure 62. Eye Diagram, 400 Mbps, PRBS31; VH = 2.0 V, VL = 0.0 V
Rev. C | Page 32 of 51
Data Sheet
ADATE304
SPI DETAILS
tCH
SCLK
tCL
tCSSA
tCSSD
tCSHA
tCSHD
CS
tCSW
tDH
tDS
SDOUT
DATA[15]
DATA[14]
DO_15LAST
DO_14LAST
CH[1]
R/W
DO_13LAST
DO_12LAST
ADDR[1]
DO_2LAST
ADDR[0]
DO_1LAST
DO_0LAST
07279-067
SDIN
tDO
Figure 63. SPI Timing Diagram
Table 17. Serial Peripheral Interface Timing Requirements
Symbol
tCH
tCL
tCSHA
tCSSA
tCSHD
tCSSD
tDH
tDS
tDO
tCSW
tCSTP
1
Parameter
SCLK minimum high
SCLK minimum low
CS assert hold
CS assert setup
CS deassert hold
CS deassert setup
SDIN hold
SDIN setup
SDOUT data out
CS minimum between assertions 1
CS minimum directly after a read request
Minimum delay after CS is deasserted before SCLK can be
stopped (not shown in Figure 63); this allows any internal
operations to complete
An extra cycle is needed after a read request to prime the read data into the SPI shift register.
Rev. C | Page 33 of 51
Min
9.0
9.0
3.0
3.0
3.0
3.0
3.0
3.0
Max
15.0
2
3
16
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK cycles
SCLK cycles
SCLK cycles
ADATE304
Data Sheet
DEFINITION OF SPI WORD
Table 18. Channel Selection
The SPI can accept variable length words, depending on the
operation. At most, the word length equals 24 bits: 16 bits of
data, two channel selects, one read/write (R/W) selector, and a
5-bit address.
Channel 1
0
Channel 0
0
0
1
1
1
0
1
Depending on the operation, the data can be smaller or, in the
case of a read operation, nonexistent.
Channel Selected
NOP (no channel selected, no register
changes)
Channel 0 selected
Channel 1 selected
Channel 0 and Channel 1 selected
Table 19. R/W Definition
R/W
0
Description
Current register specified by address shifts out of
SDOUT on next shift operation
Current data written to the register specified by
address and channel select
1
Example 1: 16-Bit Write
DATA[15:0]
CH[1:0]
R/W
07279-068
Write 16 bits of data to a register or DAC; ignore unused MSBs. For example, Bit 15 and Bit 14 are ignored, and Bit 13 through Bit 0 are
applied to the 14-bit DAC.
ADDR[4:0]
Figure 64. 16-Bit Write
Example 2: 14-Bit Write
DATA[13:0]
CH[1:0]
R/W
ADDR[4:0]
07279-069
Write 14 bits of data to the DAC.
Figure 65. 14-Bit Write
Example 3a: 2-Bit Write
DATA[1:0]
CH[1:0]
R/W
ADDR[4:0]
07279-070
Write two bits of data to the 2-bit register.
Figure 66. 2-Bit Write
Example 3b: 2-Bit Write
DATA[15:0]
CH[1:0]
R/W
ADDR[4:0]
07279-071
Write two bits of data to the 2-bit register. Bit 15 through Bit 2 are ignored and Bit 1 through Bit 0 are applied to the register.
Figure 67. 2-Bit Write
Example 4: Read Request
DATA[15:0]
CH[1:0]
R/W = 0
ADDR[4:0]
CH[1:0]
R/W
ADDR[4:0]
Figure 68. Read Request
Rev. C | Page 34 of 51
07279-072
Read request and follow with a second instruction (can be NOP) to clock out the data.
Data Sheet
ADATE304
WRITE OPERATION
CS
INPUT
SCLK
INPUT
SDIN
INPUT
DATA[2] DATA[1] DATA[0]
DATA[15] DATA[14] DATA[13]
0
1
2
13
14
15
CH[1]
CH[0]
R/W
16
17
18
SDOUT
OUTPUT
ADDR[4]
19
ADDR[3]
20
ADDR[2]
21
ADDR[1]
22
X
ADDR[0]
24
23
25
X
07279-073
NOTES
1. R/W = 1.
2. X = DON’T CARE.
Figure 69. 16-Bit SPI Write
CS
INPUT
SCLK
INPUT
SDIN
INPUT
DATA[1] DATA[0]
0
SDOUT
OUTPUT
1
CH[1]
CH[0]
R/W
2
3
4
X
ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
5
6
7
8
9
10
11
X
07279-074
NOTES
1. R/W = 1.
2. X = DON’T CARE.
Figure 70. 2-Bit SPI Write
Rev. C | Page 35 of 51
ADATE304
Data Sheet
READ OPERATION
If another operation is shifted in, it must shift in at least eight bits of
data to read back the previous specified data. The NOP address can
be used for this read if there is no need to read/write another
register. To maintain the clarity of the operation, it is strongly
recommended that the NOP address be used for all reads.
The read operation is a two-stage operation. First, a word is shifted
in, specifying which register to read. CS is deasserted for three
clock cycles, and then a second word is shifted in to obtain the
readback data. This second word can be either another operation or
an NOP address.
Any register read that is fewer than 16 bits has zeros filled in the
top bits to make it a 16-bit word.
CS
INPUT
SCLK
INPUT
SDIN
INPUT
X
READ INSTRUCTION
SDOUT
OUTPUT
X
NOP
X
READ DATA
07279-075
X
NOTES
1. X = DON’T CARE.
Figure 71. SPI Read Overview
CS
INPUT
SCLK
INPUT
SDIN
INPUT
DATA[15:0], VALUE IS A DON’T CARE
0
1
2
13
14
CH[1]
CH[0]
R/W
16
17
18
15
SDOUT
OUTPUT
X
ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
19
20
21
22
23
24
25
23
24
25
07279-076
X
NOTES
1. X = DON’T CARE.
Figure 72. SPI Read—Details of Read Request
CS
INPUT
SCLK
INPUT
SDIN
INPUT
DATA[15:0], VALUE IS A DON’T CARE
0
SDOUT
OUTPUT
1
2
RDATA[15] RDATA[14]
13
RDATA[2]
CH[1]
16
14
15
RDATA[1]
RDATA[0]
CH[0]
17
ADDR[4:0] = 0x00 (NOP)
R/W = 1
18
19
21
22
X
X
07279-077
NOTES
1. RDATA IS THE REGISTER VALUE BEING READ.
2. X = DON’T CARE.
20
Figure 73. SPI Read—Details of Read Out
Rev. C | Page 36 of 51
Data Sheet
ADATE304
RESET OPERATION
The ADATE304 contains an asynchronous reset feature. The
ADATE304 can be reset to the default values shown in Table 20
by utilizing the RST pin.
To initiate the reset operation, deassert the RST pin for a
minimum of 100 ns and deassert the CS pin for a minimum of
two SCLK cycles.
100ns
MINIMUM
RST
SCLK
MINIMUM OF TWO SCLK EDGES AFTER ASSERTING RST BEFORE RESUMING NORMAL OPERATION.
Figure 74. Reset Operation
Rev. C | Page 37 of 51
07279-078
CS
ADATE304
Data Sheet
REGISTER MAP
The ADDR[4:0] bits determine the destination register of the data being written to the ADATE304.
Table 20. Register Selection
DATA[15:0]
N/A 1
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[15:0]
DATA[2:0]
DATA[2:0]
DATA[9:0]
DATA[2:0]
DATA[0]
DATA[1:0]
DATA[1:0]
DATA[2:0]
N/A
1
CH[1:0]
N/A
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1]
CH[0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
N/A
R/W
N/A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
N/A
ADDR[4:0]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14 to 0x1F
Register Selected
NOP
VH DAC level
VL DAC level
VT/VCOM DAC level
VOL DAC level
VOH DAC level
VCH DAC level
VCL DAC level
V(IOH ) DAC level
V(IOL ) DAC level
OVD high level
OVD low level
PMUDAC level
PE/PMU enable
Channel state
PMU state
PMU measure enable
Differential comparator enable
16-bit DAC monitor
OVD_CHx alarm mask
OVD_CHx alarm state
Reserved
N/A means not applicable.
Rev. C | Page 38 of 51
Reset State
N/A
4096d
4096d
4096d
4096d
4096d
4096d
4096d
4096d
4096d
4096d
4096d
16384d
000b
000b
0d
000b
0b
00b
01b
N/A
N/A
Data Sheet
ADATE304
DETAILS OF REGISTERS
Table 21. PE/PMU Enable (ADDR[4:0] = 0x0C)
Bit
DATA[2]
Name
PMU enable
DATA[1]
Force VT
DATA[0]
PE disable
Description
0 = disable PMU force output and clamps, place PMU in MV mode
1 = enable PMU force output
When set to 0, the PMU state bits are ignored, except for the PMU sense path (DATA[7])
0 = normal driver operation
1 = force driver to VT
See Table 29 for complete functionality of this bit
0 = enable driver functions
1 = disable driver (low leakage)
See Table 29 for complete functionality of this bit
Table 22. Channel State (ADDR[4:0] = 0x0D)
Bit
DATA[2]
Name
HV mode select
DATA[1]
Load enable
DATA[0]
Driver high-Z or VT
Description
0 = HV driver in low impedance.
1 = enable HV driver.
This bit affects Channel 0 only. Ensure that the Channel 0 bit in SPI write is active.
Channel 1 bit in SPI write is don’t care.
0 = disable load.
1 = enable load.
See Table 29 for complete functionality of this bit.
0 = enable Driver high-Z function.
1 = enable Driver VTERM function.
See Table 29 for complete functionality of this bit.
Table 23. PMU State (ADDR[4:0] = 0x0E) 1, 2
Bit
DATA[9:8]
Name
PMU input selection
DATA[7]
PMU sense path
DATA[6]
DATA[5]
Reserved
PMU clamp enable
DATA[4]
PMU measure voltage or current
DATA[3]
PMU force voltage or current
DATA[2:0]
PMU range
1
2
Description
00 = VDUTGND (calibrated for 0.0 V voltage reference)
01 = 2.5 V + VDUTGND (calibrated for 0.0 A current reference)
1X = PMUDAC
0 = internal sense
1 = external sense
0 = disable clamps
1 = enable clamps
0 = measure voltage mode
1 = measure current mode
0 = force voltage mode
1 = force current mode
0XX = 2 μA range
100 = 20 μA range
101 = 200 μA range
110 = 2 mA range
111 = 32 mA range
Note that when ADDR[4:0] = 0x0C, the PMU enable bit (DATA[2]) = 0, PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage mode.
PMU State DATA[9:8] and DATA[6:0] are ignored, and only the DATA[7] PMU sense path is valid.
X means don’t care.
Rev. C | Page 39 of 51
ADATE304
Data Sheet
Table 24. PMU Measure Enable (ADDR[4:0] = 0x0F) 1
Bit
DATA[2:1]
Name
MEASOUT01 select
DATA[0]
MEASOUT01 output enable
1
Description
00 = PMU MEASOUT Channel 0
01 = PMU MEASOUT Channel 1
10 = Temperature sensor ground reference
11 = Temperature sensor
0 = MEASOUT01 is tristated
1 = MEASOUT01 is enabled
This register is written to or read from when either of the CH[1:0] bits is 1.
Table 25. Differential Comparator Enable (ADDR[4:0] = 0x10) 1
Bit
DATA[0]
1
Name
Differential Comparator Enable
Description
0 = differential comparator is disabled; the Channel 0 normal window
comparator (NWC) outputs are located on Channel 0
1 = differential comparator is enabled; the differential comparator outputs
are located on Channel 0
This register is written to or read from when either of the CH[1:0] bits is 1.
Table 26. DAC16_MON (16-Bit DAC Monitor) (ADDR[4:0] = 0x11) 1
Bit
DATA[1]
Name
16-Bit DAC mux enable
DATA[0]
16-Bit DAC mux select
1
Description
0 = 16-bit DAC mux is tristated
1 = 16-bit DAC mux is enabled
0 = 16-bit DAC Channel 0
1 = 16-bit DAC Channel 1
This register is written to or read from when either of the CH[1:0] bits is 1.
Table 27. OVD_CHx Alarm Mask (ADDR[4:0] = 0x12)
Bit
DATA[1]
Name
PMU mask
DATA[0]
OVD mask
Description
0 = disable PMU alarm flag
1 = enable PMU alarm flag
0 = disable OVD alarm flag
1 = enable OVD alarm flag
Table 28. OVD_CHx Alarm State (ADDR[4:0] = 0x13) 1
Bit
DATA[2]
Name
PMU clamp flag
DATA[1]
OVD high flag
DATA[0]
OVD low flag
1
Description
0 = PMU is not clamped
1 = PMU is clamped
0 = DUT voltage < OVD high voltage
1 = DUT voltage > OVD high voltage
0 = DUT voltage > OVD low voltage
1 = DUT voltage < OVD low voltage
This register is a read-only register.
Rev. C | Page 40 of 51
Data Sheet
ADATE304
USER INFORMATION
POWER SUPPLY CONSIDERATIONS
Power Supply Decoupling
Power Supply Sequencing
The ADATE304 is a high performance device that requires
close attention to power supply decoupling to deliver the best
performance. The use of full power planes with low inductance
capacitors placed as close to the power pins as possible is recommended. The following power connections are the most important:
It is recommended that the power supplies be brought up in the
following order:
1.
2.
3.
4.
5.
Grounds (DGND, AGND, VREF_GND)
VSS
VCC, VCOMP_VTT, and VREF
VDD
VPLUS
If the HVOUT pin is not used, the VPLUS supply can be
connected to VDD.
VPLUS to AGND (for the HVOUT driver)
VDD to VSS near the DUTx pin (for the driver)
VDD and VSS to AGND near the DUTx pin (for the
comparators)
VCC to DGND (for the digital)
Additionally, large bulk capacitors (that is, 10 μF) must be used
on every power supply on the printed circuit board (PCB).
TRUTH TABLES
Table 29. Driver and Load Truth Table1
PE Disable
DATA[0]
ADDR[4:0] = 0x0C
1
Registers
Force VT
Load Enable
DATA[1]
DATA[1]
ADDR[4:0] = 0x0C ADDR[4:0] = 0x0D
X
X
Driver High-Z/VT
DATA[0]
ADDR[4:0] = 0x0D
X
DATAx
X
RCVx
X
Driver State
High-Z without clamps
Load State
Power-down
0
0
1
0
X
0
X
0
X
0
X
0
VT
VL
Power-down
Power-down
0
0
0
0
0
0
0
0
0
1
1
0
High-Z with clamps
VH
Power-down
Power-down
0
0
0
0
0
0
0
1
1
0
1
0
High-Z with clamps
VL
Power-down
Power-down
0
0
0
0
0
0
1
1
0
1
1
0
VT
VH
Power-down
Power-down
0
0
0
0
0
1
1
0
1
0
1
0
VT
VL
Power-down
Active off
0
0
0
0
1
1
0
0
0
1
1
0
High-Z with clamps
VH
Active on
Active off
0
0
0
0
1
1
0
1
1
0
1
0
High-Z with clamps
VL
Active on
Active on
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
0
1
High-Z with clamps
VH
High-Z with clamps
Active on
Active on
Active on
1
Signals
X means don’t care.
Table 30. HVOUT Truth Table1
HVOUT Mode Select
DATA[2]
ADDR[4:0] =0x0D
1
1
1
0
1
Channel 0
RCV
1
0
0
X
Channel 0
DATA
X
0
1
X
HVOUT Driver Output
VHH mode; VHH = (VT + 1 V) × 2 + DUTGND (Channel 0 VT DAC)
VL (Channel 0 VL DAC)
VH (Channel 0 VH DAC)
Disabled (HVOUT pin set to 0 V low impedance)
X means don’t care.
Rev. C | Page 41 of 51
ADATE304
Data Sheet
Table 31. Comparator Truth Table
Differential
Comparator Enable
DATA[0]
ADDR[4:0] = 0x10
0
1
COMP_QH0
Normal window mode
Logic high: VOH0 < VDUT0
Logic low: VOH0 > VDUT0
Differential comparator mode
Logic high: VOH0 < VDUT0 − VDUT1
Logic low: VOH0 > VDUT0 − VDUT1
COMP_QL0
Normal window mode
Logic high: VOL0 < VDUT0
Logic low: VOL0 > VDUT0
Differential comparator mode
Logic high: VOL0 < VDUT0 − VDUT1
Logic low: VOL0 > VDUT0 − VDUT1
Rev. C | Page 42 of 51
COMP_QH1
Normal window mode
Logic high: VOH1 < VDUT1
Logic low: VOH1 > VDUT1
Normal window mode
Logic high: VOH1 < VDUT1
Logic low: VOH1 > VDUT1
COMP_QL1
Normal window mode
Logic high: VOL1 < VDUT1
Logic low: VOL1 > VDUT1
Normal window mode
Logic high: VOL1 < VDUT1
Logic low: VOL1 > VDUT1
Data Sheet
ADATE304
DETAILS OF DACS vs. LEVELS
•
There are ten 14-bit DACs per channel. These DACs provide
levels for the driver, comparator, load currents, VHH buffer, OVD,
and clamp levels. There are three versions of output levels as
follows:
•
−2.5 V to +7.5 V and tracks DUTGND. Controls the VH,
VL, VT/VCOM/VHH, VOH, VOL, VCH, and VCL levels.
•
−3.0 V to +7.0 V and tracks DUTGND. Controls the
OVD levels.
−2.5 V to +7.5 V and does not track DUTGND. Controls
the IOH and IOL levels.
There is one 16-bit DAC per channel. This DAC provides the
levels for the PMU. The output level is as follows:
•
−2.5 V to +7.5 V and tracks DUTGND; controls the
PMU levels.
Table 32. Level Transfer Functions
DAC Transfer Function
VOUT = 2.0 × (VREF − VREF_GND) × (Code/(214)) − 0.5 × (VREF − VREF_GND) + VDUTGND
Code = [VOUT − VDUTGND + 0.5 × (VREF − VREF_GND)] × [(214)/(2.0 × (VREF − VREF_GND))]
VOUT = 4.0 × (VREF − VREF_GND) × (Code/(214)) − 1.0 × (VREF − VREF_GND) + 2.0 + VDUTGND
Code = [VOUT − VDUTGND − 2.0 + 1.0 × (VREF − VREF_GND)] × [(214)/(4.0 × (VREF − VREF_GND))]
VOUT = 2.0 × (VREF − VREF_GND) × (Code/(214)) − 0.6 × (VREF − VREF_GND) + VDUTGND
Code = [VOUT − VDUTGND + 0.6 × (VREF − VREF_GND)] × [(214)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(214)) − 0.5 × (VREF − VREF_GND)] × (0.012/5.0)
Code = [(IOUT × (5.0/0.012)) + 0.5 × (VREF − VREF_GND)] × [(214)/(2.0 × (VREF − VREF_GND))]
VOUT = 2.0 × (VREF − VREF_GND) × (Code/(216)) − 0.5 × (VREF − VREF_GND) + VDUTGND
Code = [VOUT − VDUTGND + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) − 0.5 × (VREF − VREF_GND) − 2.5] × (0.050/5.0)
Code = [(IOUT × (5.0/0.050)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) − 0.5 × (VREF − VREF_GND) − 2.5] × (0.004/5.0)
Code = [(IOUT × (5.0/0.004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) − 0.5 × (VREF − VREF_GND) − 2.5] × (0.0004/5.0)
Code = [(IOUT × (5.0/0.0004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) − 0.5 × (VREF − VREF_GND) − 2.5] × (0.00004/5.0)
Code = [(IOUT × (5.0/0.00004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) − 0.5 × (VREF − VREF_GND) − 2.5] × (0.000004/5.0)
Code = [(IOUT × (5.0/0.000004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
1
Programmable Range 1
(All 0s to All 1s)
−2.5 V to +7.5 V
−3.0 V to +17.0 V
Levels
VH, VL, VT/VCOM,
VOL, VOH, VCH, VCL
VHH
−3.0 V to +7.0 V
OVD
−6 mA to +18 mA
IOH, IOL
−2.5 V to +7.5 V
PMUDAC
−50 mA to +50 mA
PMUDAC
(PMU FI Range A)
PMUDAC
(PMU FI Range B)
PMUDAC
(PMU FI Range C)
PMUDAC
(PMU FI Range D)
PMUDAC
(PMU FI Range E)
−4 mA to +4 mA
−400 μA to +400 μA
−40 μA to +40 μA
−4 μA to +4 μA
Programmable range includes a margin outside the specified part performance, allowing for offset/gain calibration.
Table 33. Load Transfer Functions
Load Level
IOL
IOH
1
Transfer Function 1
V(IOL)/5 V × 12 mA
V(IOH)/5 V × 12 mA
V(IOH)and V(IOL) DAC levels are not referenced to DUTGND.
Table 34. PMU Transfer Functions
PMU Mode
Force Voltage
Measure Voltage
Force Current
Measure Current
1
Transfer Functions
VOUT = PMUDAC
VMEASOUT01 = VDUTx (internal sense) or VMEASOUT01 = VPMUS_CHx (external sense)
IOUT = [PMUDAC − (VREF/2)]/(R 1 × 5)
VMEASOUT01 = (VREF/2) + VDUTGND + (IDUTx × 5 × R1)
R = 15.5 Ω for Range A; 250 Ω for Range B; 2.5 kΩ for Range C; 25 kΩ for Range D; 250 kΩ for Range E.
Table 35. PMU User Required Capacitors
Capacitor
220 pF
220 pF
330 pF
330 pF
Location
Across Pin C10 (FFCAP_0B) and Pin E10 (FFCAP_0A)
Across Pin C1 (FFCAP _1B) and Pin E1 (FFCAP_1A)
Between GND and Pin B9 (SCAP0)
Between GND and Pin B2 (SCAP1)
Rev. C | Page 43 of 51
ADATE304
Data Sheet
Table 36. Temperature Sensor
Temperature
0K
300 K
xK
Output
0V
3V
(x K) × 10 mV/K
Table 37. Power Supply Ranges
Parameter
Nominal VDD
Nominal VSS
Driver
VH range
VL range
VT range
Functional Amplitude
Reflection Clamp
VCH Range
VCL Range
Comparator Input Voltage Range
Active Load VCOM Range
PMU
Force Voltage Range
Measure Voltage Range
Force Current Voltage Range
Measure Current Voltage Range
Low Clamp Range
High Clamp Range
OVD
Range 1
+10.75 V
−5.00 V
Range 2
+10.0 V
−5.75 V
−1.15 V to +6.75 V
−1.25 V to +6.65 V
−1.25 V to +6.75 V
8.0 V
−1.9 V to +6.0 V
−2.0 V to +5.9 V
−2.0 V to +6.0 V
8.0 V
−1.0 V to +6.75 V
−1.25 V to +5.75 V
−1.25 V to +6.75 V
−1.00 V to +6.50 V
−1.0 V to +6.0 V
−2.0 V to +5.0 V
−2.0 V to +6.0 V
−1.75 V to +5.75 V
−1.25 V to +6.75 V
−1.25 V to +6.75 V
−1.25 V to +6.75 V
−1.25 V to +6.75 V
−1.25 V to +4.75 V
0.75 V to 6.75 V
−2.25 V to +7.0 V
−2.0 V to +6.0 V
−2.0 V to +6.0 V
−2.0 V to +6.0 V
−2.0 V to +6.0 V
−2.0 V to +4.0 V
0.0 V to 6.0 V
−3.0 V to +7.0 V
Table 38. Default Test Conditions (Range 1)
Name
VH DAC Level
VL DAC Level
VT/VCOM DAC Level
VOL DAC Level
VOH DAC Level
VCH DAC Level
VCL DAC Level
IOH DAC Level
IOL DAC Level
OVD Low DAC Level
OVD High DAC Level
PMUDAC DAC Level
PE/PMU Enable
Channel State
PMU State
PMU Measure Enable
Differential Comparator Enable
16-Bit DAC Monitor
OVD_CHx Alarm Mask
Data Input
Receive Input
DUTx Pin
Comparator Output
Default Test Condition
+2.0 V
+0.0 V
+1.0 V
−1.0 V
+6.0 V
+7.5 V
−2.5 V
0.0 A
0.0 A
−2.5 V
+6.5 V
0.0 V
0x0000: PMU disabled, VT not forced through driver, PE enabled
0x0000: HV mode disabled, load disabled, VTERM inactive
0x0000: Input of DUTGND, internal sense, clamps disabled, FVMV, Range E
0x0000: MEASOUT01 pin tristated
0x0000: Normal window comparator mode
0x0000: DAC16_MON tristated
0x0000: disable alarm functions
Logic low
Logic low
Unterminated
Unterminated
Rev. C | Page 44 of 51
Data Sheet
ADATE304
RECOMMENDED PMU MODE SWITCHING
SEQUENCES
PMU Force Voltage Mode to PMU Force Current Mode
To minimize any possible aberrations and voltage spikes on the
DUT output, specific mode switching sequences are recommended
for the following transitions:
•
•
•
PMU disable to PMU enable.
PMU force voltage mode to PMU force current mode.
PMU force current mode to PMU force voltage mode.
PMU Disable to PMU Enable
Step 1. Table 42 lists the state of registers in force voltage mode.
Table 42.
Register
PE/PMU Enable
Register, ADDR[4:0]
= 0x0C
PMU State Register,
ADDR[4:0] = 0x0E
Note that, in Table 39 through Table 49, X indicates the don’t
care bit.
Step 1. Table 39 lists the state of the registers in PMU disabled
mode.
Table 39.
Register
PE/PMU Enable
Register, ADDR[4:0]
= 0x0C
PMU State
Register, ADDR[4:0]
= 0x0E
Bits
DATA[2]
Setting
0
DATA[9:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2:0]
XX
X
X
X
X
X
XXX
Bits
DATA[2]
Setting
1
DATA[9:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2:0]
XX
X
X
X
X
0
XXX
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 43).
Table 43.
Register
PMU State Register,
ADDR[4:0] = 0x0E
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 40).
Bits
DATA[9:8]
Setting
01
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
X
X
X
X
1
DATA[2:0]
0XX
Table 40.
Register
PMU State
Register,
ADDR[4:0] =
0x0E
Bits
DATA[9:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
Setting
1X or
00
X
X
X
X
0
DATA[2:0]
XXX
Comments
Set desired input
selection
Table 44.
Register
VIN 16-Bit DAC,
ADDR[4:0] = 0x0B
This bit must be set
to force voltage mode
to reduce aberrations
Set desired range
Setting
1
Bits
DATA[15:0]
Setting
X
Comments
Update the VIN
16-Bit DAC
register to the
desired value
Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 45).
Table 45.
Table 41.
Bits
DATA[2]
Set to force
current mode
The 2 μA range
has the
minimum offset
current
Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 44).
Step 3. Write to Register ADDR[4:0] = 0x0C (see Table 41).
Register
PE/PMU Enable
Register,
ADDR[4:0] = 0x0C
Comments
Set 2.5 V +
DUTGND input
selection
Comments
PMU is now enabled
in force voltage
mode
Register
PMU State Register,
ADDR[4:0] = 0x0E
Rev. C | Page 45 of 51
Bits
DATA[9:8]
Setting
1X
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2:0]
X
X
X
X
1
XXX
Comments
Set VIN input
selection
Set to the
desired current
range
ADATE304
Data Sheet
Transition from PMU Force Current Mode to PMU Force
Voltage Mode
Step 1. Table 46 lists the state of the registers in force current mode.
Table 46.
Register
PE/PMU Enable Register, ADDR[4:0] = 0x0C
PMU State Register, ADDR[4:0] = 0x0E
Bits
DATA[2]
DATA[9:8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2:0]
Setting
1
XX
X
X
X
X
1
XXX
Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 48).
Table 48.
Register
VIN 16-Bit DAC,
ADDR[4:0] = 0x0B
Setting
00
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
X
X
X
X
0
DATA[2:0]
XXX
Comments
Update the VIN
16-Bit DAC
register to the
desired value
Table 49.
Register
PMU State Register,
ADDR[4:0] = 0x0E
Table 47.
Bits
DATA[9:8]
Setting
X
Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 49).
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 47).
Register
PMU State Register,
ADDR[4:0] = 0x0E
Bits
DATA[15:0]
Comments
Set DUTGND input
selection
Set to force
voltage mode
Set to the desired
current range
Rev. C | Page 46 of 51
Bits
DATA[9:8]
Setting
1X
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
X
X
X
X
0
DATA[2:0]
XXX
Comments
Set VIN input
selection
Force voltage
mode
Data Sheet
ADATE304
BLOCK DIAGRAMS
VCL
VCH
PE DISABLE DATA[0] (ADDR[4:0] = 0x0C)
FORCES SWITCH OPEN WHEN 1
VH
ROUT = 47Ω
(TRIMMED)
DRIVER
VL
DUT
DATA
VT
DRIVER HIGH-Z/VT DATA[0]
(ADDR[4:0] = 0x0D)
VT BUFFER WHEN 1
HIGH-Z BUFFER WHEN 0
V(IOH)
RCV
VCOM
FORCE VT DATA[1] (ADDR[4:0] = 0x0C)
OVERRIDES THE RCV PIN AND FORCES
VTERM MODE ON THE DRIVER AND LOAD
POWER-DOWN MODE
V(IOL)
07279-079
LOAD ENABLE DATA[1] (ADDR[4:0] = 0x0D)
FORCES SWITCHES OPEN AND POWERS
DOWN LOAD WHEN 0
Figure 75. Driver and Load Block Diagram
~5Ω
VHH = (VT + 1V) × 2 + DUTGND
HVOUT
VH
VL
DATA
48Ω
HV MODE SELECT DATA[2]
(ADDR [4:0] = 0x0D) DISABLES
HV DRIVER AND FORCES
0V ON HVOUT WHEN 0
Figure 76. HVOUT Driver Output Stage
Rev. C | Page 47 of 51
07279-080
RCV (SHOWN IN
RCV = 0 STATE)
ADATE304
Data Sheet
DUT0
VOL0
VOH0
DUT1
DU T0 –
DUT0–
DU T1
DUT1
DIFFERENTIAL
BUFFER
VOL0
–
VOH
NWC
+
+
VOL
NWC
–
–
VOH
DMC
+
2:1 COMP_QH0
MUX
DIFFERENTIAL
COMPARATOR ENABLE
DATA[0] (ADDR[4:0] = 0x10)
2:1 COMP_QL0
MUX
+
VOL
DMC
–
07279-081
VOH0
NOTES
1. DIFFERENTIAL COMPARATOR ONLY ON CHANNEL 0.
Figure 77. Comparator Block Diagram
COMPARATOR
OUTPUT (AB)
VTT = 3.3V
RECEIVER
OUT HIGH = 1.55V
50Ω
OUT CM = 1.42V
OUT LOW = 1.30V
50Ω
GND
Figure 78. Comparator Output Scheme
Rev. C | Page 48 of 51
07279-082
100Ω
Data Sheet
ADATE304
PMU MEASURE V/I DATA[4]
(ADDR[4:0] = 0x0E)
PMU SENSE PATH DATA[7]
(ADDR[4:0] = 0x0E)
EXTERNAL DUT
SENSE PIN
MEASURE V
MEASURE I
MEASOUT01 SELECT DATA[2:1]
(ADDR[4:0] = 0x0F)
MUX
MUX
PMU FORCE V/I DATA[3]
(ADDR[4:0] = 0x0E)
MEASURE
OUT
CH[1] PMU V/I
TEMP SENSE
GND REF
TEMP SENSE
10kΩ
IN-AMP G = 5
2.5 + DUTGND
REF
MUX
MUX
MEASOUT01 OUTPUT
ENABLE DATA[0]
(ADDR[4:0] = 0x0F)
ONE PER DEVICE
225kΩ
2µA
PMU INPUT SELECTION DATA[9:8]
(ADDR[4:0] = 0x0E)
20µA
22.5kΩ
200µA
2.25kΩ
250Ω DUTx
15.5Ω
2mA
MV
VIN
2.5V + DUTGND
DUTGND
FFCAP_xA
MUX
PMU CLAMP ENABLE DATA[5]
(ADDR[4:0] = 0x0E)
330pF
SCAPx
(EXTERNAL)
32mA BUFFER
FFCAP_xB
CRA = 220pF
VCH
VCL
32mA
NOTES
1. SWITCHES CONNECTED WITH DOTTED LINES REPRESENT PMU RANGE DATA[2:0] (ADDR[4:0] = 0x0E); WHEN PMU ENABLE D ATA[2] = 0 (ADDR[4:0] = 0x0C), ALL
SWITCHES OPEN AND PMU POWERS DOWN.
2. THE EXTERNAL SENSE PATH MUST CLOSE THE LOOP TO ENABLE THE CLAMPS TO OPERATE CORRECTLY.
3. 32mA RANGE HAS ITS OWN OUTPUT BUFFER.
4. 32mA BUFFER TRISTATES WHEN NOT IN USE.
Figure 79. PMU Block Diagram
Rev. C | Page 49 of 51
07279-083
MEASURE V
(AT OUTPUT OF
SENSE MUX)
ADATE304
Data Sheet
(ADDR[4:0] = 0x12) DATA[0]
OVD MASK ENABLES OVD
FLAGS TO ALARM OVD_CHx PIN
6.5V 1
OVD HIGH LEVEL
DAC (ADDR[4:0] = 0x0A, CH[1])
OVD_CHx
SHORT-CIRCUIT
CURRENT = 100µA
DUT
ADATE304
–2.5V 1
OVD LOW LEVEL
DAC (ADDR[4:0] = 0x0A, CH[0])
PMU
V/I CLAMP
FLAG
(ADDR[4:0] = 0x12) DATA[1]
PMU MASK ENABLES PMU V/I
FLAG TO ALARM OVD_CHx PIN
(ADDR[4:0] = 0x13) 2 DATA[2] DATA[1] DATA[0]
OVD HIGH/LOW LEVEL DAC IS SHARED BY EACH CHANNEL; THEREFORE, ONLY ONE OVD HIGH/LOW VOLTAGE
LEVEL CAN BE SET PER CHIP. THE OVD DACs PROVIDE A VOLTAGE RANGE OF –3V TO +7V. THE RECOMMENDED
HIGH/LOW SETTINGS ARE +6.5V/–2.5V. (THESE VALUES NEED TO BE PROGRAMMED BY THE USER UPON STARTUP/RESET.)
2THIS IS A READ ONLY REGISTER THAT ALLOWS THE USER TO DETERMINE THE CAUSE OF THE ACTIVE OVD FLAG.
Figure 80. OVD Block Diagram
Rev. C | Page 50 of 51
07279-084
1THE
Data Sheet
ADATE304
OUTLINE DIMENSIONS
A1 BALL
CORNER
9.10
9.00 SQ
8.90
A1 BALL
CORNER
10
9
8
7
6
5
4
3
2
1
A
B
C
7.20
BSC SQ
6.731
BSC SQ
D
E
F
0.80
BSC
G
H
J
K
*1.20
1.09
1.00
BOTTOM VIEW
0.90 REF
DETAIL A
DETAIL A
0.36
REF
0.38
0.33
0.28
SEATING
PLANE
0.53
0.48
0.43
BALL DIAMETER
0.83
0.76
0.69
COPLANARITY
0.12
*COMPLIANT TO JEDEC STANDARDS MO-219 WITH
EXCEPTION TO PACKAGE HEIGHT.
07-06-2012-A
TOP VIEW
Figure 81. 84-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-84-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADATE304BBCZ
1
Temperature Range
−40°C to +85°C
Package Description
84-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Z = RoHS Compliant Part.
©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07279-0-10/17(C)
Rev. C | Page 51 of 51
Package Option
BC-84-2
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