ADAU1373BCBZ-RL

Low Power Codec with Speaker and Headphone Amplifier ADAU1373 FEATURES Eight single-ended or four differential analog inputs with PGAs are provided for adjusting the gain from −12 dB to +18 dB. They can be configured for microphones or line level signals. 1 stereo ADC and 2 stereo DACs with sampling rates from 8 kHz to 48 kHz Low power: 7 mW record, 6 mW playback, 48 kHz at 1.8 V 8 single-ended or 4 differential inputs with PGA 2 microphone bias reference voltages with current sense 2 stereo digital microphone inputs Flexible analog input/output mixers 1 stereo differential or 2 stereo single-ended line outputs True ground-centered stereo Class-G headphone amplifier, capable of 2 × 50 mW into 16 Ω at 1.8 V, 10% THD Filterless stereo Class-D speaker amplifier, capable of 2 × 880 mW into 8 Ω at 3.6 V, 10% THD Differential earpiece amplifier capable of driving 32 Ω 2 PLLs, supporting input clocks from 8 kHz to 27 MHz I2C control interface Digital audio processing 3 digital audio input and output ports with ASRC I2S, PCM, right-justified, left-justified modes 4.05 mm × 3.82 mm, 81-ball, 0.4 mm pitch WLCSP package −40°C to +85°C operating temperature range Two stereo digital microphone inputs are supported; four digital microphones can be connected in total. In addition, three serial digital audio input/output ports are provided with asynchronous sample rate converters (ASRCs) to support various sampling rates, allowing for flexible system design in mobile phone applications. The inputs can be mixed and selected before the ADC or configured to bypass the ADC. Two stereo DACs are included, with a flexible mixing option for routing the signals internally. The analog output side consists of line outputs, headphone output, speaker output, and receiver output. Two stereo single-ended line level outputs, which can be configured as two differential outputs, are included. The headphone output is stereo true ground centered (eliminating the need for coupling capacitors), with efficient Class-G (rail switching) architecture. The efficient stereo filterless Class-D switching amplifier provides ~1 W of stereo power for speakers. The differential receiver amplifier can be used to connect the separate receiver speaker. Two PLL blocks, which can lock to the inputs from 8 kHz to 27 MHz, are included. APPLICATIONS The DSP allows system designers to compensate for the real-world limitations of microphones, speakers, amplifiers, and listening environments, resulting in a dramatic improvement in perceived audio quality through equalization, multiband compression, and limiting algorithms. The SigmaStudio™ graphical development tool, which includes audio processing blocks such as filters, mixers, dynamics processors, and amplifiers for fast development of custom signal flows, is used to program the ADAU1373. Mobile phones, tablet PCs, e-books, portable media players GENERAL DESCRIPTION The ADAU1373 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback. The stereo audio ADCs and DACs support sampling rates from 8 kHz to 48 kHz, as well as a digital volume control. IOVDD1 IOVDD2 IOVDD3 IOVDD4 IOVDD5 AVDD DVDD HPVDD CF1 CF2 CPVDD CPVSS SPKVDD FUNCTIONAL BLOCK DIAGRAM PLLA I2 C SPEAKER AMP DAC2 GPIO MODE ADDR SCL SDA SD ANALOG INPUTS HEADPHONE AMP DAC1 EPP EPN LOUT1L/LOUTLP, LOUT2L/LOUTLN LOUT1R/LOUTRP, LOUT2R/LOUTRN LN1FBIN, LN2FBIN HPL SGND HPR SPKLP SPKLN SPKRP SPKRN 08975-023 ADC MCLK1 MCLK2 AIN1L/AIN1P TO AIN4L/AIN4P AIN1R/AIN1N TO AIN4R/AIN4N FDSP MUX MIX MUX MIX MICBIAS1, MICBIAS2 LINEOUT2 LINEOUT1 DGND AGND HPGND SPKGND CM DMIC1_2_DATA DMIC3_4_DATA DMIC_CLK DIGITAL MICROPHONE INPUT OUTPUT MUX GPIO1 GPIO2 GPIO3 GPIO4 JACKDET BCLKA/BCLKB/BCLKC LRCLKA/LRCLKB/LRCLKC SDATAINA/SDATAINB/SDATAINC SDATAOUTA/SDATAOUTB/SDATAOUTC EARPIECE AMP SERIAL DIGITAL AUDIO INTERFACE A Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. ADAU1373 TABLE OF CONTENTS Features .............................................................................................. 1  3D Enhancement........................................................................ 66  Applications....................................................................................... 1  Digital Automatic Level Control (ALC).................................. 67  General Description ......................................................................... 1  Interrupt Request (IRQ)............................................................ 69  Functional Block Diagram .............................................................. 1  Control Ports................................................................................... 70  Revision History ............................................................................... 6  I2C Port ........................................................................................ 70  Specifications..................................................................................... 7  Register Map Summary (Default) ................................................ 73  Power Supplies .............................................................................. 7  Register Bit Descriptions........................................................... 77  Audio Performance ...................................................................... 7  INPUT_MODE Register ........................................................... 77  Power Consumption .................................................................. 15  AIN1L_CTRL Register .............................................................. 78  Digital Filter/SRC Characteristics ............................................ 17  AIN1R_CTRL Register.............................................................. 80  Digital Input/Output Specifications......................................... 17  AIN2L_CTRL Register .............................................................. 82  Digital Timing Specifications ................................................... 18  AIN2R_CTRL Register.............................................................. 84  Absolute Maximum Ratings.......................................................... 21  AIN3L_CTRL Register .............................................................. 86  Thermal Resistance .................................................................... 21  AIN3R_CTRL Register.............................................................. 88  ESD Caution................................................................................ 21  AIN4L_CTRL Register .............................................................. 90  Pin Configuration and Function Descriptions........................... 22  AIN4R_CTRL Register.............................................................. 92  Typical Performance Characteristics ........................................... 25  LLINE1_OUT Register.............................................................. 94  Detailed Block Diagram ................................................................ 38  RLINE1_OUT Register ............................................................. 96  Theory of Operation ...................................................................... 39  LLINE2_OUT Register.............................................................. 98  Analog Inputs.............................................................................. 39  RLINE2_OUT Register ........................................................... 100  Mixer Block ................................................................................. 41  LCD_OUT (Speaker) Register ............................................... 102  Analog Outputs........................................................................... 41  RCD_OUT (Speaker) Register ............................................... 104  Headphone Output..................................................................... 43  LHP_OUT Register.................................................................. 106  Speaker Output ........................................................................... 44  RHP_OUT Register ................................................................. 108  Analog-to-Digital Converter (ADC) ....................................... 45  ADC_GAIN Register............................................................... 110  Digital-to-Analog Converter (DAC) ....................................... 45  LADC_MIXER Register.......................................................... 111  Clock Generation and Distribution ......................................... 45  RADC_MIXER Register ......................................................... 112  Sampling Rates............................................................................ 49  LLINE1MIX Register............................................................... 113  Setting the PLL and Clock Rates .............................................. 49  RLINE1MIX Register .............................................................. 114  Digital Microphone Input Interface......................................... 52  LLINE2MIX Register............................................................... 115  Digital Audio Interface .............................................................. 53  RLINE2MIX Register .............................................................. 116  Serial Data Input/Output Formats ........................................... 54  LCDMIX (Speaker Output) Register..................................... 117  Asynchronous Sample Rate Converter.................................... 55  RCDMIX (Speaker Output) Register..................................... 118  Mix/Mux...................................................................................... 56  LHPMIX Register..................................................................... 119  Fixed Function DSP (FDSP) ..................................................... 57  RHPMIX Register .................................................................... 120  High-Pass Filters (HPFs) ........................................................... 57  EPMIX Register ........................................................................ 121  Dynamic Range Control (DRC)............................................... 58  HP_CTRL Register .................................................................. 122  Programmable Seven-Band Equalizer..................................... 61  HP_CTRL2 Register ................................................................ 123  Coefficient Calculations ............................................................ 63  LS_CTRL (Speaker) Register .................................................. 124  Bass Enhancement...................................................................... 65  EPCONTROL Register............................................................ 125  Rev. 0 | Page 2 of 296 ADAU1373 MICBIAS_CTRL1 Register..................................................... 126  DEEMP_CTRL Register ..........................................................162  MICBIAS_CTRL2 Register..................................................... 127  SRC_DAI_A_CTRL Register ..................................................163  OUTPUT_CONTROL (Line) Register................................. 128  SRC_DAI_B_CTRL Register...................................................164  PWDN_CTRL1 Register......................................................... 129  SRC_DAI_C_CTRL Register ..................................................165  PWDN_CTRL2 Register......................................................... 130  DIN_MIX_CTRL0 (to FDSP Channel 0 Input) Register.......................................................................................166  PWDN_CTRL3 Register......................................................... 131  DPLLA_CTRL Register........................................................... 132  PLLA_CTRL1 Register............................................................ 133  PLLA_CTRL2 Register............................................................ 133  PLLA_CTRL3 Register............................................................ 134  PLLA_CTRL4 Register............................................................ 134  PLLA_CTRL5 Register............................................................ 135  PLLA_CTRL6 Register............................................................ 136  DPLLB_CTRL Register ........................................................... 137  PLLB_CTRL1 Register ............................................................ 139  PLLB CTRL2 Register ............................................................. 139  PLLB_CTRL3 Register ............................................................ 139  PLLB_CTRL4 Register ............................................................ 140  PLLB_CTRL5 Register ............................................................ 140  PLLB_CTRL6 Register ............................................................ 141  HEADDECT Register.............................................................. 142  ADC_DAC_STATUS Register ............................................... 143  MIC_JACK_STATUS Register ............................................... 144  CHIP_FAULT_STATUS Register .......................................... 145  ADC_SETTING Register........................................................ 146  CLK1_SOURCE_DIV Register.............................................. 147  CLK1_OUTPUT_DIV Register............................................. 148  CLK2_SOURCE_DIV Register.............................................. 150  CLK2_OUTPUT_DIV Register............................................. 151  DAIA Register........................................................................... 153  DAIB Register........................................................................... 154  DAIC Register........................................................................... 155  BCLKDIVA Register................................................................ 156  BCLKDIVB Register................................................................ 157  BCLKDIVC Register................................................................ 158  SRCA_RATIOA Register ........................................................ 159  SRCA_RATIOB Register......................................................... 159  SRCB_RATIOA Register......................................................... 160  SRCB_RATIOB Register ......................................................... 160  SRCC_RATIOA Register ........................................................ 161  SRCC_RATIOB Register......................................................... 161  DIN_MIX_CTRL1 (to FDSP Channel 1 Input) Register.......................................................................................167  DIN_MIX_CTRL2 (to FDSP Channel 2 Input) Register.......................................................................................168  DIN_MIX_CTRL3 (to FDSP Channel 3 Input) Register.......................................................................................169  DIN_MIX_CTRL4 (to FDSP Channel 4 Input) Register.......................................................................................170  DOUT_MIX_CTRL0 (to Digital Audio Interface A Recording Output) Register ....................................................171  DOUT_MIX_CTRL1 (to Digital Audio Interface B Recording Output) Register ....................................................172  DOUT_MIX_CTRL2 (to Digital Audio Interface C Recording Output) Register ....................................................173  DOUT_MIX_CTRL3 (to DAC1 Playback Input) Register.......................................................................................174  DOUT_MIX_CTRL4 (to DAC2 Playback Input) Register.......................................................................................175  VOLMOD1 Register.................................................................176  VOLMOD2 Register.................................................................177  DAIA_PBL_VOL Register .......................................................178  DAIA_PBR_VOL Register.......................................................178  DAIB_PBL_VOL Register .......................................................179  DAIB_PBR_VOL Register .......................................................179  DAIC_PBL_VOL Register .......................................................180  DAIC_PBR_VOL Register.......................................................180  DAIA_RECL_VOL Register ....................................................181  DAIA_RECR_VOL Register....................................................181  DAIB_RECL_VOL Register ....................................................182  DAIB_RECR_VOL Register....................................................182  DAIC_RECL_VOL Register ....................................................183  DAIC_RECR_VOL Register....................................................183  PBAL_VOL Register.................................................................184  PBAR_VOL Register ................................................................184  PBBL_VOL Register .................................................................185  PBBR_VOL Register.................................................................185  RECL_VOL Register.................................................................186  RECR_VOL Register ................................................................186  Rev. 0 | Page 3 of 296 ADAU1373 DRECL_VOL Register ............................................................. 187  DRC3_CTRL2 Register ........................................................... 221  DRECR_VOL Register............................................................. 187  DRC3_CTRL3 Register ........................................................... 222  VOL_GAIN1 (DAI Playback) Register ................................. 188  DRC3_CTRL4 Register ........................................................... 223  VOL_GAIN2 (DAI Record) Register .................................... 189  DRC3_CTRL5 Register ........................................................... 223  VOL_GAIN3 (Codec) Register .............................................. 190  DRC3_CTRL6 Register ........................................................... 224  HPF_CTRL Register ................................................................ 191  DRC3_CTRL7 Register ........................................................... 224  BASS1 Register.......................................................................... 192  DRC3_CTRL8 Register ........................................................... 225  BASS2 Register.......................................................................... 193  DRC3_CTRL9 Register ........................................................... 225  DRC1_CTRL1 Register ........................................................... 194  DRC3_CTRL10 Register ......................................................... 226  DRC1_CTRL2 Register ........................................................... 195  DRC3_CTRL11 Register ......................................................... 226  DRC1_CTRL3 Register ........................................................... 196  DRC3_CTRL12 Register ......................................................... 228  DRC1_CTRL4 Register ........................................................... 197  DRC3_CTRL13 Register ......................................................... 229  DRC1_CTRL5 Register ........................................................... 197  DRC3_CTRL14 Register ......................................................... 230  DRC1_CTRL6 Register ........................................................... 198  DRC3_CTRL15 Register ......................................................... 231  DRC1_CTRL7 Register ........................................................... 198  DRC3_CTRL16 Register ......................................................... 232  DRC1_CTRL8 Register ........................................................... 199  MDRC_PRE_FILTER Register............................................... 233  DRC1_CTRL9 Register ........................................................... 199  MDRC_SPL_CTRL (Splitter Frequencies) Register............ 233  DRC1_CTRL10 Register ......................................................... 200  MDRC_CTRL Register............................................................ 234  DRC1_CTRL11 Register ......................................................... 200  PRE_HPF1_COEFH (MSB) Register .................................... 234  DRC1_CTRL12 Register ......................................................... 202  PRE_HPF1_COEFL (LSB) Register ...................................... 235  DRC1_CTRL13 Register ......................................................... 203  PRE_HPF2_COEFH (MSB) Register .................................... 235  DRC1_CTRL14 Register ......................................................... 204  PRE_HPF2_COEFL (LSB) Register ...................................... 235  DRC1_CTRL15 Register ......................................................... 205  PRE_HPF3_COEFH (MSB) Register .................................... 236  DRC1_CTRL16 Register ......................................................... 206  PRE_HPF3_COEFL (LSB) Register ...................................... 236  DRC2_CTRL1 Register ........................................................... 207  PRE_HPF4_COEFH (MSB) Register .................................... 236  DRC2_CTRL2 Register ........................................................... 208  PRE_HPF4_COEFL (LSB) Register ...................................... 237  DRC2_CTRL3 Register ........................................................... 209  PRE_HPF5_COEFH (MSB) Register .................................... 237  DRC2_CTRL4 Register ........................................................... 210  PRE_HPF5_COEFL (LSB) Register ...................................... 237  DRC2_CTRL5 Register ........................................................... 210  PRE_HPF_CTRL Register ...................................................... 238  DRC2_CTRL6 Register ........................................................... 211  EQ_CTRL1 Register ................................................................ 239  DRC2_CTRL7 Register ........................................................... 211  EQ_CTRL2 Register ................................................................ 240  DRC2_CTRL8 Register ........................................................... 212  E3D_CTRL1 Register .............................................................. 241  DRC2_CTRL9 Register ........................................................... 212  E3D_CTRL2 Register .............................................................. 242  DRC2_CTRL10 Register ......................................................... 213  ALC_CTRL0 Register.............................................................. 243  DRC2_CTRL11 Register ......................................................... 213  ALC_CTRL1 Register.............................................................. 244  DRC2_CTRL12 Register ......................................................... 215  ALC_CTRL2 Register.............................................................. 245  DRC2_CTRL13 Register ......................................................... 216  ALC_CTRL3 Register.............................................................. 246  DRC2_CTRL14 Register ......................................................... 217  ALC_CTRL4 Register.............................................................. 247  DRC2_CTRL15 Register ......................................................... 218  ALC_CTRL5 Register.............................................................. 249  DRC2_CTRL16 Register ......................................................... 219  ALC_CTRL6 Register.............................................................. 251  DRC3_CTRL1 Register ........................................................... 220  FDSP_SEL1 Register ................................................................ 252  Rev. 0 | Page 4 of 296 ADAU1373 FDSP_SEL2 Register................................................................ 253  EQ3_COEF0_HI Register........................................................277  FDSP_SEL3 Register................................................................ 254  EQ3_COEF0_LO Register.......................................................278  FDSP_SEL4 Register................................................................ 255  EQ3_COEF1_HI Register........................................................278  PBALPCTRL1 Register ........................................................... 256  EQ3_COEF1_LO Register.......................................................278  PBBLPCTRL2 Register............................................................ 257  EQ3_COEF2_HI Register........................................................279  DIGMICCTRL Register .......................................................... 259  EQ3_COEF2_LO Register.......................................................279  GPIOSEL1 Register.................................................................. 260  EQ3_COEF3_HI Register........................................................279  GPIOSEL2 Register.................................................................. 261  EQ3_COEF3_LO Register.......................................................280  IRQ_MASK Register ............................................................... 262  EQ3_COEF4_HI Register........................................................280  IRQ_RAW Register.................................................................. 263  EQ3_COEF4_LO Register.......................................................280  IRQ_STATE (After Mask) Register ....................................... 264  EQ4_COEF0_HI Register........................................................281  IRQEN Register........................................................................ 265  EQ4_COEF0_LO Register.......................................................281  PAD_CTRL1 Register.............................................................. 265  EQ4_COEF1_HI Register........................................................281  PAD_CTRL2 Register.............................................................. 266  EQ4_COEF1_LO Register.......................................................282  DIGEN Register........................................................................ 267  EQ4_COEF2_HI Register........................................................282  LPCNTCTRL (Low Power Control Counter) Register....... 268  EQ4_COEF2_LO Register.......................................................282  CHIP_ID_HI Register............................................................. 268  EQ4_COEF3_HI Register........................................................283  CHIP_ID_MID Register ......................................................... 269  EQ4_COEF3_LO Register.......................................................283  CHIP_ID_LOW Register........................................................ 269  EQ4_COEF4_HI Register........................................................283  SOFT_RESET Register ............................................................ 269  EQ4_COEF4_LO Register.......................................................284  Register Map—EQ Coefficients ................................................. 270  EQ5_COEF0_HI Register........................................................284  EQ1_COEF0_HI Register....................................................... 271  EQ5_COEF0_LO Register.......................................................284  EQ1_COEF0_LO Register ...................................................... 271  EQ5_COEF1_HI Register........................................................285  EQ1_COEF1_HI Register....................................................... 271  EQ5_COEF1_LO Register.......................................................285  EQ1_COEF1_LO Register ...................................................... 272  EQ5_COEF2_HI Register........................................................285  EQ1_COEF2_HI Register....................................................... 272  EQ5_COEF2_LO Register.......................................................286  EQ1_COEF2_LO Register ...................................................... 272  EQ5_COEF3_HI Register........................................................286  EQ1_COEF3_HI Register....................................................... 273  EQ5_COEF3_LO Register.......................................................286  EQ1_COEF3_LO Register ...................................................... 273  EQ5_COEF4_HI Register........................................................287  EQ1_COEF4_HI Register....................................................... 273  EQ5_COEF4_LO Register.......................................................287  EQ1_COEF4_LO Register ...................................................... 274  EQ6_COEF0_HI Register........................................................287  EQ2_COEF0_HI Register....................................................... 274  EQ6_COEF0_LO Register.......................................................288  EQ2_COEF0_LO Register ...................................................... 274  EQ6_COEF1_HI Register........................................................288  EQ2_COEF1_HI Register....................................................... 275  EQ6_COEF1_LO Register.......................................................288  EQ2_COEF1_LO Register ...................................................... 275  EQ6_COEF2_HI Register........................................................289  EQ2_COEF2_HI Register....................................................... 275  EQ6_COEF2_LO Register.......................................................289  EQ2_COEF2_LO Register ...................................................... 276  EQ7_COEF0_HI Register........................................................289  EQ2_COEF3_HI Register....................................................... 276  EQ7_COEF0_LO Register.......................................................290  EQ2_COEF3_LO Register ...................................................... 276  EQ7_COEF1_HI Register........................................................290  EQ2_COEF4_HI Register....................................................... 277  EQ7_COEF1_LO Register.......................................................290  EQ2_COEF4_LO Register ...................................................... 277  EQ7_COEF2_HI Register........................................................291  Rev. 0 | Page 5 of 296 ADAU1373 EQ7_COEF2_LO Register ...................................................... 291  Outline Dimensions ..................................................................... 293  Applications Circuit ..................................................................... 292  Ordering Guide............................................................................. 293  REVISION HISTORY 5/11—Revision 0: Initial Version Rev. 0 | Page 6 of 296 ADAU1373 SPECIFICATIONS POWER SUPPLIES Table 1. Parameter SUPPLY VOLTAGE RANGES Analog Digital Input/Output Charge Pump Speaker Amplifier 1 Symbol Min Typ Max Unit AVDD DVDD 1 IOVDD HPVDD SPKVDD 1.62 1.08 1.62 1.62 2.5 1.8 1.2 1.8 1.8 1.98 1.98 3.6 1.98 5.5 V V V V V For applications using DVDD = 1.8 V, IOVDDx ≥ DVDD. AUDIO PERFORMANCE fS = 48 kHz/24 bits, I2S format, AVDD = HPVDD = IOVDDx = 1.8 V, DVDD = 1.2 V, SPKVDD = 3.6 V, 1 kHz sine wave signal, 20 Hz to 20 kHz measurement bandwidth, TA = 25°C, unless otherwise noted. Table 2. Parameter INPUT PROGRAMMABLE GAIN AMPLIFIERS Input Resistance Single-Ended PGA Mode Single-Ended Boost Mode Differential PGA Mode Differential Boost Mode Gain Range PGA Mode Boost Mode Gain Step Size Maximum Input Level Single-Ended PGA Mode Single-Ended Boost Mode Differential PGA Mode Differential Boost Mode Equivalent Input Noise Single-Ended PGA Mode Single-Ended Boost Mode Common-Mode Rejection Ratio Differential PGA Mode Mute Attenuation Test Conditions/Comments Min Typ Max Unit +18 dB gain 0 dB gain −12 dB gain +29 dB gain +9 dB gain 0 dB gain +18 dB gain 0 dB gain −12 dB gain +20 dB gain +9 dB gain 0 dB gain 6.8 30 48 20 20 20 6.8 30 48 20 20 20 kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ Minimum position Maximum position 0 dB position +9 dB position +20 dB position PGA mode −12 +18 0 +9 +20 +1 dB dB dB dB dB dB 0 dB gain 0 dB gain 0 dB gain 0 dB gain 0.545 0.545 1.09 1.09 V rms V rms V rms V rms 0 dB gain, unweighted 20 Hz to 20 kHz +18 dB gain, unweighted 20 Hz to 20 kHz 0 dB gain, unweighted 20 Hz to 20 kHz +20 dB gain, unweighted 20 Hz to 20 kHz 7 28 7 35 μV rms μV rms μV rms μV rms 0 dB gain at 217 Hz Measured at line output reference to full scale (0 dB gain at 1 kHz) 50 80 dB dB Rev. 0 | Page 7 of 296 ADAU1373 Parameter MICROPHONE BIAS Output Voltage Output Current Output Noise PSRR Bias Current Detect Threshold Bias Short-Circuit Detect Threshold MIXER BLOCK Mixer ADC Mute Attenuation Mixer Line Output Mute Attenuation Mixer Headphone Output Mute Attenuation Mixer Speaker Output Mute Attenuation Mixer Earpiece Output Mute Attenuation LINE OUTPUT AMPLIFIER Gain Volume Control Step Size Mute Attenuation Maximum Output Level Single-Ended Mode Differential Mode Output Resistance Common-Mode Voltage DC Offset Ground-Loop Rejection Ratio Test Conditions/Comments Register 0x21, Bits[5:4] (MICB2GAIN); Bits[3:2] (MICB1GAIN) Setting 00 = 2.9 V Setting 01 = 2.2 V Setting 10 = 2.6 V Setting 11 = 1.8 V Min Typ 1.71 2.09 2.47 2.75 6 1.8 2.2 2.6 2.9 Unweighted 20 Hz to 20 kHz AVDD at 217 Hz = 100 mV p-p DVDD at 217 Hz = 100 mV p-p HPVDD at 217 Hz = 100 mV p-p SPKVDD at 217 Hz = 400 mV p-p Register 0x22 and Register 0x23, Bits[1:0] (MICBxCURD) Setting 00 = 150 μA Setting 01 = 330 μA Setting 10 = 510 μA Setting 11 = 700 μA Register 0x22 and Register 0x23, Bits[3:2] (MICBxSHT) Setting 00 = 330 μA Setting 01 = 700 μA Setting 10 = 1000 μA Setting 11 = 1400 μA Max 7 100 100 100 85 V V V V mA μV rms dB dB dB dB 150 330 510 700 μA μA μA μA 330 700 1000 1400 μA μA μA μA 90 dB 90 dB 90 dB 90 dB 90 dB 0 Variable from mute to 0 dB in 32 steps Load = 10 kΩ Load = 10 kΩ At each output pin: LOUT1L, LOUT1R, LOUT2L, and LOUT2R VCM at LOUT1L, LOUT1R, LOUT2L, and LOUT2R Differential mode between LOUTLP and LOUTLN, LOUTRP and LOUTRN Measured by injecting 1000 Hz sine wave,100 mV rms at LNxFBIN; referenced to full-scale output voltage Input Resistance into LNxFBIN Pin Rev. 0 | Page 8 of 296 Unit 90 dB dB dB 0.545 1.09 0.3 V rms V rms Ω AVDD/2 1 V mV 56 dB 120 kΩ Mute 0 ADAU1373 Parameter HEADPHONE AMPLIFIER Gain Volume Control Step Size Mute Attenuation Output Level at 1% THD + N Output Level at 10% THD + N Efficiency DC Offset Output Limiter Threshold Load Resistance Load Capacitance Turn On Time Turn Off Time SPEAKER AMPLIFIER Gain Volume Control Step Size Mute Attenuation Output Power at 1% THD + N Output Power at 10% THD + N Output Power at 1% THD + N Test Conditions/Comments Min Typ Max Unit −69 −69 0 Variable from −69 dB to +6 dB in 32 steps +6 +6 dB dB dB mW mW V rms mW mW V rms % % mV V pk V pk V pk V pk V pk V pk V pk Ω pF ms ms Load = 16 Ω Load = 32 Ω Load = 10 kΩ Load = 16 Ω Load = 32 Ω Load = 10 kΩ POUT = 3 mW, HPVDD = 1.8 V, RL = 16 Ω POUT = 3.5 mW, HPVDD = 1.8 V, RL = 32 Ω HPVDD = 1.8 V, RL = 16 Ω Peak output at HPL, HPR; setting VOUT = 1.1 V peak Peak output at HPL, HPR; setting VOUT = 0.968 V peak Peak output at HPL, HPR; setting VOUT = 0.815 V peak Peak output at HPL, HPR; setting VOUT = 0.56 V peak Peak output at HPL, HPR; setting VOUT = 0.408 V peak Peak output at HPL, HPR; setting VOUT = 0.28 V peak Peak output at HPL, HPR; setting VOUT = 0.23 V peak 12 85 27 24 1.2 50 43 1.2 25 38 ±3 1.1 0.97 0.82 0.56 0.41 0.28 0.23 16 150 17.1 1.9 Setting = 12 dB Setting = 18 dB Variable from mute to 0 dB in 32 steps SPKVDD = 2.5 V, 4 Ω + 15 μH (stereo) SPKVDD = 3.6 V, 4 Ω + 15 μH (stereo) SPKVDD = 4.2 V, 4 Ω + 15 μH (stereo) SPKVDD = 5 V, 4 Ω + 15 μH (stereo) SPKVDD = 2.5 V, 8 Ω + 33 μH (stereo) SPKVDD = 3.6 V, 8 Ω + 33 μH (stereo) SPKVDD = 4.2 V, 8 Ω + 33 μH (stereo) SPKVDD = 5 V, 8 Ω + 33 μH (stereo) SPKVDD = 2.5 V, 4 Ω + 15 μH (stereo) SPKVDD = 3.6 V, 4 Ω + 15 μH (stereo) SPKVDD = 4.2 V, 4 Ω + 15 μH (stereo) SPKVDD = 5 V, 4 Ω + 15 μH (stereo) SPKVDD = 2.5 V, 8 Ω + 33 μH (stereo) SPKVDD = 3.6 V, 8 Ω + 33 μH (stereo) SPKVDD = 4.2 V, 8 Ω + 33 μH (stereo) SPKVDD = 5 V, 8 Ω + 33 μH (stereo) SPKVDD = 2.5 V, 4 Ω + 15 μH (mono) SPKVDD = 3.6 V, 4 Ω + 15 μH (mono) SPKVDD = 4.2 V, 4 Ω + 15 μH (mono) SPKVDD = 5 V, 4 Ω + 15 μH (mono) SPKVDD = 2.5 V, 8 Ω + 33 μH (mono) SPKVDD = 3.6 V, 8 Ω + 33 μH (mono) SPKVDD = 4.2 V, 8 Ω + 33 μH (mono) SPKVDD = 5 V, 8 Ω + 33 μH (mono) Rev. 0 | Page 9 of 296 12 18 Mute 0 90 0.554 1.212 1.679 2.4 0.33 0.71 0.98 1.40 0.691 1.511 2.091 2.99 0.41 0.88 1.22 1.73 0.588 1.285 1.78 2.55 0.34 0.73 1.00 1.43 dB dB dB dB W W W W W W W W W W W W W W W W W W W W W W W W ADAU1373 Parameter Output Power at 10% THD + N Efficiency Average Switching Frequency RDS On DC Offset Load Resistance Recovery Time from Protect Mode Turn On Time Turn Off Time EARPIECE AMPLIFIER Gain Gain Step Size Mute Attenuation Output Level at 1% THD + N Output Power at 10% THD + N DC Offset Test Conditions/Comments SPKVDD = 2.5 V, 4 Ω + 15 μH (mono) SPKVDD = 3.6 V, 4 Ω + 15 μH (mono) SPKVDD = 4.2 V, 4 Ω + 15 μH (mono) SPKVDD = 5 V, 4 Ω + 15 μH (mono) SPKVDD = 2.5 V, 8 Ω + 33 μH (mono) SPKVDD = 3.6 V, 8 Ω + 33 μH (mono) SPKVDD = 4.2 V, 8 Ω + 33 μH (mono) SPKVDD = 5 V, 8 Ω + 33 μH (mono) POUT = 2.4 W, SPKVDD = 5 V, RL = 4 Ω + 15 μH (stereo) POUT = 1.2 W, SPKVDD = 3.6 V, RL = 4 Ω + 15 μH (stereo) POUT = 1.4 W, SPKVDD = 5 V, RL = 8 Ω + 33 μH (stereo) POUT = 0.71 W, SPKVDD = 3.6 V, RL = 8 Ω + 33 μH (stereo) NMOS at 100 mA PMOS at 100 mA Gain = 12 dB, SPKVDD = 3.6 V Mono mode Stereo mode Min 3 4 256 From high-Z (mute) to outputs switching state From output switching to high-Z (mute) state SPKVDD = 2.5 V, load = 8 Ω SPKVDD = 2.5 V, load = 16 Ω SPKVDD = 2.5 V, load = 32 Ω SPKVDD = 3.6 V, load = 8 Ω SPKVDD = 3.6 V, load = 16 Ω SPKVDD = 3.6 V, load = 32 Ω SPKVDD = 5 V, load = 8 Ω SPKVDD = 5 V, load = 16 Ω SPKVDD = 5 V, load = 32 Ω SPKVDD = 2.5 V, load = 8 Ω SPKVDD = 2.5 V, load = 16 Ω SPKVDD = 2.5 V, load = 32 Ω SPKVDD = 3.6 V, load = 8 Ω SPKVDD = 3.6 V, load = 16 Ω SPKVDD = 3.6 V, load = 32 Ω SPKVDD = 5 V, load = 8 Ω SPKVDD = 5 V, load = 16 Ω SPKVDD = 5 V, load = 32 Ω SPKVDD = 3.6 V, load = 32 Ω, gain = 0 dB SPKVDD = 3.6 V, load = 32 Ω, gain = 6 dB SPKVDD = 3.6 V, load = 32 Ω, gain = 12 dB 512 6 6 85 53 66 58 123 103 69 140 110 72 74 91 73 162 134 89 178 142 92 ±1 ±2 ±3 8 9.6 4.1 Rev. 0 | Page 10 of 296 Max 3.5 1.8 0 Load Resistance Turn On Time Turn Off Time Typ 0.733 1.611 2.22 3.18 0.43 0.905 1.25 1.78 89 87 93 92 350 180 210 ±3 12 Unit W W W W W W W W % % % % kHz mΩ mΩ mV Ω Ω ms ms ms dB dB dB mW mW mW mW mW mW mW mW mW mW mW mW mW mW mW mW mW mW mV mV mV Ω ms ms ADAU1373 Parameter ANALOG INPUT → ADC → DIGITAL OUTPUT ADC Resolution Dynamic Range Unweighted (RMS) A-weighted (RMS) Signal-to-Noise Ratio THD + N Offset Error Gain Drift Interchannel Isolation PSRR DIGITAL MICROPHONE INPUT → ADC→ DIGITAL OUTPUT Dynamic Range Unweighted (rms) A-weighted (rms) Signal-to-Noise Ratio THD + N Offset Error Gain Drift Interchannel Isolation PSRR ANALOG INPUT → LINE OUTPUT Dynamic Range Unweighted (RMS) A-weighted (RMS) Signal-to-Noise Ratio THD + N Interchannel Isolation PSRR ANALOG INPUT → HEADPHONE OUTPUT Dynamic Range Signal-to-Noise Ratio THD + N Interchannel Isolation PSRR Test Conditions/Comments All ADCs −60 dBFS input at 1 kHz A-weighted (rms), referred to full-scale output −1 dBFS input at 1 kHz AVDD ripple = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB All other supplies (HPVDD, SPKVDD, DVDD, IOVDDx) = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB Min Typ AVDD ripple = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB All other supplies (HPVDD, SPKVDD, DVDD, IOVDDx) = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB Unit 24 Bits 93 96 96 0.01 ±1 100 85 85 dB dB dB % mV ppm/°C dB dB 85 dB −60 dBFS input at 1 kHz A-weighted (rms) −1 dBFS at 1 kHz Max dB dB 93 96 96 0.01 ±1 100 85 85 dB % mV ppm/°C dB dB 85 dB 91 94 dB dB dB −60 dBFS input at 1 kHz Differential line output, A-weighted (rms), referred to full-scale output VOUT = 1 V, 1 kHz, RL=10 kΩ VOUT = 0.5 V, 1 kHz, RL=10 kΩ AVDD ripple = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB All other supplies (HPVDD, SPKVDD, DVDD, IOVDDx) = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB −60 dBFS input at 1 kHz Unweighted (rms) A-weighted (rms) A-weighted (rms), referred to full-scale output POUT = 27 mW, 1 kHz, RL = 16 Ω HPVDD ripple = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB All other supplies (AVDD, SPKVDD, DVDD, IOVDDx) = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB Rev. 0 | Page 11 of 296 94 0.013 0.017 85 85 % % dB dB 85 dB 96 99 99 0.01 85 85 dB dB dB % dB dB 85 dB ADAU1373 Parameter ANALOG INPUT → SPEAKER OUTPUT Dynamic Range Signal-to-Noise Ratio THD + N Interchannel Isolation PSRR ANALOG INPUT → EARPIECE OUTPUT Dynamic Range Signal-to-Noise Ratio THD + N PSRR DIGITAL INPUT → DAC → MIXER → LINE OUTPUT Dynamic Range Signal-to-Noise Ratio THD + N Full-Scale Output Voltage Interchannel Isolation Interchannel Phase Deviation Digital Volume Control Step Range PSRR DIGITAL INPUT → DAC → MIXER → HEADPHONE OUTPUT Dynamic Range Signal-to-Noise Ratio THD + N Full-Scale Output Voltage Interchannel Isolation Interchannel Phase Deviation Digital Volume Control Step Range Test Conditions/Comments −60 dBFS input at 1 kHz Unweighted (rms) A-weighted (rms) A-weighted (rms), referred to 0.7 W at 3.6 V, RL = 8 Ω SPKVDD = 5 V, POUT = 1 W, 1 kHz, RL = 8 Ω SPKVDD = 3.6 V, POUT = 0.5 W, 1kHz, RL = 8 Ω SPKVDD ripple = 100 mV p-p at 217 Hz, input referred for PGA gain = 12 dB All other supplies (AVDD, HPVDD, DVDD, IOVDDx) = 100 mV p-p at 217 Hz, input referred for PGA gain = 12 dB −60 dBFS input at 1 kHz Unweighted (rms) A-weighted (rms) A-weighted (rms), referred to 40 mW at 3.6 V, RL = 32 Ω POUT = 60 mW, 1 kHz, RL = 8 Ω POUT = 30 mW, 1 kHz, RL = 8 Ω AVDD ripple = 100 mV p-p at 217 Hz, input referred for PGA gain = 12 dB All other supplies (HPVDD, DVDD, SPKVDD, IOVDDx) = 100 mV p-p at 217 Hz, input referred for PGA gain = 12 dB 20 Hz to 20 kHz, −60 dBFS input, unweighted (rms) 20 Hz to 20 kHz, −60 dBFS input, A-weighted (rms) 20 Hz to 20 kHz, A-weighted, relative to full scale At −1 dBFS, 1 kHz Scales linearly with AVDD AVDD ripple = 100 mV p-p at 217 Hz, input referred for PGA gain = 12 dB All other supplies (HPVDD, DVDD, SPKVDD, IOVDDx) = 100 mV p-p at 217 Hz, input referred for PGA gain = 12 dB 20 Hz to 20 kHz, −60 dBFS input, unweighted (rms) 20 Hz to 20 kHz, −60 dBFS input, A-weighted (rms) 20 Hz to 20 kHz, A-weighted, relative to full scale At −1 dBFS, 1 kHz Rev. 0 | Page 12 of 296 Min Typ Max Unit 98 101 101 0.013 0.017 85 85 dB dB dB % % dB dB 85 dB 95 98 98 0.1 0.2 85 dB dB dB % % dB 85 dB 93 96 96 0.01 1.0 100 0.1 dB dB dB % V rms dB Degrees 0.375 95 85 dB dB dB 85 dB 96 99 99 0.01 100 0.1 dB dB dB % V rms dB Degrees 0.375 95 dB dB ADAU1373 Parameter DIGITAL INPUT → DAC → MIXER → SPEAKER OUTPUT Dynamic Range Signal-to-Noise Ratio THD + N Interchannel Isolation Interchannel Phase Deviation Digital Volume Control Step Range DIGITAL INPUT→ DAC → MIXER → EARPIECE OUTPUT Dynamic Range Signal-to-Noise Ratio THD + N Full-Scale Output Voltage Digital Volume Control Step Range REFERENCE Common-Mode Reference Output CHARGE PUMP Supply Voltage Outputs CPVDD Below Supply Switching Threshold Above Supply Switching Threshold CPVSS Below Supply Switching Threshold Above Supply Switching Threshold Switching Frequency Flying Capacitor Value Supply Switching Threshold Start-Up Time PLLx Input Frequency Lock Time (Analog PLL) Jitter (Cycle-to-Cycle) rms Test Conditions/Comments 20 Hz to 20 kHz, −60 dBFS input, unweighted (rms) 20 Hz to 20 kHz, −60 dBFS input, A-weighted (rms) 20 Hz to 20 kHz, A-weighted, relative to full scale At −1 dBFS, 1 kHz 20 Hz to 20 kHz, −60 dBFS input, unweighted (rms) 20 Hz to 20 kHz, −60 dBFS input, A-weighted (rms) 20 Hz to 20 kHz, A-weighted, relative to full scale At −1 dBFS, 1 kHz Scales linearly with SPKVDD; SPKVDD = 3.6 V CM pin 1.62 0.47 Typ Max Unit 93 96 97 0.01 100 0.1 dB dB dB % dB Degrees 0.375 95 dB dB 93 96 97 0.1 1.53 dB dB dB % V rms 0.375 95 dB dB AVDD/2 V 1.8 1.98 V 0.9 1.8 V V −0.9 −1.8 500 1 0.4 0.5 V V kHz μF V ms 0.008 10 3 27 MHz ms 470 280 200 ps ps ps 310 260 310 210 ps ps ps ps Measured at GPIOx with master clock output set at 256 × fS (12.288 MHz, where fS = 48 kHz) Analog PLL Only (DPLL Bypassed) 8 MHz Input (Fractional Mode) 27 MHz Input (Fractional Mode) 12.288 MHz Input (Integer Mode) Digital PLL + Analog PLL 8 kHz LRCLKx Input 96 kHz LRCLKx Input 512 kHz (8 kHz × 64) BCLKx Input 2.048 MHz (8 kHz × 256) MCLKx Input MCLKx Clock Output Frequency GPIOx Drive Capability Min 49.152 IOVDDx = 1.8 V IOVDDx = 3.3 V 4 20 Rev. 0 | Page 13 of 296 MHz mA mA ADAU1373 Parameter IRQ RESPONSE TIME ASRCx_IRQ_STATUS Test Conditions/Comments One clock cycle = 1/256 × fS = 81.4 ns at fS = 48 kHz Typ 4 3 DRC_IRQ_STATUS, PLL_UNLOCK_STATUS HP_CFG_STATUS, HP_DECT_STATUS, AFAULT_STATUS JACK DETECT Debounce Time DIGITAL MICROPHONE INPUT Clock Output Frequency Decimator Operating Frequency Min 256 ms + 3 Depends on internal sample rate = 64 × fS Depends on internal sample rate = 128 × fS Rev. 0 | Page 14 of 296 Max Unit Clock cycles Clock cycles Clock cycles 128 ms 3.072 6.144 MHz MHz ADAU1373 POWER CONSUMPTION Table 3 lists some commonly used paths, as well as the typical current that is consumed by the part under quiescent conditions. The total power consumed includes the power in the loads, as specified. TA = 25°C, line output load = 10 kΩ, headphone stereo = 16 Ω, speaker load = 8 Ω + 33 μH, and earpiece = 32 Ω, audio port configured as the slave, fS = 48 kHz, MCLK = 12.288 MHz, unless otherwise specified. Table 3. Mode POWER-DOWN No Clocks MCLKx = 12.288 MHz POWER-UP No Clocks (Default State) MCLKx = 12.288 MHz, PLL Bypassed With Clocks (PLL Enabled, LRCLKA = 48 kHz, DPLL + APLL Enabled, Master Mode) ANALOG BYPASS (NO CLOCKS) Analog Input → Line Output Analog Input → Headphone Output Analog Input → Speaker Output (Mono) Analog Input → Speaker Output (Stereo) Analog Input → Earpiece Output AVDD (V) DVDD (V) HPVDD (V) SPKVDD (V) IOVDD (V) IAVDD (mA) IDVDD (mA) IHPVDD (mA) ISPKVDD (mA) IIOVDD (mA) Total Power (mW) 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 1.08 1.2 1.2 1.98 1.08 1.2 1.2 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 2.5 3.6 4.2 5.5 2.5 3.6 4.2 5.5 1.62 1.8 1.8 3.63 1.62 1.8 1.8 3.63 0.008 0.012 0.0124 0.0178 0.032 0.0378 0.0378 0.045 0.01 0.011 0.011 0.0149 0.19 0.22 0.22 0.4 0.001 0.0014 0.0015 0.002 0.001 0.0014 0.0015 0.002 0.0014 0.0035 0.0055 0.0147 0.0014 0.0035 0.0055 0.0147 0.008 0.008 0.008 0.008 0.017 0.017 0.017 0.017 0.04184 0.06432 0.07572 0.178596 0.2897 0.37776 0.38844 1.02762 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 1.08 1.2 1.2 1.98 1.08 1.2 1.2 1.98 1.08 1.2 1.2 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 2.5 3.6 4.2 5.5 2.5 3.6 4.2 5.5 2.5 3.6 4.2 5.5 1.62 1.8 1.8 3.63 1.62 1.8 1.8 3.63 1.62 1.8 1.8 3.63 0.31 0.32 0.32 0.34 0.34 0.35 0.35 0.37 1.77 1.83 1.83 1.91 0.046 0.0495 0.0495 0.083 0.23 0.256 0.256 0.47 1.06 1.26 1.26 2.34 0.0012 0.0018 0.0018 0.0023 0.0013 0.0018 0.0018 0.0023 0.0013 0.0018 0.0018 0.0023 0.041 0.065 0.079 0.118 0.041 0.065 0.079 0.118 0.041 0.065 0.079 0.118 0.008 0.008 0.008 0.008 0.017 0.017 0.017 0.017 1.72 1.72 1.72 1.72 0.669284 0.88704 0.98484 1.520134 0.931346 1.20504 1.30284 2.378464 6.903206 8.13924 8.23704 15.31215 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.08 1.2 1.2 1.98 1.08 1.2 1.2 1.98 1.08 1.2 1.2 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 2.5 3.6 4.2 5.5 2.5 3.6 4.2 5.5 2.5 3.6 4.2 1.62 1.8 1.8 3.63 1.62 1.8 1.8 3.63 1.62 1.8 1.8 1.62 1.66 1.66 1.72 1.33 1.35 1.35 1.37 1.44 1.46 1.47 0.045 0.049 0.049 0.083 0.045 0.05 0.05 0.083 0.045 0.05 0.05 0.0012 0.0018 0.0018 0.0023 1.35 1.37 1.37 1.39 0.0012 0.0018 0.0018 0.041 0.068 0.086 0.128 0.041 0.065 0.079 0.118 3.58 4.47 4.92 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 2.790404 3.30924 3.42564 4.307534 4.50566 5.2044 5.3022 6.30718 11.3463 18.79764 23.38764 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 1.98 1.08 1.2 1.2 1.98 1.08 1.2 1.2 1.98 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 5.5 2.5 3.6 4.2 5.5 2.5 3.6 4.2 5.5 3.63 1.62 1.8 1.8 3.63 1.62 1.8 1.8 3.63 1.49 1.98 2.02 2.01 2.04 0.89 0.91 0.91 0.92 0.083 0.045 0.05 0.05 0.083 0.045 0.049 0.049 0.083 0.0023 0.0012 0.0018 0.0018 0.0023 0.0012 0.0018 0.0018 0.0023 5.94 5.67 7.17 7.99 9.77 0.82 0.9 0.94 1.07 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 35.81813 17.4461 29.52564 37.25364 57.97213 3.555304 4.95444 5.66244 7.904534 Rev. 0 | Page 15 of 296 ADAU1373 Mode RECORD PATH (MCLK = 12.288 MHz) Analog Input → ADC → Digital Audio Interface A Digital Microphone Input → Decimator → Digital Audio Interface A PLAYBACK PATH Digital Input → DAC → Line Output Digital Input → DAC → Headphone Output Digital Input → DAC → Speaker Output Digital Input → DAC → Earpiece Output AVDD (V) DVDD (V) HPVDD (V) SPKVDD (V) IOVDD (V) IAVDD (mA) IDVDD (mA) IHPVDD (mA) ISPKVDD (mA) IIOVDD (mA) Total Power (mW) 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 1.08 1.2 1.2 1.98 1.08 1.2 1.2 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 2.5 3.6 4.2 5.5 2.5 3.6 4.2 5.5 1.62 1.8 1.8 3.63 1.62 1.8 1.8 3.63 2.73 3.42 3.4 3.78 0.038 0.044 0.044 0.05 0.73 0.64 0.64 1.15 0.59 0.655 0.655 1.18 0.0014 0.0018 0.0018 0.0023 0.0012 0.0018 0.0018 0.0023 0.041 0.065 0.079 0.0118 0.041 0.065 0.079 0.0118 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.017 5.343308 7.19184 7.25364 9.892564 0.830744 1.13304 1.23084 2.566564 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.08 1.2 1.2 1.98 1.08 1.2 1.2 1.98 1.08 1.2 1.2 1.98 1.08 1.2 1.2 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 1.98 1.62 1.8 1.8 2.5 3.6 4.2 5.5 2.5 3.6 4.2 5.5 2.5 3.6 4.2 5.5 2.5 3.6 4.2 1.62 1.8 1.8 3.63 1.62 1.8 1.8 3.63 1.62 1.8 1.8 3.63 1.62 1.8 1.8 2.62 2.82 2.82 2.92 2.44 2.51 2.51 2.59 3.09 3.18 3.18 3.27 1.97 2.06 2.06 0.045 0.82 0.82 1.486 0.73 0.82 0.82 1.49 0.732 0.82 0.82 1.49 0.66 0.74 0.74 0.0012 0.0018 0.0018 0.0023 1.35 1.37 1.37 1.39 0.0013 0.0018 0.0018 0.0023 0.0012 0.0018 0.0018 0.041 0.068 0.086 0.128 0.041 0.068 0.086 0.128 5.68 7.17 7.97 9.73 0.82 0.897 0.94 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.017 4.424984 6.33864 6.45504 9.494144 7.05824 8.2434 8.3598 11.59631 20.02601 32.55384 40.21584 63.00606 5.983684 7.85904 8.57784 Rev. 0 | Page 16 of 296 ADAU1373 DIGITAL FILTER/SRC CHARACTERISTICS Table 4. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay [1950/(128 × fS)] DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay [1791/(128 × fS)] SAMPLE RATE CONVERTER Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Output/Input Sample Rate Ratio Signal-to-Noise Ratio, A-weighted Dynamic Range, A-weighted THD + N Maximum Group Delay Maximum Start-Up Time Test Conditions/Comments Min ±0.04 dB −6 dB 0 Typ Max Unit 0.423 fS Hz Hz dB Hz dB ms 0.5 fS ±0.04 0.577 fS −60 f > 0.577 fS fS = 48 kHz 0.317 ±0.03 dB −6 dB 0 0.423 fS 0.5 fS ±0.03 0.577 fS −60 f > 0.577 fS fS = 48 kHz 0.292 0.04 dB −6 dB 0 0.418 fS 0.5 fS 0.02 0.582 fS −100 1:8 f > 0.582 fS Hz Hz dB Hz dB 8:1 100 100 90 48 kHz in, 8 kHz out 48 kHz in, 8 kHz out Hz Hz dB Hz dB ms 120 3.7 15 dB dB dB ms ms DIGITAL INPUT/OUTPUT SPECIFICATIONS Table 5. Parameter INPUT SPECIFICATIONS Input Voltage High (VIH) Input Voltage Low (VIL) Input Leakage OUTPUT SPECIFICATIONS High Output Voltage High (VOH) Output Voltage Low (VOL) INPUT CAPACITANCE Test Conditions/Comments Min Typ Max Unit 0.25 × IOVDD 10 10 V V μA μA 0.4 5 V V pF 0.6 × IOVDD IIH at VIH = 2.4 V IIL at VIL = 0.8 V IOH = 1 mA IOL = 1 mA IOVDD − 0.6 Rev. 0 | Page 17 of 296 ADAU1373 DIGITAL TIMING SPECIFICATIONS −40°C < TA < +85°C, IOVDDx = 1.8 V ± 10%. Table 6. Parameter MASTER CLOCK Duty Cycle SERIAL PORT tBIL tBIH tLIS tLIH tSIS tSIH tSODM 2 I C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tDH tSCR tSCF tSDR tSDF tBFT DIGITAL MICROPHONE tDCF tDCR tDDV tDDH tMIN 45 Limit tMAX Description 55 % 50 ns ns ns ns ns ns ns BCLKx pulse width low BCLKx pulse width high LRCLKx setup; time to BCLK rising LRCLKx hold; time from BCLK rising DAC_SDATA setup; time to BCLK rising DAC_SDATA hold; time from BCLK rising ADC_SDATA delay; time from BCLK falling in master mode kHz μs μs μs μs ns ns ns ns ns ns μs SCL frequency SCL high SCL low Setup time; relevant for repeated start condition Hold time; after this period of time, the first clock is generated Data setup time Data hold time SCL rise time SCL fall time SDA rise time SDA fall time Bus-free time; time between stop and start RL = 1 MΩ, CL = 14 pF Digital microphone clock fall time Digital microphone clock rise time Digital microphone delay time for valid data Digital microphone delay time for data, three-stated 5 5 5 5 5 5 400 0.6 1.3 0.6 0.6 100 5 300 300 300 300 0.6 22 0 Unit 10 10 30 12 ns ns ns ns Rev. 0 | Page 18 of 296 ADAU1373 Digital Timing Diagrams tLIH tBIH BCLKx tBIL tLIS LRCLKx tSIS DAC_SDATA LEFT-JUSTIFIED MODE MSB MSB – 1 tSIH tSIS DAC_SDATA I2S MODE MSB tSIH tSIS tSIS DAC_SDATA RIGHT-JUSTIFIED MODE LSB MSB tSIH tSIH 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 08975-003 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 2. Serial Input Port Timing tBIH BCLKx tBIL LRCLKx ADC_SDATA LEFT-JUSTIFIED MODE tSODM MSB MSB – 1 tSODM ADC_SDATA I2S MODE MSB tSODM ADC_SDATA RIGHT-JUSTIFIED MODE MSB LSB 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 08975-004 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 3. Serial Output Port Timing Rev. 0 | Page 19 of 296 ADAU1373 tDS tSCH tSCH SDA tDH tSCLH SCL tSCLL tSCF tSCS tBFT Figure 4. I2C Port Timing tDCF tDCR DMIC_CLK DMIC1_2_DATA DATA1 DATA2 tDDH tDDV DATA1 Figure 5. Digital Microphone Timing Rev. 0 | Page 20 of 296 DATA2 08975-005 tDDV tDDH 08975-024 tSCR ADAU1373 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 7. Parameter Power Supply SPKVDD, IOVDDx DVDD, AVDD HPVDD Analog Input Voltage (Signal Pins) AIN4R/AIN4N, AIN3R/AIN3N, AIN2R/AIN2N, AIN1R/AIN1N, AIN4L/AIN4P, AIN3L/AIN3P, AIN2L/AIN4P, AIN1L/AIN1P Digital Input Voltage (Signal Pins) MCLK1, BCLKA, LRCLKA, SDATAINA, GPIO1 MCLK2, BCLKB, LRCLKB, SDATAINB, GPIO2 BCLKC, LRCLKC, SDATAINC, GPIO3 DMIC1_2_DATA, DMIC3_4_DATA, DMIC_CLK SDA, SCL, GPIO4, MODE, ADDR, SD Temperature Operating Range Storage Range Junction Range Lead Temperature (Soldering, 60 sec) θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.3 V to +5.5 V −0.3 V to +1.98 V −0.3 V to +1.98 V Table 8. Thermal Resistance Package Type 81-Lead, 4.0 mm × 3.8 mm WLCSP1 –0.3 V to AVDD + 0.3 V 1 θJA 30 Unit °C/W Applicable for a 4-layer board. For more information on the WLCSP, see the AN-617 Application Note, MicroCSP Wafer Level Chip Scale Package. ESD CAUTION –0.3 V to IOVDD1 + 0.3 V –0.3 V to IOVDD2 + 0.3 V –0.3 V to IOVDD3 + 0.3 V –0.3 V to IOVDD4 + 0.3 V –0.3 V to IOVDD5 + 0.3 V −40°C to +85°C −65°C to +150°C −65°C to +165°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 21 of 296 ADAU1373 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 CORNER 1 2 3 4 5 6 7 8 9 A B C D E F G H TOP VIEW (BALL SIDE DOWN) Not to Scale 08975-006 J Figure 6. Pin Configuration Table 9. Pin Function Descriptions Pin No. A1 A2 A3 Mnemonic DGND MODE IOVDD4 Type PWR D_IN PWR A4 A5 A6 A7 A8 A9 DMIC_CLK AIN4R/AIN4N AIN3R/AIN3N AIN2R/AIN2N AIN1R/AIN1N AVDD D_OUT A_IN A_IN A_IN A_IN PWR B1 B2 B3 DVDD ADDR IOVDD5 PWR D_IN PWR B4 B5 B6 B7 B8 B9 DMIC1_2_DATA AIN4L/AIN4P AIN3L/AIN3P AIN2L/AIN2P AIN1L/AIN1P CM D_IN A_IN A_IN A_IN A_IN A_OUT Description Digital Ground. The AGND and DGND pins must be tied directly together in a common ground plane. Mode Select I2C Operation. Must be pulled low for I2C mode. Supply for Digital Microphone Input Port. Set IOVDD4 between 1.8 V and 3.3 V and decouple to DGND using a 100 nF capacitor. Clock Output for Digital Microphone. Right Channel Input 4 (AIN4R)/Inverting Input 4 (AIN4N). Right Channel Input 3 (AIN3R)/Inverting Input 3 (AIN3N). Right Channel Input 2 (AIN2R)/Inverting Input 2 (AIN2N). Right Channel Input 1 (AIN1R)/Inverting Input 1 (AIN1N). 1.5 V to 1.8 V Analog Supply for DAC and Microphone Bias. Decouple this pin to AGND using a 100 nF capacitor. Digital Core Supply. Decouple this pin to DGND with a 100 nF capacitor. Address Setting Pin for I2C Port. Pull high/low to IOVDD4, using a resistor for the desired chip address. Supply for I2C Port. Set IOVDD5 between 1.8 V and 3.3 V and decouple to DGND using a 100 nF capacitor. Serial Data Input Digital Microphone 1 and Serial Data Input Digital Microphone 2. Left Channel Input 4 (AIN4L)/Noninverting Input 4 (AIN4P). Left Channel Input 3 (AIN3L)/Noninverting Input 3 (AIN3P). Left Channel Input 2 (AIN2L)/Noninverting Input 2 (AIN2P). Left Channel Input 1 (AIN1L)/Noninverting Input 1 (AIN1P). AVDD/2 V Common-Mode Reference. Connect a 1 μF ceramic decoupling capacitor between this pin and ground to reduce crosstalk between the ADCs and DACs. This pin can be used to bias external analog circuits, as long as they are not drawing current from CM (for example, the noninverting input of an op amp). Rev. 0 | Page 22 of 296 ADAU1373 Pin No. C1 Mnemonic IOVDD1 Type PWR C2 C3 C4 C5 C6 C7 MCLK1 SDA GPIO4 SCL DMIC3_4_DATA LOUT1L/LOUTLP D_IN D_I/O D_I/O D_IN D_IN A_OUT C8 C9 D1 D2 D3 D4 D5 D6 D7 MICBIAS1 MICBIAS2 MCLK2 BCLKA LRCLKA SDATAOUTA SDATAINA GPIO1 LOUT1R/LOUTRP A_OUT A_OUT D_IN D_I/O D_I/O D_OUT D_IN D_I/O A_OUT D8 LOUT2L/LOUTLN A_OUT D9 LOUT2R/LOUTRN A_OUT E1 IOVDD3 PWR E2 E3 E4 E5 E6 E7 LRCLKB SDATAOUTB BCLKB DGND GPIO2 LN1FBIN D_I/O D_OUT D_I/O PWR D_I/O A_IN E8 LN2FBIN A_IN E9 AVDD PWR F1 F2 F3 F4 LRCLKC BCLKC SDATAINC IOVDD2 D_I/O D_I/O D_IN PWR F5 F6 F7, F8 F9 G1, G2 G3 G4 G5 G6 G7 G8 G9 GPIO3 SDATAINB AGND RESERVED SPKVDD SDATAOUTC RESERVED JACKDET SD SGND HPL HPR D_I/O D_IN PWR A_IN PWR D_OUT D_IN D_IN D_IN A_IN A_OUT A_OUT Description Supply for Digital Audio Input/Output Interface A. Set IOVDD1 between 1.8 V and 3.3 V. Decouple this pin to DGND with a 100 nF capacitor. External Master Clock Input 1 (8 kHz to 27 MHz). Serial Data for I2C. This pin is a bidirectional open drain and must be pulled up to IOVDD5 with a resistor. General-Purpose Input/Output 4. Serial Clock for I2C Port. This pin is input only and must be pulled up to IOVDD5 with a resistor. Serial Data Input Digital Microphone 3 and Serial Data Input Digital Microphone 4. Left Channel Line Output 1, Single-Ended Mode (LOUT1L)/Noninverting Left Channel Line Output, Differential Mode (LOUTLP). Bias Voltage for Electret Microphone 1. Bias Voltage for Electret Microphone 2. External Master Clock Input 2 (8 kHz to 27 MHz). Serial Bit Clock, Digital Audio Interface A. Frame Clock, Digital Audio Interface A. Serial Data Output, Digital Audio Interface A. Serial Data Input, Digital Audio Interface A. General-Purpose Input/Output 1. Right Channel Line Output 1, Single-Ended Mode (LOUT1R)/Noninverting Right Channel Line Output, Differential Mode (LOUTRP). Left Channel Line Output 2, Single-Ended Mode (LOUT2L)/Inverting Left Channel Line Output, Differential Mode (LOUTLN). Right Channel Line Output 2, Single-Ended Mode (LOUT2R)/Inverting Right Channel Line Output, Differential Mode (LOUTRN). Supply for Digital Audio Input/Output Interface C. Set IOVDD3 between 1.8 V and 3.3 V and decouple to DGND with a 100 nF capacitor. Frame Clock, Digital Audio Interface B. Serial Data Output, Digital Audio Interface B. Serial Bit Clock, Digital Audio Interface B. Digital Ground. The AGND and DGND pins must be tied directly together in a common ground plane. General-Purpose Input/Output 2. Line Output Amplifier 1 Feedback. This pin can be used to sense the ground noise at the line output jack; use a 2.2 μF capacitor to connect this pin to AGND at the line output jack. Line Output Amplifier 2 Feedback. This pin can be used to sense the ground noise at the line output jack; use a 2.2 μF capacitor to connect this pin to AGND at the line output jack. 1.5 V to 1.8 V Analog Supply for DAC and Microphone Bias. Decouple this pin to AGND with a 100 nF capacitor in parallel with a 10 μF capacitor. Frame Clock, Digital Audio Interface C. Serial Bit Clock, Digital Audio Interface C. Serial Data Input, Digital Audio Interface C. Supply for Digital Audio Input/Output Interface B. Set IOVDD2 between 1.8 V and 3.3 V and decouple to DGND with a 100 nF capacitor. General-Purpose Input/Output 3. Serial Data Input, Digital Audio Interface B. Analog Ground. Reserved for Internal Use. Do not connect. Supply for Speaker Class-D Amplifier. Serial Data Output, Digital Audio Interface C. Reserved. Connect to DGND. TLL-Compatible Logic Input. Detects insertion/removal of headphone plug. Shutdown Control. Set high for normal operation; set low for full chip power-down. Headphone Signal Return Sense. Connect directly to headphone socket ground for lowest dc offset. Left Headphone Output. Right Headphone Output. Rev. 0 | Page 23 of 296 ADAU1373 Pin No. H1 H2, H3 H4, H5 H6 H7 Mnemonic SPKRN SPKVDD SPKGND EPP CPVSS Type A_OUT PWR PWR A_OUT PWR H8 HPVDD PWR H9 CPVDD PWR J1 J2 J3 J4 J5 J6 J7 J8 J9 SPKGND SPKRP SPKLN SPKLP SPKGND EPN CF2 HPGND CF1 PWR A_OUT A_OUT A_OUT PWR A_OUT PWR PWR PWR Description Right Channel Speaker Output, Negative. Supply for Speaker Amplifier. Ground for Speaker Amplifier. Earpiece Amplifier Output, Positive. Headphone Amplifier Charge Pump, Negative Supply Output. Decouple this pin to HPGND with a 1 μF MLCC X7R capacitor. 1.62 V to 2 V Supply for Headphone Amplifier Charge Pump. Decouple this pin to AGND with a 1 μF capacitor. Headphone Amplifier Charge Pump, Positive Supply Output. Decouple this pin to HPGND with a 1 μF MLCC X7R capacitor. Ground for Speaker Amplifier. Right Channel Speaker Output, Positive. Left Channel Speaker Output, Negative. Left Channel Speaker Output, Positive. Ground for Speaker Amplifier. Earpiece Amplifier Output, Negative. Charge Pump Flying Capacitor Connection 2. Charge Pump Ground. Charge Pump Flying Capacitor Connection 1. Rev. 0 | Page 24 of 296 ADAU1373 TYPICAL PERFORMANCE CHARACTERISTICS 0 10 –10 –20 –30 1 –50 THD + N (%) AMPLITUDE (dBr) –40 –60 –70 –80 –90 0.1 –100 0.01 –110 –120 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) 0.001 08975-050 0 100 1k 08975-053 –130 –140 10k FREQUENCY (Hz) Figure 7. FFT, −60 dBFS, Analog In → Line Out Figure 10. THD + N vs. Frequency, −20 dBFS, Analog In → Line Out 0 –17 –10 –20 –18 –30 –19 AMPLITUDE (dBr) AMPLITUDE (dBr) –40 –50 –60 –70 –80 –90 –20 –21 –100 –110 –22 –120 2.5 5.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY (kHz) 20.0 –23 08975-051 0 100 1k 08975-054 –130 –140 10k FREQUENCY (Hz) Figure 11. Frequency Response, −20 dBFS, Analog In → Line Out Figure 8. FFT, −1 dBFS, Analog In → Line Out 10 0 –20 AMPLITUDE (dBr) THD + N (%) 1 0.1 –40 –60 –80 –100 0.01 –140 1 10 100 OUTPUT (mV) 08975-052 0.001 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY (kHz) Figure 12. FFT, −60 dBFS, Analog In → Speaker Out Figure 9. THD + N vs. Output Level, Analog In → Line Out Rev. 0 | Page 25 of 296 20.0 08975-055 –120 ADAU1373 0 10 –20 1 THD + N (%) AMPLITUDE (dBr) –40 –60 –80 0.1 –100 0.01 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) 0.001 08975-056 –140 100 1k 08975-059 –120 10k FREQUENCY (Hz) Figure 16. THD + N vs. Frequency, −20 dBFS, Analog In → Speaker Out Figure 13. FFT, −1 dBFS, Analog In → Speaker Out 10 –17.0 –17.5 –18.0 –18.5 AMPLITUDE (dBr) THD + N (%) 1 0.1 0.01 –19.0 –19.5 –20.0 –20.5 –21.0 –21.5 –22.0 100m –23.0 08975-057 10m 1 OUTPUT POWER (W) 100 1k 08975-060 –22.5 0.001 1m 10k FREQUENCY (Hz) Figure 14. THD + N vs. Output Power, 4 Ω + 15 μH, Analog In → Speaker Out Figure 17. Frequency Response, 8 Ω + 33 μH, Analog In → Speaker Out 10 –20 –40 AMPLITUDE (dBr) THD + N (%) 1 0.1 –60 –80 –100 0.01 –140 10m 100m OUTPUT POWER (W) 1 08975-058 0.001 1m Figure 15. THD + N vs. Output Power, 8 Ω + 33 μH, Analog In → Speaker Out Rev. 0 | Page 26 of 296 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY (kHz) Figure 18. FFT, −60 dBFS, Analog In → Headphone Out 20.0 08975-061 –120 ADAU1373 0 10 –20 1 THD + N (%) AMPLITUDE (dBr) –40 –60 –80 0.1 –100 0.01 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) 0.001 08975-062 –140 100 1k 08975-065 –120 10k FREQUENCY (Hz) Figure 22. THD + N vs. Frequency, −20 dBFS,16 Ω, Analog In → Headphone Out Figure 19. FFT, −1 dBFS, Analog In → Headphone Out –17.0 10 –17.5 –18.0 –18.5 AMPLITUDE (dBr) THD + N (%) 1 0.1 –19.0 –19.5 –20.0 –20.5 –21.0 –21.5 0.01 –22.0 1m 10m –23.0 08975-063 100 100m OUTPUT POWER (W) Figure 20. THD+N vs. Output Power, 16 Ω, Analog In → Headphone Out 100 1k 08975-066 –22.5 0.001 10 10k FREQUENCY (kHz) Figure 23. Frequency Response, −20 dBFS, 16 Ω, Analog In → Headphone Out 10 –20 –40 AMPLITUDE (dBr) THD + N (%) 1 0.1 –60 –80 –100 0.01 –140 100µ 1m OUTPUT POWER (W) 10m 08975-064 0.001 10µ Figure 21. THD + N vs. Output Power, 32 Ω, Analog In → Headphone Out Rev. 0 | Page 27 of 296 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY (kHz) Figure 24. FFT, −60 dBFS, Analog In → Earpiece Out 20.0 08975-067 –120 ADAU1373 0 –17.0 –17.5 –20 –18.0 –18.5 –40 AMPLITUDE (dBr) AMPLITUDE (dBr) –19.0 –19.5 –60 –20.0 –80 –20.5 –21.0 –100 –21.5 –22.0 –120 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 –23.0 08975-068 –140 20.0 FREQUENCY (kHz) 100 1k 08975-071 –22.5 10k FREQUENCY (Hz) Figure 25. FFT, −1 dBFS, Digital Microphone In → Earpiece Out Figure 28. Frequency Response, 32 Ω, Analog In → Earpiece Out 10 0 –20 –40 THD + N (%) AMPLITUDE (dBr) 1 0.1 –60 –80 –100 1m 10m 100m OUTPUT POWER (W) –140 08975-069 0.01 100µ 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) 08975-072 –120 Figure 29. FFT, −60 dBFS, Digital In → Line Out Figure 26. THD + N vs. Output Power, 32 Ω, Analog In → Earpiece Out 0 10 –20 –40 AMPLITUDE (dBr) THD + N (%) 1 0.1 –60 –80 –100 0.01 –140 100 1k FREQUENCY (Hz) 10k 08975-070 0.001 Figure 27. THD + N vs. Frequency, −20 dBFS, 32 Ω, Analog In → Earpiece Out Rev. 0 | Page 28 of 296 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY (kHz) Figure 30. FFT, −1 dBFS, Digital In → Line Out 20.0 08975-073 –120 ADAU1373 –60 10 –65 –70 –75 1 –85 PSRR (dB) THD + N (%) –80 0.1 –90 –95 –100 –105 0.01 –110 100m 1 OUTPUT (W) 08975-074 10m –120 100 1k 08975-136 –115 0.001 10k FREQUENCY (Hz) Figure 31. THD + N vs. Output Level, Digital In → Line Out Figure 34. PSRR vs. Frequency Ripple on AVDD, Digital In → Line Out 0 10 –20 –40 AMPLITUDE (dBr) THD + N (%) 1 0.1 –60 –80 –100 0.01 100 1k 10k FREQUENCY (Hz) –140 08975-075 0.001 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) 08975-077 –120 Figure 35. FFT, −60 dBFS, 8 Ω + 33 μH, Digital In → Speaker Out Figure 32. THD+N vs. Frequency, −20 dBFS, Digital In → Line Out –17 0 –20 –18 AMPLITUDE (dBr) –20 –21 –60 –80 –100 –22 100 1k 10k FREQUENCY (Hz) –140 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) Figure 36. FFT, −1 dBFS, 8 Ω + 33 μH, Digital In → Speaker Out Figure 33. Frequency Response, −20 dBFS, Digital In → Line Out Rev. 0 | Page 29 of 296 08975-078 –23 –120 08975-076 AMPLITUDE (dBr) –40 –19 ADAU1373 10 –17 –18 AMPLITUDE (dBr) THD + N (%) 1 0.1 –19 –20 –21 0.01 10m 100m –23 08975-079 0.001 1m 1 OUTPUT POWER (W) 100 1k 08975-082 –22 10k FREQUENCY (Hz) Figure 40. Frequency Response, 8 Ω + 33 μH, Digital In → Speaker Out Figure 37. THD + N vs. Output Power, 8 Ω + 33 μH, Digital In → Speaker Out 2.0 10 1.8 1.6 OUTPUT POWER (W) THD + N (%) 1 0.1 0.01 1.4 1.2 10% 1.0 1% 0.8 0.6 0.4 10m 100m 0 2.5 08975-080 0.001 1m 1 OUTPUT POWER (W) Figure 38. THD + N vs. Output Power, 4 Ω + 15 μH, Digital In → Speaker Out 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 08975-118 0.2 Figure 41. Output Power vs. SPKVDD, 8 Ω + 33 μH (Stereo), Digital In → Speaker Out 3.5 10 3.0 OUTPUT POWER (W) THD + N (%) 1 0.1 0.01 2.5 2.0 10% 1% 1.5 1.0 100 1k 10k FREQUENCY (Hz) Figure 39. THD + N vs. Frequency, −20 dBFS, 8 Ω + 33 μH, Digital In → Speaker Out 0 2.5 08975-081 0.001 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 08975-119 0.5 Figure 42. Output Power vs. SPKVDD, 4 Ω + 15 μH (Stereo), Digital In → Speaker Out Rev. 0 | Page 30 of 296 ADAU1373 0 –50 –55 –20 –60 –65 –40 AMPLITUDE (dBr) –70 PSRR (dB) –75 –80 –85 –90 –95 –60 –80 –100 –100 –105 –120 –110 100 1k 10k FREQUENCY (Hz) –140 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY (kHz) 20.0 08975-084 –120 08975-120 –115 Figure 46. FFT, −1 dBFS, 16 Ω, Digital In → Headphone Out Figure 43. PSRR vs. Frequency Ripple on SPKVDD, 8 Ω + 33 μH, Digital In → Speaker Out 10 100 90 80 1 60 THD + N (%) EFFICIENCY (%) 70 50 40 0.1 30 0.01 0 0 200 400 600 800 1000 1200 1400 1600 OUTPUT POWER (mW) 08975-121 SPKVDD = 3.6V SPKVDD = 4.2V SPKVDD = 5V 10 Figure 44. Efficiency vs. Output Power, 8 Ω + 33 μH, Digital In → Speaker Out 0.001 10µ 100µ 1m 10m OUTPUT POWER (W) 08975-085 20 Figure 47. THD + N vs. Output Power, 16 Ω, Digital In → Headphone Out 0 10 –20 1 THD + N (%) –60 –80 –100 0.1 0.01 –140 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) Figure 45. FFT, −60 dBFS, 16 Ω, Digital In → Headphone Out 0.001 10µ 100µ 1m OUTPUT POWER (W) 10m 08975-086 –120 08975-083 AMPLITUDE (dBr) –40 Figure 48. THD + N vs. Output Power, 32 Ω, Digital In → Headphone Out Rev. 0 | Page 31 of 296 ADAU1373 –60 10 –65 –70 1 –75 –85 PSRR (dB) THD + N (dB) –80 0.1 –90 –95 –100 0.01 –105 –110 100 1k 10k FREQUENCY (Hz) –120 08975-087 0.001 100 08975-124 –115 10k 1k FREQUENCY (Hz) Figure 49. THD + N vs. Frequency, −20 dBFS,16 Ω, Digital In → Headphone Out Figure 52. PSRR vs. Frequency, 16 Ω, Digital In → Headphone Out –17 60 –18 50 40 –19 AMPLITUDE (dBr) 30 1% THD + N 20 –20 –21 –22 10 1.72 1.82 1.92 SUPPLY VOLTAGE (V) –23 100 08975-122 0 1.62 Figure 50. Output Power vs. HPVDD, 16 Ω, Digital In → Headphone Out 10k FREQUENCY (Hz) Figure 53. Frequency Response, −20 dBFS, 16 Ω, Digital In → Headphone Out 45 0 40 –20 35 10% THD + N –40 30 25 AMPLITUDE (dBr) OUTPUT POWER (mW) 1k 08975-088 OUTPUT POWER (mW) 10% THD + N 1% THD + N 20 15 –60 –80 –100 10 1.72 1.82 SUPPLY VOLTAGE (V) 1.92 08975-123 0 1.62 –140 Figure 51. Output Power vs. HPVDD, 32 Ω, Digital In → Headphone Out Rev. 0 | Page 32 of 296 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY (kHz) Figure 54. FFT, −60 dBFS, 32 Ω, Digital In → Earpiece Out 20.0 08975-089 –120 15 ADAU1373 –17 0 –20 –18 –19 AMPLITUDE (dBr) AMPLITUDE (dBr) –40 –60 –80 –20 –21 –100 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) –23 08975-090 –140 100 1k 08975-093 –22 –120 10k FREQUENCY (Hz) Figure 58. Frequency Response, 32 Ω, Digital In → Earpiece Out Figure 55. FFT, −1 dBFS, 32 Ω, Digital In → Earpiece Out 45 10 40 OUTPUT POWER (W) 35 THD + N (%) 1 0.1 10% 30 25 1% 20 15 10 1µ 10µ 100µ 1m 10m 0 2.5 08975-091 0.01 100n 100m OUTPUT POWER (W) 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 08975-125 5 Figure 59. Output Power vs. SPKVDD, 32 Ω, Digital In → Earpiece Out Figure 56. THD + N vs. Output Power, 32 Ω, Digital In → Earpiece Out –50 10 –55 –60 –65 1 –70 PSRR (dB) THD + N (%) –75 0.1 –80 –85 –90 –95 –100 0.01 –105 –110 1k FREQUENCY (Hz) 10k –120 Figure 57. THD + N vs. Frequency, −20 dBFS, 32 Ω, Digital In → Earpiece Out Rev. 0 | Page 33 of 296 100 1k 10k FREQUENCY (Hz) Figure 60. PSRR vs. Frequency, 32 Ω, Digital In → Earpiece Out 08975-126 100 08975-092 –115 0.001 0 –20 –60 CMRR (dB) AMPLITUDE (dBr) –40 –80 –100 –120 –140 –180 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) 08975-094 –160 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 –105 –110 –115 –120 100 1k 08975-143 ADAU1373 10k FREQUENCY (Hz) Figure 64. CMRR vs. Frequency, Analog In → Digital Out, PGA Gain = 0 dB Figure 61. FFT, −60 dBFS, Analog In → Digital Out, PGA Gain = 0 dB –50 0 –55 –20 –60 –65 –40 –75 PSRR (dB) –80 –100 –85 –90 –95 –120 –100 –140 –105 –110 –160 –115 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) –120 08975-095 –180 –80 100 1k 08975-127 AMPLITUDE (dBr) –70 –60 10k FREQUENCY (Hz) Figure 62. FFT, −1 dBFS, Analog In → Digital Out, PGA Gain = 0 dB Figure 65. PSRR vs. Frequency Ripple on AVDD, Analog In → Digital Out, PGA Gain = 0 dB 0 –17 –20 –18 AMPLITUDE (dBr) –19 –20 –21 –60 –80 –100 –120 –140 –22 100 1k 10k FREQUENCY (kHz) –180 Figure 63. Frequency Response, −20 dBFS, Analog In → Digital Out, PGA Gain = 0 dB 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY (kHz) Figure 66. FFT, −60 dBFS, Digital In → Digital Out Rev. 0 | Page 34 of 296 20.0 08975-097 –23 –160 08975-096 AMPLITUDE (dBr) –40 ADAU1373 0 0 –20 –20 –40 –60 –60 DNR (dB) AMPLITUDE (dBr) –40 –80 –100 –80 –120 –100 –140 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) –140 THD + N (%) THD + N (dB) 0.1 10k FREQUENCY (Hz) 08975-099 0.01 1k –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 –105 –110 –115 –120 –125 Figure 68. THD + N vs. Frequency, 0 dBFS, Digital In → Digital Out 0 –20 –30 –40 THD + N (dB) –60 –70 –80 –90 –100 –110 –120 –130 15.0 20.0 25.0 30.0 35.0 40.0 45.0 12.5 17.5 22.5 27.5 32.5 37.5 42.5 47.5 SAMPLE RATE FREQUENCY (kHz) –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 –105 –110 –115 –120 –125 08975-100 DNR (dB) –50 10.0 25 30 35 40 45 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 12.5 17.5 22.5 27.5 32.5 37.5 42.5 47.5 SAMPLE RATE FREQUENCY (kHz) Figure 71. THD + N vs. fS Out Sample Rate, fS In = 8 kHz, ASRC –10 –140 20 Figure 70. DNR vs. fS Out Sample Rate, fS In = 8 kHz, ASRC 1 100 15 SAMPLE RATE FREQUENCY (kHz) Figure 67. FFT, −1 dBFS, Digital In → Digital Out 0.001 10 08975-102 2.5 Figure 69. DNR vs. fS Out Sample Rate, fS In = 8 kHz, ASRC 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 12.5 17.5 22.5 27.5 32.5 37.5 42.5 47.5 SAMPLE RATE FREQUENCY (kHz) Figure 72. THD + N vs. fS Out Sample Rate, fS In = 48 kHz, ASRC Rev. 0 | Page 35 of 296 08975-103 0 08975-098 –180 08975-101 –120 –160 ADAU1373 0 –20 AMPLITUDE (dBr) –40 –60 –80 4 –100 –120 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) A[W]: 1A CH4 1V DATA: 27 BW DATA: 41 80µs T 357.6µs Figure 73. FFT, −60 dBFS, Analog In → ADC → DAC → Line Out 1.25GS/s 1M POINTS B1 START 08975-138 0 08975-104 B1 –140 Figure 76. Turn Off Speaker Out 0 –20 –60 4 –80 –100 –120 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY (kHz) CH4 500mV Figure 74. FFT, −1 dBFS, Analog In → ADC → DAC → Line Out BW 4ms 25MS/s T 16.7776ms 1M POINTS B1 START 08975-139 2.5 08975-105 0 B1 START 08975-140 B1 –140 Figure 77. Turn On Headphone Out 4 4 B1 B1 CH4 1V BW 1ms T 4.264ms 100MS/s 1M POINTS B1 START 08975-137 AMPLITUDE (dBr) –40 CH4 500mV BW 1ms 100MS/s T 2.0176ms 1M POINTS Figure 78. Turn Off Headphone Out Figure 75. Turn On Speaker Out Rev. 0 | Page 36 of 296 ADAU1373 4 4 CH4 500mV 1ms 100MS/s T 1.4376ms 1M POINTS B1 START Figure 79. Turn On Earpiece Out CH4 500mV BW 1ms 100MS/s T 3.69760ms 1M POINTS Figure 80. Turn Off Earpiece Out Rev. 0 | Page 37 of 296 B1 START 08975-142 B1 BW 08975-141 B1 ADAU1373 CHARGE PUMP PLLA RESERVED (No connect) AVDD DVDD HPVDD SPKVDD CM CF1 CF2 CPVDD CPVSS DETAILED BLOCK DIAGRAM POWER-ON RESET REFERENCE LINEMIX PLLB IOVDD1 CH1 SDATAINA CH2 GPIO1 GPIO1 MCLK1 MCLK1 MUX MIX CH3 VOL CH4 AIF CLKA AIF CLKB MDRC/DRC SEVEN BAND EQ 3D BASS ENHANCE CH5 IOVDD2 SDATAOUTB SERIAL DIGITAL AUDIO INT. B CH1 CH2 MUX CH3 MIX VOL CH4 ASRCB SDATAINB GPIO2 MCLK2 MCLK2 AIF CLKA AIF CLKB ADAU1373 IOVDD3 BCLKC GPIO3 AIF CLKA AIF CLKB IOVDD5 MODE ADDR SCL I2C SDA SD GPIO4 DMIC1/DMIC2 OR ADC DATA LEFT ADC GPIO4 DECIMATOR DMIC1/DMIC2 PDM DATA HPGND DMIC3/ DMIC4 SINGLE DIFF LN2FBIN 12dB SPKLP SPKLN CLASS-D –70dB TO 0dB 12dB SPKRP SPKRN BSTEN EPP EPN 6dB TO 12dB JACKDETECT LOGIC CPVDD CPVSS –70dB TO 0dB IN1L IN1R IN2L IN2R IN3L IN3R IN4L IN4R JACKDET HPL SGND –70dB TO 0dB HPR MICBIAS2 MICBIAS1 MICBIAS2 MICBIAS1 IOUT –12dB TO +20dB 0dB TO +20dB –12dB TO +20dB 0dB TO +20dB –12dB TO +20dB 0dB TO +20dB –12dB TO +20dB 0dB TO +20dB –12dB TO +20dB 0dB TO +20dB –12dB TO +20dB 0dB TO +20dB –12dB TO +20dB 0dB TO +20dB –12dB TO +20dB SPKGND DMIC1_2_DATA DIGITAL MIC INTERFACE DGND DMIC_CLK AGND DMIC3_4_DATA 0dB TO +20dB RIGHT ADC IOVDD4 –70dB TO 0dB –70dB TO 0dB LOUT1L/ LOUTLP LOUT1R/ LOUTRP LN1FBIN LOUT2L/ LOUTLN LOUT2R/ LOUTRN AIN1L/ AIN1P AIN1R/ AIN1N AIN2L/ AIN2P AIN2R/ AIN2N AIN3L/ AIN3P AIN3R/ AIN3N AIN4L/ AIN4P AIN4R/ AIN4N 08975-001 GPIO3 RDAC2 LDAC2 RDAC1 LDAC1 ADCMIX SDATAINC RIGHT DAC2 ASRCC DECIMATOR SDATAOUTC SERIAL DIGITAL AUDIO INT. C DMIC3/DMIC4-DATA LRCLKC DIFF –70dB TO 0dB LEFT DAC2 DIGITAL ENGINE GPIO2 SINGLE RIGHT DAC1 CH5 HPF ALC BCLKB LRCLKB LEFT DAC1 ASRCA SPEAKERMIX SDATAOUTA SERIAL DIGITAL AUDIO INT. A RECEIVERMIX LRCLKA DSP HEADPHONEMIX BCLKA –70dB TO 0dB –70dB TO 0dB Figure 81. Rev. 0 | Page 38 of 296 ADAU1373 THEORY OF OPERATION ANALOG INPUTS Mono Differential Mode The ADAU1373 provides four stereo (unbalanced)/mono differential inputs. Each input gain and mode of operation can be set independently, using the I2C registers. Figure 82 shows the typical input block for the stereo and mono differential inputs in the programmable gain amplifier (PGA) modes and boost modes. In mono differential mode, the AINxL/AINxP pins are used as positive inputs, and the AINxR/AINxN pins are used as negative inputs for the differential amplifier. Each input can receive either a microphone or a line level signal. Each input can be set to either stereo single-ended mode or mono differential mode. In addition, the gain for the input amplifiers can be set to PGA mode or boost mode. In PGA mode, the gain can be varied from −12 dB to +18 dB (in 1 dB steps); whereas in boost mode, it can be varied using one of the following three steps: 0 dB, 9 dB, or 20 dB. In PGA mode, the input resistance varies as per the gain, with a minimum of ~5.6 kΩ. In boost mode, the input resistance is constant at ~20 kΩ. Stereo Single-Ended Mode In stereo single-ended mode, the AINxL/AINxP pins are used as the left channel inputs, and the AINxR/AINxN pins are used as the right channel inputs. STEREO PGA MODE AINxL The input amplifers use AVDD as the supply voltage. The AINxP/AINxN input pins are internally biased to AVDD/2, which is the common-mode voltage for the amplifiers. The common-mode pin (CM, Ball B9) must be decoupled using the 10 μF electrolytic capacitor, as well as a 100 nF, X7R ceramic capacitor to keep the reference clean for lower noise. In addition, the input pins must be provided with an ac coupling capacitor to the desired source. The typical value of the coupling capacitor can be calculated using the desired 3 dB roll-off frequency, as follows: Frequency f (3 dB) = 1/(2 × π × RIN × CIN) where RIN = 5.6 kΩ. Typically, a 2.2 μF capacitor is recommended. This sets the lower frequency cutoff, at 20 Hz, at approximately −1.5 dB. STEREO BOOST MODE LEFT MIX AINxL VCM AINxR VCM RIGHT MIX AINxR VCM DIFFERENTIAL BOOST MODE LEFT MIX AINxP VCM AINxN RIGHT MIX VCM DIFFERENTIAL PGA MODE AINxP LEFT MIX LEFT MIX VCM RIGHT MIX AINxN RIGHT MIX VCM 08975-025 VCM Figure 82. Typical Input Block for Stereo/Mono Differential Inputs in PGA Modes and Boost Modes Rev. 0 | Page 39 of 296 (1) ADAU1373 The MICBIAS1 and MICBIAS2 pins (Ball C8 and Ball C9, respectively) provide a voltage reference for electret analog microphones. These pins are independent MICBIASx voltage outputs that can be set using Register 0x21 to Register 0x23 of the I2C control registers. The MICBIASx voltage can be set via Register 0x21. Four output voltage settings are available: 1.8 V, 2.2 V, 2.6 V, and 2.9 V. If using a differential or balanced condenser microphone configuration, see Figure 84. MICBIASx PGA MODE 2kΩ AINxL/AINxP LEFT MICROPHONE AINxL/AINxN R1* Current sense circuits can detect the current going out of the MICBIAS1 pin or MICBIAS2 pin. This current detect function can be used to sense the presence of the electret microphone. The internally generated current sense logic output can be used as an interrupt on any of the four GPIOs to communicate to the system controller. The current sense can be enabled or disabled using Register 0x22 for MICBIAS1 and Register 0x23 for MICBIAS2. Additional options include overcurrent protection, which can be used to sense the short circuit of MICBIAS1 or MICBIAS2 to ground at the microphone inputs. The overcurrent threshold is programmable, allowing for flexibility in system design. The MICBIASx pins can also be used to supply voltage to digital microphones or analog microphones with separate power supply pins. However, the maximum current that is available from the MICBIAS1 or MICBIAS2 pin is 1.8 mA. ADAU1373 –12dB TO +18dB 2kΩ PGA MODE AINxR/AINxN RIGHT MICROPHONE AINxR/AINxP R2* –12dB TO +18dB 08975-022 Microphone Bias *R1 AND R2 CAN BE 2k Ω FOR DIFFERENTIAL OR 0Ω FOR PSEUDO-DIFFERENTIAL INPUT. Figure 84. Condenser Microphone Input, Differential Line Input Connection To use the analog input as the line input, configure the input to either stereo (single-ended) or mono (differential), as desired (see Figure 85 or Figure 86, respectively). Microphone Input Connection ADAU1373 To use the microphone input, first identify the type of microphone being used. The ADAU1373 provides microphone bias for condenser microphones. Set the bias voltage as required in the application. It is recommended that the bias be connected to the desired microphone input using a 2 kΩ resistor. LEFT LINE INPUT AINxL/AINxP –12dB TO +18dB If using a single-ended condenser microphone, see Figure 83 for the correct connection configuration. ADAU1373 PGA MODE RIGHT LINE INPUT LEFT MICROPHONE AINxR/AINxN 08975-010 AINxL/AINxP –12dB TO +18dB –12dB TO +18dB 2kΩ Figure 85. Single-Ended Line Input MICBIASx RIGHT PGA 2kΩ +INPUT AINxR/AINxN –12dB TO +18dB Figure 83. Condenser Microphone Input, Single-Ended –INPUT AINxR/AINxN Figure 86. Differential Line Input Rev. 0 | Page 40 of 296 08975-011 –12dB TO +18dB 08975-008 RIGHT MICROPHONE ADAU1373 AINxL/AINxP ADAU1373 Input Impedance Earpiece Mixer Output The input resistance for Analog Input 1 through Analog Input 4 (AINx, Ball A5 through Ball A8 and Ball B5 through Ball B8) depends on the gain mode setting. The input resistance is lowest (at approximately 5.6 kΩ) for a +18 dB gain in PGA mode, and it is highest (at approximately 47 kΩ) for a −12 dB setting. In boost mode, the input resistance is constant at 20 kΩ. The input resistance must be considered when calculating the required input coupling capacitor. It is recommended that the lowest value of the impedance be used when determining the microphone input coupling capacitor. The mixer prior to the earpiece amplifier allows selection of any or all of the four analog inputs, as well as the DAC output. When multiple inputs are selected, they are mixed prior to the earpiece output amplifier. Register 0x1C can be used to select the signals going to the earpiece mixer. Common-Mode Input Voltage The common-mode voltage at the input pins (AINx) is typically at AVDD/2. The common-mode voltage at the inputs is turned off when the inputs are muted. The common-mode voltage rises slowly as the inputs are unmuted and charges the input capacitors. To prevent the turn on pop, it is recommended that the inputs be unmuted in the ADAU1373 and be muted at the source. If this recommendation is not adhered to, there is a possibility of a turn on pop as the common-mode voltage at the inputs charges up. MIXER BLOCK The ADAU1373 provides the analog mixer block for mixing the analog inputs. The mixer block is available prior to the ADC, line output, headphone output, speaker output, and earpiece output, which provides the system designer with many configuration options. ADC Mixer Input ANALOG OUTPUTS Line Output The ADAU1373 provides two single-ended stereo line level outputs on LOUT1L (Ball C7) and LOUT1R (Ball D7) or on LOUT2L (Ball D8) and LOUT2R (Ball D9). The line level outputs can be configured as single-ended or differential. The stereo differential outputs are available on LOUTLP (Ball C7) and LOUTLN (Ball D8) or on LOUTRP (Ball D7) and LOUTRN (Ball D9). The line output control register (Register 0x24) can be used to set the line output mode. The outputs have series resistance to protect against output short circuit. The typical recommended load impedance is approximately 47 kΩ. The line output amplifier uses AVDD as its supply; therefore, the common-mode output level on the line output pins is AVDD/2. Coupling capacitors must be used before connecting the outputs to the desired load. The value of the capacitors can be determined by the following: Frequency f (3 dB) = 1/(2 × π × ROUT × COUT) where ROUT = 0.3 Ω. Set the desired 3 dB low frequency at the output. The line outputs can receive input from any or all of the four inputs directly or from the DAC (see Figure 87 and Figure 88 for block diagrams). The mixer prior to the line output amplifier allows selection of any or all of the four analog inputs, as well as the DAC outputs. When multiple inputs are selected, they are mixed prior to the line output amplifier. Register 0x14 through Register 0x17 can be used to select the signals that are input to the line mixer. The line outputs have a ground noise rejection feature that can be enabled using Register 0x24, Bit 2 (LNFBEN). When enabled, the line output amplifier rejects the noise on LN1FBIN (Ball E7) and LN2FBIN (Ball E8). To use this feature, E7 and E8 must be connected directly to the ground node (typically, the sleeve contact of the line output socket) using a capacitor. The ground noise rejection feature is very useful in applications where the line outputs are used to connect to an external audio system (such as a home theater or docking station) that works on a different power supply and can cause a ground loop when connected to the line output using a single-ended (unbalanced) connection. Headphone Mixer Output Line Output Full-Scale Level The mixer prior to the headphone output amplifier allows selection of any or all of the four analog inputs, as well as the DAC outputs. When multiple inputs are selected, they are mixed prior to the headphone output amplifier. Register 0x1A and Register 0x1B can be used to select the signals going to the headphone mixer. The full-scale output for the line output depends on AVDD. At AVDD = 1.8 V, the full-scale output level is 0.5 V rms singleended or 1 V rms differential. The full-scale input level scales linearly with the level of AVDD. The mixer prior to the ADC input allows selection of any or all of the four analog inputs. When multiple inputs are selected, they are mixed prior to the ADC. Register 0x12 and Register 0x13 can be used to select the signals that are input to the ADC mixer. Line Mixer Output Speaker Mixer Output The mixer prior to the headphone output amplifier allows selection of any or all of the four analog inputs, as well as the DAC outputs. Register 0x18 and Register 0x19 can be used to select the signals going to the speaker mixer. Line Output Volume Control The line output level can be controlled using Register 0x09 (Left Channel Line Output 1 volume control), Register 0x0A (Right Channel Line Output 1 volume control), Register 0x0B (Left Channel Line Output 2 volume control), and Register 0x0C (Right Channel Line Output 2 volume). The volume control range is from mute to 0 dB in 32 steps. Rev. 0 | Page 41 of 296 ADAU1373 LINE OUTPUT – STEREO SINGLE-ENDED (UNBALANCED) ADAU1373 IN1L IN2L IN3L IN4L DAC1L DAC1R DAC2L DAC2R L + R MIX STEREO L+R TO LEFT –75dB TO 0dB L+R TO RIGHT C7 LOUT1L/ C1 LOUTLP E7 LN1FBIN MUTE IN1R IN2R IN3R IN4R DAC1L DAC1R DAC2L DAC2R LINEOUT1 LEFT 1µF C2 1 2.2µF –75dB TO 0dB STEREO L+R TO LEFT L+R TO RIGHT MUTE IN1L IN2L IN3L IN4L DAC1L DAC1R DAC2L DAC2R D7 DIFF LOUT1R/ C3 LOUTRP 1µF R1 47kΩ UNBAL STEREO L+R TO LEFT –75dB TO 0dB L+R TO RIGHT D8 LOUT2L/ C4 LOUTLN E8 LN2FBIN MUTE IN1R IN2R IN3R IN4R DAC1L DAC1R DAC2L DAC2R LINEOUT1 RIGHT R2 47kΩ LINEOUT2 LEFT 1µF C5 1 2.2µF –75dB TO 0dB STEREO L+R TO LEFT L+R TO RIGHT MUTE D9 DIFF LOUT2R/ C6 LOUTRN LINEOUT2 RIGHT 1µF R3 47kΩ UNBAL R4 47kΩ 08975-027 1IF USING GROUND NOISE REJECTION FEATURE, CONNECT AT THE LINEOUT SOCKET GROUND PIN. Figure 87. Line Output Block Diagram, Stereo Single-Ended LINE OUTPUT – STEREO DIFFERENTIAL ADAU1373 IN1R IN2R IN3R IN4R DAC1L DAC1R DAC2L DAC2R IN1L IN2L IN3L IN4L DAC1L DAC1R DAC2L DAC2R L + R MIX STEREO L + R TO LEFT –75dB TO 0dB L + R TO RIGHT C7 LOUT1L/ LOUTLP E7 LN1FBIN LINEOUT LEFT + 1µF MUTE C2 1 2.2µF –75dB TO 0dB STEREO L + R TO LEFT L + R TO RIGHT MUTE D8 DIFF LOUT2L/ C3 LOUTLN 1µF R1 47kΩ UNBAL STEREO L + R TO LEFT –75dB TO 0dB D7 L + R TO RIGHT LOUT1R/ LOUTRP C4 LINEOUT LEFT – R2 47kΩ LINEOUT RIGHT + 1µF MUTE E8 IN1R IN2R IN3R IN4R DAC1L DAC1R DAC2L DAC2R C1 LN2FBIN C5 1 2.2µF –75dB TO 0dB STEREO L + R TO LEFT L + R TO RIGHT MUTE DIFF D9 UNBAL LOUT2R/ C6 LOUTRN 1µF R3 47kΩ 1IF USING GROUND NOISE REJECTION FEATURE, CONNECT AT THE LINEOUT SOCKET GROUND PIN. Figure 88. Line Output Block Diagram, Stereo Differential Rev. 0 | Page 42 of 296 LINEOUT RIGHT – R4 47kΩ 08975-028 IN1L IN2L IN3L IN4L DAC1L DAC1R DAC2L DAC2R ADAU1373 HEADPHONE OUTPUT The ADAU1373 provides a high efficiency Class-G stereo headphone output that is true ground centered; therefore, no external coupling capacitors are required for connection to the headphones. The headphones can be connected directly to the headphone output pins, HPL (Ball G8) and HPR (Ball G9). The headphone amplifier uses the supply provided at HPVDD (Ball H8). The recommended operating supply voltage is 1.8 V. This supply voltage must be decoupled with a 1 μF electrolytic capacitor, along with a 100 nF ceramic X7R capacitor. The headphone amplifier uses Class-G architecture and generates the required power supplies, using a flying capacitor with a built-in charge pump connected across CF1 (Ball J9) and CF2 (Ball J7). The charge pump switching frequency is approximately 500 kHz. The generated supply voltages are available at CPVDD (Ball H9, positive rail), and CPVSS (Ball H7, negative rail). The voltage at this node depends on the input signal to the amplifier. For lower input signal levels, the positive and negative rails are lowered, typically ±0.9 V for 1.8 V HPVDD. As the signal level increases, CPVDD and CPVSS are raised to a higher voltage of ±1.8 V for 1.8 V HPVDD. This rail switching allows the amplifier to achieve higher efficiency. In most typical usage conditions, the amplifier works on the lower ±0.9 V CPVDD and CPVSS voltages, thereby consuming lower power. In addition, as the amplifier generates the positive and negative rails, the output amplifier is true ground centered, thereby eliminating the need for big coupling capacitors to drive the load. For good audio performance, it is recommended that 1 μF, X7R ceramic decoupling capacitors be used for CPVDD and CPVSS. These capacitors serve as a reservoir for the headphone amplifier. In high efficiency mode, the rails are fixed at ±0.9 V, independent of the input signal level. This mode reduces the output power available from the amplifier and also reduces the amount of current consumed by the battery. In low efficiency mode, the rails are fixed at ±1.8 V, independent of the input signal level. This mode enables the amplifier to produce higher output levels, but current consumption is higher than in high efficiency mode. It is recommended that the default mode, Class-G mode, be used because the supply rails are switched based on the input level. The headphone amplifier also has a built-in overcurrent protection circuit that protects the amplifier against a short circuit to ground on the outputs. The overcurrent detect threshold level can be programmed to the desired load impedance level using Register 0x1D, Bits[1:0]. The available settings are 200 mA, 250 mA, 300 mA, and 350 mA. The turn on time for the headphone amplifier is programmable using Register 0x1D, Bits[5:4]. Four settings are available: 2 ms, 4 ms, 8 ms, and 16 ms. The headphone jack insertion detect feature can be used to turn off the speaker amplifier when the headphones are connected to the amplifier, thereby saving extra power consumed from the battery. Register 0x36, Bits[1:0] and Register 0x38, Bit 4 are provided to turn on this feature. Note that this feature requires the use of a headphone jack with a switch. See Figure 89 for more information. ≥ AVDD 100kΩ TYP The amplifier has built-in short-circuit protection and, therefore, shuts down in the event of a short circuit on the headphone outputs. ADAU1373 JACKDET HPL The headphone amplifier is designed to drive headphones with a minimum impedance of 16 Ω. The output level of the amplifier can be controlled using Register 0x0F (left channel headphone output volume control bits) and Register 0x10 (right channel headphone output volume control bits). In addition, the headphone amplifier can be set to different working modes, depending on the performance and power consumption requirements (Register 0x1D, Bits[3:2]). The available modes include Class-G (default), high efficiency, and low efficiency. In Class-G mode, the amplifier rails are switched between ±0.9 V and ±1.8 V, depending on the signal level. The threshold for rail switching in Class-G operation can be set to 300 mV, 400 mV, or 500 mV using Register 0x1E, Bits[6:5]. HPR SGND HEADPHONE JACK 08975-029 SGND (Ball G7) is provided for sensing the dc potential at the headphone socket. It is recommended that SGND be connected directly to the ground pin of the headphone socket, which ensures the lowest dc offset at the amplifier output and eliminates popand-click turn on/turn off for the amplifier. In addition, it helps reduce crosstalk between the left and right channel outputs. Figure 89. Headphone Jack Detect Option 1 In a typical application, the headphone amplifier is powered down, and its output is typically high impedance when inactive. Using Register 0x1E, Bit 4 (HIZ), the headphone outputs can be pulled down with a 300 Ω resistor. When set to a lower impedance, the JACKDET pin (Ball G5) is pulled to ground via the 300 Ω internal resistance of the headphone amplifier. When the headphone plug is inserted into the headphone socket, the switch at the tip of the socket is disconnected. This, in turn, pulls the JACKDET pin to logic high via Resistor R1. This change in logic level at the JACKDET pin can be used to initiate the interrupt on the GPIOx pin or can be read in the IRQ status register (Register 0xE7), Bit 1 (HP_DECT_STATUS). Rev. 0 | Page 43 of 296 ADAU1373 Figure 90 shows another option for similar functionality. The circuit in Figure 90 does not use the amplifier to pull down the JACKDET pin (Ball G5); instead, it uses an isolated switch in the headphone jack. SPKxN outputs. In addition, it monitors the junction temperature internally and shuts down if the temperature exceeds 150°C ± 15°C. In fault situations, the amplifier is switched to high-Z mode for safe and reliable operation. The logic change of the JACKDET pin is reported in Bit 4, Register 0x38. In addition, the debounced version of the logic change is provided in Register 0xE6, Bit 1. Register 0x36 can be used to control the state of the headphone amplifier and speaker amplifier. Table 10 lists the possible settings. The amplifier uses three-level PDM switching and an analog modulator with internal feedback. This method ensures good PSRR on the outputs. Three-level switching eliminates the need for an external output filter for connecting the speakers. However, it is important to ensure that the speakers be placed within 10 cm from the ADAU1373 to reduce EMI from the switching outputs. For best EMI performance, proper board layout is required. It is recommended that the supply voltage pins (G1, G2, H2, and H3) be decoupled to SPKGND (H4, H5, J1, and J5) with two 100 nF, X7R ceramic capacitors. Table 10. Headphone/Speaker Amplifier Control Settings 1 Reg. 0x36, Bit 1 0 1 1 1 1 Reg. 0x36, Bit 0 X1 0 0 1 1 Headphone Amplifier Status No change Power-down No change Power-down No change Speaker Amplifier Status No change No change Power-down Power-down No change The high efficiency amplifier outputs reduce power dissipation; however, thermal performance depends on layout of the board. The amplifier receives the input from the speaker mixer and includes a circuit to prevent pop-and-click during turn off and turn on. X = don’t care. The amplifier output level can be controlled using Register 0x0D (speaker out left gain control) and Register 0x0E (speaker out right gain control). For example, if Register 0x36, Bits[1:0] = 10 and JACKDET is high, the headphone amplifier is shut down, and the speaker amplifier status is unchanged. Note that the headphone or speaker amplifier cannot be turned on automatically, based on a JACKDET pin event. The amplifiers must be enabled via Register 0x27, a power management register. The amplifier can be set to work in mono or stereo mode using Register 0x1F. In mono mode, the left and right channel signals are mixed before being output to the speaker. The summed signal can be made available to either the left or right speaker output. SPEAKER OUTPUT Register 0x1F, Bits[5:4] can be used to set the mono amplifier mode for higher output current capability to drive low impedance loads. In this mode, the left and right channel output FETs are fed from one modulator only. The corresponding left and right channel outputs must be connected externally to take advantage of the low impedance drive capability. The ADAU1371 provides stereo Class-D amplifier outputs to drive the speakers directly. The three-level switching scheme allows the speaker load to be connected directly without any output filters; it also reduces idle power consumption and EMI by reducing switching. The amplifier outputs are differential and use full bridge topology. The amplifier has basic protections, such as the output short to SPKVDD, SPKGND, and the SPKxP and ADAU1373 PROG MIC-BIAS2 HP-L PCB JACK EVENT DETECT JACKDET SPKVDD MICBIASx 2kΩ AINxP 100kΩ TYP + MIC-PRE2 The default amplifier gain is 12 dB; it can be changed to 18 dB using Register 0x1F, Bit 3 (right channel) and Bit 2 (left channel). HPL 1µF HPR SGND 2.5mm/3.5mm MINI JACK HP-R Figure 90. Headphone Jack Detect Option 2 Rev. 0 | Page 44 of 296 08975-108 JACKDET Pin Status X1 1 0 1 0 ADAU1373 In addition, the amplifier provides edge rate control. The edge rate control can be used to set the switching output slew rate for precise EMI control. The edge rate can be used to reduce EMI in the 30 MHz to 100 MHz band. The slower edge rate reduces EMI but also compromises audio performance. The higher edge rate improves audio performance, but there is more energy in the 30 MHz to 100 MHz band than at the lower edge rate. The EDGE bits (Bits[1:0]) in Register 0x1F can be used for edge rate control. The ADC output level can be controlled before DSP processing in Register 0x72 (ADC left channel recording volume control) and Register 0x73 (ADC right channel recording volume control). Peak Detect The ADC has a peak detection feature that can be enabled or disabled using the PDETECT bit (Bit 0) in Register 0x3C. ADC RESET ADAU1373 LEFT AND RIGHT Digital ADC Volume Control The ADC can be reset by writing Bits[2:1] = 11 in Register 0x3C. By default, ADC reset is disabled. SPKLP ADC STATUS SPKLN The ADC status bits are available for reading via the NOCLKADC bit (Bit 0) in Register 0x37. +12dB/18dB DIGITAL-TO-ANALOG CONVERTER (DAC) SPKRN The ADAU1373 consists of two stereo Σ-Δ DACs (DAC1 and DAC2). Each DAC uses a 128 × fS clock and 24-bit resolution. The DACs receive input from either the DSP or the ADC. 08975-030 SPKRP Figure 91. Amplifier Connection Diagram, Mono Mode If only the DAC output is used during playback through the speaker, a mode is available that allows the DAC output to be sent directly and internally to the speaker simplifier block input instead of passing it through the mixer stage, which improves the signal-to-noise ratio at the speaker output by 6 dB. However, in this mode, the speaker mixer block is disabled, and only the DAC output can be routed to the speaker amplifier. The DIRCD bit (Bit 6) in Register 0x1F is used to enable this feature. ANALOG-TO-DIGITAL CONVERTER (ADC) The ADAU1373 consists of a stereo sigma-delta (Σ-Δ) ADC. The ADC uses a 128 × fS clock and 24-bit resolution. The input signal to the ADC is provided via the ADC mixer. Any or all of the four inputs can be selected to be sent to the ADC using the ADCLMIXx bits (Bits[4:0]) in Register 0x12 for the left channel and the ADCRMIXx bits (Bits[4:0]) in Register 0x13 for the right channel. The ADC output can be made available on the digital audio ports or sent to the on-chip DAC for analog output. DAC output can be routed to the line output, headphone output, earpiece output, or speaker output. DAC Full-Scale Level The full-scale output for the DAC, with 0 dBFS input, depends on AVDD. At AVDD = 3.3 V, the full-scale output level is 0.55 V rms single-ended or 1 V rms differential. The full-scale input level scales linearly with the level of AVDD. Digital DAC Volume Control The DAC output level can be attenuated using Register 0x6E (DAC1 left channel playback volume control), Register 0x6F (DAC1 right channel playback volume control), Register 0x70 (DAC2 left channel playback volume control), and Register 0x71 (DAC2 right channel playback volume control). DAC Status The DAC status bits are available for reading at Bits[6:5] in Register 0x37. ADC Full-Scale Level CLOCK GENERATION AND DISTRIBUTION The full-scale input to the ADCs (0 dBFS) depends on AVDD. At AVDD = 3.3 V, the full-scale input level is 0.55 V rms singleended or 1 V rms differential. The full-scale input level scales linearly with the level of AVDD. For single-ended and pseudodifferential signals, the full-scale value corresponds to the signal level at the pins, which is 0 dBFS. Signal levels above the full-scale value cause the ADCs to clip. The ADAU1373 requires an external clock for operation. Flexible clocking control enables the use of many different input clock rates. The on-chip PLL can be used to dejitter the external clock. Two identical PLL blocks, PLLA and PLLB, are provided and can be bypassed if not required. Figure 92 shows the top level block diagram for PLL. PLL TOP LEVEL CLOCK > 8MHz 44.1kHz × 1024/ 48kHz × 1024 APLL ÷X ×(R + N/M) DPLL ÷ Nd × Md CLOCK < 8MHz 08975-012 BCLKA BCLKB BCLKC MCLK1 LRCLKA LRCLKB LRCLKC GPIO1 GPIO2 GPIO3 GPIO4 MCLK2 Figure 92. PLL Top Level Block Diagram Rev. 0 | Page 45 of 296 ADAU1373 The PLL block consists of a digital PLL (DPLL), followed by an analog PLL (APLL) with multiplexer. This architecture allows flexibility in providing the clock to the ADAU1373. The DPLL can accept clock rates from 8 kHz to 8 MHz and outputs clock frequencies from 8 MHz to 27 MHz. The APLL can accept the clock output from the DPLL and provide further fine resolution to generate the clocks for internal blocks. If the input clock is greater than 8 MHz, the DPLL can be powered down to save power. In such a case, the external clock can be sent directly to the APLL. See Figure 93 for a diagram of clock distribution inside the ADAU1373. PLLA REG. 0x28 DPLLA_CTRL BCLKA BCLKB BCLKC MCLK1 LRCLKA LRCLKB LRCLKC GPIO1 GPIO2 GPIO3 GPIO4 MCLK2 EXTERNAL CLOCK > 8MHz ÷N CLK1SDIV ANALOG PLLA DPLLA_CLK_OUT fINA ÷X × (R + N/M) ×1024 (1024 × 48kHz)/(1024 × 44.1kHz) ÷ (K + 1) CLK1 OUT 3-BIT DIVIDER K = 0 TO 7 ÷ 1 TO 8 R = 0 TO 15 X = 1 TO 4 X = 1 DEFAULT M AND N 16-BIT BINARY NUMBER R = 2 DEFAULT M = 253 DEFAULT N = 0 DEFAULT PLLA BYPASS CORE CLOCK ENABLE DPLLA LOCK INDICATOR DPLLA DPLLA_REF_SEL APLLA CLOCK OUT EXTERNAL CLOCK PLL DPLLA_NDIV 1....1024 IN 11 STEPS 8kHz TO 8MHz CLK1_SOURCE_DIV (REG. 0x40) REG. 0x29 THROUGH REG. 0x2E PLLA CONTROL REGISTER MCLK1DIV 48kHz × 256 44.1kHz × 256 ÷ (J + 1) 32kHz × 256 3-BIT DIVIDER J = 0 TO 7 ÷ 1 TO 8 128 × fs ÷2 128 × fs 256 × fs ADC CLK/ DAC1/2 CLK INT CLK/ DEC CLK/ FDSP CLK ASRC CLK/ AIFCLKA CLK1_OUTPUT_DIV (REG. 0x41) CLK1ODIV ÷ (P + 1) 5-BIT DIVIDER P = 0 TO 31 ÷ 1 TO 32 MCLK1 OUT PLLB REG. 0x2F DPLLB_CTRL BCLKA BCLKB BCLKC MCLK1 LRCLKA LRCLKB LRCLKC GPIO1 GPIO2 GPIO3 GPIO4 MCLK2 EXTERNAL CLOCK > 8MHz ÷N ANALOG PLLB DPLLB_CLK_OUT fINB ÷X × (R + N/M) ×1024 (1024 × 48kHz)/(1024 × 44.1kHz) R = 0 TO 15 X = 1 TO 4 X = 1 DEFAULT M AND N 16-BIT BINARY NUMBER R = 2 DEFAULT M = 253 DEFAULT PLLB BYPASS N = 0 DEFAULT DPLLB LOCK INDICATOR DPLLB DPLLB_REF_SEL APLLB CLOCK OUT EXTERNAL CLOCK PLL DPLLB_NDIV 1....1024 IN 11 STEPS 8kHz TO 8MHz CLK2_SOURCE_DIV (REG. 0x42) CLK2SDIV MCLK2DIV REG. 0x30 THROUGH REG. 0x35 PLLB CONTROL REGISTER CLK2 OUT ÷ (K + 1) 3-BIT DIVIDER K = 0 TO 7 ÷ 1 TO 8 ÷ (J + 1) 3-BIT DIVIDER J = 0 TO 7 ÷ 1 TO 8 32kHz × 256 44.1kHz × 256 48kHz × 256 256 × fs CLK2_OUTPUT_DIV (REG. 0x43) CLK2ODIV ÷ (P + 1) 5-BIT DIVIDER P = 0 TO 31 ÷ 1 TO 32 DECIMATOR DIGITAL MIC 2 INPUT DIGITAL MIC 1 INPUT DECIMATOR ANALOG IN MIXER DEC_CLK (128 × fS) DEC_CLK (128 × fS) OUTPUT MIXER DAC1_PB FS_A_EXT DIN_A FDSP_CH1_DOUT FDSP_CH1_DIN DEC_CLK (128 × fS) DAC2_PB DAC2 DOUT_A FDSP_CH0_DIN ADC/ DMIC1_DOUT DAC1 BCLK_A FDSP_CH0_DOUT DEC_CLK (128 × fS) ADC ADC/ DMIC1 MCLK2_OUT DMIC2_DOUT 64 × f S DMIC_CLK AIFCLKB FS_A_INT DIGITAL AUDIO INTERFACE A FS_DSP BCLK_A DOUT_A MIX/MUX DSP BCLK_DSP ASRCA DIN_A DOUT_DSP DIN_DSP AIFA_REC AIFA_PB FDSP_CH2_DOUT FDSP_CH2_DIN AIFCLK_A AIFCLK_B FS_B_EXT BCLK_B DOUT_B DIN_B FS_B_INT DIGITAL AUDIO INTERFACE B FS_DSP BCLK_B DOUT_B BCLK_DSP ASRCB DIN_B DOUT_DSP DIN_DSP AIFB_REC AIFB_PB FDSP_CH3_DOUT FDSP_CH3_DIN AIFCLK_A AIFCLK_B FS_C_INT BCLK_C DOUT_C DIN_C DIGITAL AUDIO INTERFACE C FS_DSP BCLK_C DOUT_C DIN_C BCLK_DSP ASRCC DOUT_DSP DIN_DSP AIFCLK A AIFCLK B (256 × f S) AIFC_REC AIFC_PB FDSP_CH4_DOUT FDSP_CH4_DIN ASRC_CLK (256 × fS) FDSP_CLK (128 × fS) Figure 93. Clock Distribution Rev. 0 | Page 46 of 296 08975-013 FS_C_EXT ADAU1373 DPLL APLL The DPLL consists of a phase comparator, followed by a highpass filter and integrators. The following equation shows the relationship of input-to-output frequency: The APLL provides the fine resolution required to generate clocks for the internal blocks. It uses either the clock input at the MCLK1 pin (Ball C2) or a DPLL output as a reference to generate the core clock. The PLL can be set for either integer or fractional mode. The PLL multiplier and divider (X, R, M, and N) are programmed using Register 0x29 to Register 0x2D for PLLA and Register 0x30 to Register 0x34 for PLLB. The PLL can accept input frequencies in the range of 8 MHz to 27 MHz, either directly from an external source, if the external clock input is greater than 8 MHz, or from the DPLL, if the external clock input is within a range of 8 kHz to 8 MHz. The PLL lock range is 45.158 MHz to 49.152 MHz. fOUT = (fIN/ND) × MD where: fOUT is the DPLL output frequency (8 MHz to 27 MHz). fIN is the DPLL input frequency (8 kHz to 8 MHz). ND is the divider. It can be set to 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024, using Bits[3:0] (DPLLA_NDIV) in Register 0x28 for DPLLA and Bits[3:0] (DPLLB_NDIV) Register 0x2F for DPLLB. MD is the multiplier (fixed internally to 1024). DPLL Divider Example fIN = 8 kHz fOUT = 8 MHz ND = 8 × 1024/8 = 1.024 This sets the PLL output frequency based on the sample rate governed by the following equation: fPLL = 256 × fS × (J + 1) × (K + 1) Setting ND to 1 results in fOUT ≥ 8 MHz. Therefore, ND should be set to 1. Core Clock The core clock is derived directly from the external clock at the MCLK1 or MCLK2 pins or from the PLL. The PLLA_EN bit for PLLA (Bit 0 in Address 0x2E) and the PLLB_EN bit for PLLB (Bit 0 in Address 0x35) can be used to enable or disable the PLL. Clocks for the converters, the serial ports, and the DSP are derived from the core clock. The core clock rate is always an integer multiple of the desired sample rate used inside the part. Case 1—PLL Bypassed (Using External Clock as Core Clock) If the PLL is bypassed, the clock available at MCLK1 (Ball C2) or MCLK2 (Ball D1) is used as the core clock. Therefore, fCORE = fIN. As the PLL is bypassed, the frequency of the clock at the MCLKx pins must be set properly, using the clock divider bits, CLK1SDIV, Bits[5:3], and MCLK1DIV, Bits[2:0], in Register 0x40 for PLLA and CLK2SDIV, Bits[5:3], and MCLK2DIV, Bits[2:0] in Register 0x42 for PLLB. The required external clock rate can be determined by the following equation, in which J and K are the clock dividers: fIN × (R + N/M) ÷X TO PLL CLOCK DIVIDER 08975-014 where J, K = 0, 1, 2, …7. Figure 94. APLL Block Diagram The APLL can be used in either integer mode or fractional mode. Integer Mode Integer mode is used when the MCLK frequency is an integer multiple of the PLL output (1024 × fS) frequency, governed by the following equation: fPLL = (R/X) × fIN where fPLL = 1024 × fS For example, if fIN = 12.288 MHz and fS = 48 kHz, then fPLL (PLL Required Output) = 1024 × 48 kHz = 49.152 MHz R/X = 49.152 MHz/12.288 MHz = 4 Therefore, R and X are set as follows: R = 4, and X = 1 (default). In integer mode, the values set for N and M are ignored. Table 13 shows common integer PLL parameter settings for fS = 48 kHz sampling rates. Fractional Mode fIN = 256 × fS × (J + 1) × (K + 1) See Table 14, Table 15, and Table 16 for some possible options for external clock rates. Note that clock rates greater than 50 MHz require careful attention to the clock driver and board layout to maintain signal integrity. Be sure that this clock is available to the MCLKx input pins before enabling the COREN bit (Bit 7, core clock enable) in Register 0x40. Fractional mode is used when the available MCLK is a fractional multiple of the desired PLL output; it is governed by the following: fPLL = fIN × (R + (N/M))/X For example, MCLK = 12 MHz and fS = 48 kHz. The PLL output is 1024 × fS. PLL Output = 1024 × 48 kHz = 49.152 MHz To find the values of R, N, and M, use the following equation: Case 2—PLL Enabled fPLL = fIN × (R + (N/M))/X The internal PLL can be used to generate the core clock from the external clock. The internal PLL has two modes of operation: integer mode and fractional mode. Therefore, fCORE = fPLL. where fPLL = 49.152, and fIN = 12 MHz. (R + (N/M))/X = 49.152 MHz/12 MHz = 4 + (12/125) See Table 11 and Table 12 for common fractional PLL parameter settings for 44.1 kHz and 48 kHz sampling rates. Rev. 0 | Page 47 of 296 ADAU1373 Table 11, Table 12, and Table 13 also list the typical PLL settings at 44.1 kHz and 48 kHz sample rates. Note that the PLL control setting in hexadecimal format represents the 48 bits (six bytes) for either PLLA or PLLB. For PLLA, the six bytes should be written starting from Register 0x29 through Register 0x2E. For PLLB, the six bytes should be written starting from Register 0x30 through Register 0x35. To program the PLL during initialization or reconfiguration of the clock setting, use the following procedure: PLL Lock Acquisition 4. The core clock for the device is disabled until the core clock enable bit (Bit 7, COREN) in Register 0x40 is set to 1. It is recommended that the audio outputs not be turned on until PLL lock is established. 5. 1. 2. 3. 6. Bring the required blocks out of power-down (Register 0x25 to Register 0x27). Ensure that the core clock is disabled (Register 0x40, Bit 7 = 0). Enable the PLL (Register 0x2E, Bit 0, for PLLA; Register 0x35, Bit 0, for PLLB). Set the PLL control registers for the desired clock rate (Register 0x28 to Register 0x2D for PLLA and Register 0x2F to Register 0x34 for PLLB). Poll the lock bit (Register 0x2E, Bit 2, and Register 0x35, Bit 2, for APLL and Register 0x2E, Bit 3, and Register 0x35, Bit 3, for DPLL). If the lock bit is set, proceed to Step 6; otherwise, continue to poll. If no lock is established, check the clock rate settings and clock to the device. To ensure that the various blocks in the device are clocked correctly, assert the core clock enable bit only after PLL lock is acquired. Table 11. Fractional PLL Parameter Settings for 44.1 kHz Base Sample Rate (PLL Output = 45.1584 MHz = 1024 × fS) MCLK Input (MHz) 8 12 13 14.4 19.2 19.68 19.8 24 26 27 Input Divider (X) 1 1 1 2 2 2 2 2 2 2 Integer (R) 5 3 3 6 4 4 4 3 3 3 Denominator (M) 625 625 8125 125 125 1025 1375 625 8125 1875 Numerator (N) 403 477 3849 34 88 604 772 477 3849 647 PLL Control Setting (Hex) 0x0271 0193 2901 0x0271 01DD 1901 0x1FBD 0F09 1901 0x007D 0022 3301 0x007D 0058 2301 0x0401 025C 2301 0x055F 0304 2301 0x0271 01DD 1B01 0x1FBD 0F09 1B01 0x0753 0287 1B01 Table 12. Fractional PLL Parameter Settings for 48 kHz Base Sample Rate (PLL Output = 49.152 MHz = 1024 × fS) MCLK Input (MHz) 8 12 13 14.4 19.2 19.68 19.8 24 26 27 Input Divider (X) 1 1 1 2 2 2 2 2 2 2 Integer (R) 6 4 3 6 5 4 4 4 3 3 Denominator (M) 125 125 1625 75 25 205 825 125 1625 1125 Numerator (N) 18 12 1269 62 3 204 796 12 1269 721 PLL Control Setting (Hex) 0x007D 0012 3101 0x007D 000C 2101 0x0659 04F5 1901 0x004B 003E 3301 0x0019 0003 2B01 0x00CD 00CC 2301 0x0339 031C 2301 0x007D 000C 2301 0x0659 04F5 1B01 0x0465 02D1 1B01 Table 13. Integer PLL Parameter Settings for fS = 48 kHz (PLL Output = 49.152 MHz = 1024 × fS) MCLK Input (MHz) 12.288 24.576 1 Input Divider (X) 1 1 Integer (R) 4 2 Denominator (M) Don’t care Don’t care X = don’t care. Rev. 0 | Page 48 of 296 Numerator (N) Don’t care Don’t care PLL Control Setting (Hex) 1 0xXXXX XXXX 2001 0xXXXX XXXX 1001 ADAU1373 SAMPLING RATES Step 2—Determine Divider J and Divider K The ADCs, DACs, and DSP share a common sampling rate (fS) that is determined based on the core clock rate. Three digital audio interface ports are available for the ADAU1373. Each port is provided with an asynchronous sample rate converter (ASRC). If the ASRCs are used, the sample rate at the digital ports can be different from the internal sample rate. However, the sample rate used internally must be equal to or higher than the sample rate at the ports. The PLL output or external clock input is divided down to get the required 256 × fS core clock. Two clock dividers (CLK1SDIV, Bits[5:3], and MCLK1DIV, Bits[2:0] in Register 0x40 for PLLA and CLK2SDIV, Bits[5:3], and MCLK2DIV, Bits[2:0] in Register 0x42 for PLLB) are provided; each clock divider can be set from 1 to 8. The CLKxSDIV bits set the K value, and the MCLKxDIV bits set the J value of the divider. See Figure 93 for more details. See Table 14, Table 15, and Table 16 for some possible options. SETTING THE PLL AND CLOCK RATES Next, depending on the whether the direct external clock or PLL is used, select the appropriate equation from the following sections. For proper operation of the ADAU1373, the device must be set for correct clock rates. Following are the recommended steps: External Mode Step 1—Sample Rate (fS) Determine the desired operating sample rate (fS) for the internal blocks. fS is based on either 48 kHz (48 kHz, 32 kHz, 24 kHz, 16 kHz, 8 kHz) or 44.1 kHz (44.1 kHz, 22.05 kHz, 11.025 kHz, 8.0182 kHz). If the ASRCs are bypassed, this is the operating sample rate at Digital Audio Interface A, Digital Audio Interface B, and Digital Audio Interface C. In the external mode, the external clock frequency determines the internal device operation clock rate. If using external mode, fIN = 256 × D × fS where D = (J + 1) × (K + 1). For external clock use, see Table 14, Table 15, and Table 16 for some possible choices. Note that clock input frequencies above 50 MHz, although possible, require careful attention—especially on clock driver and board layout to maintain signal integrity and lower EMI. Table 14. 48 kHz Sample Rate (fS) Input MCLK fIN 256 × fS (12.288 MHz) 512 × fS (24.576 MHz) 768 × fS (36.864 MHz) 1024 × fS (49.152 MHz) Register Setting CLKxSDIV, Bits[5:3] 000 000 000 000 Divider K=0 0 0 0 0 Divider Ratio K+1 1 1 1 1 Register Setting MCLKxDIV, Bits[5:3] 000 001 010 011 Divider J 0 1 2 3 Divider Ratio J+1 1 2 3 4 Divider K=0 0 0 0 0 Divider Ratio K+1 1 1 1 1 Register Setting MCLKxDIV, Bits[5:3] 000 001 010 011 Divider J 0 1 2 3 Divider Ratio J+1 1 2 3 4 Divider K=0 0 0 0 0 0 0 Divider Ratio K+1 1 1 1 1 1 1 Register Setting MCLKxDIV, Bits[5:3] 000 001 010 011 100 101 Divider J 0 1 2 3 4 5 Divider Ratio J+1 1 2 3 4 5 6 Table 15. 44.1 kHz Sample Rate (fS) Input MCLK fIN 256 × fS (11.289 MHz) 512 × fS (22.5792 MHz) 768 × fS (33.8688 MHz) 1024 × fS (45.1584 MHz) Register Setting CLKxSDIV, Bits[5:3] 000 000 000 000 Table 16. 32 kHz Sample Rate (fS) Input MCLK fIN 256 × fS (8.192 MHz) 512 × fS (16.384 MHz) 768 × fS (24.576 MHz) 1024 × fS (32.768 MHz) 1280 × fS (40.96 MHz) 1536 × fS (49.152 MHz) Register Setting CLKxSDIV, Bits[5:3] 000 000 000 000 000 000 Rev. 0 | Page 49 of 296 ADAU1373 PLL Mode If using the PLL, set the dividers so that fPLL is within the range of 45.158 MHz (1024 kHz × 44.1 kHz) to 49.152 MHz (1024 kHz × 48 kHz). Example 1—Using a PLL Sample Rate of 48 kHz For a 48 kHz sample rate (fS), select the J and K such that fPLL is within the range of 45 MHz to 50 MHz. fPLL = 256 × D × 48,000 For D = 3, fPLL = 36.864 MHz; for D = 4, fPLL = 49.152 MHz; and for D = 5, fPLL = 61.44 MHz. Setting D = 4 ensures that fPLL is within the PLL range of 45 MHz to 50 MHz. To determine the divider values, there are two options, as follows: By setting J = K = 1, then D = 4 because D = (J + 1) × (K + 1). By setting J = 0, K = 3 also results in D = (J + 1) × (K + 1) = 4. Example 2—Using a PLL Sample Rate of 44.1 kHz For a 44.1 kHz sample rate (fS), select the J and K such that fPLL is within the range of 45 MHz to 50 MHz. fPLL = 256 × D × 44,100 where D = (J + 1) × (K + 1). For D = 3, fPLL = 33.868 MHz; for D = 4, fPLL = 45.158 MHz; and for D = 5, fPLL = 56.448 MHz. Setting D = 4 ensures that fPLL is within the PLL range of 45 MHz to 50 MHz. To determine the divider values, there are two options, as follows: By setting J = K = 1, then D = 4 because X = (J + 1) × (K + 1). By setting J = 0, K = 3 also results in D = (J + 1) × (K + 1) = 4. Example 3—Using a PLL Sample Rate of 32 kHz For a 32 kHz sample rate (fS), select the J and K such that fPLL is within the range of 45 MHz to 50 MHz. fPLL = 256 × D × 32,000 where D = (J + 1) × (K + 1). Setting J = 1 and K = 2 can result in D = 6. Setting J = 0 and K = 5 also results in D = 6. Step 3—Calculate APLL multiplier/dividers (X, R, N, M) If using the analog PLL only, then fIN ≥ 8 MHz. Next, using the fPLL calculated in Step 2, calculate the PLL X, R, N, and M values. where D = (J + 1) × (K + 1). • • To determine the divider values, there are two options, as follows: • • fPLL = 256 × fS × (J + 1) × (K + 1) • • For D =5, fPLL = 40.96 MHz; for D = 6, fPLL = 49.152 MHz; and for D = 7, fPLL = 57.344 MHz. Setting D = 6 ensures that fPLL is within the PLL range of 45 MHz to 50 MHz. For integer mode, use the following: fPLL = (R/X) × fIN N and M are ignored. For fractional mode, use the following: fPLL = fIN × (R + (N/M))/X Select the values of R and X for integer mode or R, X, N, and M for fractional mode. If the available clock in the system (fIN) is known, and using the PLL output frequency (fPLL) from Step 2, the values required for X, R, N, and M for fractional mode or X and R for integer mode can be calculated using the following equation: (R/X) = fIN/fPLL (integer mode) (R + N/M)/X = fIN/fPLL (fractional mode) Wide selections are possible; refer to Table 11, Table 12, and Table 13 for popular choices. Step 4—Master Clock Output The internal core clock, fCORE, can be made available at the GPIO1/GPIO2/GPIO3/GPIO4 pins by setting Register 0xE3 or Register 0xE4. The master clock output frequency can be set using the 5-bit divider (Register 0x41 for PLLA and Register 0x43 for PLLB). Table 17 lists the registers that are used to set the PLL, and Table 18 provides descriptions of the 48 bits that are used for PLL control. Rev. 0 | Page 50 of 296 ADAU1373 Table 17. PLL Control Register Summary Reg 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x40 Name DPLLA_CTRL PLLA_CTRL1 PLLA_CTRL2 PLLA_CTRL3 PLLA_CTRL4 PLLA_CTRL5 PLLA_CTRL6 DPLLB_CTRL PLLB_CTRL1 PLLB_CTRL2 PLLB_CTRL3 PLLB_CTRL4 PLLB_CTRL5 PLLB_CTRL6 CLK1_ SOURCE_DIV 0x41 CLK1_ OUTPUT_DIV 0x42 CLK2_ SOURCE_DIV 0x43 CLK2_ OUTPUT_DIV Bit 7 Bit 6 Bit 5 DPLLA_REF_SEL Bit 4 Bit 3 Bit 2 Bit 1 DPLLA_NDIV Bit 0 PLLA_M_HI PLLA_M_LO PLLA_N_HI PLLA_N_LO RESERVED PLLA_R RESERVED DPLLB_REF_SEL DPLLA_LOCKED PLLA_LOCKED PLLA_X DPLLA_BYPASS DPLLB_NDIV PLLA_TYPE PLLA_EN PLLB_LOCKED PLLB_X DPLLB_BYPASS MCLK1DIV PLLB_TYPE PLLB_EN PLLB_M_HI PLLB_M_LO PLLB_N_HI PLLB_N_LO RESERVED PLLB_R RESERVED COREN DPLLB_LOCKED CLK1S_SEL RESERVED CLK2EN CLK1SDIV CLK1OEN CLK1ODIV CLK2S_SEL RESERVED CLK2SDIV CLK2OEN MCLK2DIV CLK2ODIV Reset 0x00 0x00 0x00 0x00 0x00 0x00 0x10 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW MMRW 0x00 RW 0x00 MMRW 0x00 RW Table 18. PLLA/PLLB Control Register Settings (PLLA: Register 0x28 to Register 0x2E; PLLB: Register 0x2F to Register 0x35) Bits [47:32] Bit Name PLLx_M_HI[7:0], PLLx_M_LO[7:0] [31:16] PLLx_N_HI[7:0], PLLx_N_LO[7:0] [15] [14:11] Reserved PLLx_R[3:0] Settings 0010 0011 0100 0101 0110 0111 1000 [10:9] PLLx_X[1:0] 00 01 10 11 8 PLLx_TYPE 0 1 [7:4] Reserved Description Denominator of the fractional APLL: a 16-bit binary number. The PLLA/PLLB Control M value can be set using Register 0x29 and Register 0x2A for PLLA and Register 0x30 and Register 0x31 for PLLB. The M integer is 16 bits wide. The upper eight bits are stored in Register 0x29 and Register 0x30, and the lower eight bits are stored in Register 0x2A and Register 0x31. The default value is 0x00FD: M = 253. Numerator of the fractional APLL: a 16-bit binary number. The N value can be set using Register 0x2B and Register 0x2C for PLLA and Register 0x32 and Register 0x33 for PLLB. The upper eight bits are stored in Register 0x2B and Register 0x32, and the lower eight bits are stored in Register 0x2C and Register 0x33. The default value is 0: N = 0. Reserved. Integer part of APLL: four bits. Only values of 2 to 8 are valid. The four bits are stored in Register 0x2D for PLLA (Bits[6:3]) and Register 0x34 for PLLB (Bits[6:3]). R = 2 (default). R = 3. R = 4. R = 5. R = 6. R = 7. R = 8. APLL input clock divider. The two bits are stored in Register 0x2D for PLLA (Bits[2:1]) and Register 0x34 for PLLB (Bits[2:1]). X = 1 (default). X = 2. X = 3. X = 4. APLL operation mode. This bit is stored in Register 0x2D for PLLA (Bit 0) and Register 0x34 for PLLB (Bit 0). Integer mode (default). Fractional mode. Reserved. Rev. 0 | Page 51 of 296 ADAU1373 Bit Name DPLLx_LOCKED 2 PLLx_LOCKED 1 DPLLx_BYPASS 0 PLLx_EN Settings Description DPLLx lock (read-only bit). This bit is stored in Register 0x2E for PLLA (Bit 3) and Register 0x35 for PLLB (Bit 3). 0: DPLLx unlocked (default). 1: DPLLx locked. APLL lock (read-only bit). This bit is stored in Register 0x2E for PLLA (Bit 2) and Register 0x35 for PLLB (Bit 2). 0: APLL unlocked (default). 1: APLL locked. DPLL bypass bit. This bit is stored in Register 0x2E for PLLA (Bit 1) and Register 0x35 for PLLB (Bit 1). 0: DPLLx not bypassed (default). 1: DPLLx bypassed. APLL enable bit. This bit is stored in Register 0x2E for PLLA (Bit 0) and Register 0x35 for PLLB (Bit 0). 0: APLL disabled (default). 1: APLL enabled. DIGITAL MICROPHONE INPUT INTERFACE ADAU1373 The ADAU1373 supports the digital microphone inputs. The digital microphone output data can be connected at the DMIC1_2_DATA and DMIC3_4_DATA pins (Ball B4 and Ball C6, respectively). The bit clock for the digital microphone is available at the DMIC_CLK pin (Ball A4). The bit clock is fixed at 64 × fS (see Figure 5 for the waveforms). Four digital microphones or two stereo pairs of digital microphones can be connected to the ADAU1373 (see Figure 95 and Figure 96). The single pair of digital microphones shares the decimator with ADC; therefore, when using DMIC1_2_DATA, the ADC is not available. However, DMIC3_4_DATA has a separate decimator and, therefore, can be used independently. 0.1µF DMIC1_2_DATA DMIC_CLK DMIC3_4_DATA 0.1µF DMIC1_2_DATA DMIC_CLK DMIC3_4_DATA DMIC1 DMIC2 Figure 96. Digital Microphone Connection Diagram for Two Microphones To enable digital microphone support, the digital recording engine must be enabled first, using Register 0xEB. The Digital Microphone 1/Digital Microphone 2 engine can be enabled using Bit 2 of Register 0xEB, and the Digital Microphone Input 3/Digital Microphone 4 engine can be enabled using Bit 3 of Register 0xEB. ADAU1373 IOVDD4 IOVDD4 08975-106 Bits 3 DMIC1 After the recording engine is enabled, the digital microphone input block can be enabled using Register 0xE2, Bit 0 for Input 1/ Input 2 (DMIC1_2_DATA) and Bit 2 for Input 3/Input 4 (DMIC3_4_DATA). The digital microphone data input is then routed through the decimator and the recording engine to digital mix/mux. DMIC2 By default, the digital microphone inputs are configured as a stereo pair. If using only one microphone, use Register 0xE2, Bit 7, to set it as mono input. The bit clock required for the digital microphone is available at the DMIC_CLK pin (Ball A4), and the drive capability can be set using Register 0xE9, Bit 3. DMIC4 08975-107 DMIC3 Figure 95. Digital Microphone Connection Diagram for Four Microphones Rev. 0 | Page 52 of 296 ADAU1373 DIGITAL AUDIO INTERFACE The ADAU1373 provides three digital audio interface ports: Digital Audio Interface A, Digital Audio Interface B, and Digital Audio Interface C. Each port can receive and transmit audio data in various serial formats. The ports can be configured as master or slave, accommodating many possible system design combinations. Each port has a frame clock (LRCLKA to LRCLKC), a bit clock (BCLKA to BCLKC), and data receive and data transmit pins (SDATAINA to SDATAINC and SDATAOUTA to SDATAOUTC) available. The possible serial audio data formats are right justified, left justified, I2S, and DSP mode. The format for the ports can be set using Register 0x44 for Digital Audio Interface A, Register 0x45 for Digital Audio Interface B, and Register 0x46 for Digital Audio Interface C. The serial data is received or transmitted MSB first, followed by the remaining data bits. For more information about the serial data input/output formats, see Figure 98 to Figure 100. The registers allow each port to be set independently, as either master or slave. In addition, these registers provide controls for bit clock polarity, swapping left/right data, inverting the frame clock, and adjusting data width. Figure 97 shows the audio interface and ASRC block diagram. Digital Audio Interface A, Digital Audio Interface B, and Digital Audio Interface C can go through the ASRC or directly to the internal digital engine. The ASRCs on each port allow system design flexibility to accommodate sample rates at the ports that are different from those accommodated by the internal DSP. The digital audio interface ports can be independently configured as master or slave by using the MSx bit (Bit 6) in Register 0x44, Register 0x45, and Register 0x46 for Digital Audio Interface A, Digital Audio Interface B, and Digital Audio Interface C, respectively. This allows a number of different options for using the three ports. When the ports are configured in master mode, the ports derive the bit clock and frame clock using either AIFCLKA or AIFCLKB, which are derived from PLLA and PLLB, respectively. The sample rate can be selected using Bits[4:2] in Register 0x47, Register 0x48, and Register 0x49 for Digital Audio Interface A, Digital Audio Interface B, and Digital Audio Interface C, respectively. In slave mode, the port accepts the bit clock and the frame clock from the master in the system. If the ASRCs are enabled, the port is not required to be synchronous to the master clock. However, if the ASRCs are disabled, ensure that the port is synchronous to the master in the system by providing the master clock from the respective master. DAC1 DAC2 ADC/ DMCA DMCB CODEC ENGINE fS_A_INT BCLK_A DOUT_A DIGITAL AUDIO INTERFACE A DOUT_A fS_DSP BCLK_DSP ASRCA DOUT_DSP DIN_A DIN_DSP fS_B_EXT fS_B_INT fS_DSP BCLK_B BCLK_B BCLK_DSP DIN_A DOUT_B DIN_B DIGITAL AUDIO INTERFACE B DOUT_B DIN_B fS_C_EXT fS_C_INT BCLK_C BCLK_C DOUT_C DIN_C DIGITAL AUDIO INTERFACE C AIFCLKA DOUT_C ASRCB DIN_DSP MIX/MUX AIFB_REC AIFB_PB FDSP_CH2_DOUT FDSP_CH2_DIN DSP FDSP_CH3_DOUT FDSP_CH3_DIN fS_DSP BCLK_DSP ASRCC DIN_C AIFCLKB (256 × fS) DOUT_DSP AIFA_REC AIFA_PB DOUT_DSP DIN_DSP AIFC_REC AIFC_PB FDSP_CH4_DOUT FDSP_CH4_DIN ASRC CLK (256 × fS) FDSP CLK (128 × fS ) Figure 97. Digital Audio Interface and ASRC Block Diagram Rev. 0 | Page 53 of 296 08975-015 fS_A_EXT BCLKA ADAU1373 The mode selection is performed by writing to the FORMATx bits (Bits[1:0]) of the digital audio interface settings registers (Register 0x44, Register 0x45, and Register 0x46). All modes are MSB first and operate with data of 16 bits to 32 bits. SERIAL DATA INPUT/OUTPUT FORMATS The flexible serial data input and output ports of the ADAU1373 can be set to accept or transmit data in 2-channel format. Data is processed in twos complement, MSB first format. The left channel data field always precedes the right channel data field in 2-channel streams. The digital audio input can support the following audio formats: I2S mode Left justified Right justified Digital signal processor (DSP) mode LRCLKx LEFT CHANNEL RIGHT CHANNEL BCLKx LSB MSB LSB MSB 08975-017 SDATAINx, SDATAOUTx 1/fS Figure 98. I2S Mode—16 Bits to 24 Bits per Channel MSB LSB MSB LSB 08975-018 SDATAINx, SDATAOUTx RIGHT CHANNEL LEFT CHANNEL LRCLKx BCLKx 1/fS Figure 99. Left-Justified Mode—16 Bits to 24 Bits per Channel RIGHT CHANNEL LEFT CHANNEL SDATAINx, SDATAOUTx MSB LSB MSB LSB 1/fS Figure 100. Right-Justified Mode—16 Bits to 24 Bits per Channel 1/fS LEFT CHANNEL RIGHT CHANNEL LRCLKx SDATAINx/ SDATAOUTx 1 2 3 N 1 2 3 08975-034 BCLKx N Figure 101. DSP/Pulse Code Modulation (PCM) Mode Audio Interface Submode 1 (SM1), Register 0x44 to Register 0x46, Bit LRPx = 0 1/fS LEFT CHANNEL LRCLKx RIGHT CHANNEL FALLING EDGE CAN OCCUR ANYWHERE IN THIS AREA BCLKx SDATAINx/ SDATOUTx 1 2 3 N 1 2 3 N Figure 102. DSP/PCM Mode Audio Interface Submode 2 (SM2), Register 0x44 to Register 0x46, Bit LRPx = 1 Rev. 0 | Page 54 of 296 08975-019 LRCLKx BCLKx 08975-035 • • • • The serial data clocks must be synchronous with the ADAU1373 master clock input. The LRCLKx (Ball D3, Ball E2, and Ball F1) and BCLKx (Ball D2, Ball E4, and Ball F2) pins are used to clock both the serial input and output ports. The ADAU1373 can be set as the master or the slave in a system. See Figure 98 to Figure 102 for the proper configurations for standard audio data formats. ADAU1373 ASYNCHRONOUS SAMPLE RATE CONVERTER The ADAU1373 includes three bidirectional ASRCs to convert the sample rate for the selected digital audio interface port. The ASRCs can be set in automatic ratio detect mode to calculate the required ratio between the input and internal sample rate. This mode writes the value in Register 0x4A and Register 0x4B for Digital Audio Interface A, Register 0x4C and Register 0x4D for Digital Audio Interface B, and Register 0x4E and Register 0x4F for Digital Audio Interface C. The automatic ratio detect can be disabled, and the fractional value can be written into the same registers for manual setting. The maximum sample rate is 48 kHz for the ASRC, as well as for the internal DSP. This sets the limitation on the ASRC such that the interface port sample rate must be equal to or less than the internal core sample rate. The output-to-input sample rate ratio number is split into the integer part and the fractional part. The integer part is three bits wide, and the fractional part is 12 bits wide. The total available range is 1:8 to 8:1. The ASRC is bidirectional and converts the sample rate at the port side to the DSP side and vice versa. The DSP side of the ASRC always works at the core sample rate and should be the highest sample rate of all the ports. Register 0x4A to Register 0x4F can be used to set the ASRC ratio manually for ASRCA, ASRCB, and ASRCC. The following section explains the manual setting of the sample rate conversion ratio. Manual Setting of Sample Rate Conversion Ratio Bits[6:4] in Register 0x4A contain the SRCAINT bits for the integer portion; and the SRCARFRE_HI bits (Bits[3:0]), along with the SRCAFRE_LOW bits (Bits[7:0] in Register 0x4B), form the total 12-bit fractional portion. Bits[6:4] in Register 0x4C contain the SRCBINT bits for the integer portion; and the SRCBRFRE_HI bits (Bits[3:0]), along with the SRCBRFRE_LOW bits (Bits[7:0] in Register 0x4D), form the total 12-bit fractional portion. Bits[6:4] in Register 0x4E contain the SRCCINT bits for the integer portion; and the SRCCRFRE_HI bits (Bits[3:0]), along with the SRCCRFRE_LOW bits (Bits[7:0] in Register 0x4F), form the total 12-bit fractional portion. The fractional part is 12 bits wide with an upper nibble (Bits[11:8]) and a lower byte (Bits[7:0]). The upper bits are set using Register 0x4A, Register 0x4C, and Register 0x4E, Bits[3:0] (SRCxRFRE_HI) and the lower byte is set using Register 0x4B, Register 0x4D, and Register 0x4F, Bits[7:0] (SRCxRFRE_LOW) for Digital Audio Interface A, Digital Audio Interface B, and Digital Audio Interface C, respectively. Example A If the target sample rate is 48 kHz and the source sample rate is 44.1 kHz, then 48/44.1 = 1.088435 Separate the integer portion, which is 1, and the fractional portion, which is 0.088435. For the integer value of the ratio in hexadecimal format, set SRCxINT, Bits[2:0] = 0x1 (hexadecimal). Next, to enter the fractional value, first convert the number to a 12-bit integer and then to hexadecimal format. 0.088435 × 4096 = 362.231 ≈ 362 = 0x16A (hex) The upper nibble is 0x1 (hexadecimal), whereas the lower byte is 0x6A (hexadecimal). That is, SRCxRFRE_HI, Bits[3:0] = 0x1, and SRCxRFRE_LOW, Bits[7:0] = 0x6A. Example B If the target sample rate is 44.1 kHz and the source sample rate is 8 kHz, then 44.1/8 = 5.5125 Separate the integer portion, which is 5, and the fractional portion, which is 0.5125. For the integer value of the ratio in hexadecimal format, set SRCxINT, Bits[2:0] = 0x5 (hexadecimal). Next, to enter the fractional value, first convert the number to a 12-bit integer and then to hexadecimal format. 0.5125 × 4096 = 2099.2 ≈ 131 = 0x83 (hex) The upper nibble is 0x0 (hexadecimal), whereas the lower byte is 0x83 (hexadecimal).That is, SRCxRFRE_HI, Bits[3:0] = 0x0, and SRCxRFRE_LOW, Bits[7:0] = 0x83. The ratio can be calculated using the following steps: 1. 2. 3. 4. Calculate the ratio. Split the ratio number into integer and fractional parts. Set M as the integer part of fS_DSP/fS_x_INT or fS_DSP/fS_x_EXT, and set N as the fractional part. Integer Part M can be set from 1 to 8 using Register 0x4A, Register 0x4C, and Register 0x4E, Bits[6:4] (SRCxINT), for ASRCA, ASRCB, and ASRCC, respectively. Round Fractional Part N, using the following equation: ROUND (N × 212) = ROUND (N × 4096) 5. Convert the number to hexadecimal format. Rev. 0 | Page 55 of 296 ADAU1373 as DAC1 and DAC2. The digital volume controls on each of the inputs, as well as the outputs, can be used to adjust the levels. The soft mode allows the volume to be updated for clickless operation. MIX/MUX The ADAU1373 provides very flexible mixing and multiplexing of the digital signals to and from the DSP and to and from the codec/Digital Audio Interface A/Digital Audio Interface B/ Digital Audio Interface C. The input mixing and routing matrix allows the digital data from Digital Audio Interface A, Digital Audio Interface B, and Digital Audio Interface C, as well as the ADC and digital microphone, to be selected or mixed to any of the DSP input channels (that is, DSP Channel 0 to DSP Channel 4). Similarly, the output mixing and routing matrix allows the data from DSP Channel 0 to DSP Channel 4 to be mixed and routed to Digital Audio Interface A, Digital Audio Interface B, and Digital Audio Interface C, as well For recording purposes, the data from the ADC or the digital microphone can be sent to Digital Audio Interface A, Digital Audio Interface B, and Digital Audio Interface C. Similarly, for playback, the data from the ports can be sent to the DACs and then to the analog outputs. The mixing block allows complete record and playback datapaths. DSPOUT_CH0 INTERFACE_A DSPOUT_CH1 INTERFACE_B DSPOUT_CH2 INTERFACE_C ADC The routing matrix also allows the data to be looped back from the internal ADC to the DACs or from Digital Audio Interface A to Digital Audio Interface B or Digital Audio Interface C. INTERFACE_A DSPOUT_CH3 DSPIN_CH0 DSPOUT_CH4 ADC_LRSWAP DMIC DMICLRSWAP DSPOUT_CH0 INTERFACE_A DSPOUT_CH1 INTERFACE_B DSPOUT_CH2 INTERFACE_C ADC INTERFACE_B DSPOUT_CH3 DSPIN_CH1 DSPOUT_CH4 ADC_LRSWAP DMIC DMICLRSWAP DSPOUT_CH0 INTERFACE_A DSPOUT_CH1 INTERFACE_B DSPOUT_CH2 INTERFACE_C ADC DSPIN_CH2 DSP INTERFACE_C DSPOUT_CH3 DSPOUT_CH4 ADC_LRSWAP DMIC DMICLRSWAP DSPOUT_CH0 INTERFACE_A DSPOUT_CH1 INTERFACE_B DSPOUT_CH2 INTERFACE_C ADC DSPIN_CH3 DAC1 DSPOUT_CH3 DSPOUT_CH4 ADC_LRSWAP DMIC DMICLRSWAP DSPOUT_CH0 INTERFACE_A DSPOUT_CH1 INTERFACE_B DSPOUT_CH2 INTERFACE_C ADC ADC_LRSWAP DSPIN_CH4 DAC2 DSPOUT_CH3 DSPOUT_CH4 08975-036 DMIC DMICLRSWAP Figure 103. Digital Mix/Mux Block Rev. 0 | Page 56 of 296 ADAU1373 DE-EMPHASIS PRE HPF INTERFACE B INPUT DE-EMPHASIS PRE HPF INTERFACE C INPUT DE-EMPHASIS PRE HPF ADC OUTPUT PRE HPF DIGITAL MIC OUTPUT PRE HPF ALC 1 2 FDSP_PRE_ MIX_MUX MDRC 7-BAND BIQUAD FDSP_DIN0 FDSP_DOUT0 INTERFACE A OUTPUT FDSP_DIN1 FDSP_DOUT1 INTERFACE B OUTPUT FDSP_DIN2 FDSP FDSP_DOUT2 INTERFACE C FDSP_POST_ OUTPUT MIX_MUX FDSP_DIN3 FDSP_DOUT3 DAC1 INPUT FDSP_DIN4 FDSP_DOUT4 DAC2 INPUT 3D BASS DRC 1 2 3 NOTE: EITHER MDRC OR DRC CAN BE USED AT A TIME POST HPF 08975-037 INTERFACE A INPUT Figure 104. Fixed Function DSP (FDSP) Input and Output Connections and Available Processing Blocks the last three LSB bits. Register 0xBD provides an individual control bit for each filter enable or disable. FIXED FUNCTION DSP (FDSP) Figure 104 shows the fixed function DSP input and output connections, as well as the available processing blocks. The FDSP works at a 128 × fS clock rate and has five input and output channels. The pre-HPF frequency transfer function is as follows: H ( z) = The five high-pass filters are available at the input channels to help remove the dc offset. In addition, the following blocks are provided to enhance the signal: • • • • • • ALC MDRC or three full-band DRCs Seven-band EQ 3D enhancement Bass enhancement High-pass filter 1+ a 1 − z −1 × 2 1 − a × z −1 where Parameter a is determined by the cutoff frequency, fC, and related to the sample rate, fS. Use the following equations to calculate Parameter a: WC = 2 × π × fC/fS a = 1 − sin wc cos wc For the pre-HPF, the coefficients are quantized to 10 bits, so that the decimal integer values of these coefficients are as follows: HIGH-PASS FILTERS (HPFs) aINT = round(a × 2048) The ADAU1373 provides five fully programmable HPFs in front of the data path and one configurable HPF following the FDSP blocks. The five fully programmable HPFs (called pre-HPFs) are used to remove the dc content or the low frequency components from the input signals. An additional HPF, located at the end of the FDSP chain and called the post-HPF, is designed to remove dc or low frequency components that may be introduced by the nonlinear processing in the FDSP blocks. All of these HPFs are first-order IIR with changeable 3 dB cutoff frequencies. Pre-HPFs All coefficients of the five pre-HPFs are in 11-bit format and fully programmable. Each coefficient takes up two register addresses, from Register 0xB3 to Register 0xBC. For each coefficient, the first register is the first eight MSB bits, and the second register is Pre-HPF Working Example If the required cutoff frequency for the first pre-HPF is 900 Hz and the sampling rate is 48 kHz, then wC = 2 × π × fC/fS = 0.1178097 a = 1− sin wc = 0.8886221 cos wc aINT = round(a × 2048) = 1820 aHEX = 71C Therefore, set Bits[7:0] in Register 0xB3, Register 0xB5, Register 0xB7, Register 0xB9, and Register 0xBB as the MSBs and Bits[2:0] in Register 0xB4, Register 0xB6, Register 0xB8, Register 0xBA, and Register 0xBC as the LSBs for the pre-HPFs. Rev. 0 | Page 57 of 296 ADAU1373 Post-HPFs MDRC The post-HPF cutoff frequency is selectable via Register 0x7D, Bits[7:3] as 3.7 Hz for dc removal or from 50 Hz up to 800 Hz, with a 50 Hz step for low frequency component filtering. This HPF block can be enabled or disabled for the left or right channel, controlled by Register 0x7D, Bits[1:0]. The HPF calculates the dc value of the signal, which is subtracted from the signal when enabled. When the HPF block is disabled, Bit 2 of Register 0x7D determines whether the calculated dc value is maintained and subtracted from the input signal or cleared to 0. The MDRC provides a multiband dynamic range control by splitting the signal into three bands, depending on the frequency: low, mid, and high. Each of the bands is processed separately, and individual controls are provided for each band DRC. The MDRC can be enabled or disabled by the MDRC_EN bit (Register 0xB2, Bit 0) (see the MDRC block diagram in Figure 106). Figure 105 shows the post-HPF frequency response plots for various cutoff frequency settings. The 3 dB cutoff frequency of the HPF can be set from 50 Hz to 800 Hz in 50 Hz steps, configured using the MDRC_HPF bits (Register 0xB0, Bits[5:2]). The 3-band MDRC is composed of a second-order high-pass IIR filter, a second-order low-pass IIR filter, the frequency splitter, and three individual DRCs for low, mid, and high bands. 0 The LPF cutoff frequency can be set to 4 kHz, 8 kHz, or 20 kHz via the MDRC_LPF bits (Register 0xB0, Bits[1:0]). –5 The HPF and LFP can be enabled or disabled by using the MDRC_LPFEN and MDRC_HPFEN bits in Register 0xB2. –15 The crossover frequencies between the low band and high band are defined in Register 0xB1 by the MDRC_CROSS_LOW bits (Bits[3:0]) and the MDRC_CROSS_HIGH bits (Bits[7:4]). The crossover frequency between low band and mid band can be varied from 100 Hz to 1600 Hz in steps of 100 Hz. The crossover frequency for the mid-to-high bands can be varied from 1 kHz to 16 kHz in steps of 1 kHz. –20 –25 –30 –40 20 100 1k 08975-038 –35 5k FREQUENCY (Hz) All of the previous frequency values are based on a 48 kHz sampling rate. If the input signals are of a different sampling rate, the values should be scaled accordingly. Figure 105. Post-HPF Frequency Response DYNAMIC RANGE CONTROL (DRC) Using the DRC The DRC is used to control the dynamic range of the signal. It provides the capability to match the dynamic range of the incoming signal with the dynamic range of the signal fed to the next block or device without losing the signal-to-noise ratio. The ADAU1373 provides three DRCs that can be used as full band. The DRCs are shared between full-band DRC or MDRC. When the full-band DRCs are in use, the MDRC is not available. For fullband DRC, the crossover filters can be disabled in Register 0xB2 via the MDRC_HPFEN bit (Bit 1) and the MDRC_LPFEN bit (Bit 2). Each of the three DRCs has its own registers: Register 0x80 to Register 0x8F for DRC1, Register 0x90 to Register 0x9F for DRC2, and Register 0xA0 to Register 0xAF for DRC3, plus enable or disable bits, which are set by the DRCEN bits (Bits[1:0]) in Register 0x8D, Register 0x9D, and Register 0xAD. The ADAU1373 provides three full-band DRCs or one multiband DRC (MDRC). However, at any given time, either the three fullband DRCs or the MDRC can be used. Register 0x80 through Register 0xB2 are used for setting the MDRC or full-band DRCs. The MDRC and the seven-band EQ share the same register addresses (Register 0x80 through Register 0xBD). Therefore, for the MDRC, ensure that the EQ coefficient writing enable bit (EQ_WR_EN, Bit 0 in Register 0xBE) = 0; whereas for the seven-band EQ, the EQ_WR_EN bit = 1. DRC LOW BAND FREQUENCY SPLITTER HPF LPF 50Hz TO 800Hz (50Hz STEP) 4kHz/ 8kHz/20kHz DRC MID BAND |H(f)| f DRC HIGH BAND Figure 106. MDRC Block Diagram Rev. 0 | Page 58 of 296 08975-039 MAGNITUDE (dBFS) –10 ADAU1373 • • • The DRCNGSRC bit (Bit 5) can be used for selecting the noise gate detector. The DRCCESRC bit (Bit 4) can be used for selecting the compressor/expander detector. The DRCLMSRC bit (Bit 3) can be used for selecting the limiter detector. OUTPUT LIMITER POINT1 COMPRESSOR EXPANDER DRCTHY3 DRCTHY4 The DRC can be set to function as limiter, compressor, expander, or noise gate. See Figure 107 for the input/output plot showing the various modes of operation of the DRC. The DRC allows flexibility in setting up the thresholds, as well as attack and release time controls. The DRC allows independent adjustment of the thresholds by providing control of the x-axis and y-axis using Register 0x82 to Register 0x89 for DRC1, Register 0x92 to Register 0x99 for DRC2, and Register 0xA2 to Register 0xA9 for DRC3. Bit DRCTHX1 to Bit DRCTHX4 in these registers can be used to set the input level threshold point on the x-axis, and Bit DRCTHY1 to Bit DRCTHY4 can be used to set the output level point on the y-axis. The available range is −96 dB to 0 dB for each threshold. POINT2 DRCTHY1 DRCTHY2 POINT3 POINT4 NOISE GATE DRCTHX4 DRCTHX3 DRCTHX2 DRCTHX1 INPUT 08975-040 The DRCs consist of both peak and rms signal detectors. Either the peak or the rms detector can be assigned for noise gate, compressor/expander, and limiter. Bits[5:3] in Register 0x8D, Register 0x9D, and Register 0xAD are provided for selecting the detectors, as follows: Figure 107. DRC Output vs. Input Plot The DRC gain can be set using the DRCG bits (Bits[5:2]) in Register 0x8C, Register 0x9C, and Register 0xAC. The range available is −24 dB to +21 dB. See Table 19 for a listing of the DRC detector selection registers and bits and their functions. Table 20 lists the registers and bits that control the dynamic behavior of the DRC. Table 19. DRC Setting Bits and Functions Register Address 0x8C, 0x9C, 0xAC 0x8D, 0x9D, 0xAD 0x8D, 0x9D, 0xAD 0x8D, 0x9D, 0xAD 0x8D, 0x9D, 0xAD 0x8D, 0x9D, 0xAD 0x8D, 0x9D, 0xAD 0x8D, 0x9D, 0xAD Bits [5:2] 7 6 5 4 3 2 [1:0] Bit Name DRCG DRCNGTGT DRCNGHDEN DRCNGSRC DRCCESRC DRCLMSRC DRCNGEN DRCEN Description Sets the DRC gain; available range is from −24 dB to +21 dB. Sets the DRC noise gate target. Enables or disables the DRC noise gate recovery hold. Selects the DRC noise gate level detector; selects either rms or peak detector. Selects the DRC compressor/expander level detector; selects either rms or peak detector. Selects the DRC limiter level detector; selects either rms or peak detector. Noise gate enable control; provides independent noise gate control. DRC enable control; enables or disables the DRC. The input source for the DRC can be selected as left channel, right channel, or both. Table 20. DRC Dynamic Behavior Control Register Address 0x80, 0x90, 0xA0 0x81, 0x91, 0xA1 0x81, 0x91, 0xA1 0x8A, 0x9A, 0xAA 0x8A, 0x9A, 0xAA 0x8B, 0x9B, 0xAB Bits [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] Bit Name DRCLELTAV DRCLELATT DRCLELDEC DRCGSATT DRCGSDEC DRCHTNOR 0x8B, 0x9B, 0xAB [3:0] DRCHTNG Description Sets rms signal detector averaging time. Available range is from 750 μs to 24.576 sec. Sets DRC attack time. Available range is 46.875 μs to 1.536 sec. Sets DRC decay (release) time. Available range is 0.75 ms to 24.576 sec. Sets DRC gain smooth attack time. Available range is 46.875 μs to 1.536 sec. Sets DRC gain smooth decay time. Available range is 0.75 ms to 24.576 sec. Sets DRC normal operation hold time. Available range is from 0 ms up to 1.37 sec; value increments by 2× the previous value, beginning with 0.67 ms. Sets DRC noise gate hold time. Available range is from 0 ms up to 1.37 sec; value increments by 2× the previous value, beginning with 0.67 ms. Rev. 0 | Page 59 of 296 ADAU1373 1.0 LIMITER THRESHOLD (DRCTHX1) 0.5 1.0 x10–4 NOISE GATE THRESHOLD (DRCTHX4) 0.5 0 0 –0.5 –0.5 –1.0 0.2 –1.0 INPUT LIMITER TARGET LEVEL (DRCTHY1) 0 1000 2000 3000 INPUT 4000 5000 6000 1000 2000 3000 OUTPUT 4000 5000 6000 x10–4 2 0.1 1 0 0 –0.1 –1 RELEASE (DECAY) TIME (NO HOLD TIME) (DRCTHY1) –14 OUTPUT –2 ATTACK TIME (DRCLELATT) –16 0 –20 –10 1000 2000 3000 4000 5000 DRC GAIN (dB) 6000 7000 8000 –20 08975-041 0 NOISE GATE RECOVERY (DECAY) TIME ATTACK TIME 10 –18 –22 0 HOLD TIME FOR NOISE GATE –30 0 1000 2000 Figure 108. Limiter Dynamic Behavior—Working Example 3000 4000 DRC GAIN (dB) 5000 6000 08975-043 –0.2 Figure 110. Noise Gate Dynamic—Working Example 1.0 Working Example 0.5 0 If the required LPF cutoff frequency is 20 kHz, the HPF cutoff frequency is 350 Hz, low band crossover frequency is 1 kHz, and high band crossover frequency is 8 kHz, as shown in Figure 111. –0.5 –1.0 INPUT 0.2 0.1 H(f) 0 –0.1 –0.2 OUTPUT 0 1000 2000 3000 4000 5000 DRC GAIN (dB) 6000 7000 8000 350 Figure 109. Limiter Dynamic—Working Example Showing Hold Time MID BAND 1000 HIGH BAND 8000 20000 fIN (Hz) 08975-044 LOW BAND HOLD TIME DURING RECOVERY (DRCHTNOR) 08975-042 –14 –15 –16 –17 –18 –19 –20 –21 Figure 111. MDRC Example The DRC can generate an interrupt request when enabled. See Table 21 for a listing of the interrupt request register and bit controls. • • • To configure MDRC HPF and LPF, set Register 0xB0 to 0x1A. To configure MDRC crossover frequencies, set Register 0xB1 to 0x79. To enable MDRC HPF and LPF, set Register 0xB2 to 0x07. Table 21. Interrupt Request Register and Bit Controls Register Address 0x8F, 0x9F, 0xAF Bits 1 Bit Name DRCIRQ_MODE 0x8F, 0x9F, 0xAF 0x8E, 0x9E, 0xAE 0 [6:2] DRCIRQ_EN SIG_DET_RMS 0x8E, 0x9E, 0xAE [1:0] SIG_DET_PK Function DRC interrupt mode. 0: selects the input signal rms value as the interrupt source; 1: selects the ratio between the peak and rms signal of the input signal. DRC interrupt enable. RMS detector level. Defines the rms value above which the IRQ circuits send out the interruption signal when the DRCIRQ_MODE bit = 0. Available range: −76.5 dB to −30 dB. Peak to rms detector ratio. Defines the peak to rms value above which the IRQ circuits send out the interruption signal when the DRCIRQ_MODE bit = 1. Available range: 12 dB to 30 dB. Rev. 0 | Page 60 of 296 ADAU1373 BIQUAD2 BIQUAD3 BIQUAD4 BIQUAD5 SEVEN-BAND EQUALIZER FIRSTORDER IIR 1 FIRSTORDER IIR 1 08975-045 BIQUAD1 Figure 112. Seven-Band Equalizer Block Diagram PROGRAMMABLE SEVEN-BAND EQUALIZER The programmable seven-band equalizer is composed of five biquad filters (Band 1 to Band 5) and two first-order IIR filters (Band 6 and Band 7). See Figure 112 for a system block diagram. The EQ shares Register 0x80 through Register 0xBD with the MDRC. All the filter coefficients are programmable via the corresponding registers. The filter bank can also be configured as some other filters, including de-emphasis and notch filter, when all five midfrequency bands are not needed. Table 22. Register 0x80 to Register 0xBD EQ Coefficients Register Address 0x80 0x81 0x82 0x83 0x84 0x85 ... 0xBC 0xBD Bit Name EQ1_COEF0_HI[15:8] EQ1_COEF0_LO[7:0] EQ1_COEF1_HI[15:8] EQ1_COEF1_LO[7:0] EQ1_COEF2_HI[15:8] EQ1_COEF2_LO[7:0] ... EQ7_COEF2_HI[15:8] EQ7_COEF2_LO[7:0] Descripton EQ Band 1, Coefficient 0 MSB EQ Band 1, Coefficient 0 LSB EQ Band 1, Coefficient 1 MSB EQ Band 1, Coefficient 1 LSB EQ Band 1, Coefficient 2 MSB EQ Band 1, Coefficient 2 LSB ... EQ Band 7, Coefficient 2 MSB EQ Band 7, Coefficient 2 LSB To operate as a seven-band equalizer, the two first-order IIR filters are usually configured as one low-pass shelving filter and one high-pass shelving filter, and the biquad filters are configured as peak filters. The first-order IIR filter cutoff frequency and gain are adjustable using the filter coefficient registers. In addition, the five biquad filters have adjustable gain, the center frequency for the peak filters, or cutoff frequency for shelving filters. For a frequency band that is 3 V) Enable (VBAT ≤ 3 V) Microphone Bias 1 Current Limit Enable/Disable Control. Disable (default) Enable Microphone Bias 1 Overcurrent Detection Enable/disable Control. Disable (default) Enable Microphone Bias 1 Current Detection Enable/Disable Control. Disable (default) Enable Microphone Bias 1 Overcurrent Threshold Value. 330 μA (default) 700 μA 1000 μA 1400 μA Microphone Bias 1 Current Detection Threshold Value. 150 μA (default) 330 μA 510 μA 700 μA Rev. 0 | Page 126 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 MICBIAS_CTRL2 REGISTER Address: 0x23, Reset: 0x00, Name: MICBIAS_CTRL2 Microphone Bias 2 Control Table 69. Bit Descriptions for MICBIAS_CTRL2 Bits 7 6 Bit Name RESERVED MICB2LIM Settings 0 1 5 MICB2OCEN 0 1 4 MICB2CURDEN 0 1 [3:2] MICB2SHT 00 01 10 11 [1:0] MICB2CURD 00 01 10 11 Description Reserved. Microphone Bias 2 Current Limit Enable/Disable Control. Disable (default) Enable Microphone Bias 2 Overcurrent Detect Enable/Disable Control. Disable (default) Enable Microphone Bias 2 Current Detect Enable/Disable Control. Disable (default) Enable Microphone Bias 2 Overcurrent Detect Threshold Select. 330 μA (default) 700 μA 1000 μA 1400 μA Microphone Bias 2 Current Detect Threshold Select. 150 μA (default) 330 μA 510 μA 700 μA Rev. 0 | Page 127 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 OUTPUT_CONTROL (LINE) REGISTER Address: 0x24, Reset: 0x00, Name: OUTPUT_CONTROL Line Output Mode Control Table 70. Bit Descriptions for OUTPUT_CONTROL Bits [7:6] Bit Name RNSM Settings 00 01 10 11 [5:4] LNSM 00 01 10 11 3 LDIFF 0 1 2 LNFBEN 0 1 1 ZCTO 0 1 0 VMID 0 1 Description Line Output 2 Mono Stereo Control. Lineout 2 Mute (Default) Lineout 2 Mono L + R in Left Output Lineout 2 Mono L + R in Right Output Lineout 2 Stereo Line Output 1 Mono Stereo Control. Lineout 1 Mute (Default) Lineout 1 Mono L + R in Left Output Lineout 1 Mono L + R in Right Output Lineout 1 Stereo Line Output Mode Control. Lineout Single-Ended (Unbalanced) Lineout Differential Line Output Ground Sense Control. Disable (Default) Enable Volume Change Timeout Control. 32 ms 64 ms Reference Voltage Mode. AVDD/2 0.8 V Fix Voltage Mode Rev. 0 | Page 128 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 PWDN_CTRL1 REGISTER Address: 0x25, Reset: 0x00, Name: PWDN_CTRL1 Power-Down Block Control 1 Table 71. Bit Descriptions for PWDN_CTRL1 Bits 7 Bit Name LADCPDB Settings 0 1 6 RADCPDB 0 1 5 MICB2PDB 0 1 4 MICB1PDB 0 1 3 AIN4PDB 0 1 2 AIN3PDB 0 1 1 AIN2PDB 0 1 0 AIN1PDB 0 1 Description Right Channel ADC Power-Down Control. Power down (default) Power up Left Channel ADC Power-Down Control. Power down (default) Power up Microphone Bias 2 Power-Down Control. Power down (default) Power up Microphone Bias 1 Power-Down Control. Power down (default) Power up Analog Input 4 Power-Down Control. Power down (default) Power up Analog Input 3 Power-Down Control. Power down (default) Power up Analog Input 2 Power-Down Control. Power down (default) Power up Analog Input 1 Power-Down Control. Power down (default) Power up Rev. 0 | Page 129 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 PWDN_CTRL2 REGISTER Address: 0x26, Reset: 0x00, Name: PWDN_CTRL2 Power-Down Block Control 2 Table 72. Bit Descriptions for PWDN_CTRL2 Bits 7 Bit Name LDAC2PDB Settings 0 1 6 RADC2PDB 0 1 5 LDAC1PDB 0 1 4 RDAC1PDB 0 1 3 LLN2PDB 0 1 2 RLN2PDB 0 1 1 LLN1PDB 0 1 0 RLN1PDB 0 1 Description Left Channel DAC 2 Power-Down Control. Power down (default) Power up Right Channel DAC 2 Power-Down Control. Power down (default) Power up Left Channel DAC1 Power-Down Control. Power down (default) Power up Right Channel DAC1 Power-Down Control. Power down (default) Power up Lineout2 Left Power-Down Control. Power down (default) Power up Lineout2 Right Power-Down Control. Power down (default) Power up Lineout1 Left Power-Down Control. Power down (default) Power up Lineout1 Right Power-Down Control. Power down (default) Power up Rev. 0 | Page 130 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 PWDN_CTRL3 REGISTER Address: 0x27, Reset: 0x00, Name: PWDN_CTRL3 Power-Down Block Control 3 Table 73. Bit Descriptions for PWDN_CTRL3 Bits 7 6 Bit Name ZDPDB VBATPWDB Settings 0 1 5 4 RESERVED EPPDB 0 1 3 LCDPDB 0 1 2 RCDPDB 0 1 1 HPPDB 0 1 0 PWDB 0 1 Description Zero Cross Detection Power-Down Control. VBAT Power-Down Control. Power down (default) Power up Reserved. Earpiece Amplifier Power Control. Power down (default) Power up Speaker Amplifier Right Power Control. Power down (default) Power up Speaker Amplifier Left Power Control. Power down (default) Power up Headphone Power Control. Power down (default) Power up Low Voltage Power-Down Control. Power down (default) Power up Rev. 0 | Page 131 of 296 Reset 0x0 0x0 Access RW RW 0x0 0x0 RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DPLLA_CTRL REGISTER Address: 0x28, Reset: 0x00, Name: DPLLA_CTRL DPLLA Control Table 74. Bit Descriptions for DPLLA_CTRL Bits [7:4] Bit Name DPLLA_REF_SEL Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1110 1111 1101 1100 Description DPLLA Source Select. DPLLA source selection can be set to one of the following: Digital Audio Interface A/B/C bit clock/frame clock or GPIO1/2/3/4 or Master Clock Input 1/2. MCLK1 DPLLA reference clock input: Digital Audio Interface A bit clock DPLLA reference clock input: Digital Audio Interface B bit clock DPLLA reference clock input: Digital Audio Interface C bit clock DPLLA reference clock input: Digital Audio Interface A frame clock DPLLA reference clock input: Digital Audio Interface B frame clock DPLLA reference clock input: Digital Audio Interface C frame clock DPLLA reference clock input: GPIO1 DPLLA reference clock input: GPIO2 DPLLA reference clock input: GPIO3 DPLLA reference clock input: GPIO4 MCLK2 Reserved Reserved Reserved Reserved Rev. 0 | Page 132 of 296 Reset 0x0 Access RW ADAU1373 Bits [3:0] Bit Name DPLLA_NDIV Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1100 1101 1110 1111 1011 Description DPLLA Clock Divider Setting. DPLLA clock divider settings from 1 to 1024 in 16 steps. DPLLA output clock frequency: DPLLA input DPLLA output clock frequency: DPLLA input clock frequency × 1024 DPLLA output clock frequency: DPLLA input clock frequency × 512 DPLLA output clock frequency: DPLLA input clock frequency × 256 DPLLA output clock frequency: DPLLA input clock frequency × 128 DPLLA output clock frequency: DPLLA input clock frequency × 64 DPLLA output clock frequency: DPLLA input clock frequency × 32 DPLLA output clock frequency: DPLLA input clock frequency × 16 DPLLA output clock frequency: DPLLA input clock frequency × 8 DPLLA output clock frequency: DPLLA input clock frequency × 4 DPLLA output clock frequency: DPLLA input clock frequency × 2 Reserved Reserved Reserved Reserved Reserved Reset 0x0 Access RW Reset 0x00 Access RW Reset 0x00 Access RW PLLA_CTRL1 REGISTER Address: 0x29, Reset: 0x00, Name: PLLA_CTRL1 PLLA Fractional Mode Denominator M High Byte Table 75. Bit Descriptions for PLLA_CTRL1 Bits [7:0] Bit Name PLLA_M_HI Settings Description Denominator (M) of the Fractional PLLA Upper Byte. PLLA Fractional Mode Denominator M divider setting upper byte. PLLA_CTRL2 REGISTER Address: 0x2A, Reset: 0x00, Name: PLLA_CTRL2 PLLA Fractional Mode Denominator M Lower Byte Table 76. Bit Descriptions for PLLA_CTRL2 Bits [7:0] Bit Name PLLA_M_LO Settings Description Denominator (M) of the Fractional PLLA Lower Byte. PLLA Fractional Mode Denominator M divider setting lower byte. Rev. 0 | Page 133 of 296 ADAU1373 PLLA_CTRL3 REGISTER Address: 0x2B, Reset: 0x00, Name: PLLA_CTRL3 PLLA Fractional Mode N Table 77. Bit Descriptions for PLLA_CTRL3 Bits [7:0] Bit Name PLLA_N_HI Settings Description Numerator (N) of the Fractional PLLA Upper Byte. PLLA Fractional Mode Numerator N upper byte. Reset 0x00 Access RW Reset 0x00 Access RW PLLA_CTRL4 REGISTER Address: 0x2C, Reset: 0x00, Name: PLLA_CTRL4 Numerator (N) of the Fractional PLLA Lower Byte Table 78. Bit Descriptions for PLLA_CTRL4 Bits [7:0] Bit Name PLLA_N_LO Settings Description Numerator (N) of the Fractional PLLA Lower Byte. PLLA Fractional Mode Numerator N lower byte. Rev. 0 | Page 134 of 296 ADAU1373 PLLA_CTRL5 REGISTER Address: 0x2D, Reset: 0x00, Name: PLLA_CTRL5 PLLA Type, X and R Value Setting Table 79. Bit Descriptions for PLLA_CTRL5 Bits 7 [6:3] Bit Name RESERVED PLLA_R Settings 0010 0011 0100 0101 0110 0111 1000 [2:1] PLLA_X 00 01 10 11 0 PLLA_TYPE 0 1 Description Reserved. Integer Part of PLLA. Integer (R) of PLLA. R=2 R=3 R=4 R=5 R=6 R=7 R=8 PLLA Input Clock Divider. PLLA input clock divider (X). X=1 X=2 X=3 X=4 PLLA Operation Mode. PLLA mode (fractional or integer). Integer Fractional Rev. 0 | Page 135 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW ADAU1373 PLLA_CTRL6 REGISTER Address: 0x2E, Reset: 0x02, Name: PLLA_CTRL6 PLLA Control/Status Table 80. Bit Descriptions for PLLA_CTRL6 Bits [7:4] 3 Bit Name RESERVED DPLLA_LOCKED Settings 1 0 2 PLLA_LOCKED 1 0 1 DPLLA_BYPASS 0 1 0 PLLA_EN 0 1 Description Reserved. DPLLA Lock Indicator. DPLLA lock status indicator. Digital PLLA locked Digital PLLA unlocked PLLA Lock Indicator. PLLA lock status indicator. Analog PLLA locked Analog PLLA unlocked DPLLA Bypass. DPLLA bypass select. DPLL in PLLA not bypassed DPLL in PLLA bypassed PLLA Enable Setting. PLLA enable/disable control. PLLA disable PLLA enable Rev. 0 | Page 136 of 296 Reset 0x0 0x0 Access RW R 0x0 R 0x1 RW 0x0 RW ADAU1373 DPLLB_CTRL REGISTER Address: 0x2F, Reset: 0x00, Name: DPLLB_CTRL DPLLB Control Table 81. Bit Descriptions for DPLLB_CTRL Bits [7:4] Bit Name DPLLB_REF_SEL Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DPLLB Source Select. DPLLB clock divider settings from 1 to 1024 in 16 steps. MCLK1 Audio Interface A bit clock Audio Interface B bit clock Audio Interface C bit clock Audio Interface A Frame Clock Audio Interface B Frame Clock Audio Interface C Frame Clock GPIO1 GPIO2 GPIO3 GPIO4 MCLK2 Reserved Reserved Reserved Reserved Rev. 0 | Page 137 of 296 Reset 0x0 Access RW ADAU1373 Bits [3:0] Bit Name DPLLB_NDIV Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DPLLB Clock Divider Setting. DPLLB source selection can be set to one of the following: Digital Audio Interface A/B/C bit clock/frame clock or GPIO1/2/3/4 or Master Clock Input 1/2. DPLLB output clock frequency: DPLLB input DPLLB output clock frequency: DPLLB input clock frequency × 1024 DPLLB output clock frequency: DPLLB input clock frequency × 512 DPLLB output clock frequency: DPLLB input clock frequency × 256 DPLLB output clock frequency: DPLLB input clock frequency × 128 DPLLB output clock frequency: DPLLB input clock frequency × 64 DPLLB output clock frequency: DPLLB input clock frequency × 32 DPLLB output clock frequency: DPLLB input clock frequency × 16 DPLLB output clock frequency: DPLLB input clock frequency × 8 DPLLB output clock frequency: DPLLB input clock frequency × 4 DPLLB output clock frequency: DPLLB input clock frequency × 2 Reserved Reserved Reserved Reserved Reserved Rev. 0 | Page 138 of 296 Reset 0x0 Access RW ADAU1373 PLLB_CTRL1 REGISTER Address: 0x30, Reset: 0x00, Name: PLLB_CTRL1 PLLB Fractional Mode Denominator M High Byte Table 82. Bit Descriptions for PLLB_CTRL1 Bits [7:0] Bit Name PLLB_M_HI Settings Description Denominator of the Fractional PLLB MSB. PLLB Fractional Mode Denominator M upper byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW PLLB CTRL2 REGISTER Address: 0x31, Reset: 0x00, Name: PLLB_CTRL2 PLLB Fractional Mode Denominator M Lower Byte Table 83. Bit Descriptions for PLLB_CTRL2 Bits [7:0] Bit Name PLLB_M_LO Settings Description Denominator of the Fractional PLLB LSB. PLLB Fractional Mode Denominator M lower byte. PLLB_CTRL3 REGISTER Address: 0x32, Reset: 0x00, Name: PLLB_CTRL3 PLLB Fractional Mode N Table 84. Bit Descriptions for PLLB_CTRL3 Bits [7:0] Bit Name PLLB_N_HI Settings Description Numerator of the fractional PLLB. PLLB Fractional Mode Numerator N upper byte. Rev. 0 | Page 139 of 296 ADAU1373 PLLB_CTRL4 REGISTER Address: 0x33, Reset: 0x00, Name: PLLB_CTRL4 Numerator (N) of the Fractional PLLB Lower Byte Table 85. Bit Descriptions for PLLB_CTRL4 Bits [7:0] Bit Name PLLB_N_LO Settings Description Numerator of the Fractional PLLB LSB. PLLB Fractional Mode Numerator N lower byte. Reset 0x00 Access RW Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW PLLB_CTRL5 REGISTER Address: 0x34, Reset: 0x00, Name: PLLB_CTRL5 PLLB Type, X and R Value Setting Table 86. Bit Descriptions for PLLB_CTRL5 Bits 7 [6:3] Bit Name RESERVED PLLB_R Settings Description 0010 0011 0100 0101 0110 0111 1000 [2:1] PLLB_X 00 01 10 11 0 PLLB_TYPE 0 1 Integer Part of PLLB. Integer (R) of PLLB. R=2 R=3 R=4 R=5 R=6 R=7 R=8 PLLB Input Clock Divider. PLLB input clock divider (X). X=1 X=2 X=3 X=4 PLLB Operation Mode. PLLB mode (fractional or integer). Integer Fractional Rev. 0 | Page 140 of 296 ADAU1373 PLLB_CTRL6 REGISTER Address: 0x35, Reset: 0x02, Name: PLLB_CTRL6 PLLB Control/Status Table 87. Bit Descriptions for PLLB_CTRL6 Bits [7:4] 3 Bit Name RESERVED DPLLB_LOCKED Settings 1 0 2 PLLB_LOCKED 1 0 1 DPLLB_BYPASS 0 1 0 PLLB_EN 0 1 Description Reserved. DPLLB Lock Indicator. DPLLB lock status indicator. Digital PLL in PLLB locked Digital PLL in PLLB unlocked PLLB Lock Indicator. PLLB lock status indicator. Analog PLL in PLLB locked Analog PLL in PLLB unlocked DPLLB Bypass. DPLLB bypass select. DPLL in PLLB not bypassed DPLL in PLLB bypassed PLLB Enable Setting. PLLB enable/disable control. PLLB disable PLLB enable Rev. 0 | Page 141 of 296 Reset 0x0 0x0 Access RW R 0x0 R 0x1 RW 0x0 RW ADAU1373 HEADDECT REGISTER Address: 0x36, Reset: 0x00, Name: HEADDECT Headphone Jack Detect Function Control. Every write to these bits toggles the HP_CFG_RAW_STATE bit (Bit 2) in Register 0xE6. Table 88. Bit Descriptions for HEADDECT Bits [7:2] [1:0] Bit Name RESERVED HEADSET Settings 00 10 11 01 Description Reserved. Headphone Detect. Headphone jack detect function control. HP = no change, SPK = no change (JACKDET pin = 0/1) HP = no change, SPK = power down (JACKDET pin = 0) or HP = power down, SPK = no change (JACKDET pin = 1) HP = no change, SPK = no change (JACKDET pin = 0) or HP = power down, SPK = power down (JACKDET pin = 1) HP = no change, SPK = no change (JACKDET pin = 0/1) Rev. 0 | Page 142 of 296 Reset 0x0 0x0 Access RW RW ADAU1373 ADC_DAC_STATUS REGISTER Address: 0x37, Reset: 0x00, Name: ADC_DAC_STATUS ADC/DAC Status Table 89. Bit Descriptions for ADC_DAC_STATUS Bits 7 6 Bit Name RESERVED NOCLKDAC2 Settings 0 1 5 NOCLKDAC1 0 1 [4:1] 0 RESERVED NOCLKADC 0 1 Description Reserved. Clock Status DAC2. Normal DAC2 clock loss Clock Status DAC1. Normal DAC1 clock loss Reserved. Clock Status ADC. Normal ADC clock loss Rev. 0 | Page 143 of 296 Reset 0x0 0x0 Access R R 0x0 R 0x0 0x0 R R ADAU1373 MIC_JACK_STATUS REGISTER Address: 0x38, Reset: 0x00, Name: MIC_JACK_STATUS Microphone/Jack Status Table 90. Bit Descriptions for MIC_JACK_STATUS Bits [7:5] 4 3 2 1 0 Bit Name RESERVED JACKDECT Settings Description Reserved. 0 1 No jack insertion detected Jack insertion detected 0 1 Microphone Bias 2 current normal Microphone Bias 2 overcurrent detected 0 1 Microphone Bias 2 current not detected Microphone Bias 2 current detected 0 1 Microphone Bias 1 current normal Microphone Bias 1 overcurrent detected MICB2OC MICB2THS MICB1OC MICB1THS 0 1 Microphone Bias 1 current not detected Microphone Bias 1 current detected Rev. 0 | Page 144 of 296 Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 R ADAU1373 CHIP_FAULT_STATUS REGISTER Address: 0x39, Reset: 0x00, Name: CHIP_FAULT_STATUS Chip Status Table 91. Bit Descriptions for CHIP_FAULT_STATUS Bits [7:5] 4 Bit Name RESERVED OCEP Settings 0 1 3 OCCDR 0 1 2 OCCDL 0 1 1 OCHP 0 1 0 OT 0 1 Description Reserved. Overcurrent for Earpiece. Earpiece amplifier overcurrent indicator. No overcurrent Overcurrent Overcurrent for Left Channel Class-D Speaker. Speaker amplifier left channel overcurrent indicator. No overcurrent Overcurrent Overcurrent for Right Channel Class-D Speaker. Speaker amplifier right channel overcurrent indicator. No overcurrent Overcurrent Overcurrent for Headphone. Headphone amplifier overcurrent indicator. No overcurrent Overcurrent Die Overtemperature Signal. Junction overtemperature indicator. Die temperature < 150°C Die temperature > 150°C Rev. 0 | Page 145 of 296 Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 R ADAU1373 ADC_SETTING REGISTER Address: 0x3C, Reset: 0x00, Name: ADC_SETTING Table 92. Bit Descriptions for ADC_SETTING Bits [7:3] 2 1 0 Bit Name RESERVED ADC_RESET_FORCE Settings Description 0 1 ADC reset force disable (default) ADC reset force enable 0 1 No reset (default) Reset 0 1 Peak detection disable (default) Peak detection enable ADC_RESET PDETECT Rev. 0 | Page 146 of 296 Reset 0x00 0x0 Access RW RW 0x0 RW 0x0 RW ADAU1373 CLK1_SOURCE_DIV REGISTER Address: 0x40, Reset: 0x00, Name: CLK1_SOURCE_DIV Clock 1 Divide and Core Clock Enable Control Table 93. Bit Descriptions for CLK1_SOURCE_DIV Bits 7 Bit Name COREN Settings 0 1 6 CLK1S_SEL 0 1 [5:3] CLK1SDIV 000 001 010 011 100 101 110 111 [2:0] MCLK1DIV 000 001 010 011 100 101 110 111 Description Core Clock Enable. Core clock enable or disable control. Core clock disable (default) Core clock enable PLLA Bypass Signal. Clock source selection. Clock source can be set to either PLLA output or external input. Use PLLA clock as Source Clock 1 (default) Use external clock as Source Clock 1 Source Clock 1 Divider. Source Clock 1 divider settings, 0 through 7 in eight steps. Source Clock Divider K = 0 Source Clock Divider K = 1 Source Clock Divider K = 2 Source Clock Divider K = 3 Source Clock Divider K = 4 Source Clock Divider K = 5 Source Clock Divider K = 6 Source Clock Divider K = 7 Master Clock 1 Divider. Master Clock 1 divider settings, 0 through 7 in eight steps. Divider J = 0 Divider J = 1 Divider J = 2 Divider J = 3 Divider J = 4 Divider J = 5 Divider J = 6 Divider J = 7 Rev. 0 | Page 147 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 CLK1_OUTPUT_DIV REGISTER Address: 0x41, Reset: 0x00, Name: CLK1_OUTPUT_DIV Master Clock 1 Output Divider Control for PLLA Table 94. Bit Descriptions for CLK1_OUTPUT_DIV Bits [7:6] 5 Bit Name RESERVED CLK1OEN Settings 0 1 [4:0] CLK1ODIV 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 Description Reserved. CLK1 Output Enable. Output clock enable control. CLK1 output disable (default) CLK1 output enable Output Clock 1 Divider. Output clock divider, settings 0 through 31. Output Clock Divider P = 0 Output Clock Divider P = 1 Output Clock Divider P = 2 Output Clock Divider P = 3 Output Clock Divider P = 4 Output Clock Divider P = 5 Output Clock Divider P = 6 Output Clock Divider P = 7 Output Clock Divider P = 8 Output Clock Divider P = 9 Output Clock Divider P = 10 Rev. 0 | Page 148 of 296 Reset 0x0 0x0 Access RW RW 0x00 RW ADAU1373 Bits [4:0] Bit Name CLK1ODIV Settings 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Description Output Clock Divider P = 11 Output Clock Divider P = 12 Output Clock Divider P = 13 Output Clock Divider P = 14 Output Clock Divider P = 15 Output Clock Divider P = 16 Output Clock Divider P = 17 Output Clock Divider P = 18 Output Clock Divider P = 19 Output Clock Divider P = 20 Output Clock Divider P = 21 Output Clock Divider P = 22 Output Clock Divider P = 23 Output Clock Divider P = 24 Output Clock Divider P = 25 Output Clock Divider P = 26 Output Clock Divider P = 27 Output Clock Divider P = 28 Output Clock Divider P = 29 Output Clock Divider P = 30 Output Clock Divider P = 31 Rev. 0 | Page 149 of 296 Reset Access ADAU1373 CLK2_SOURCE_DIV REGISTER Address: 0x42, Reset: 0x00, Name: CLK2_SOURCE_DIV Clock 2 Divide and Core Clock Enable Control Table 95. Bit Descriptions for CLK2_SOURCE_DIV Bits 7 Bit Name CLK2EN Settings 0 1 6 CLK2S_SEL 0 1 [5:3] CLK2SDIV 000 001 010 011 100 101 110 111 [2:0] MCLK2DIV 000 001 010 011 100 101 110 111 Description Clock 2 Enable. Core clock enable or disable control. Clock 2 disable (default) Clock 2 enable PLLB Bypass Signal. Clock source selection. Clock source can be set to either PLLB output or external input. Use PLLB clock as Source Clock 2 (default) Use external clock as Source Clock 2 Source Clock 2 Divider. Source Clock 2 divider settings, 0 through 7 in eight steps. Source Clock Divider K = 0 Source Clock Divider K = 1 Source Clock Divider K = 2 Source Clock Divider K = 3 Source Clock Divider K = 4 Source Clock Divider K = 5 Source Clock Divider K = 6 Source Clock Divider K = 7 Master Clock 2 Divider. Master Clock 2 divider settings, 0 through 7 in eight steps. Divider J = 0 Divider J = 1 Divider J = 2 Divider J = 3 Divider J = 4 Divider J = 5 Divider J = 6 Divider J = 7 Rev. 0 | Page 150 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 CLK2_OUTPUT_DIV REGISTER Address: 0x43, Reset: 0x00, Name: CLK2_OUTPUT_DIV Master Clock 2 Output Divider Control for PLLB Table 96. Bit Descriptions for CLK2_OUTPUT_DIV Bits [7:6] 5 Bit Name RESERVED CLK2OEN Settings 0 1 [4:0] CLK2ODIV 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 Description Reserved. CLK2 Output Enable. Output clock enable control. CLK2 output disable (default) CLK2 output enable Output Clock 2 Divider. Output clock divider settings, 0 through 31. Output Clock Divider P = 0 Output Clock Divider P = 1 Output Clock Divider P = 2 Output Clock Divider P = 3 Output Clock Divider P = 4 Output Clock Divider P = 5 Output Clock Divider P = 6 Output Clock Divider P = 7 Output Clock Divider P = 8 Output Clock Divider P = 9 Output Clock Divider P = 10 Rev. 0 | Page 151 of 296 Reset 0x0 0x0 Access RW RW 0x00 RW ADAU1373 Bits Bit Name Settings 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Description Output Clock Divider P = 11 Output Clock Divider P = 12 Output Clock Divider P = 13 Output Clock Divider P = 14 Output Clock Divider P = 15 Output Clock Divider P = 16 Output Clock Divider P = 17 Output Clock Divider P = 18 Output Clock Divider P = 19 Output Clock Divider P = 20 Output Clock Divider P = 21 Output Clock Divider P = 22 Output Clock Divider P = 23 Output Clock Divider P = 24 Output Clock Divider P = 25 Output Clock Divider P = 26 Output Clock Divider P = 27 Output Clock Divider P = 28 Output Clock Divider P = 29 Output Clock Divider P = 30 Output Clock Divider P = 31 Rev. 0 | Page 152 of 296 Reset Access ADAU1373 DAIA REGISTER Address: 0x44, Reset: 0x0A, Name: DAIA Digital Audio Interface A Settings 1 Table 97. Bit Descriptions for DAIA Bits 7 Bit Name BCLKINVA Settings 0 1 6 MSA 0 1 5 SWAPA 0 1 4 LRPA 0 1 [3:2] WLA 00 01 10 11 [1:0] FORMATA 00 01 10 11 Description BCLK Inversion Control. Bit clock polarity inversion setting. BCLK not inverted (default) BCLK inverted Master Mode Enable. Digital Audio Interface A master/slave setting. Enable slave mode (default) Enable master mode Swap Audio Interface Data Control. Left/right channel data swap setting. Output left- and right-channel data as normal (default) Swap left- and right-channel DAC data in audio interface Polarity Control for Clocks in Right-Justified, Left-Justified, and I2S Modes. Polarity invert setting for frame clock. Normal DACLRC and ADCLRC (default) Invert DACLRC and ADCLRC polarity Data-Word Length Control. Digital Audio Interface A data-word length setting: 16/20/24/32 bits. 16 bits 20 bits 24 bits (default) 32 bits Digital Audio Interface A Format Control. Digital Audio Interface A serial format setting RJ/LJ/I2S/DSP mode. Right justified Left justified I2S format (default) DSP mode Rev. 0 | Page 153 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x2 RW 0x2 RW ADAU1373 DAIB REGISTER Address: 0x45, Reset: 0x0A, Name: DAIB Digital Audio Interface B Settings 1 Table 98. Bit Descriptions for DAIB Bits 7 Bit Name BCLKINVB Settings 0 1 6 MSB 0 1 5 SWAPB 0 1 4 LRPB 0 1 [3:2] WLB 00 01 10 11 [1:0] FORMATB 00 01 10 11 Description BCLK Inversion Control. Bit clock polarity inversion setting. BCLK not inverted (default) BCLK inverted Master Mode Enable. Digital Audio Interface B master/slave setting. Enable slave mode (default) Enable master mode Swap Audio Interface Data Control. Left/right channel data swap setting. Output left- and right-channel data as normal (default) Swap left- and right-channel DAC data in audio interface Polarity Control for Clocks in Right-Justified, Left-Justified, and I2S Modes. Polarity invert setting for frame clock. Normal DACLRC and ADCLRC (default) Invert DACLRC and ADCLRC polarity Data-Word Length Control. Digital Audio Interface B data-word length setting: 16/20/24/32 bits. 16 bits 20 bits 24 bits (default) 32 bits Digital Audio Interface B Format Control. Digital Audio Interface B serial format setting RJ/LJ/I2S/DSP mode. Right justified Left justified I2S format (default) DSP mode Rev. 0 | Page 154 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x2 RW 0x2 RW ADAU1373 DAIC REGISTER Address: 0x46, Reset: 0x0A, Name: DAIC Digital Audio Interface C Settings 1 Table 99. Bit Descriptions for DAIC Bits 7 Bit Name BCLKINVC Settings 0 1 6 MSC 0 1 5 SWAPC 0 1 4 LRPC 0 1 [3:2] WLC 00 01 10 11 [1:0] FORMATC 00 01 10 11 Description BCLK Inversion Control. Bit clock polarity inversion setting. BCLK not inverted (default) BCLK inverted Master Mode Enable. Digital Audio Interface C master/slave setting. Enable slave mode (default) Enable master mode Swap Audio Interface Data Control. Left/right channel data swap setting. Output left- and right-channel data as normal (default) Swap left- and right-channel DAC data in audio interface Polarity Control for Clocks in Right-Justified, Left-Justified, and I2S Modes. Polarity invert setting for frame clock. Normal DACLRC and ADCLRC (default) Invert DACLRC and ADCLRC polarity Data-Word Length Control. Digital Audio Interface C data-word length setting: 16/20/24/32 bits. 16 bits 20 bits 24 bits (default) 32 bits Digital Audio Interface C Format Control. Digital Audio Interface C serial format setting RJ/LJ/I2S/DSP mode. Right justified Left justified I2S format (default) DSP mode Rev. 0 | Page 155 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x2 RW 0x2 RW ADAU1373 BCLKDIVA REGISTER Address: 0x47, Reset: 0x00, Name: BCLKDIVA Digital Audio Interface A Settings 2 Table 100. Bit Descriptions for BCLKDIVA Bits [7:6] 5 Bit Name RESERVED DAIA_SOURCE Settings 0 1 [4:2] DAIA_SR 000 001 010 011 100 101 110 111 [1:0] BPFA 00 01 10 11 Description Reserved. Source Clock of the Digital Audio Interface A in Master Mode. Master clock source for Interface A can be set to either PLLA or PLLB. From PLLA From PLLB Sample Rate of Digital Audio Interface A. Sample rate for Interface A can be set to 32 kHz/24 kHz/16 kHz/12 kHz/8 kHz/8.0182 kHz. fS (48 kHz) 2/3 fS (32 kHz) 1/2 fS (24 kHz) 1/3 fS (16 kHz) 1/4 fS (12 kHz) 1/6 fS (8 kHz) 2/11 fS (44.1K based, 8.0182 kHz) fS Number of Bit Clocks per Frame of Digital Audio Interface A. Number of bit clocks per frame can be set to 32/64/128/256. 256 128 64 32 Rev. 0 | Page 156 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW ADAU1373 BCLKDIVB REGISTER Address: 0x48, Reset: 0x00, Name: BCLKDIVB Digital Audio Interface B Settings 2 Table 101. Bit Descriptions for BCLKDIVB Bits [7:6] 5 Bit Name RESERVED DAIB_SOURCE Settings 0 1 [4:2] DAIB_SR 000 001 010 011 100 101 110 111 [1:0] BPFB 00 01 10 11 Description Reserved. Source Clock of the Digital Audio Interface B in Master Mode. Master clock source for Interface B can be set to either PLLA or PLLB. From PLLA From PLLB Sample Rate of Digital Audio Interface B. Sample rate for Interface B can be set to 32 kHz/24 kHz/16 kHz/12 kHz/8 kHz/8.0182 kHz. fS (48 kHz) 2/3 fS (32 kHz) 1/2 fS (24 kHz) 1/3 fS (16 kHz) 1/4 fS (12 kHz) 1/6 fS (8 kHz) 2/11 fS (44.1K based, 8.0182 kHz) fS Number of Bit Clocks per Frame of Digital Audio Interface B. Number of bit clocks per frame can be set to 32/64/128/256. 256 128 64 32 Rev. 0 | Page 157 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW ADAU1373 BCLKDIVC REGISTER Address: 0x49, Reset: 0x00, Name: BCLKDIVC Digital Audio Interface C Settings 2 Table 102. Bit Descriptions for BCLKDIVC Bits [7:6] 5 Bit Name RESERVED DAIC_SOURCE Settings 0 1 [4:2] DAIC_SR 000 001 010 011 100 101 110 111 [1:0] BPFC 00 01 10 11 Description Reserved. Source Clock of Digital Audio Interface C in Master Mode. Master clock source for Interface C can be set to either PLLA or PLLB. From PLLA From PLLB Sample Rate of Digital Audio Interface C. Sample rate for Interface C can be set to 32 kHz/24 kHz/16 kHz/12 kHz/8 kHz/8.0182 kHz. fS (48 kHz) 2/3 fS (32 kHz) 1/2 fS (24 kHz) 1/3 fS (16 kHz) 1/4 fS (12 kHz) 1/6 fS (8 kHz) 2/11 fS (44.1K based, 8.0182 kHz) fS Number of Bit Clocks per Frame of Digital Audio Interface C. Number of bit clocks per frame can be set to 32/64/128/256. 256 128 64 32 Rev. 0 | Page 158 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW ADAU1373 SRCA_RATIOA REGISTER Address: 0x4A, Reset: 0x00, Name: SRCA_RATIOA Sample Rate Converter A Setting Table 103. Bit Descriptions for SRCA_RATIOA Bits 7 Bit Name SRCAMODE Settings 0 1 [6:4] [3:0] SRCAINT SRCARFRE_HI Description SRCA Working Mode. SRCA ratio can be set to autodetect or manual mode. In manual mode the SRC ratio must be set using SRCAINT, SRCARFRE_HI, and SRCARFRE_LOW bits. The format is 3.12. Enable ASRCA ratio autodetect; the data is automatically written in the SRCA INT/FRAC ratio register (default) Disable ASRCA ratio autodetect, using the data set in the SRCA INT/FRAC ratio register Integer Part of the SRCA Ratio Setting. Upper Four Bits for the SRCA Ratio Setting. Reset 0x0 Access RW 0x0 0x0 RW RW Reset 0x00 Access RW SRCA_RATIOB REGISTER Address: 0x4B, Reset: 0x00, Name: SRCA_RATIOB Sample Rate Converter A Setting Table 104. Bit Descriptions for SRCA_RATIOB Bits [7:0] Bit Name SRCARFRE_LOW Settings Description Lower Byte for the SRCA Ratio Setting. Rev. 0 | Page 159 of 296 ADAU1373 SRCB_RATIOA REGISTER Address: 0x4C, Reset: 0x00, Name: SRCB_RATIOA Sample Rate Converter B Setting Table 105. Bit Descriptions for SRCB_RATIOA Bits 7 Bit Name SRCBMODE Settings 0 1 [6:4] [3:0] SRCBINT SRCBRFRE_HI Description SRCB Working Mode. SRCB ratio can be set to autodetect or manual mode. In manual mode the SRC ratio needs to be set using SRCBINT, SRCBRFRE_HI, and SRCBRFRE_LOW bits. The format is 3.12. Enable ASRCB ratio autodetect; the data is automatically written in the SRCB INT/FRAC ratio register (default) Disable ASRCB ratio autodetect, using the data set in the SRCB INT/FRAC ratio register Integer Part of the SRCB Ratio Setting. Upper Four Bits for the SRCB Ratio Setting. Reset 0x0 Access RW 0x0 0x0 RW RW Reset 0x00 Access RW SRCB_RATIOB REGISTER Address: 0x4D, Reset: 0x00, Name: SRCB_RATIOB Sample Rate Converter B Setting Table 106. Bit Descriptions for SRCB_RATIOB Bits [7:0] Bit Name SRCBRFRE_LOW Settings Description Lower Byte for the SRCB Ratio Setting. Rev. 0 | Page 160 of 296 ADAU1373 SRCC_RATIOA REGISTER Address: 0x4E, Reset: 0x00, Name: SRCC_RATIOA Sample Rate Converter C Setting Table 107. Bit Descriptions for SRCC_RATIOA Bits 7 Bit Name SRCCMODE Settings 0 1 [6:4] [3:0] SRCCINT SRCCRFRE_HI Description SRCC Working Mode. SRCC ratio can be set to autodetect or manual mode. In manual mode, the SRCC ratio needs to be set using SRCCINT, SRCCRFRE_HI, and SRCCRFRE_LOW bits. The format is 3.12. Enable ASRCC ratio autodetect; the data is automatically written in the SRCC INT/FRAC ratio register (default) Disable ASRCC ratio autodetect, using the data set in the SRCC INT/FRAC ratio register Integer Part of the SRCC Ratio Setting. Upper Four Bits for the SRCC Ratio Setting. Reset 0x0 Access RW 0x0 0x0 RW RW Reset 0x00 Access RW SRCC_RATIOB REGISTER Address: 0x4F, Reset: 0x00, Name: SRCC_RATIOB Sample Rate Converter C Setting Table 108. Bit Descriptions for SRCC_RATIOB Bits [7:0] Bit Name SRCCRFRE_LOW Settings Description Lower Byte for the SRCC Ratio Setting. Rev. 0 | Page 161 of 296 ADAU1373 DEEMP_CTRL REGISTER Address: 0x50, Reset: 0x00, Name: DEEMP_CTRL De-Emphasis Enable/Disable Control for Digital Audio Interface A/B/C Table 109. Bit Descriptions for DEEMP_CTRL Bits [7:5] [4:3] Bit Name RESERVED DEMPFS Settings 00 01 10 11 2 DEMPCEN 0 1 1 DEMPBEN 0 1 0 DEMPAEN 0 1 Description Reserved. De-Emphasis FS Select. Bypass 48 kHz 44.1 kHz 32 kHz Enable De-Emphasis for AIFC. Digital Audio Interface C de-emphasis enable/disable. De-emphasis on AIFC input disable De-emphasis on AIFC input enable Enable De-Emphasis for AIFB. Digital Audio Interface B de-emphasis enable/disable. De-emphasis on AIFB input disable De-emphasis on AIFB input enable Enable De-Emphasis for AIFA. Digital Audio Interface A de-emphasis enable/disable. De-emphasis on AIFA input disable De-emphasis on AIFA input enable Rev. 0 | Page 162 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 SRC_DAI_A_CTRL REGISTER Address: 0x51, Reset: 0x08, Name: SRC_DAI_A_CTRL SRCA and Digital Audio Interface A Control Table 110. Bit Descriptions for SRC_DAI_A_CTRL Bits [7:6] 5 Bit Name RESERVED SRCA_RECWRONG Settings 0 1 4 SRCA_PBWRONG 0 1 3 SRCAUNLOCK 1 0 2 SRCAPBEN 0 1 1 SRCARECEN 0 1 0 DAIAEN 0 1 Description Reserved. SRCA Record Wrong. SRCA record status bit. Not wrong (default) Wrong SRCA Playback Wrong. SRCA playback status bit. Not wrong (default) Wrong SRCA Unlock. SRCA lock status bit. Not locked (default) Locked Playback Channel SRCA Enable. Playback path SRCA enable/disable control. Disable (default) Enable Recording channel SRCA Enable. Record path SRCA enable/disable control. Disable (default) Enable Digital Audio Interface A Enable. Digital Audio Interface A enable/disable control. Disable (default) Enable Rev. 0 | Page 163 of 296 Reset 0x0 0x0 Access RW R 0x0 R 0x1 R 0x0 RW 0x0 RW 0x0 RW ADAU1373 SRC_DAI_B_CTRL REGISTER Address: 0x52, Reset: 0x08, Name: SRC_DAI_B_CTRL SRCB and Digital Audio Interface B Control Table 111. Bit Descriptions for SRC_DAI_B_CTRL Bits [7:6] 5 Bit Name RESERVED SRCB_RECWRONG Settings 0 1 4 SRCB_PBWRONG 0 1 3 SRCBUNLOCK 1 0 2 SRCBPBEN 0 1 1 SRCBRECEN 0 1 0 DAIBEN 0 1 Description Reserved. SRCB Record Wrong. SRCB record status bit. Not wrong (default) Wrong SRCB Playback Wrong. SRCB playback status bit. Not wrong (default) Wrong SRCB Unlock. SRCB lock status bit. Not lock (default) Locked Playback Channel SRCB Enable. Playback path SRCB enable/disable control. Disable (default) Enable Recording Channel SRCB Enable. Record path SRCB enable/disable control. Disable (default) Enable Digital Audio Interface B Enable. Digital Audio Interface B enable/disable control. Disable (default) Enable Rev. 0 | Page 164 of 296 Reset 0x0 0x0 Access RW R 0x0 R 0x1 R 0x0 RW 0x0 RW 0x0 RW ADAU1373 SRC_DAI_C_CTRL REGISTER Address: 0x53, Reset: 0x08, Name: SRC_DAI_C_CTRL SRCC and Digital Audio Interface C Control Table 112. Bit Descriptions for SRC_DAI_C_CTRL Bits [7:6] 5 Bit Name RESERVED SRCC_RECWRONG Settings 0 1 4 SRCC_PBWRONG 0 1 3 SRCCUNLOCK 1 0 2 SRCCPBEN 0 1 1 SRCCRECEN 0 1 0 DAICEN 0 1 Description Reserved. SRCC Record Wrong. SRCC record status bit. Not wrong (default) Wrong SRCC Playback Wrong. SRCC playback status bit. Not wrong (default) Wrong SRCC Unlock. SRCC lock status bit. Not lock (default) Locked Playback Channel SRCC Enable. Playback path SRCC enable/disable control. Disable (default) Enable Recording Channel SRCC Enable. Record path SRCC enable/disable control. Disable (default) Enable Digital Audio Interface C Enable. Digital Audio Interface C enable/disable control. Disable (default) Enable Rev. 0 | Page 165 of 296 Reset 0x0 0x0 Access RW R 0x0 R 0x1 R 0x0 RW 0x0 RW 0x0 RW ADAU1373 DIN_MIX_CTRL0 (TO FDSP CHANNEL 0 INPUT) REGISTER Address: 0x56, Reset: 0x00, Name: DIN_MIX_CTRL0 DSP Input Mixer Control Channel 0 Table 113. Bit Descriptions for DIN_MIX_CTRL0 Bits 7 6 Bit Name RESERVED DIN_CHAN0_DMIC_SWAP Settings 0 1 5 DIN_CHAN0_DMIC 0 1 4 DIN_CHAN0_ADC_SWAP 0 1 3 DIN_CHAN0_ADC 0 1 2 DIN_CHAN0_AIFC_PB 0 1 1 DIN_CHAN0_AIFB_PB 0 1 0 DIN_CHAN0_AIFA_PB 0 1 Description Reserved. DIN Channel 0 Select (DMIC Recording Channel Output, Left Channel/Right Channel Swap). DSP data in Channel 0: DMIC (left/right swapped) select. Not select Select DIN Channel 0 Select (DMIC Recording Channel Output). DSP data in Channel 0: DMIC select. Not select Select DIN Channel 0 Select (Codec Recording Channel Output, Left Channel/ Right Channel Swap). DSP data in Channel 0: ADC select. Not select Select DIN Channel 0 Select (Codec Recording Channel Output). DSP data in Channel 0: ADC (left/right swapped) select. Not select Select DIN Channel 0 Select (Audio Interface C Playback Input). DSP data in Channel 0: Audio Interface C input select. Not select Select DIN Channel 0 Select (Audio Interface B Playback Input). DSP data in Channel 0: Audio Interface B input select. Not select Select DIN Channel 0 Select (Audio Interface A Playback Input). DSP data in Channel 0: Audio Interface A input select. Not select Select Rev. 0 | Page 166 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DIN_MIX_CTRL1 (TO FDSP CHANNEL 1 INPUT) REGISTER Address: 0x57, Reset: 0x00, Name: DIN_MIX_CTRL1 DSP Input Mixer Control Channel 1 Table 114. Bit Descriptions for DIN_MIX_CTRL1 Bits 7 6 Bit Name RESERVED DIN_CHAN1_DMIC_SWAP Settings 0 1 5 DIN_CHAN1_DMIC 0 1 4 DIN_CHAN1_ADC_SWAP 0 1 3 DIN_CHAN1_ADC 0 1 2 DIN_CHAN1_AIFC_PB 0 1 1 DIN_CHAN1_AIFB_PB 0 1 0 DIN_CHAN1_AIFA_PB 0 1 Description Reserved. DIN Channel 1 Select (DMIC Recording Channel Output, Left Channel/Right Channel Swap). DSP data in Channel 1: DMIC (left/right swapped) select. Not select Select DIN Channel 1 Select (DMIC Recording Channel Output). DSP data in Channel 1: DMIC select. Not select Select DIN Channel 1 Select (Codec Recording Channel Output, Left Channel/ Right Channel Swap). DSP data in Channel 1: ADC select. Not select Select DIN Channel 1 Select (Codec Recording Channel Output). DSP data in Channel 1: ADC (left/right swapped) select. Not select Select DIN Channel 1 Select (Audio Interface C Playback Input). DSP data in Channel 1: Audio Interface C input select. Not select Select DIN Channel 1 Select (Audio Interface B Playback Input). DSP data in Channel 1: Audio Interface B input select. Not select Select DIN Channel 1 Select (Audio Interface A Playback Input). DSP data in Channel 1: Audio Interface A input select. Not select Select Rev. 0 | Page 167 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DIN_MIX_CTRL2 (TO FDSP CHANNEL 2 INPUT) REGISTER Address: 0x58, Reset: 0x00, Name: DIN_MIX_CTRL2 DSP Input Mixer Control Channel 2 Table 115. Bit Descriptions for DIN_MIX_CTRL2 Bits 7 6 Bit Name RESERVED DIN_CHAN2_DMIC_SWAP Settings 0 1 5 DIN_CHAN2_DMIC 0 1 4 DIN_CHAN2_ADC_SWAP 0 1 3 DIN_CHAN2_ADC 0 1 2 DIN_CHAN2_AIFC_PB 0 1 1 DIN_CHAN2_AIFB_PB 0 1 0 DIN_CHAN2_AIFA_PB 0 1 Description Reserved. DIN Channel 2 Select (DMIC Recording Channel Output, Left Channel/Right Channel Swap). DSP data in Channel 2: DMIC (left/right swapped) select. Not select Select DIN Channel 2 Select (DMIC Recording Channel Output). DSP data in Channel 2: DMIC select. Not select Select DIN Channel 2 Select (Codec Recording Channel Output, Left Channel/ Right Channel Swap). DSP data in Channel 2: ADC select. Not select Select DIN Channel 2 Select (Codec Recording Channel Output). DSP data in Channel 2: ADC (left/right swapped) select. Not select Select DIN Channel 2 Select (Audio Interface C Playback Input). DSP data in Channel 2: Audio Interface C input select. Not select Select DIN Channel 2 Select (Audio Interface B Playback Input). DSP data in Channel 2: Audio Interface B input select. Not select Select DIN Channel 2 Select (Audio Interface A Playback Input). DSP data in Channel 2: Audio Interface A input select. Not select Select Rev. 0 | Page 168 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DIN_MIX_CTRL3 (TO FDSP CHANNEL 3 INPUT) REGISTER Address: 0x59, Reset: 0x00, Name: DIN_MIX_CTRL3 DSP Input Mixer Control Channel 3 Table 116. Bit Descriptions for DIN_MIX_CTRL3 Bits 7 6 Bit Name RESERVED DIN_CHAN3_DMIC_SWAP Settings 0 1 5 DIN_CHAN3_DMIC 0 1 4 DIN_CHAN3_ADC_SWAP 0 1 3 DIN_CHAN3_ADC 0 1 2 DIN_CHAN3_AIFC_PB 0 1 1 DIN_CHAN3_AIFB_PB 0 1 0 DIN_CHAN3_AIFA_PB 0 1 Description Reserved. DIN Channel 3 Select (DMIC Recording Channel Output, Left Channel/Right Channel Swap). DSP data in Channel 3: DMIC (left/right swapped) select. Not select Select DIN Channel 3 Select (DMIC Recording Channel Output). DSP data in Channel 3: DMIC Select. Not select Select DIN Channel 3 Select (Codec Recording Channel Output, Left Channel/Right Channel Swap). DSP data in Channel 3: ADC select. Not select Select DIN Channel 3 Select (Codec Recording Channel Output). DSP data in Channel 3: ADC (left/right swapped) select. Not select Select DIN Channel 3 Select (Audio Interface C Playback Input). DSP data in Channel 3: Audio Interface C input select. Not select Select DIN Channel 3 Select (Audio Interface B Playback Input). DSP data in Channel 3: Audio Interface B input select. Not select Select DIN Channel 3 Select (Audio Interface A Playback Input). DSP data in Channel 3: Audio Interface A input select. Not select Select Rev. 0 | Page 169 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DIN_MIX_CTRL4 (TO FDSP CHANNEL 4 INPUT) REGISTER Address: 0x5A, Reset: 0x00, Name: DIN_MIX_CTRL4 DSP Input Mixer Control Channel 4 Table 117. Bit Descriptions for DIN_MIX_CTRL4 Bits 7 6 Bit Name RESERVED DIN_CHAN4_DMIC_SWAP Settings 0 1 5 DIN_CHAN4_DMIC 0 1 4 DIN_CHAN4_ADC_SWAP 0 1 3 DIN_CHAN4_ADC 0 1 2 DIN_CHAN4_AIFC_PB 0 1 1 DIN_CHAN4_AIFB_PB 0 1 0 DIN_CHAN4_AIFA_PB 0 1 Description Reserved. DIN Channel 4 Select (DMIC Recording Channel Output, Left Channel/Right Channel Swap). DSP data in Channel 4: DMIC (left/right swapped) select. Not select Select DIN Channel 4 Select (DMIC Recording Channel Output). DSP data in Channel 4: DMIC select. Not select Select DIN Channel 4 Select (Codec Recording Channel Output, Left Channel/Right Channel Swap). DSP data in Channel 4: ADC select. Not select Select DIN Channel 4 Select (Codec Recording Channel Output). DSP data in Channel 3: ADC (left/right swapped) select. Not select Select DIN Channel 4 Select (Audio Interface C Playback Input). DSP data in Channel 4: Audio Interface C input select. Not select Select DIN Channel 4 Select (Audio Interface B Playback Input). DSP data in Channel 4: Audio Interface B input select. Not select Select DIN Channel 4 Select (Audio Interface A Playback Input). DSP data in Channel 4: Audio Interface A input select. Not select Select Rev. 0 | Page 170 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DOUT_MIX_CTRL0 (TO DIGITAL AUDIO INTERFACE A RECORDING OUTPUT) REGISTER Address: 0x5B, Reset: 0x00, Name: DOUT_MIX_CTRL0 DSP Output Mix Control Interface A Table 118. Bit Descriptions for DOUT_MIX_CTRL0 Bits [7:5] 4 Bit Name RESERVED DOUT_CHAN4_AIFA_REC Settings 0 1 3 DOUT_CHAN3_AIFA_REC 0 1 2 DOUT_CHAN2_AIFA_REC 0 1 1 DOUT_CHAN1_AIFA_REC 0 1 0 DOUT_CHAN0_AIFA_REC 0 1 Description Reserved. FDSP Channel 4 Output to Digital Audio Interface A. DSP output Channel 4 to Digital Audio Interface A enable/disable. Not select Select FDSP Channel 3 Output to Digital Audio Interface A. DSP output Channel 3 to Digital Audio Interface A enable/disable. Not select Select FDSP Channel 2 Output to Digital Audio Interface A. DSP output Channel 2 to Digital Audio Interface A enable/disable. Not select Select FDSP Channel 1 Output to Digital Audio Interface A. DSP output Channel 1 to Digital Audio Interface A enable/disable. Not select Select FDSP Channel 0 Output to Digital Audio Interface A. DSP output Channel 0 to Digital Audio Interface A enable/disable. Not select Select Rev. 0 | Page 171 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DOUT_MIX_CTRL1 (TO DIGITAL AUDIO INTERFACE B RECORDING OUTPUT) REGISTER Address: 0x5C, Reset: 0x00, Name: DOUT_MIX_CTRL1 DSP Output Mix Control Interface B Table 119. Bit Descriptions for DOUT_MIX_CTRL1 Bits [7:5] 4 Bit Name RESERVED DOUT_CHAN4_AIFB_REC Settings 0 1 3 DOUT_CHAN3_AIFB_REC 0 1 2 DOUT_CHAN2_AIFB_REC 0 1 1 DOUT_CHAN1_AIFB_REC 0 1 0 DOUT_CHAN0_AIFB_REC 0 1 Description Reserved. FDSP Channel 4 Output to Digital Audio Interface B. DSP output Channel 4 to Digital Audio Interface B enable/disable. Not select Select FDSP Channel 3 Output to Digital Audio Interface B. DSP output Channel 3 to Digital Audio Interface B enable/disable. Not select Select FDSP Channel 2 Output to Digital Audio Interface B. DSP output Channel 2 to Digital Audio Interface B enable/disable. Not select Select FDSP Channel 1 Output to Digital Audio Interface B. DSP output Channel 1 to Digital Audio Interface B enable/disable. Not select Select FDSP Channel 0 Output to Digital Audio Interface B. DSP output Channel 0 to Digital Audio Interface B enable/disable. Not select Select Rev. 0 | Page 172 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DOUT_MIX_CTRL2 (TO DIGITAL AUDIO INTERFACE C RECORDING OUTPUT) REGISTER Address: 0x5D, Reset: 0x00, Name: DOUT_MIX_CTRL2 DSP Output Mix Control Interface C Table 120. Bit Descriptions for DOUT_MIX_CTRL2 Bits [7:5] 4 Bit Name RESERVED DOUT_CHAN4_AIFC_REC Settings 0 1 3 DOUT_CHAN3_AIFC_REC 0 1 2 DOUT_CHAN2_AIFC_REC 0 1 1 DOUT_CHAN1_AIFC_REC 0 1 0 DOUT_CHAN0_AIFC_REC 0 1 Description Reserved. FDSP Channel 4 Output to Digital Audio Interface C. DSP output Channel 4 to Digital Audio Interface C enable/disable. Not select Select FDSP Channel 3 Output to Digital Audio Interface C. DSP output Channel 3 to Digital Audio Interface C enable/disable. Not select Select FDSP Channel 2 Output to Digital Audio Interface C. DSP output Channel 2 to Digital Audio Interface C enable/disable. Not select Select FDSP Channel 1 Output to Digital Audio Interface C. DSP output Channel 1 to Digital Audio Interface C enable/disable. Not select Select FDSP Channel 0 Output to Digital Audio Interface C. DSP output Channel 0 to Digital Audio Interface C enable/disable. Not select Select Rev. 0 | Page 173 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DOUT_MIX_CTRL3 (TO DAC1 PLAYBACK INPUT) REGISTER Address: 0x5E, Reset: 0x00, Name: DOUT_MIX_CTRL3 DSP Output Mix Control DAC1 Table 121. Bit Descriptions for DOUT_MIX_CTRL3 Bits [7:5] 4 Bit Name RESERVED DOUT_CHAN4_DAC1 Settings 0 1 3 DOUT_CHAN3_DAC1 0 1 2 DOUT_CHAN2_DAC1 0 1 1 DOUT_CHAN1_DAC1 0 1 0 DOUT_CHAN0_DAC1 0 1 Description Reserved. FDSP Channel 4 Output to DAC1. DSP output Channel 4 to DAC1 enable/disable. Not select Select FDSP Channel 3 Output to DAC1. DSP output Channel 3 to DAC1 enable/disable. Not select Select FDSP Channel 2 Output to DAC1. DSP output Channel 2 to DAC1 enable/disable. Not select Select FDSP Channel 1 Output to DAC1. DSP output Channel 1 to DAC1 enable/disable. Not select Select FDSP Channel 0 Output to DAC1. DSP output Channel 0 to DAC1 enable/disable. Not select Select Rev. 0 | Page 174 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DOUT_MIX_CTRL4 (TO DAC2 PLAYBACK INPUT) REGISTER Address: 0x5F, Reset: 0x00, Name: DOUT_MIX_CTRL4 DSP Output Mix Control DAC2 Table 122. Bit Descriptions for DOUT_MIX_CTRL4 Bits [7:5] 4 Bit Name RESERVED DOUT_CHAN4_DAC2 Settings 0 1 3 DOUT_CHAN3_DAC2 0 1 2 DOUT_CHAN2_DAC2 0 1 1 DOUT_CHAN1_DAC2 0 1 0 DOUT_CHAN0_DAC2 0 1 Description Reserved. FDSP Channel 4 Output to DAC2. DSP output Channel 4 to DAC2 enable/disable. Not select Select FDSP Channel 3 Output to DAC2. DSP output Channel 3 to DAC2 enable/disable. Not select Select FDSP Channel 2 Output to DAC2. DSP output Channel 2 to DAC2 enable/disable. Not select Select FDSP Channel 1 Output to DAC2. DSP output Channel 1 to DAC2 enable/disable. Not select Select FDSP Channel 0 Output to DAC2. DSP output Channel 0 to DAC2 enable/disable. Not select Select Rev. 0 | Page 175 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 VOLMOD1 REGISTER Address: 0x60, Reset: 0x00, Name: VOLMOD1 Digital Volume Change Selection Either Soft or Hard (Forced) Table 123. Bit Descriptions for VOLMOD1 Bits [7:6] 5 Bit Name RESERVED DAICRECVOLM Settings 0 1 4 DAIBRECVOLM 0 1 3 DAIARECVOLM 0 1 2 DAICPBVOLM 0 1 1 DAIBPBVOLM 0 1 0 DAIAPBVOLM 0 1 Description Reserved. Audio Interface C Recording Volume Control Work Mode. Audio Interface C recording volume control update mode. Soft (default) Force Audio Interface B Recording Volume Control Work Mode. Audio Interface B recording volume control update mode. Soft (default) Force Audio Interface A Recording Volume Control Work Mode. Audio Interface A recording volume control update mode. Soft (default) Force Audio Interface C Playback Volume Control Work Mode. Audio Interface C playback volume control update mode. Soft (default) Force Audio Interface B Playback Volume Control Work Mode. Audio Interface B playback volume control update mode. Soft (default) Force Audio Interface A Playback Volume Control Work Mode. Audio Interface A playback volume control update mode. Soft (default) Force Rev. 0 | Page 176 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 VOLMOD2 REGISTER Address: 0x61, Reset: 0x00, Name: VOLMOD2 Digital Volume Change Selection, Either Soft or Hard (Forced) Table 124. Bit Descriptions for VOLMOD2 Bits [7:4] 3 Bit Name RESERVED CODECDRECVOLM Settings 0 1 2 CODECRECVOLM 0 1 1 CODECPBBVOLM 0 1 0 CODECPBAVOLM 0 1 Description Reserved. Codec DMIC Recording Volume Control Work Mode. Digital microphone playback volume control update mode. Soft (default) Force Codec Recording Volume Control Work Mode. ADC recording volume control update mode. Soft (default) Force Codec Playback B Volume Control Work Mode. DAC2 playback volume control update mode. Soft (default) Force Codec Playback A Volume Control Work Mode. DAC1 playback volume control update mode. Soft (default) Force Rev. 0 | Page 177 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DAIA_PBL_VOL REGISTER Address: 0x62, Reset: 0x00, Name: DAIA_PBL_VOL Digital Audio Interface A Left Channel Playback Volume Control Table 125. Bit Descriptions for DAIA_PBL_VOL Bits [7:0] Bit Name DAIAPBLVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Digital Audio Interface A Playback Datapath Left Channel Volume. Interface A left channel playback volume control. 0 dB −0.375 dB 0.375 dB steps down to −95.625 dB Reset 0x00 Access RW Reset 0x00 Access RW DAIA_PBR_VOL REGISTER Address: 0x63, Reset: 0x00, Name: DAIA_PBR_VOL Digital Audio Interface A Right Channel Playback Volume Control Table 126. Bit Descriptions for DAIA_PBR_VOL Bits [7:0] Bit Name DAIAPBRVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Digital Audio Interface A Playback Datapath Right Channel Volume. Interface A right channel playback volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Rev. 0 | Page 178 of 296 ADAU1373 DAIB_PBL_VOL REGISTER Address: 0x64, Reset: 0x00, Name: DAIB_PBL_VOL Digital Audio Interface B Left Channel Playback Volume Control Table 127. Bit Descriptions for DAIB_PBL_VOL Bits [7:0] Bit Name DAIBPBLVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Digital Audio Interface B Playback Datapath Left Channel Volume. Interface B left channel playback volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Reset 0x00 Access RW Reset 0x00 Access RW DAIB_PBR_VOL REGISTER Address: 0x65, Reset: 0x00, Name: DAIB_PBR_VOL Digital Audio Interface B Right Channel Playback Volume Control Table 128. Bit Descriptions for DAIB_PBR_VOL Bits [7:0] Bit Name DAIBPBRVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Digital Audio Interface B PB Datapath Right Channel Volume. Interface B right channel playback volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Rev. 0 | Page 179 of 296 ADAU1373 DAIC_PBL_VOL REGISTER Address: 0x66, Reset: 0x00, Name: DAIC_PBL_VOL Digital Audio Interface C Left Channel Playback Volume Control Table 129. Bit Descriptions for DAIC_PBL_VOL Bits [7:0] Bit Name DAICPBLVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Digital Audio Interface C Playback Datapath Left Channel Volume. Interface C left channel playback volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Reset 0x00 Access RW Reset 0x00 Access RW DAIC_PBR_VOL REGISTER Address: 0x67, Reset: 0x00, Name: DAIC_PBR_VOL Digital Audio Interface C Right Channel Playback Volume Control Table 130. Bit Descriptions for DAIC_PBR_VOL Bits [7:0] Bit Name DAICPBRVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Digital Audio Interface C Playback Datapath R Channel Volume. Interface C right channel playback volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Rev. 0 | Page 180 of 296 ADAU1373 DAIA_RECL_VOL REGISTER Address: 0x68, Reset: 0x00, Name: DAIA_RECL_VOL Digital Audio Interface A Left Channel Recording Volume Control Table 131. Bit Descriptions for DAIA_RECL_VOL Bits [7:0] Bit Name DAIARECLVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Digital Audio Interface A Record Datapath Left Channel Volume. Interface A left channel recording volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Reset 0x00 Access RW Reset 0x00 Access RW DAIA_RECR_VOL REGISTER Address: 0x69, Reset: 0x00, Name: DAIA_RECR_VOL Digital Audio Interface A Right Channel Recording Volume Control Table 132. Bit Descriptions for DAIA_RECR_VOL Bits [7:0] Bit Name DAIARECRVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Digital Audio Interface A Record Datapath Right Channel Volume. Interface A right channel recording volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Rev. 0 | Page 181 of 296 ADAU1373 DAIB_RECL_VOL REGISTER Address: 0x6A, Reset: 0x00, Name: DAIB_RECL_VOL Digital Audio Interface B Left Channel Recording Volume Control Table 133. Bit Descriptions for DAIB_RECL_VOL Bits [7:0] Bit Name DAIBRECLVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Digital Audio Interface B Record Datapath Left Channel Volume. Interface B left channel recording volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Reset 0x00 Access RW Reset 0x00 Access RW DAIB_RECR_VOL REGISTER Address: 0x6B, Reset: 0x00, Name: DAIB_RECR_VOL Digital Audio Interface B Right Channel Recording Volume Control Table 134. Bit Descriptions for DAIB_RECR_VOL Bits [7:0] Bit Name DAIBRECRVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Digital Audio Interface B Record Datapath Right Channel Volume. Interface B right channel recording volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Rev. 0 | Page 182 of 296 ADAU1373 DAIC_RECL_VOL REGISTER Address: 0x6C, Reset: 0x00, Name: DAIC_RECL_VOL Digital Audio Interface C Left Channel Recording Volume Control Table 135. Bit Descriptions for DAIC_RECL_VOL Bits [7:0] Bit Name DAICRECLVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Digital Audio Interface C Record Datapath Left Channel Volume. Interface C left channel recording volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Reset 0x00 Access RW Reset 0x00 Access RW DAIC_RECR_VOL REGISTER Address: 0x6D, Reset: 0x00, Name: DAIC_RECR_VOL Digital Audio Interface C Right Channel Recording Volume Control Table 136. Bit Descriptions for DAIC_RECR_VOL Bits [7:0] Bit Name DAICRECRVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Digital Audio Interface C Record Datapath Right Channel Volume. Interface C right channel recording volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Rev. 0 | Page 183 of 296 ADAU1373 PBAL_VOL REGISTER Address: 0x6E, Reset: 0x00, Name: PBAL_VOL DAC1 Left Channel Playback Volume Control Table 137. Bit Descriptions for PBAL_VOL Bits [7:0] Bit Name PBALVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Codec PBA Datapath Left Channel Volume. DAC1 left channel playback volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Reset 0x00 Access RW Reset 0x00 Access RW PBAR_VOL REGISTER Address: 0x6F, Reset: 0x00, Name: PBAR_VOL DAC1 Right Channel Playback Volume Control Table 138. Bit Descriptions for PBAR_VOL Bits [7:0] Bit Name PBARVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Codec PBA Datapath Right Channel Volume. DAC1 right channel playback volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Rev. 0 | Page 184 of 296 ADAU1373 PBBL_VOL REGISTER Address: 0x70, Reset: 0x00, Name: PBBL_VOL DAC2 Left Channel Playback Volume Control Table 139. Bit Descriptions for PBBL_VOL Bits [7:0] Bit Name PBBLVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Codec PBB Datapath Left Channel Volume. DAC2 left channel playback volume control. 0 dB −0.375 dB 0.375 dB steps down to −95.625 dB Reset 0x00 Access RW Reset 0x00 Access RW PBBR_VOL REGISTER Address: 0x71, Reset: 0x00, Name: PBBR_VOL DAC2 Right Channel Playback Volume Control Table 140. Bit Descriptions for PBBR_VOL Bits [7:0] Bit Name PBBRVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Codec PBB Datapath Right Channel Volume. DAC2 right channel playback volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Rev. 0 | Page 185 of 296 ADAU1373 RECL_VOL REGISTER Address: 0x72, Reset: 0x00, Name: RECL_VOL ADC Left Channel Recording Volume Control Table 141. Bit Descriptions for RECL_VOL Bits [7:0] Bit Name RECLVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Codec Record Datapath Left Channel Volume. ADC left channel recording volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Reset 0x00 Access RW Reset 0x00 Access RW RECR_VOL REGISTER Address: 0x73, Reset: 0x00, Name: RECR_VOL ADC Right Channel Recording Volume Control Table 142. Bit Descriptions for RECR_VOL Bits [7:0] Bit Name RECRVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Codec Record Datapath Right Channel Volume. ADC right channel recording volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Rev. 0 | Page 186 of 296 ADAU1373 DRECL_VOL REGISTER Address: 0x74, Reset: 0x00, Name: DRECL_VOL Digital Microphone Left Channel Recording Volume Control Table 143. Bit Descriptions for DRECL_VOL Bits [7:0] Bit Name DRECLVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Codec DMIC Record Datapath Left Channel Volume. Digital microphone left channel recording volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Reset 0x00 Access RW Reset 0x00 Access RW DRECR_VOL REGISTER Address: 0x75, Reset: 0x00, Name: DRECR_VOL Digital Microphone Right Channel Recording Volume Control Table 144. Bit Descriptions for DRECR_VOL Bits [7:0] Bit Name DRECRVOL Settings 00000000 00000001 xxxxxxxx 11111111 Description Codec DMIC Record Datapath Right Channel Volume. Digital microphone right channel recording volume control. 0 dB (default) −0.375 dB 0.375 dB steps down to −95.625 dB Rev. 0 | Page 187 of 296 ADAU1373 VOL_GAIN1 (DAI PLAYBACK) REGISTER Address: 0x76, Reset: 0x00, Name: VOL_GAIN1 Digital Audio Interface Playback Path Volume Control Gain Table 145. Bit Descriptions for VOL_GAIN1 Bits [7:6] 5 Bit Name RESERVED DAICPBRVOL_GAIN Settings 0 1 4 DAICPBLVOL_GAIN 0 1 3 DAIBPBRVOL_GAIN 0 1 2 DAIBPBLVOL_GAIN 0 1 1 DAIAPBRVOL_GAIN 0 1 0 DAIAPBLVOL_GAIN 0 1 Description Reserved. Digital Audio Interface C Playback Datapath Right Channel Volume Gain. Interface C right channel playback gain. 0 dB gain (default) 6 dB gain Digital Audio Interface C Playback Datapath Left Channel Volume Gain. Interface C left channel playback gain. 0 dB gain (default) 6 dB gain Digital Audio Interface B Playback Datapath Right Channel Volume Gain. Interface B right channel playback gain. 0 dB gain (default) 6 dB gain Digital Audio Interface B Playback Datapath Left Channel Volume Gain. Interface B left channel playback gain. 0 dB gain (default) 6 dB gain Digital Audio Interface A Playback Datapath Right Channel Volume Gain. Interface A right channel playback gain. 0 dB gain (default) 6 dB gain Digital Audio Interface A Playback Datapath Left Channel Volume Gain. Interface A left channel playback gain. 0 dB gain (default) 6 dB gain Rev. 0 | Page 188 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 VOL_GAIN2 (DAI RECORD) REGISTER Address: 0x77, Reset: 0x00, Name: VOL_GAIN2 Digital Audio Interface Recording Path Volume Control Gain Table 146. Bit Descriptions for VOL_GAIN2 Bits [7:6] 5 Bit Name RESERVED DAICRECRVOL_GAIN Settings 0 1 4 DAICRECLVOL_GAIN 0 1 3 DAIBRECRVOL_GAIN 0 1 2 DAIBRECLVOL_GAIN 0 1 1 DAIARECRVOL_GAIN 0 1 0 DAIARECLVOL_GAIN 0 1 Description Reserved. Digital Audio Interface C Record Datapath Right Channel Volume Gain. Interface C right channel recording gain. 0 dB gain (default) 6 dB gain Digital Audio Interface C Record Datapath Left Channel Volume Gain. Interface C left channel recording gain. 0 dB gain (default) 6 dB gain Digital Audio Interface B Record Datapath Right Channel Volume Gain. Interface B right channel recording gain. 0 dB gain (default) 6 dB gain Digital Audio Interface B REC Datapath Left Channel Volume Gain. Interface B left channel recording gain. 0 dB gain (default) 6 dB gain Digital Audio Interface A Record Datapath Right Channel Volume Gain. Interface A right channel recording gain. 0 dB gain (default) 6 dB gain Digital Audio Interface A Record Datapath Left Channel Volume Gain. Interface A left channel recording gain. 0 dB gain (default) 6 dB gain Rev. 0 | Page 189 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 VOL_GAIN3 (CODEC) REGISTER Address: 0x78, Reset: 0x00, Name: VOL_GAIN3 Codec Playback/Recording Path Volume Control Gain Table 147. Bit Descriptions for VOL_GAIN3 Bits 7 Bit Name DRECRVOL_GAIN Settings 0 1 6 DRECLVOL_GAIN 0 1 5 RECRVOL_GAIN 0 1 4 RECLVOL_GAIN 0 1 3 PBBRVOL_GAIN 0 1 2 PBBLVOL_GAIN 0 1 1 PBARVOL_GAIN 0 1 Description Codec DMIC Record Datapath Right Channel Volume Gain. Digital microphone right channel recording volume gain. 0 dB gain (default) 6 dB gain Codec DMIC Record Datapath Left Channel Volume Gain. Digital microphone left channel recording volume gain. 0 dB gain (default) 6 dB gain Codec Record Datapath Right Channel Volume Gain. ADC right channel recording volume gain. 0 dB gain (default) 6 dB gain Codec Record Datapath Left Channel Volume Gain. ADC left channel recording volume gain. 0 dB gain (default) 6 dB gain Codec Playback B Datapath Right Channel Volume Gain. DAC2 right channel playback volume gain. 0 dB gain (default) 6 dB gain Codec Playback B Datapath Left Channel Volume Gain. DAC2 left channel playback volume gain. 0 dB gain (default) 6 dB gain Codec Playback A Datapath Right Channel Volume Gain. DAC1 right channel playback volume gain. 0 dB gain (default) 6 dB gain Rev. 0 | Page 190 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 Bits 0 Bit Name PBALVOL_GAIN Settings 0 1 Description Codec Playback A Datapath Left Channel Volume Gain. DAC1 left channel playback volume gain. 0 dB gain (default) 6 dB gain Reset 0x0 Access RW HPF_CTRL REGISTER Address: 0x7D, Reset: 0x00, Name: HPF_CTRL DSP High-Pass Filter Setting Table 148. Bit Descriptions for HPF_CTRL Bits [7:3] Bit Name HPFF Settings 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 2 HPFOR 0 1 Description High-Pass Filter 3 dB Cutoff Frequency. High-pass filter cutoff frequency selection: 3.7 Hz, 50 Hz to 800 Hz in 16 steps. 3.7 Hz 50 Hz 100 Hz 150 Hz 200 Hz 250 Hz 300 Hz 350 Hz 400 Hz 450 Hz 500 Hz 550 Hz 600 Hz 650 Hz 700 Hz 750 Hz 800 Hz Store/Clear High-Pass Filter DC Value When HPF Disabled. High-pass filter dc value control. Clear dc value Store dc value Rev. 0 | Page 191 of 296 Reset 0x00 Access RW 0x0 RW ADAU1373 Bits [1:0] Bit Name HPFEN Settings 00 01 10 11 Description High-Pass Filter Enable. High-pass filter enable/disable control. Both channels disabled (default) Right channel enabled Left channel enabled Both channels enabled Reset 0x0 Access RW Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW BASS1 REGISTER Address: 0x7E, Reset: 0x00, Name: BASS1 Bass Enhancement Control Register Table 149. Bit Descriptions for BASS1 Bits [7:6] 5 Bit Name RESERVED BASS_LPF Settings 0 1 [4:2] BASS_CUT 000 001 010 011 100 101 110 111 [1:0] BASS_SPK 00 01 10 11 Description Reserved. Bass Output Frequency Range. Cutoff frequency setting for low-pass filter bass enhancement. 801 Hz 1001 Hz Signal Extend Density (Clip Level). Overdrive level for bass enhancement. Reserved 0.125 0.250 0.370 0.500 0.625 0.750 0.875 High-Pass Filter Cutoff Frequency. Cutoff frequency setting for high-pass filter bass enhancement. 158 Hz 232 Hz 347 Hz 520 Hz Rev. 0 | Page 192 of 296 ADAU1373 BASS2 REGISTER Address: 0x7F, Reset: 0x00, Name: BASS2 Bass Enhancement Control Register Table 150. Bit Descriptions for BASS2 Bits [7:5] [4:2] Bit Name RESERVED BASS_GAIN Settings 000 001 010 011 100 101 110 111 [1:0] BASS_SEL 00 01 10 11 Description Reserved. Bass Enhancement Gain. Gain control setting for bass enhancement. Reserved 0 dB 6 dB 9.5 dB 12 dB 14 dB 15.5 dB 17 dB Left/Right Channel Selection. Channel selection for bass enhancement. Both channels off Left channel on Right channel on Both channels on Rev. 0 | Page 193 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW ADAU1373 DRC1_CTRL1 REGISTER Address: 0x80, Reset: 0x78, Name: DRC1_CTRL1 DRC1 Level Detector Averaging Time and DRC Noise Gate Recovery Time Setting Table 151. Bit Descriptions for DRC1_CTRL1 Bits [7:4] Bit Name DRCNGREC Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] DRCLELTAV 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Description DRC1 Noise Gate Recovery Time. 46.875 μs 93.75 μs 187.5 μs 375 μs 750 μs 1.5 ms 3 ms 6 ms (default) 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec DRC1 RMS Detector Average Time. 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms (default) 384 ms 768 ms 1.536 sec Rev. 0 | Page 194 of 296 Reset 0x7 Access RW 0x8 RW ADAU1373 Bits Bit Name Settings 1100 1101 1110 1111 Description 3.072 sec 6.144 sec 12.288 sec 24.576 sec Reset Access Reset 0x1 Access RW DRC1_CTRL2 REGISTER Address: 0x81, Reset: 0x18, Name: DRC1_CTRL2 DRC1 Attack and Decay Time Setting Table 152. Bit Descriptions for DRC1_CTRL2 Bits [7:4] Bit Name DRCLELATT Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DRC1 Peak Detector Attack Time. 46.875 μs 93.75 μs (default) 187.5 μs 375 μs 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec Rev. 0 | Page 195 of 296 ADAU1373 Bits [3:0] Bit Name DRCLELDEC Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DRC1 Peak Detector Decay Time. 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms (default) 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec 12.288 sec 24.576 sec Reset 0x8 Access RW Reset 0x00 Access RW DRC1_CTRL3 REGISTER Address: 0x82, Reset: 0x00, Name: DRC1_CTRL3 DRC1 Threshold Point X1 on X-Axis (Input Level) Table 153. Bit Descriptions for DRC1_CTRL3 Bits [7:0] Bit Name DRCTHX1 Settings 00000000 00000001 00000010 xxxxxxx 11000000 Description DRC1 X-Axis Threshold 1. 0 dB (default) −0.5 dB −1 dB 0.5 dB step −96 dB Rev. 0 | Page 196 of 296 ADAU1373 DRC1_CTRL4 REGISTER Address: 0x83, Reset: 0x00, Name: DRC1_CTRL4 DRC1 Threshold Point X2 on X-Axis (Input Level) Table 154. Bit Descriptions for DRC1_CTRL4 Bits [7:0] Bit Name DRCTHX2 Settings 00000000 00000001 00000010 xxxxxxx 11000000 Description DRC1 X-Axis Threshold 2. 0 dB (default) −0.5 dB −1 dB 0.5 dB step −96 dB Reset 0x00 Access RW Reset 0x00 Access RW DRC1_CTRL5 REGISTER Address: 0x84, Reset: 0x00, Name: DRC1_CTRL5 DRC1 Threshold Point X3 on X-Axis (Input Level) Table 155. Bit Descriptions for DRC1_CTRL5 Bits [7:0] Bit Name DRCTHX3 Settings 00000000 00000001 00000010 xxxxxxx 11000000 Description DRC1 X-Axis Threshold 3. 0 dB (default) −0.5 dB −1 dB 0.5 dB step −96 dB Rev. 0 | Page 197 of 296 ADAU1373 DRC1_CTRL6 REGISTER Address: 0x85, Reset: 0xC0, Name: DRC1_CTRL6 DRC1 Threshold Point X4 on X-Axis (Input Level) Table 156. Bit Descriptions for DRC1_CTRL6 Bits [7:0] Bit Name DRCTHX4 Settings 00000000 00000001 00000010 xxxxxxx 11000000 Description DRC1 X-Axis Threshold 4. 0 dB −0.5 dB −1 dB 0.5 dB step −96 dB (default) Reset 0xC0 Access RW Reset 0x00 Access RW DRC1_CTRL7 REGISTER Address: 0x86, Reset: 0x00, Name: DRC1_CTRL7 DRC1 Threshold Point Y1 on Y-Axis (Output Level) Table 157. Bit Descriptions for DRC1_CTRL7 Bits [7:0] Bit Name DRCTHY1 Settings 00000000 00000001 00000010 xxxxxxx 11000000 Description DRC1 Y-Axis Threshold 1. 0 dB (default) −0.5 dB −1 dB 0.5 dB step −96 dB Rev. 0 | Page 198 of 296 ADAU1373 DRC1_CTRL8 REGISTER Address: 0x87, Reset: 0x00, Name: DRC1_CTRL8 DRC1 Threshold Point Y2 on Y-Axis (Output Level) Table 158. Bit Descriptions for DRC1_CTRL8 Bits [7:0] Bit Name DRCTHY2 Settings 00000000 00000001 00000010 xxxxxxx 11000000 Description DRC1 Y-Axis Threshold 2. 0 dB (default) −0.5 dB −1 dB 0.5 dB step −96 dB Reset 0x00 Access RW Reset 0x00 Access RW DRC1_CTRL9 REGISTER Address: 0x88, Reset: 0x00, Name: DRC1_CTRL9 DRC1 Threshold Point Y3 on Y-Axis (Output Level) Table 159. Bit Descriptions for DRC1_CTRL9 Bits [7:0] Bit Name DRCTHY3 Settings 00000000 00000001 00000010 xxxxxxx 11000000 Description DRC1 Y-Axis Threshold 3. 0 dB (default) −0.5 dB −1 dB 0.5 dB step −96 dB Rev. 0 | Page 199 of 296 ADAU1373 DRC1_CTRL10 REGISTER Address: 0x89, Reset: 0xC0, Name: DRC1_CTRL10 DRC1 Threshold Point Y4 on Y-Axis (Output Level). Table 160. Bit Descriptions for DRC1_CTRL10 Bits [7:0] Bit Name DRCTHY4 Settings 00000000 00000001 00000010 xxxxxxx 11000000 Description DRC1 Y-Axis Threshold 4. 0 dB −0.5 dB −1 dB 0.5 dB step −96 dB (default) DRC1_CTRL11 REGISTER Address: 0x8A, Reset: 0x88, Name: DRC1_CTRL11 DRC1 Gain Smoothing Attack and Decay Time Setting Rev. 0 | Page 200 of 296 Reset 0xC0 Access RW ADAU1373 Table 161. Bit Descriptions for DRC1_CTRL11 Bits [7:4] Bit Name DRCGSATT Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] DRCGSDEC 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DRC1 Gain Smooth Attack Time. 46.875 μs 93.75 μs 187.5 μs 375 μs 750 μs 1.5 ms 3 ms 6 ms 12 ms (default) 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec DRC1 Gain Smooth Decay Time. 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms (default) 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec 12.288 sec 24.576 sec Rev. 0 | Page 201 of 296 Reset 0x8 Access RW 0x8 RW ADAU1373 DRC1_CTRL12 REGISTER Address: 0x8B, Reset: 0x7A, Name: DRC1_CTRL12 DRC1 Noise Gate Hold Time and Normal Operation Hold Time Setting Table 162. Bit Descriptions for DRC1_CTRL12 Bits [7:4] Bit Name DRCHTNOR Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] DRCHTNG 0000 0001 0010 0011 0100 0101 Description DRC1 Hold Time for Normal Operation. 0 ms 0.67 ms 1.34 ms 2.68 ms 5.36 ms 10.72 ms 21.44 ms 42.88 ms (default) 85.76 ms 171.52 ms 341.33 ms 686 ms 1.37 sec Reserved Reserved Reserved DRC1 Hold Time for Noise Gating. 0 ms 0.67 ms 1.34 ms 2.68 ms 5.36 ms 10.72 ms Rev. 0 | Page 202 of 296 Reset 0x7 Access RW 0xA RW ADAU1373 Bits Bit Name Settings 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description 21.44 ms 42.88 ms 85.76 ms 171.52 ms 341.33 ms (default) 686 ms 1.37 sec Reserved Reserved Reserved Reset Access Reset 0x7 Access RW DRC1_CTRL13 REGISTER Address: 0x8C, Reset: 0xDF, Name: DRC1_CTRL13 DRC1 Gain Setting Table 163. Bit Descriptions for DRC1_CTRL13 Bits [5:2] Bit Name DRCG Settings 0000 0001 xxxx 0111 1111 Description DRC1 Adjust Gain. DRC1 gain setting. 21 dB 18 dB 3 dB step size 0 dB (default) −24 dB Rev. 0 | Page 203 of 296 ADAU1373 DRC1_CTRL14 REGISTER Address: 0x8D, Reset: 0x20, Name: DRC1_CTRL14 DRC1 Enable Control Table 164. Bit Descriptions for DRC1_CTRL14 Bits 7 Bit Name DRCNGTGT Settings 0 1 6 DRCNGHDEN 0 1 5 DRCNGSRC 0 1 4 DRCCESRC 0 1 3 DRCLMSRC 0 1 2 DRCNGEN 0 1 [1:0] DRCEN 00 01 10 11 Description DRC1 Noise Gate Recovery Target. Target: DRC minimum output Target: determined by DRC curve DRC1 Noise Gate Recovery Hold Enable. DRC noise gate recovery hold time disable DRC noise gate recovery hold time enable DRC1 Noise Gate Recovery Source. RMS Peak (default) DRC1 Compressor/Expander Source. RMS Peak DRC1 Limiter Source. RMS Peak DRC1 Noise Gating Enable. DRC noise gate disable DRC noise gate enable DRC1 Enable. None (default) Right channel enable Left channel enable Both channels enable Rev. 0 | Page 204 of 296 Reset 0x0 Access RW 0x0 RW 0x1 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DRC1_CTRL15 REGISTER Address: 0x8E, Reset: 0x00, Name: DRC1_CTRL15 DRC1 Peak to RMS Ratio and RMS Detector Setting Register Table 165. Bit Descriptions for DRC1_CTRL15 Bits 7 [6:2] Bit Name RESERVED SIG_DET_RMS Settings 00000 00001 00010 xxxxx 11111 [1:0] SIG_DET_PK 00 01 10 11 Description Reserved. DRC1 IRQ RMS Value. DRC RMS detector setting. −30 dB −31.5 dB −33 dB −1.5 dB step size −76.5 dB DRC1 IRQ Source Ratio Between Peak and RMS. DRC peak to rms ratio setting. 12 dB 18 dB 24 dB 30 dB Rev. 0 | Page 205 of 296 Reset 0x0 0x00 Access RW RW 0x0 RW ADAU1373 DRC1_CTRL16 REGISTER Address: 0x8F, Reset: 0x00, Name: DRC1_CTRL16 DRC1 IRQ Enable/Disable and IRQ Source Selection Setting Register Table 166. Bit Descriptions for DRC1_CTRL16 Bits [7:3] 2 Bit Name RESERVED ALG_NGEN Settings 0 1 1 DRCIRQ_MODE 0 1 0 DRCIRQ_EN 0 1 Description Reserved. Analog Noise Gate Enable. Analog noise gate disable Analog noise gate enable DRC1 IRQ Mode. DRC IRQ source selection setting. DRC IRQ source: rms DRC IRQ source: Peak to rms ratio DRC1 IRQ Enable Control. DRC IRQ enable/disable control. DRC IRQ disable DRC IRQ enable Rev. 0 | Page 206 of 296 Reset 0x00 0x0 Access RW RW 0x0 RW 0x0 RW ADAU1373 DRC2_CTRL1 REGISTER Address: 0x90, Reset: 0x78, Name: DRC2_CTRL1 DRC2 Level Detector Averaging Time and DRC Noise Gate Recovery Time Setting Table 167. Bit Descriptions for DRC2_CTRL1 Bits [7:4] Bit Name DRCNGREC Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] DRCLELTAV 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Description DRC2 Noise Gate Recovery Time. 46.875 μs 93.75 μs 187.5 μs 375 μs 750 μs 1.5 ms 3 ms 6 ms (default) 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec DRC2 RMS Detector Average Time. 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms (default) 384 ms 768 ms Rev. 0 | Page 207 of 296 Reset 0x7 Access RW 0x8 RW ADAU1373 Bits Bit Name Settings 1011 1100 1101 1110 1111 Description 1.536 sec 3.072 sec 6.144 sec 12.288 sec 24.576 sec Reset Access Reset 0x1 Access RW DRC2_CTRL2 REGISTER Address: 0x91, Reset: 0x18, Name: DRC2_CTRL2 DRC2 Attack and Decay Time Setting Table 168. Bit Descriptions for DRC2_CTRL2 Bits [7:4] Bit Name DRCLELATT Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DRC2 Peak Detector Attack Time. 46.875 μs 93.75 μs (default) 187.5 μs 375 μs 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec Rev. 0 | Page 208 of 296 ADAU1373 Bits [3:0] Bit Name DRCLELDEC Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DRC2 Peak Detector Decay Time. 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms (default) 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec 12.288 sec 24.576 sec Reset 0x8 Access RW Reset 0x00 Access RW DRC2_CTRL3 REGISTER Address: 0x92, Reset: 0x00, Name: DRC2_CTRL3 DRC2 Threshold Point X1 on X-Axis (Input Level) Table 169. Bit Descriptions for DRC2_CTRL3 Bits [7:0] Bit Name DRCTHX1 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC2 X-Axis Threshold 1. 0 dB (default) −0.5 dB −1 dB 0.5 dB step size −96 dB Rev. 0 | Page 209 of 296 ADAU1373 DRC2_CTRL4 REGISTER Address: 0x93, Reset: 0x00, Name: DRC2_CTRL4 DRC2 Threshold Point X2 on X-Axis (Input Level) Table 170. Bit Descriptions for DRC2_CTRL4 Bits [7:0] Bit Name DRCTHX2 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC2 X-Axis Threshold 2. 0 dB (default) −0.5 dB −1 dB 0.5 dB step size −96 dB Reset 0x00 Access RW Reset 0x00 Access RW DRC2_CTRL5 REGISTER Address: 0x94, Reset: 0x00, Name: DRC2_CTRL5 DRC2 Threshold Point X3 on X-Axis (Input Level) Table 171. Bit Descriptions for DRC2_CTRL5 Bits [7:0] Bit Name DRCTHX3 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC2 X-Axis Threshold 3. 0 dB (default) −0.5 dB −1 dB 0.5 dB step size −96 dB Rev. 0 | Page 210 of 296 ADAU1373 DRC2_CTRL6 REGISTER Address: 0x95, Reset: 0xC0, Name: DRC2_CTRL6 DRC2 Threshold Point X4 on X-Axis (Input Level) Table 172. Bit Descriptions for DRC2_CTRL6 Bits [7:0] Bit Name DRCTHX4 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC2 X-Axis Threshold 4. 0 dB −0.5 dB −1 dB 0.5 dB step size −96 dB (default) Reset 0xC0 Access RW Reset 0x00 Access RW DRC2_CTRL7 REGISTER Address: 0x96, Reset: 0x00, Name: DRC2_CTRL7 DRC2 Threshold Point Y1 on Y-Axis (Output Level) Table 173. Bit Descriptions for DRC2_CTRL7 Bits [7:0] Bit Name DRCTHY1 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC2 Y-Axis Threshold 1. 0 dB (default) −0.5 dB −1 dB 0.5 dB step size −96 dB Rev. 0 | Page 211 of 296 ADAU1373 DRC2_CTRL8 REGISTER Address: 0x97, Reset: 0x00, Name: DRC2_CTRL8 DRC2 Threshold Point Y2 on Y-Axis (Output Level) Table 174. Bit Descriptions for DRC2_CTRL8 Bits [7:0] Bit Name DRCTHY2 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC2 Y-Axis Threshold 2. 0 dB (default) −0.5 dB −1 dB 0.5 dB step size −96 dB Reset 0x00 Access RW Reset 0x00 Access RW DRC2_CTRL9 REGISTER Address: 0x98, Reset: 0x00, Name: DRC2_CTRL9 DRC2 Threshold Point Y3 on Y-Axis (Output Level) Table 175. Bit Descriptions for DRC2_CTRL9 Bits [7:0] Bit Name DRCTHY3 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC2 Y-Axis Threshold 3. 0 dB (default) −0.5 dB −1 dB 0.5 dB step size −96 dB Rev. 0 | Page 212 of 296 ADAU1373 DRC2_CTRL10 REGISTER Address: 0x99, Reset: 0xC0, Name: DRC2_CTRL10 DRC2 Threshold Point Y4 on Y-Axis (Output Level) Table 176. Bit Descriptions for DRC2_CTRL10 Bits [7:0] Bit Name DRCTHY4 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC2 Y-Axis Threshold 4. 0 dB −0.5 dB −1 dB 0.5 dB step size −96 dB (default) DRC2_CTRL11 REGISTER Address: 0x9A, Reset: 0x88, Name: DRC2_CTRL11 DRC2 Gain Smoothing Attack and Decay Time Setting Rev. 0 | Page 213 of 296 Reset 0xC0 Access RW ADAU1373 Table 177. Bit Descriptions for DRC2_CTRL11 Bits [7:4] Bit Name DRCGSATT Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] DRCGSDEC 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DRC2 Gain Smooth Attack Time. 46.875 μs 93.75 μs 187.5 μs 375 μs 750 μs 1.5 ms 3 ms 6 ms 12 ms (default) 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec DRC Gain Smooth Decay Time. 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms (default) 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec 12.288 sec 24.576 sec Rev. 0 | Page 214 of 296 Reset 0x8 Access RW 0x8 RW ADAU1373 DRC2_CTRL12 REGISTER Address: 0x9B, Reset: 0x7A, Name: DRC2_CTRL12 DRC2 Noise Gate Hold Time and Normal Operation Hold Time Setting Table 178. Bit Descriptions for DRC2_CTRL12 Bits [7:4] Bit Name DRCHTNOR Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] DRCHTNG 0000 0001 0010 0011 0100 0101 Description DRC2 Hold Time for Normal Operation. 0 ms 0.67 ms 1.34 ms 2.68 ms 5.36 ms 10.72 ms 21.44 ms 42.88 ms (default) 85.76 ms 171.52 ms 341.33 ms 686 ms 1.37 sec Reserved Reserved Reserved DRC2 Hold Time for Noise Gating. 0 ms 0.67 ms 1.34 ms 2.68 ms 5.36 ms 10.72 ms Rev. 0 | Page 215 of 296 Reset 0x7 Access RW 0xA RW ADAU1373 Bits Bit Name Settings 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description 21.44 ms 42.88 ms 85.76 ms 171.52 ms 341.33 ms (default) 686 ms 1.37 sec Reserved Reserved Reserved Reset Access Reset 0x7 Access RW DRC2_CTRL13 REGISTER Address: 0x9C, Reset: 0xDF, Name: DRC2_CTRL13 DRC2 Gain Setting Table 179. Bit Descriptions for DRC2_CTRL13 Bits [5:2] Bit Name DRCG Settings 0000 0001 xxxx 0111 1111 Description DRC2 Adjust Gain. DRC2 gain. 21 dB 18 dB 3 dB step size 0 dB (default) −24 dB Rev. 0 | Page 216 of 296 ADAU1373 DRC2_CTRL14 REGISTER Address: 0x9D, Reset: 0x20, Name: DRC2_CTRL14 DRC2 Enable Control Table 180. Bit Descriptions for DRC2_CTRL14 Bits 7 Bit Name DRCNGTGT Settings 0 1 6 DRCNGHDEN 0 1 5 DRCNGSRC 0 1 4 DRCCESRC 0 1 3 DRCLMSRC 0 1 2 DRCNGEN 0 1 [1:0] DRCEN 00 01 10 11 Description DRC2 Noise Gate Recovery Target. Target: DRC minimum output Target: determined by DRC curve DRC2 Noise Gate Recovery Hold Enable. DRC noise gate recovery hold time disable DRC noise gate recovery hold time enable DRC2 Noise Gate Recovery Source. RMS Peak (default) DRC2 Compressor/Expander Source. RMS Peak DRC2 Limiter Source. RMS Peak DRC2 Noise Gating Enable. DRC noise gate disable DRC noise gate enable DRC2 Enable. None (default) Right channel enable Left channel enable Both channels enable Rev. 0 | Page 217 of 296 Reset 0x0 Access RW 0x0 RW 0x1 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DRC2_CTRL15 REGISTER Address: 0x9E, Reset: 0x00, Name: DRC2_CTRL15 DRC2 Peak to RMS Ratio and RMS Detector Setting Register Table 181. Bit Descriptions for DRC2_CTRL15 Bits 7 [6:2] Bit Name RESERVED SIG_DET_RMS Settings 00000 00001 00010 xxxxx 11111 [1:0] SIG_DET_PK 00 01 10 11 Description Reserved. DRC2 IRQ RMS Value. DRC rms detector setting. −30 dB −31.5 dB −33 dB −1.5 dB step size −76.5 dB DRC2 IRQ Source Ratio Between Peak and RMS. DRC peak to rms ratio setting. 12 dB 18 dB 24 dB 30 dB Rev. 0 | Page 218 of 296 Reset 0x0 0x00 Access RW RW 0x0 RW ADAU1373 DRC2_CTRL16 REGISTER Address: 0x9F, Reset: 0x00, Name: DRC2_CTRL16 DRC2 IRQ Enable/Disable and IRQ Source Selection Setting Register Table 182. Bit Descriptions for DRC2_CTRL16 Bits [7:3] 2 Bit Name RESERVED ALG_NGEN Settings Description 0 1 1 DRCIRQ_MODE 0 1 0 DRCIRQ_EN 0 1 Analog Noise Gate Enable. Analog noise gate disable Analog noise gate enable DRC2 IRQ Mode. DRC IRQ source selection setting. DRC IRQ source: rms DRC IRQ source: peak to rms ratio DRC2 IRQ Enable Control. DRC IRQ enable/disable control. DRC IRQ disable DRC IRQ enable Rev. 0 | Page 219 of 296 Reset 0x00 0x0 Access RW RW 0x0 RW 0x0 RW ADAU1373 DRC3_CTRL1 REGISTER Address: 0xA0, Reset: 0x78, Name: DRC3_CTRL1 DRC3 Level Detector Averaging Time and DRC Noise Gate Recovery Time Setting Table 183. Bit Descriptions for DRC3_CTRL1 Bits [7:4] Bit Name DRCNGREC Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] DRCLELTAV 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Description DRC3 Noise Gate Recovery Time. 46.875 μs 93.75 μs 187.5 μs 375 μs 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec DRC3 RMS Detector Average Time. 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms Rev. 0 | Page 220 of 296 Reset 0x7 Access RW 0x8 RW ADAU1373 Bits Bit Name Settings 1011 1100 1101 1110 1111 Description 1.536 sec 3.072 sec 6.144 sec 12.288 sec 24.576 sec Reset Access Reset 0x1 Access RW DRC3_CTRL2 REGISTER Address: 0xA1, Reset: 0x18, Name: DRC3_CTRL2 DRC3 Attack and Decay Time Setting Table 184. Bit Descriptions for DRC3_CTRL2 Bits [7:4] Bit Name DRCLELATT Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DRC3 Peak Detector Attack Time. 46.875 μs 93.75 μs (default) 187.5 μs 375 μs 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec Rev. 0 | Page 221 of 296 ADAU1373 Bits [3:0] Bit Name DRCLELDEC Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DRC3 Peak Detector Decay Time. 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms (default) 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec 12.288 sec 24.576 sec Reset 0x8 Access RW Reset 0x00 Access RW DRC3_CTRL3 REGISTER Address: 0xA2, Reset: 0x00, Name: DRC3_CTRL3 DRC3 Threshold Point X1 on X-Axis (Input Level) Table 185. Bit Descriptions for DRC3_CTRL3 Bits [7:0] Bit Name DRCTHX1 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC3 X-Axis Threshold 1. 0 dB (default) −0.5 dB −1 dB 0.5 dB step −96 dB Rev. 0 | Page 222 of 296 ADAU1373 DRC3_CTRL4 REGISTER Address: 0xA3, Reset: 0x00, Name: DRC3_CTRL4 DRC3 Threshold Point X2 on X-Axis (Input Level) Table 186. Bit Descriptions for DRC3_CTRL4 Bits [7:0] Bit Name DRCTHX2 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC3 X-Axis Threshold 2. 0 dB (default) −0.5 dB −1 dB 0.5 dB step −96 dB Reset 0x00 Access RW Reset 0x00 Access RW DRC3_CTRL5 REGISTER Address: 0xA4, Reset: 0x00, Name: DRC3_CTRL5 DRC3 Threshold Point X3 on X-Axis (Input Level) Table 187. Bit Descriptions for DRC3_CTRL5 Bits [7:0] Bit Name DRCTHX3 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC3 X-Axis Threshold 3. 0 dB (default) −0.5 dB −1 dB 0.5 dB step −96 dB Rev. 0 | Page 223 of 296 ADAU1373 DRC3_CTRL6 REGISTER Address: 0xA5, Reset: 0xC0, Name: DRC3_CTRL6 DRC3 Threshold Point X4 on X-Axis (Input Level) Table 188. Bit Descriptions for DRC3_CTRL6 Bits [7:0] Bit Name DRCTHX4 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC3 X-Axis Threshold 4. 0 dB −0.5 dB −1 dB 0.5 dB step −96 dB (default) Reset 0xC0 Access RW Reset 0x00 Access RW DRC3_CTRL7 REGISTER Address: 0xA6, Reset: 0x00, Name: DRC3_CTRL7 DRC3 Threshold Point Y1 on Y-Axis (Output Level) Table 189. Bit Descriptions for DRC3_CTRL7 Bits [7:0] Bit Name DRCTHY1 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC3 Y-Axis Threshold 1. 0 dB (default) −0.5 dB −1 dB 0.5 dB step −96 dB Rev. 0 | Page 224 of 296 ADAU1373 DRC3_CTRL8 REGISTER Address: 0xA7, Reset: 0x00, Name: DRC3_CTRL8 DRC3 Threshold Point Y2 on Y-Axis (Output Level) Table 190. Bit Descriptions for DRC3_CTRL8 Bits [7:0] Bit Name DRCTHY2 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC3 Y-Axis Threshold 2. 0 dB (default) −0.5 dB −1 dB 0.5 dB step −96 dB Reset 0x00 Access RW Reset 0x00 Access RW DRC3_CTRL9 REGISTER Address: 0xA8, Reset: 0x00, Name: DRC3_CTRL9 DRC3 Threshold Point Y3 on Y-Axis (Output Level) Table 191. Bit Descriptions for DRC3_CTRL9 Bits [7:0] Bit Name DRCTHY3 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC3 Y-Axis Threshold 3. 0 dB (default) −0.5 dB −1 dB 0.5 dB step −96 dB Rev. 0 | Page 225 of 296 ADAU1373 DRC3_CTRL10 REGISTER Address: 0xA9, Reset: 0xC0, Name: DRC3_CTRL10 DRC3 Threshold Point Y4 on Y-Axis (Output Level) Table 192. Bit Descriptions for DRC3_CTRL10 Bits [7:0] Bit Name DRCTHY4 Settings 00000000 00000001 00000010 xxxxxxxx 11000000 Description DRC3 Y-Axis Threshold 4. 0 dB −0.5 dB −1 dB 0.5 dB step −96 dB (default) DRC3_CTRL11 REGISTER Address: 0xAA, Reset: 0x88, Name: DRC3_CTRL11 DRC3 Gain Smoothing Attack and Decay Time Setting Rev. 0 | Page 226 of 296 Reset 0xC0 Access RW ADAU1373 Table 193. Bit Descriptions for DRC3_CTRL11 Bits [7:4] Bit Name DRCGSATT Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] DRCGSDEC 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description DRC3 Gain Smooth Attack Time. 46.875 μs 93.75 μs 187.5 μs 375 μs 750 μs 1.5 ms 3 ms 6 ms 12 ms (default) 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec DRC3 Gain Smooth Decay Time. 750 μs 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms (default) 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec 12.288 sec 24.576 sec Rev. 0 | Page 227 of 296 Reset 0x8 Access RW 0x8 RW ADAU1373 DRC3_CTRL12 REGISTER Address: 0xAB, Reset: 0x7A, Name: DRC3_CTRL12 DRC3 Noise Gate Hold Time and Normal Operation Hold Time Setting Table 194. Bit Descriptions for DRC3_CTRL12 Bits [7:4] Bit Name DRCHTNOR Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] DRCHTNG 0000 0001 0010 0011 0100 0101 Description DRC3 Hold Time for Normal Operation. 0 ms 0.67 ms 1.34 ms 2.68 ms 5.36 ms 10.72 ms 21.44 ms 42.88 ms (default) 85.76 ms 171.52 ms 341.33 ms 686 ms 1.37 sec Reserved Reserved Reserved DRC3 Hold Time for Noise Gating. 0 ms 0.67 ms 1.34 ms 2.68 ms 5.36 ms 10.72 ms Rev. 0 | Page 228 of 296 Reset 0x7 Access RW 0xA RW ADAU1373 Bits Bit Name Settings 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description 21.44 ms 42.88 ms 85.76 ms 171.52 ms 341.33 ms (default) 686 ms 1.37 sec Reserved Reserved Reserved Reset Access Reset 0x7 Access RW DRC3_CTRL13 REGISTER Address: 0xAC, Reset: 0xDF, Name: DRC3_CTRL13 DRC3 Gain Setting Table 195. Bit Descriptions for DRC3_CTRL13 Bits [5:2] Bit Name DRCG Settings 0000 0001 xxxx 0111 1111 Description DRC3 Adjust Gain. DRC3 gain setting. 21 dB 18 dB 3 dB step 0 dB (default) −24 dB Rev. 0 | Page 229 of 296 ADAU1373 DRC3_CTRL14 REGISTER Address: 0xAD, Reset: 0x20, Name: DRC3_CTRL14 DRC3 Enable Control Table 196. Bit Descriptions for DRC3_CTRL14 Bits 7 Bit Name DRCNGTGT Settings 0 1 6 DRCNGHDEN 0 1 5 DRCNGSRC 0 1 4 DRCCESRC 0 1 3 DRCLMSRC 0 1 2 DRCNGEN 0 1 [1:0] DRCEN 00 01 10 11 Description DRC3 Noise Gate Recovery Target. Target: DRC minimum output Target: determined by DRC curve DRC3 Noise Gate Recovery Hold Enable. DRC noise gate recovery hold time disable DRC noise gate recovery hold time enable DRC3 Noise Gate Recovery Source. RMS Peak (default) DRC3 Compressor/Expander Source. RMS Peak DRC3 Limiter Source. RMS Peak DRC3 Noise Gating Enable. DRC noise gate disable DRC noise gate enable DRC3 Enable. None (default) Right channel enable Left channel enable Both channels enable Rev. 0 | Page 230 of 296 Reset 0x0 Access RW 0x0 RW 0x1 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 DRC3_CTRL15 REGISTER Address: 0xAE, Reset: 0x00, Name: DRC3_CTRL15 DRC3 Peak to RMS Ratio and RMS Detector Setting Register Table 197. Bit Descriptions for DRC3_CTRL15 Bits 7 [6:2] Bit Name RESERVED SIG_DET_RMS Settings 00000 00001 00010 xxxxx 11111 [1:0] SIG_DET_PK 00 01 10 11 Description Reserved. DRC3 IRQ RMS Value. DRC rms detector setting. −30 dB −31.5 dB −33 dB −1.5 dB step size −76.5 dB DRC3 IRQ Source Ratio Between Peak and RMS. DRC peak to rms ratio setting. 12 dB 18 dB 24 dB 30 dB Rev. 0 | Page 231 of 296 Reset 0x0 0x00 Access RW RW 0x0 RW ADAU1373 DRC3_CTRL16 REGISTER Address: 0xAF, Reset: 0x00, Name: DRC3_CTRL16 DRC3 IRQ Enable/Disable and IRQ Source Selection Setting Register Table 198. Bit Descriptions for DRC3_CTRL16 Bits [7:3] 2 Bit Name RESERVED ALG_NGEN Settings 0 1 1 DRCIRQ_MODE 0 1 0 DRCIRQ_EN 0 1 Description Reserved. Analog Noise Gate Enable. Analog noise gate disable Analog noise gate enable DRC IRQ Mode. DRC IRQ source selection setting. DRC IRQ source: rms DRC IRQ source: Peak to rms ratio DRC IRQ Enable Control. DRC IRQ enable/disable control. DRC IRQ disable DRC IRQ enable Rev. 0 | Page 232 of 296 Reset 0x00 0x0 Access RW RW 0x0 RW 0x0 RW ADAU1373 MDRC_PRE_FILTER REGISTER Address: 0xB0, Reset: 0x00, Name: MDRC_PRE_FILTER MDRC Low-Pass and High-Pass Filter Setting Table 199. Bit Descriptions for MDRC_PRE_FILTER Bits [7:6] [5:2] Bit Name RESERVED MDRC_HPF Settings 0000 0001 xxxx 1111 [1:0] MDRC_LPF 00 01 10 Description Reserved. MDRC High-Pass Filter Cutoff Frequency. 50 Hz 100 Hz 50 Hz step size 800 Hz MDRC Low-Pass Filter Cutoff Frequency. 4 kHz 8 kHz 20 kHz Reset 0x0 0x0 Access RW RW 0x0 RW Reset 0x0 Access RW 0x0 RW MDRC_SPL_CTRL (SPLITTER FREQUENCIES) REGISTER Address: 0xB1, Reset: 0x00, Name: MDRC_SPL_CTRL MDRC Band Splitting Crossover Frequency Setting Table 200. Bit Descriptions for MDRC_SPL_CTRL Bits [7:4] Bit Name MDRC_CROSS_HIGH Settings 0000 0001 xxxx 1111 [3:0] MDRC_CROSS_LOW 0000 0001 xxxx 1111 Description MDRC Crossover Filter High Band Frequency. 1 kHz 2 kHz 1 kHz step size 16 kHz MDRC Crossover Filter Low Band Frequency. 100 Hz 200 Hz 100 Hz step size 1.6 kHz Rev. 0 | Page 233 of 296 ADAU1373 MDRC_CTRL REGISTER Address: 0xB2, Reset: 0x00, Name: MDRC_CTRL MDRC Enable Setting Table 201. Bit Descriptions for MDRC_CTRL Bits [7:3] 2 Bit Name RESERVED MDRC_LPFEN Settings 0 1 1 MDRC_HPFEN 0 1 0 MDRC_EN 0 1 Description Reserved MDRC Low-Pass Filter Enable. Disable Enable MDRC High-Pass Filter Enable. Disable Enable MDRC Enable. Disable Enable Reset 0x00 0x0 Access RW RW 0x0 RW 0x0 RW Reset 0xFF Access RW PRE_HPF1_COEFH (MSB) REGISTER Address: 0xB3, Reset: 0xFF, Name: PRE_HPF1_COEFH High-Pass Filter 1 Coefficient MSB Table 202. Bit Descriptions for PRE_HPF1_COEFH Bits [7:0] Bit Name PRE_HPF1_COEFH Settings Description Pre-HPF1 Coefficient[10:3]. Rev. 0 | Page 234 of 296 ADAU1373 PRE_HPF1_COEFL (LSB) REGISTER Address: 0xB4, Reset: 0xFF, Name: PRE_HPF1_COEFL High-Pass Filter 1 Coefficient LSB Table 203. Bit Descriptions for PRE_HPF1_COEFL Bits [7:3] [2:0] Bit Name RESERVED PRE_HPF1_COEFL Settings Description Reserved. Pr-HPF1 Coefficient[2:0]. Reset 0x1F 0x7 Access RW RW Reset 0xFF Access RW Reset 0x1F 0x7 Access RW RW PRE_HPF2_COEFH (MSB) REGISTER Address: 0xB5, Reset: 0xFF, Name: PRE_HPF2_COEFH High-Pass Filter 2 Coefficient MSB Table 204. Bit Descriptions for PRE_HPF2_COEFH Bits [7:0] Bit Name PRE_HPF2_COEFH Settings Description Pre-HPF2 Coefficient[10:3]. PRE_HPF2_COEFL (LSB) REGISTER Address: 0xB6, Reset: 0xFF, Name: PRE_HPF2_COEFL High-Pass Filter 2 Coefficient LSB Table 205. Bit Descriptions for PRE_HPF2_COEFL Bits [7:3] [2:0] Bit Name RESERVED PRE_HPF2_COEFL Settings Description Reserved. Pre-HPF2 Coefficient[2:0]. Rev. 0 | Page 235 of 296 ADAU1373 PRE_HPF3_COEFH (MSB) REGISTER Address: 0xB7, Reset: 0xFF, Name: PRE_HPF3_COEFH High-Pass Filter 3 Coefficient MSB Table 206. Bit Descriptions for PRE_HPF3_COEFH Bits [7:0] Bit Name PRE_HPF3_COEFH Settings Description Pre-HPF3 Coefficient[10:3]. Reset 0xFF Access RW Reset 0x1F 0x7 Access RW RW Reset 0xFF Access RW PRE_HPF3_COEFL (LSB) REGISTER Address: 0xB8, Reset: 0xFF, Name: PRE_HPF3_COEFL High-Pass Filter 3 Coefficient LSB Table 207. Bit Descriptions for PRE_HPF3_COEFL Bits [7:3] [2:0] Bit Name RESERVED PRE_HPF3_COEFL Settings Description Reserved. Pre-HPF3 Coefficient[2:0]. PRE_HPF4_COEFH (MSB) REGISTER Address: 0xB9, Reset: 0xFF, Name: PRE_HPF4_COEFH High-Pass Filter 4 Coefficient MSB Table 208. Bit Descriptions for PRE_HPF4_COEFH Bits [7:0] Bit Name PRE_HPF4_COEFH Settings Description Pre-HPF4 Coefficient[10:3]. Rev. 0 | Page 236 of 296 ADAU1373 PRE_HPF4_COEFL (LSB) REGISTER Address: 0xBA, Reset: 0xFF, Name: PRE_HPF4_COEFL High-Pass Filter 4 Coefficient LSB Table 209. Bit Descriptions for PRE_HPF4_COEFL Bits [7:3] [2:0] Bit Name RESERVED PRE_HPF4_COEFL Settings Description Reserved. Pre-HPF4 Coefficient[2:0]. Reset 0x1F 0x7 Access RW RW Reset 0xFF Access RW Reset 0x1F 0x7 Access RW RW PRE_HPF5_COEFH (MSB) REGISTER Address: 0xBB, Reset: 0xFF, Name: PRE_HPF5_COEFH High-Pass Filter 5 Coefficient MSB Table 210. Bit Descriptions for PRE_HPF5_COEFH Bits [7:0] Bit Name PRE_HPF5_COEFH Settings Description Pre-HPF5 Coefficient[10:3]. PRE_HPF5_COEFL (LSB) REGISTER Address: 0xBC, Reset: 0xFF, Name: PRE_HPF5_COEFL High-Pass Filter 5 Coefficient LSB Table 211. Bit Descriptions for PRE_HPF5_COEFL Bits [7:3] [2:0] Bit Name RESERVED PRE_HPF5_COEFL Settings Description Reserved. Pre-HPF5 Coefficient[2:0]. Rev. 0 | Page 237 of 296 ADAU1373 PRE_HPF_CTRL REGISTER Address: 0xBD, Reset: 0x1F, Name: PRE_HPF_CTRL High-Pass Filter 1 Through High-Pass Filter 4 Enable Control Table 212. Bit Descriptions for PRE_HPF_CTRL Bits [7:5] 4 3 2 1 0 Bit Name RESERVED PRE_HPF5_EN PRE_HPF4_EN PRE_HPF3_EN PRE_HPF2_EN PRE_HPF1_EN Settings Description Reserved. Pre-Mix HPF5 Enable. Pre-Mix HPF4 Enable. Pre-Mix HPF3 Enable. Pre-Mix HPF2 Enable. Pre-Mix HPF1 Enable. Rev. 0 | Page 238 of 296 Reset 0x0 0x1 0x1 0x1 0x1 0x1 Access RW RW RW RW RW RW ADAU1373 EQ_CTRL1 REGISTER Address: 0xBE, Reset: 0x00, Name: EQ_CTRL1 Equalizer Control Table 213. Bit Descriptions for EQ_CTRL1 Bits [7:5] 4 Bit Name RESERVED EQ_UPDING Settings 0 1 3 EQ_UPD_CLR 0 1 2 EQ_FORMAT 0 1 1 EQ_UPD 1 0 0 EQ_WR_EN 1 0 Description Reserved. EQ Update Status. Normal EQ updating EQ Update Clear. Equalizer update clear. Normal operation Interrupt coefficient update EQ Coefficient Format Selection. Equalizer coefficient format selection. Default (Q3.13) Large gain (Q4.14) EQ Coefficient Registers Update Flag. Equalizer coefficient registers update status. Update None EQ Coefficient Write/Read Enable. Equalizer coefficient registers update status. W/R enable Disable Rev. 0 | Page 239 of 296 Reset 0x0 0x0 Access RW R 0x0 R 0x0 RW 0x0 R 0x0 RW ADAU1373 EQ_CTRL2 REGISTER Address: 0xBF, Reset: 0x00, Name: EQ_CTRL2 Equalizer Control Table 214. Bit Descriptions for EQ_CTRL2 Bits 7 Bit Name EQEN Settings 0 1 6 EQBP7 0 1 5 EQBP6 0 1 4 EQBP5 0 1 3 EQBP4 0 1 2 EQBP3 0 1 1 EQBP2 0 1 0 EQBP1 0 1 Description EQ Enable. Equalizer enable/disable control. EQ disable EQ enable EQ Band 7 Bypass When EQ Enabled. Equalizer 7 bypass control. No bypass Bypass EQ Band 7 EQ Band 6 Bypass When EQ Enabled. Equalizer 6 bypass control. No bypass Bypass EQ Band 6 EQ Band 5 Bypass When EQ Enabled. Equalizer 5 bypass control. No bypass Bypass EQ Band 5 EQ Band 4 Bypass When EQ Enabled. Equalizer 4 bypass control. No bypass Bypass EQ Band 4 EQ Band 3 Bypass When EQ Enabled. Equalizer 3 bypass control. No bypass Bypass EQ Band 3 EQ Band 2 Bypass When EQ Enabled. Equalizer 2 bypass control. No bypass Bypass EQ Band 2 EQ Band 1 Bypass When EQ Enabled. Equalizer 1 bypass control. No bypass Bypass EQ Band 1 Rev. 0 | Page 240 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 E3D_CTRL1 REGISTER Address: 0xC0, Reset: 0x00, Name: E3D_CTRL1 3D Enhancement Control Register Table 215. Bit Descriptions for E3D_CTRL1 Bits [7:4] Bit Name E3D_LEVEL Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] E3D_ALPHA 0000 0001 0010 0011 0100 0101 0110 Description 3D Enhancement Level Control. 3D effect level setting for 3D enhancement. 0%; no 3D effect 6.67% 13.33% 20% 26.67% 33.33% 40% 46.67% 53.33% 60% 66.67% 73.33% 80% 86.67% 93.33% 100% 3D Enhancement Depth Control. Filter cutoff frequency setting for 3D enhancement. No 3D effect 1.5 kHz at 48 kHz sampling rate 2.2 kHz at 48 kHz sampling rate 3.6 kHz at 48 kHz sampling rate 5.5 kHz at 48 kHz sampling rate 8.1 kHz at 48 kHz sampling rate 13 kHz at 48 kHz sampling rate Rev. 0 | Page 241 of 296 Reset 0x0 Access RW 0x0 RW ADAU1373 E3D_CTRL2 REGISTER Address: 0xC1, Reset: 0x00, Name: E3D_CTRL2 3D Enhancement Control Register Table 216. Bit Descriptions for E3D_CTRL2 Bits [7:4] [3:1] Bit Name RESERVED E3D_GAIN Settings 000 001 010 011 100 101 110 111 0 E3D_EN 0 1 Description Reserved. 3D Enhancement Gain Setting. E3D Gain: 1 0.125 0.25 0.375 0.5 0.625 0.75 0.875 3D Enhancement Enable. 3D enhancement enable/disable control. Enhancement disable Enhancement enable Rev. 0 | Page 242 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW ADAU1373 ALC_CTRL0 REGISTER Address: 0xC2, Reset: 0x00, Name: ALC_CTRL0 ALC Control Register Table 217. Bit Descriptions for ALC_CTRL0 Bits [7:4] Bit Name ALCTAV Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 [3:0] ALCHLD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Description ALC RMS Estimate Time. ALC average time setting for rms value estimation. 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec ALC Hold Time. ALC recovery hold time. 0 ms 2.67 ms 5.34 ms 10.68 ms 21.36 ms 42.72 ms 85.44 ms 170.88 ms 341.76 ms 683.52 ms 1.367 sec 2.734 sec 5.468 sec Rev. 0 | Page 243 of 296 Reset 0x0 Access RW 0x0 RW ADAU1373 ALC_CTRL1 REGISTER Address: 0xC3, Reset: 0x00, Name: ALC_CTRL1 ALC Control Register Table 218. Bit Descriptions for ALC_CTRL1 Bits [7:4] Bit Name ALCATT Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] ALCREC 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Description ALC Attack Time. ALC attack time setting. 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec 6.144 sec 6.144 sec 6.144 sec ALC Recovery Time. ALC recovery time setting. 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec 3.072 sec Rev. 0 | Page 244 of 296 Reset 0x0 Access RW 0x0 RW ADAU1373 Bits [3:0] Bit Name ALCREC Settings 1010 1011 1100 1101 1110 1111 Description 6.144 sec 12.288 sec 24.576 sec 24.576 sec 24.576 sec 24.576 sec Reset Access Reset 0x0 Access RW ALC_CTRL2 REGISTER Address: 0xC4, Reset: 0x00, Name: ALC_CTRL2 ALC Control Register Table 219. Bit Descriptions for ALC_CTRL2 Bits [7:4] Bit Name ALCLVL Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description ALC Peak Limiter Threshold. ALC peak limiter threshold level setting. −22.5 dBFS −21 dBFS −19.5 dBFS −18 dBFS −16.5 dBFS −15 dBFS −13.5 dBFS −12 dBFS −10.5 dBFS −9 dBFS −7.5 dBFS −6 dBFS −4.5 dBFS −3 dBFS −1.5 dBFS 0 dBFS Rev. 0 | Page 245 of 296 ADAU1373 Bits [3:0] Bit Name ALCREF Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description ALC Target Level. ALC reference level setting. −24 dBFS −22.5 dBFS −21 dBFS −19.5 dBFS −18 dBFS −16.5 dBFS −15 dBFS −13.5 dBFS −12 dBFS −10.5 dBFS −9 dBFS −7.5 dBFS −6 dBFS −4.5 dBFS −3 dBFS −1.5 dBFS Reset 0x0 Access RW Reset 0x0 Access RW ALC_CTRL3 REGISTER Address: 0xC5, Reset: 0x00, Name: ALC_CTRL3 ALC Control Register Table 220. Bit Descriptions for ALC_CTRL3 Bits [7:4] Bit Name ALCRIP Settings 0000 0001 0010 0011 0100 0101 0110 Description ALC Reference Ripple Remove. ALC ripple level setting. The setting, with respect to reference level, defines the input level range in which there can be no change in ALC gain. 0 dB −0.5 dB −1.0 dB −1.5 dB −2.0 dB −2.5 dB −3.0 dB Rev. 0 | Page 246 of 296 ADAU1373 Bits Bit Name [3:0] ALCMAX Settings 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Description −3.5 dB −4.0 dB −4.5 dB −5.0 dB −5.5 dB −6.0 dB −6.5 dB −7.0 dB −7.5 dB ALC Maximum Gain Control. ALC maximum gain setting. 60 dB 54 dB 48 dB 42 dB 36 dB 30 dB 24 dB 18 dB 12 dB 6 dB 0 dB −6 dB −12 dB ALC_CTRL4 REGISTER Address: 0xC6, Reset: 0x00, Name: ALC_CTRL4 ALC Control Register Rev. 0 | Page 247 of 296 Reset Access 0x0 RW ADAU1373 Table 221. Bit Descriptions for ALC_CTRL4 Bits [7:4] Bit Name ALCNGTH Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] ALCNGHLD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Description ALC Noise Gate Threshold. ALC noise gate threshold level setting. −81 dBFS −78 dBFS −75 dBFS −72 dBFS −69 dBFS −66 dBFS −63 dBFS −60 dBFS −57 dBFS −54 dBFS −51 dBFS −48 dBFS −45 dBFS −42 dBFS −39 dBFS −36 dBFS ALC Noise Gate Hold Time. The ALC holds the gain for the set time when input level is below noise gate threshold. 0 ms 2.67 ms 5.33 ms 10.67 ms 21.33 ms 42.67 ms 85.33 ms 170.67 ms 341.33 ms 682.67 ms 1.365 sec 2.730 sec 5.460 sec Rev. 0 | Page 248 of 296 Reset 0x0 Access RW 0x0 RW ADAU1373 ALC_CTRL5 REGISTER Address: 0xC7, Reset: 0x00, Name: ALC_CTRL5 ALC Control Register Table 222. Bit Descriptions for ALC_CTRL5 Bits [7:4] Bit Name ALCNGATT Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] ALCNGREC 0000 0001 0010 0011 0100 0101 0110 Description ALC Noise Gate Attack Time. Valid only when NGMODE set to 10 or 11. ALC noise gate attack time setting. This setting is valid only in Noise Gate Mode 2 and Noise Gate Mode 3. 6 ms 12 ms 24 ms 48 ms 96 ms 192 ms 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec 12.288 sec 24.576 sec 24.576 sec 24.576 sec 24.576 sec ALC Noise Gate Recovery Time. Valid only when NGMODE set to 11. ALC noise gate recovery time setting. This setting is valid only in Noise Gate Mode 3. 1.5 ms 3 ms 6 ms 12 ms 24 ms 48 ms 96 ms Rev. 0 | Page 249 of 296 Reset 0x0 Access RW 0x0 RW ADAU1373 Bits Bit Name Settings 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description 192 ms 384 ms 768 ms 1.536 sec 3.072 sec 6.144 sec 6.144 sec 6.144 sec 6.144 sec Reset Rev. 0 | Page 250 of 296 Access ADAU1373 ALC_CTRL6 REGISTER Address: 0xC8, Reset: 0x00, Name: ALC_CTRL6 ALC Control Register Table 223. Bit Descriptions for ALC_CTRL6 Bits 7 Bit Name HLDRST Settings 1 0 6 ALCHPF 1 0 [5:4] NGMODE 00 01 10 11 [3:2] ALCEN 00 01 10 11 [1:0] ALCMODE 00 01 10 11 Description Recovery Hold Time Counter Clear Control. Noise gate reset hold time setting. The noise gate is not reset for the hold time set in Register 0xC6. Hold time reset after noise gate Hold time no reset after noise gate ALC Embedded High-Pass Filter Enable. ALC high-pass filter enable/disable setting. The high-pass filter is fixed at 3.7 Hz at a 48 kHz sample rate. High-pass filter enable High-pass filter disable ALC Noise Gate Mode. ALC noise gate mode selection: Noise Gate Mode 1, Noise Gate Mode 2, Noise Gate Mode 3, or disable noise gate. No noise gate Noise Gate Mode 1; keeps the gain before ALC enters noise gate Noise Gate Mode 2; sets the PGA gain to 0 dB Noise Gate Mode 3; mutes the ALC output to −120 dB ALC Enable Control. ALC enable/disable control. Both channels disabled Right channel enabled Left channel enabled Both channels enabled ALC Operation Mode Control. ALC can be applied to digital/analog PGA or both by setting this register. Control digital PGA Control analog PGA Control both analog/digital PGA No use Rev. 0 | Page 251 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 FDSP_SEL1 REGISTER Address: 0xDC, Reset: 0x00, Name: FDSP_SEL1 DSP Datapath Selection Control Register Table 224. Bit Descriptions for FDSP_SEL1 Bits 7 [6:4] Bit Name RESERVED DRC3_SEL Settings 000 001 010 011 100 101 3 [2:0] RESERVED DRC2_SEL 000 001 010 011 100 101 Description Reserved. DRC3 Datapath Selection. EQ datapath selection. None Datapath 1 Datapath 2 Datapath 3 Datapath 4 Datapath 5 Reserved. DRC2 Datapath Selection. DRC datapath selection. None Datapath 1 Datapath 2 Datapath 3 Datapath 4 Datapath 5 Rev. 0 | Page 252 of 296 Reset 0x0 0x0 Access RW RW 0x0 0x0 RW RW ADAU1373 FDSP_SEL2 REGISTER Address: 0xDD, Reset: 0x00, Name: FDSP_SEL2 DSP Datapath Selection Control Register Table 225. Bit Descriptions for FDSP_SEL2 Bits 7 [6:4] Bit Name RESERVED EQ_SEL Settings 000 001 010 011 100 101 3 [2:0] RESERVED DRC1_SEL 000 001 010 011 100 101 Description Reserved. EQ Datapath Selection. None Datapath 1 Datapath 2 Datapath 3 Datapath 4 Datapath 5 Reserved. DRC1 Datapath Selection. None Datapath 1 Datapath 2 Datapath 3 Datapath 4 Datapath 5 Rev. 0 | Page 253 of 296 Reset 0x0 0x0 Access RW RW 0x0 0x0 RW RW ADAU1373 FDSP_SEL3 REGISTER Address: 0xDE, Reset: 0x00, Name: FDSP_SEL3 DSP Datapath Selection Control Register Table 226. Bit Descriptions for FDSP_SEL3 Bits 7 [6:4] Bit Name RESERVED E3D_SEL Settings 000 001 010 011 100 101 3 [2:0] RESERVED HPF_SEL 000 001 010 011 100 101 Description Reserved. E3D Datapath Selection. 3D enhancement datapath selection. None Datapath 1 Datapath 2 Datapath 3 Datapath 4 Datapath 5 Reserved. High-Pass Filter Datapath Selection. None Datapath 1 Datapath 2 Datapath 3 Datapath 4 Datapath 5 Rev. 0 | Page 254 of 296 Reset 0x0 0x0 Access RW RW 0x0 0x0 RW RW ADAU1373 FDSP_SEL4 REGISTER Address: 0xDF, Reset: 0x00, Name: FDSP_SEL4 DSP Datapath Selection Control Register Table 227. Bit Descriptions for FDSP_SEL4 Bits 7 [6:4] Bit Name RESERVED BASS_EN_SEL Settings 000 001 010 011 100 101 3 ALC_4CHEN 0 1 [2:0] ALC_SEL 000 001 010 011 100 101 Description Reserved. Bass Enhancement Datapath Selection. None Datapath 1 Datapath 2 Datapath 3 Datapath 4 Datapath 5 ALC 4 Channel Input Enable. ALC 4 channel input enable/disable control. Disable Enable ALC Datapath Selection. None Datapath 1 Datapath 2 Datapath 3 Datapath 4 Datapath 5 Rev. 0 | Page 255 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW ADAU1373 PBALPCTRL1 REGISTER Address: 0xE0, Reset: 0x00, Name: PBALPCTRL1 DAC1 Playback Power Control Register Table 228. Bit Descriptions for PBALPCTRL1 Bits 7 Bit Name PBALPANA Settings 0 1 [6:3] PBALPWL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Playback Module A Low Power Control Mode. Playback Module A low power control mode. Only digital DAC and digital Playback Module A Monitor Word Length Select. Playback Module A monitor word length select. 18 bit (default) 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit Rev. 0 | Page 256 of 296 Reset 0x0 Access RW 0x0 RW ADAU1373 Bits [2:1] Bit Name PBALPMODE Settings 00 01 10 11 0 PBALPEN 0 1 Description Playback Module A Low Power Control Mode Channel Select. Playback Module A low power control mode channel select. Left channel and right channel (default) Only left channel Only right channel Left channel or right channel Playback Module A Low Power Control Mode Enable. Playback Module A low power control mode enable. Disable (default) Enable Reset 0x0 Access RW 0x0 RW Reset 0x0 Access RW 0x0 RW PBBLPCTRL2 REGISTER Address: 0xE1, Reset: 0x00, Name: PBBLPCTRL2 DAC2 Playback Power Control Register Table 229. Bit Descriptions for PBBLPCTRL2 Bits 7 Bit Name PBBLPANA Settings 0 1 [6:3] PBBLPWL 0000 0001 0010 0011 0100 0101 0110 0111 Description Playback Module B Low Power Control Mode. Playback Module B low power control mode. Digital only Digital and DAC Playback Module B Monitor Word Length Select. Playback Module B monitor word length select. 18 bit (default) 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit Rev. 0 | Page 257 of 296 ADAU1373 Bits Bit Name [2:1] PBBLPMODE Settings 1000 1001 1010 1011 1100 1101 1110 1111 00 01 10 11 0 PBBLPEN 0 1 Description 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit Playback Module B Low Power Control Mode Channel Select. Playback Module B low power control mode channel select. Left channel and right channel (default) Only left channel Only right channel Left channel or right channel Playback Module B Low Power Control Mode Enable. Playback Module B low power control mode enable. Disable (default) Enable Rev. 0 | Page 258 of 296 Reset Access 0x0 RW 0x0 RW ADAU1373 DIGMICCTRL REGISTER Address: 0xE2, Reset: 0x00, Name: DIGMICCTRL Digital Microphone Control Register Table 230. Bit Descriptions for DIGMICCTRL Bits 7 Bit Name MICLRMODE Settings 0 1 [6:4] DMICPOLSWAP 000 001 010 011 100 101 110 111 3 DMICBLRSWAP 0 1 2 DIGMICBEN 0 1 1 DMICALRSWAP 0 1 Description Digital Microphone 1_2 and Digital Microphone 3_4 Co-Input Working Mode. When enabled, uses DMIC1 from DMIC1_2_DATA pin and DMIC3 from DMIC3_4_DATA pin as two mono inputs to decimator. Stereo input to decimator (default) Two mono inputs to decimator Input Data Polarity Inversion. Use to invert the input data polarity. No change (default) DMIC3_4_DATA left/right polarity invert DMIC1_2_DATA left/right polarity invert DMIC1_2_DATA left and DMIC3_4_DATA left polarity invert DMIC3_4_DATA left polarity invert DMIC1_2_DATA left polarity invert DMIC1_2_DATA left/right and DMIC3_4_DATA left polarity invert DMIC1_2_DATA left and DMIC3_4_DATA left/right polarity invert Digital Microphone 3 and 4 Data Input Left Channel/Right Channel Swap. No swap (default) Swap Enable/Disable Control for DMIC3_4_DATA Pin (Ball E6). Disable (default) Enable Digital Microphone 1 and 2 Data Input Left Channel/Right Channel Swap. No swap (default) Swap Rev. 0 | Page 259 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 Bits 0 Bit Name DIGMICAEN Settings 0 1 Description Enable/Disable Control for DMIC1_2_DATA Pin (Ball B4). Shares the decimator with the ADC so that, when enabled, Digital Microphone 1 and 2 data is input into the decimator. The ADC output is disabled. Disable (default) Enable Reset 0x0 Access RW Reset 0x0 Access RW 0x0 RW GPIOSEL1 REGISTER Address: 0xE3, Reset: 0x00, Name: GPIOSEL1 GPIO Configuration Control Register Table 231. Bit Descriptions for GPIOSEL1 Bits [7:4] Bit Name GPIO2SEL Settings 0000 0001 0010 0011 0100 0101 0110 [3:0] GPIO1SEL 0000 0001 0010 0011 0100 0101 0110 Description GPIO2 Function Select. GPIO2 as PLL reference clock input GPIO2 as analog 8 MHz clock output GPIO2 as IRQ GPIO2 as MCLK1 output GPIO2 as MCLK2 output GPIO2 as output high GPIO2 as output low GPIO1 Function Select. GPIO1 as PLL reference clock input (default) GPIO1 as analog 8 MHz clock output GPIO1 as IRQ GPIO1 as MCLK1 output GPIO1 as MCLK2 output GPIO1 as output high GPIO1 as output low Rev. 0 | Page 260 of 296 ADAU1373 GPIOSEL2 REGISTER Address: 0xE4, Reset: 0x00, Name: GPIOSEL2 GPIO Configuration Control Register Table 232. Bit Descriptions for GPIOSEL2 Bits [7:4] Bit Name GPIO4SEL Settings 0000 0001 0010 0011 0100 0101 0110 [3:0] GPIO3SEL 0000 0001 0010 0011 0100 0101 0110 Description GPIO4 Function Select. GPIO4 as PLL reference clock input GPIO4 as analog 8 m clk out GPIO4 as IRQ GPIO4 as MCLK1 out GPIO4 as MCLK2 out GPIO4 as output high GPIO4 as output low GPIO3 Function Select. GPIO3 as PLL reference clock input (default) GPIO3 as analog 8 m clk out GPIO3 as IRQ GPIO3 as MCLK1 out GPIO3 as MCLK2 out GPIO3 as output high GPIO3 as output low Rev. 0 | Page 261 of 296 Reset 0x0 Access RW 0x0 RW ADAU1373 IRQ_MASK REGISTER Address: 0xE5, Reset: 0x00, Name: IRQ_MASK Interrupt Mask Control Register Table 233. Bit Descriptions for IRQ_MASK Bits 7 Bit Name ASRCC_IRQ_MASK Settings 0 1 6 ASRCB_IRQ_MASK 0 1 5 ASRCA_IRQ_MASK 0 1 4 DRC_IRQ_MASK 0 1 3 PLL_UNLOCK_MASK 0 1 2 HP_CFG_MASK 0 1 1 HP_DECT_MASK 0 1 0 AFAULT_MASK 0 1 Description Mask the IRQ of ASRCC. Interrupt mask setting for ASRCC. Mask (default) No mask Mask the IRQ of ASRCB. Interrupt mask setting for ASRCB. Mask (default) No mask Mask the IRQ of ASRCA. Interrupt mask setting for ASRCA. Mask (default) No mask Mask the IRQ of DRC IRQ. Interrupt mask setting for DRC IRQ. Mask (default) No mask Mask the IRQ of PLL_UNLOCK. Interrupt mask setting for PLL unlock. Mask (default) No mask Mask the IRQ of Headphone Setting Change. Interrupt mask setting for headphone setting change. Mask (default) No mask Mask the IRQ of Headphone Detect. Interrupt mask setting for headphone fault. Mask (default) No mask Mask the IRQ of Analog Fault. Interrupt mask setting for analog fault. Mask (default) No mask Rev. 0 | Page 262 of 296 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 IRQ_RAW REGISTER Address: 0xE6, Reset: 0x02, Name: IRQ_RAW Interrupt Status Register Table 234. Bit Descriptions for IRQ_RAW Bits 7 Bit Name ASRCC_IRQ_RAW_STATE Settings 0 1 6 ASRCB_IRQ_RAW_STATE 0 1 5 ASRCA_IRQ_RAW_STATE 0 1 4 DRC_IRQ_RAW_STATE 0 1 3 PLL_UNLOCK_RAW_STATE 0 1 2 HP_CFG_RAW_STATE 0 1 1 HP_DECT_RAW_STATE 0 1 0 AFAULT_RAW_STATE 0 1 Description Raw State of ASRCC_IRQ. Raw status of ASRCC. Normal Fault Raw State of ASRCB_IRQ. Raw status of ASRCB. Normal Fault Raw State of ASRCA_IRQ. Raw status of ASRCA. Normal Fault Raw State of DRC_IRQ. Raw status of DRC IRQ. Normal ADC clip Raw State of PLL_UNLOCK. Raw status of PLL unlock. Normal Unlock Raw State of Headphone Setting Change. Raw status of headphone setting fault. Normal Changed Raw State of Headphone Detect. Raw status of headphone fault. Normal Changed Raw State of Analog Fault. Raw status of analog fault. Normal Fault Rev. 0 | Page 263 of 296 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x1 R 0x0 R ADAU1373 IRQ_STATE (AFTER MASK) REGISTER Address: 0xE7, Reset: 0x00, Name: IRQ_STATE Interrupt Request State Register Table 235. Bit Descriptions for IRQ_STATE Bits 7 Bit Name ASRCC_IRQ_STATUS Settings 0 1 6 ASRCB_IRQ_STATUS 0 1 5 ASRCA_IRQ_STATUS 0 1 4 DRC_IRQ_STATUS 0 1 3 PLL_UNLOCK_STATUS 0 1 2 HP_CFG_STATUS 0 1 1 HP_DECT_STATUS 0 1 0 AFAULT_STATUS 0 1 Description ASRCC_IRQ State After Mask. ASRCC interrupt. Normal Fault ASRCB_IRQ State After Mask. ASRCB interrupt. Normal Fault ASRCA_IRQ State After Mask. ASRCA interrupt. Normal Fault DRC IRQ State After Mask. DRC interrupt. Normal Fault PLL_UNLOCK IRQ State After Mask. PLL unlock interrupt. Normal Fault Headphone Setting Change IRQ State After Mask. Headphone setting change interrupt. Normal Changed Headphone Detect IRQ State After Mask. Headphone fault interrupt. Normal Changed Analog Fault IRQ State After Mask. Analog fault interrupt. Normal Fault Rev. 0 | Page 264 of 296 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R ADAU1373 IRQEN REGISTER Address: 0xE8, Reset: 0x00, Name: IRQEN Interrupt Request Enable/Disable Register Table 236. Bit Descriptions for IRQEN Bits [7:1] 0 Bit Name RESERVED IRQEN Settings 0 1 Description Reserved. Interrupt Gen Enable. Interrupt request enable/disable control. Disable (default) Enable Reset 0x0 0x0 Access RW RW Reset 0x0 0x0 Access RW RW 0x1 RW PAD_CTRL1 REGISTER Address: 0xE9, Reset: 0x1F, Name: PAD_CTRL1 Pin Drive Capability Control Register Table 237. Bit Descriptions for PAD_CTRL1 Bits [7:6] 5 Bit Name RESERVED I2CFILTER_BYPASS Settings 0 1 4 I2CDRV 0 1 Description Reserved. I2C Pad Filter Bypass. I2C pad filter enable/disable control. Using I2C filter (default) Bypass Driving ability of I2C. Driving ability setting for I2C clock and data. Low High (default) Rev. 0 | Page 265 of 296 ADAU1373 Bits 3 Bit Name DMICCLKDRV Settings 0 1 2 CDRV 0 1 1 BDRV 0 1 0 ADRV 0 1 Description Driving Ability of DMIC CLOCK. Driving ability setting for digital microphone clock. Low High (default) Driving Ability of Audio Interface C. Driving ability setting of Audio Interface C. Low High (default) Driving Ability of Audio Interface B. Driving ability setting of Audio Interface B. Low High (default) Driving Ability of Audio Interface A. Driving ability setting of Audio Interface A. Low High (default) Reset 0x1 Access RW 0x1 RW 0x1 RW 0x1 RW Reset 0x0 0x1 Access RW RW 0x1 RW 0x1 RW 0x1 RW PAD_CTRL2 REGISTER Address: 0xEA, Reset: 0x0F, Name: PAD_CTRL2 Pin Drive Capability Control Register Table 238. Bit Descriptions for PAD_CTRL2 Bits [7:4] 3 Bit Name RESERVED GPIO4DRV Settings 0 1 2 GPIO3DRV 0 1 1 GPIO2DRV 0 1 0 GPIO1DRV 0 1 Description Reserved. Driving Ability of GPIO4. Driving ability setting for GPIO4. Low High (default) Driving Ability of GPIO3. Driving ability setting for GPIO3. Low High (default) Driving Ability of GPIO2. Driving ability setting for GPIO2. Low High (default) Driving Ability of GPIO1. Driving ability setting for GPIO1. Low High (default) Rev. 0 | Page 266 of 296 ADAU1373 DIGEN REGISTER Address: 0xEB, Reset: 0x00, Name: DIGEN Pin Drive Capability Control Register Table 239. Bit Descriptions for DIGEN Bits [7:5] 4 Bit Name RESERVED FDSPEN Settings 0 1 3 DRECEN 0 1 2 RECEN 0 1 1 PBBEN 0 1 0 PBAEN 0 1 Description Reserved. FDSP Engine Enable. Disable (default) Enable Digital Microphone Recording Engine Enable. Used to enable the Digital Microphone 3 and 4 data (DMIC3_4_DATA pin) to DSP. Disable (default) Enable Codec Recording Engine Enable. Used to enable the codec recording engine or Digital Microphone 1 and 2 data (DMIC1_2_DATA pin) to DSP. Disable (default) Enable Codec Playback Engine B Enable. Disable (default) Enable Codec Playback Engine A Enable. Disable (default) Enable Rev. 0 | Page 267 of 296 Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW ADAU1373 LPCNTCTRL (LOW POWER CONTROL COUNTER) REGISTER Address: 0xEC, Reset: 0x00, Name: LPCNTCTRL Low Power Control Counter Table 240. Bit Descriptions for LPCNTCTRL Bits [7:4] Bit Name LPC_B_CNT Settings 0000 0001 0010 0011 0100 0101 0110 0111 [3:0] LPC_A_CNT 0000 0001 0010 0011 0100 0101 0110 0111 Description Low Power Control B Counter. 256 samples 512 samples 1024 samples 2048 samples 4096 samples 8192 samples 16384 samples 32768 samples Low Power Control A Counter. 256 samples 512 samples 1024 samples 2048 samples 4096 samples 8192 samples 16384 samples 32768 samples Reset 0x0 Access RW 0x0 RW Reset 0x13 Access R CHIP_ID_HI REGISTER Address: 0xED, Reset: 0x13, Name: CHIP_ID_HI Chip Identification Register High Byte Table 241. Bit Descriptions for CHIP_ID_HI Bits [7:0] Bit Name CHIP_ID_HI Settings 00010011 Description Chip ID for ADAU1373_REVB. Chip identification register high byte. 13 (first two digits of the part number) Rev. 0 | Page 268 of 296 ADAU1373 CHIP_ID_MID REGISTER Address: 0xEE, Reset: 0x73, Name: CHIP_ID_MID Chip Identification Register Middle Byte Table 242. Bit Descriptions for CHIP_ID_MID Bits [7:0] Bit Name CHIP_ID_MID Settings 01110011 Description Chip ID for ADAU1373_REVB. Chip Identification register middle byte. 73 (last two digits of the part number) Reset 0x73 Access R Reset 0x0B Access R Reset 0x00 Access RW CHIP_ID_LOW REGISTER Address: 0xEF, Reset: 0x0B, Name: CHIP_ID_LO Chip Identification Register Low Byte Table 243. Bit Descriptions for CHIP_ID_LO Bits [7:0] Bit Name CHIP_ID_LOW Settings 00001011 Description Chip ID for ADAU1373_REVB. Chip identification register lower byte. 0B (die revision) SOFT_RESET REGISTER Address: 0xFF, Reset: 0x00, Name: SOFT_RESET Software Reset Register Table 244. Bit Descriptions for SOFT_RESET Bits [7:0] Bit Name SOFT_RST Settings Description Software Reset Register. Write 0x00 to reset all registers. Rev. 0 | Page 269 of 296 ADAU1373 REGISTER MAP—EQ COEFFICIENTS Table 245 shows the register map for seven-band EQ coefficients. Register 0x80 through Register 0xBD should be used for programming the EQ coefficients. Register addresses are in hexadecimal format. Table 245. EQ Register Summary Reg. 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 Name EQ1_COEF0_HI EQ1_COEF0_LO EQ1_COEF1_HI EQ1_COEF1_LO EQ1_COEF2_HI EQ1_COEF2_LO EQ1_COEF3_HI EQ1_COEF3_LO EQ1_COEF4_HI EQ1_COEF4_LO EQ2_COEF0_HI EQ2_COEF0_LO EQ2_COEF1_HI EQ2_COEF1_LO EQ2_COEF2_HI EQ2_COEF2_LO EQ2_COEF3_HI EQ2_COEF3_LO EQ2_COEF4_HI EQ2_COEF4_LO EQ3_COEF0_HI EQ3_COEF0_LO EQ3_COEF1_HI EQ3_COEF1_LO EQ3_COEF2_HI EQ3_COEF2_LO EQ3_COEF3_HI EQ3_COEF3_LO EQ3_COEF4_HI EQ3_COEF4_LO EQ4_COEF0_HI EQ4_COEF0_LO EQ4_COEF1_HI EQ4_COEF1_LO EQ4_COEF2_HI EQ4_COEF2_LO EQ4_COEF3_HI EQ4_COEF3_LO EQ4_COEF4_HI EQ4_COEF4_LO EQ5_COEF0_HI EQ5_COEF0_LO EQ5_COEF1_HI EQ5_COEF1_LO EQ5_COEF2_HI EQ5_COEF2_LO EQ5_COEF3_HI EQ5_COEF3_LO EQ5_COEF4_HI EQ5_COEF4_LO EQ6_COEF0_HI EQ6_COEF0_LO EQ6_COEF1_HI EQ6_COEF1_LO EQ6_COEF2_HI EQ6_COEF2_LO Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 EQ1_COEF0_HI EQ1_COEF0_LO EQ1_COEF1_HI EQ1_COEF1_LO EQ1_COEF2_HI EQ1_COEF2_LO EQ1_COEF3_HI EQ1_COEF3_LO EQ1_COEF4_HI EQ1_COEF4_LO EQ2_COEF0_HI EQ2_COEF0_LO EQ2_COEF1_HI EQ2_COEF1_LO EQ2_COEF2_HI EQ2_COEF2_LO EQ2_COEF3_HI EQ2_COEF3_LO EQ2_COEF4_HI EQ2_COEF4_LO EQ3_COEF0_HI EQ3_COEF0_LO EQ3_COEF1_HI EQ3_COEF1_LO EQ3_COEF2_HI EQ3_COEF2_LO EQ3_COEF3_HI EQ3_COEF3_LO EQ3_COEF4_HI EQ3_COEF4_LO EQ4_COEF0_HI EQ4_COEF0_LO EQ4_COEF1_HI EQ4_COEF1_LO EQ4_COEF2_HI EQ4_COEF2_LO EQ4_COEF3_HI EQ4_COEF3_LO EQ4_COEF4_HI EQ4_COEF4_LO EQ5_COEF0_HI EQ5_COEF0_LO EQ5_COEF1_HI EQ5_COEF1_LO EQ5_COEF2_HI EQ5_COEF2_LO EQ5_COEF3_HI EQ5_COEF3_LO EQ5_COEF4_HI EQ5_COEF4_LO EQ6_COEF0_HI EQ6_COEF0_LO EQ6_COEF1_HI EQ6_COEF1_LO EQ6_COEF2_HI EQ6_COEF2_LO Rev. 0 | Page 270 of 296 Bit 2 Bit 1 Bit 0 Reset 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW MMRW ADAU1373 Reg. 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD Name EQ7_COEF0_HI EQ7_COEF0_LO EQ7_COEF1_HI EQ7_COEF1_LO EQ7_COEF2_HI EQ7_COEF2_LO Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 EQ7_COEF0_HI EQ7_COEF0_LO EQ7_COEF1_HI EQ7_COEF1_LO EQ7_COEF2_HI EQ7_COEF2_LO Bit 2 Bit 1 Bit 0 Reset 0x00 0x00 0x00 0x00 0x00 0x00 RW MMRW MMRW MMRW MMRW MMRW MMRW EQ1_COEF0_HI REGISTER Address: 0x80, Reset: 0x00, Name: EQ1_COEF0_HI Equalizer 1 Coefficient 0 Upper Byte Table 246. Bit Descriptions for EQ1_COEF0_HI Bits [7:0] Bit Name EQ1_COEF0_HI Settings Description EQ1 Coefficient. Equalizer 1 Coefficient 0 Upper Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ1_COEF0_LO REGISTER Address: 0x81, Reset: 0x00, Name: EQ1_COEF0_LO Equalizer 1 Coefficient 0 Lower Byte Table 247. Bit Descriptions for EQ1_COEF0_LO Bits [7:0] Bit Name EQ1_COEF0_LO Settings Description EQ1 Coefficient. Equalizer 1 Coefficient 0 Lower Byte. EQ1_COEF1_HI REGISTER Address: 0x82, Reset: 0x00, Name: EQ1_COEF1_HI Equalizer 1 Coefficient 1 Upper Byte Table 248. Bit Descriptions for EQ1_COEF1_HI Bits [7:0] Bit Name EQ1_COEF1_HI Settings Description EQ1 Coefficient. Equalizer 1 Coefficient 1 Upper Byte. Rev. 0 | Page 271 of 296 ADAU1373 EQ1_COEF1_LO REGISTER Address: 0x83, Reset: 0x00, Name: EQ1_COEF1_LO Equalizer 1 Coefficient 1 Lower Byte Table 249. Bit Descriptions for EQ1_COEF1_LO Bits [7:0] Bit Name EQ1_COEF1_LO Settings Description EQ1 Coefficient. Equalizer 1 Coefficient 1 Lower Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ1_COEF2_HI REGISTER Address: 0x84, Reset: 0x00, Name: EQ1_COEF2_HI Equalizer 1 Coefficient 2 Upper Byte Table 250. Bit Descriptions for EQ1_COEF2_HI Bits [7:0] Bit Name EQ1_COEF2_HI Settings Description EQ1 Coefficient. Equalizer 1 Coefficient 2 Upper Byte. EQ1_COEF2_LO REGISTER Address: 0x85, Reset: 0x00, Name: EQ1_COEF2_LO Equalizer 1 Coefficient 2 Lower Byte Table 251. Bit Descriptions for EQ1_COEF2_LO Bits [7:0] Bit Name EQ1_COEF2_LO Settings Description EQ1 Coefficient. Equalizer 1 Coefficient 2 Lower Byte. Rev. 0 | Page 272 of 296 ADAU1373 EQ1_COEF3_HI REGISTER Address: 0x86, Reset: 0x00, Name: EQ1_COEF3_HI Equalizer 1 Coefficient 3 Upper Byte Table 252. Bit Descriptions for EQ1_COEF3_HI Bits [7:0] Bit Name EQ1_COEF3_HI Settings Description EQ1 Coefficient. Equalizer 1 Coefficient 3 Upper Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ1_COEF3_LO REGISTER Address: 0x87, Reset: 0x00, Name: EQ1_COEF3_LO Equalizer 1 Coefficient 3 Lower Byte Table 253. Bit Descriptions for EQ1_COEF3_LO Bits [7:0] Bit Name EQ1_COEF3_LO Settings Description EQ1 Coefficient. Equalizer 1 Coefficient 3 Lower Byte. EQ1_COEF4_HI REGISTER Address: 0x88, Reset: 0x00, Name: EQ1_COEF4_HI Equalizer 1 Coefficient 4 Upper Byte Table 254. Bit Descriptions for EQ1_COEF4_HI Bits [7:0] Bit Name EQ1_COEF4_HI Settings Description EQ1 Coefficient. Equalizer 1 Coefficient 4 Upper Byte. Rev. 0 | Page 273 of 296 ADAU1373 EQ1_COEF4_LO REGISTER Address: 0x89, Reset: 0x00, Name: EQ1_COEF4_LO Equalizer 1 Coefficient 4 Lower Byte Table 255. Bit Descriptions for EQ1_COEF4_LO Bits [7:0] Bit Name EQ1_COEF4_LO Settings Description EQ1 Coefficient. Equalizer 1 Coefficient 4 Lower Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ2_COEF0_HI REGISTER Address: 0x8A, Reset: 0x00, Name: EQ2_COEF0_HI Equalizer 2 Coefficient 0 Upper Byte Table 256. Bit Descriptions for EQ2_COEF0_HI Bits [7:0] Bit Name EQ2_COEF0_HI Settings Description EQ2 Coefficient. Equalizer 2 Coefficient 0 Upper Byte. EQ2_COEF0_LO REGISTER Address: 0x8B, Reset: 0x00, Name: EQ2_COEF0_LO Equalizer 2 Coefficient 0 Lower Byte Table 257. Bit Descriptions for EQ2_COEF0_LO Bits [7:0] Bit Name EQ2_COEF0_LO Settings Description EQ2 Coefficient. Equalizer 2 Coefficient 0 Lower Byte. Rev. 0 | Page 274 of 296 ADAU1373 EQ2_COEF1_HI REGISTER Address: 0x8C, Reset: 0x00, Name: EQ2_COEF1_HI Equalizer 2 Coefficient 1 Upper Byte Table 258. Bit Descriptions for EQ2_COEF1_HI Bits [7:0] Bit Name EQ2_COEF1_HI Settings Description EQ2 Coefficient. Equalizer 2 Coefficient 1 Upper Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ2_COEF1_LO REGISTER Address: 0x8D, Reset: 0x00, Name: EQ2_COEF1_LO Equalizer 2 Coefficient 1 Lower Byte Table 259. Bit Descriptions for EQ2_COEF1_LO Bits [7:0] Bit Name EQ2_COEF1_LO Settings Description EQ2 Coefficient. Equalizer 2 Coefficient 1 Lower Byte. EQ2_COEF2_HI REGISTER Address: 0x8E, Reset: 0x00, Name: EQ2_COEF2_HI Equalizer 2 Coefficient 2 Upper Byte Table 260. Bit Descriptions for EQ2_COEF2_HI Bits [7:0] Bit Name EQ2_COEF2_HI Settings Description EQ2 Coefficient. Equalizer 2 Coefficient 2 Upper Byte. Rev. 0 | Page 275 of 296 ADAU1373 EQ2_COEF2_LO REGISTER Address: 0x8F, Reset: 0x00, Name: EQ2_COEF2_LO Equalizer 2 Coefficient 2 Lower Byte Table 261. Bit Descriptions for EQ2_COEF2_LO Bits [7:0] Bit Name EQ2_COEF2_LO Settings Description EQ2 Coefficient. Equalizer 2 Coefficient 2 Lower Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ2_COEF3_HI REGISTER Address: 0x90, Reset: 0x00, Name: EQ2_COEF3_HI Equalizer 2 Coefficient 3 Upper Byte Table 262. Bit Descriptions for EQ2_COEF3_HI Bits [7:0] Bit Name EQ2_COEF3_HI Settings Description EQ2 Coefficient. Equalizer 2 Coefficient 3 Upper Byte. EQ2_COEF3_LO REGISTER Address: 0x91, Reset: 0x00, Name: EQ2_COEF3_LO Equalizer 2 Coefficient 3 Lower Byte Table 263. Bit Descriptions for EQ2_COEF3_LO Bits [7:0] Bit Name EQ2_COEF3_LO Settings Description EQ2 Coefficient. Equalizer 2 Coefficient 3 Lower Byte. Rev. 0 | Page 276 of 296 ADAU1373 EQ2_COEF4_HI REGISTER Address: 0x92, Reset: 0x00, Name: EQ2_COEF4_HI Equalizer 2 Coefficient 4 Upper Byte Table 264. Bit Descriptions for EQ2_COEF4_HI Bits [7:0] Bit Name EQ2_COEF4_HI Settings Description EQ2 Coefficient. Equalizer 2 Coefficient 4 Upper Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ2_COEF4_LO REGISTER Address: 0x93, Reset: 0x00, Name: EQ2_COEF4_LO Equalizer 2 Coefficient 4 Lower Byte Table 265. Bit Descriptions for EQ2_COEF4_LO Bits [7:0] Bit Name EQ2_COEF4_LO Settings Description EQ2 Coefficient. Equalizer 2 Coefficient 4 Lower Byte. EQ3_COEF0_HI REGISTER Address: 0x94, Reset: 0x00, Name: EQ3_COEF0_HI Equalizer 3 Coefficient 0 Upper Byte Table 266. Bit Descriptions for EQ3_COEF0_HI Bits [7:0] Bit Name EQ3_COEF0_HI Settings Description EQ3 Coefficient. Equalizer 3 Coefficient 0 Upper Byte. Rev. 0 | Page 277 of 296 ADAU1373 EQ3_COEF0_LO REGISTER Address: 0x95, Reset: 0x00, Name: EQ3_COEF0_LO Equalizer 3 Coefficient 0 Lower Byte Table 267. Bit Descriptions for EQ3_COEF0_LO Bits [7:0] Bit Name EQ3_COEF0_LO Settings Description EQ3 Coefficient. Equalizer 3 Coefficient 0 Lower Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ3_COEF1_HI REGISTER Address: 0x96, Reset: 0x00, Name: EQ3_COEF1_HI Equalizer 3 Coefficient 1 Upper Byte Table 268. Bit Descriptions for EQ3_COEF1_HI Bits [7:0] Bit Name EQ3_COEF1_HI Settings Description EQ3 Coefficient. Equalizer 3 Coefficient 1 Upper Byte. EQ3_COEF1_LO REGISTER Address: 0x97, Reset: 0x00, Name: EQ3_COEF1_LO Equalizer 3 Coefficient 1 Lower Byte Table 269. Bit Descriptions for EQ3_COEF1_LO Bits [7:0] Bit Name EQ3_COEF1_LO Settings Description EQ3 Coefficient. Equalizer 3 Coefficient 1 Lower Byte. Rev. 0 | Page 278 of 296 ADAU1373 EQ3_COEF2_HI REGISTER Address: 0x98, Reset: 0x00, Name: EQ3_COEF2_HI Equalizer 3 Coefficient 2 Upper Byte Table 270. Bit Descriptions for EQ3_COEF2_HI Bits [7:0] Bit Name EQ3_COEF2_HI Settings Description EQ3 Coefficient. Equalizer 3 Coefficient 2 Upper Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ3_COEF2_LO REGISTER Address: 0x99, Reset: 0x00, Name: EQ3_COEF2_LO Equalizer 3 Coefficient 2 Lower Byte Table 271. Bit Descriptions for EQ3_COEF2_LO Bits [7:0] Bit Name EQ3_COEF2_LO Settings Description EQ3 Coefficient. Equalizer 3 Coefficient 2 Lower Byte. EQ3_COEF3_HI REGISTER Address: 0x9A, Reset: 0x00, Name: EQ3_COEF3_HI Equalizer 3 Coefficient 3 Upper Byte Table 272. Bit Descriptions for EQ3_COEF3_HI Bits [7:0] Bit Name EQ3_COEF3_HI Settings Description EQ3 Coefficient. Equalizer 3 Coefficient 3 Upper Byte. Rev. 0 | Page 279 of 296 ADAU1373 EQ3_COEF3_LO REGISTER Address: 0x9B, Reset: 0x00, Name: EQ3_COEF3_LO Equalizer 3 Coefficient 3 Lower Byte Table 273. Bit Descriptions for EQ3_COEF3_LO Bits [7:0] Bit Name EQ3_COEF3_LO Settings Description EQ3 Coefficient. Equalizer 3 Coefficient 3 Lower Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ3_COEF4_HI REGISTER Address: 0x9C, Reset: 0x00, Name: EQ3_COEF4_HI Equalizer 3 Coefficient 4 Upper Byte Table 274. Bit Descriptions for EQ3_COEF4_HI Bits [7:0] Bit Name EQ3_COEF4_HI Settings Description EQ3 Coefficient. Equalizer 3 Coefficient 4 Upper Byte. EQ3_COEF4_LO REGISTER Address: 0x9D, Reset: 0x00, Name: EQ3_COEF4_LO Equalizer 3 Coefficient 4 Lower Byte Table 275. Bit Descriptions for EQ3_COEF4_LO Bits [7:0] Bit Name EQ3_COEF4_LO Settings Description EQ3 Coefficient. Equalizer 3 Coefficient 4 Lower Byte. Rev. 0 | Page 280 of 296 ADAU1373 EQ4_COEF0_HI REGISTER Address: 0x9E, Reset: 0x00, Name: EQ4_COEF0_HI Equalizer 4 Coefficient 0 Upper Byte Table 276. Bit Descriptions for EQ4_COEF0_HI Bits [7:0] Bit Name EQ4_COEF0_HI Settings Description EQ4 Coefficient. Equalizer 4 Coefficient 0 Upper Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ4_COEF0_LO REGISTER Address: 0x9F, Reset: 0x00, Name: EQ4_COEF0_LO Equalizer 4 Coefficient 0 Lower Byte Table 277. Bit Descriptions for EQ4_COEF0_LO Bits [7:0] Bit Name EQ4_COEF0_LO Settings Description EQ4 Coefficient. Equalizer 4 Coefficient 0 Lower Byte. EQ4_COEF1_HI REGISTER Address: 0xA0, Reset: 0x00, Name: EQ4_COEF1_HI Equalizer 4 Coefficient 1 Upper Byte Table 278. Bit Descriptions for EQ4_COEF1_HI Bits [7:0] Bit Name EQ4_COEF1_HI Settings Description EQ4 Coefficient. Equalizer 4 Coefficient 1 Upper Byte. Rev. 0 | Page 281 of 296 ADAU1373 EQ4_COEF1_LO REGISTER Address: 0xA1, Reset: 0x00, Name: EQ4_COEF1_LO Equalizer 4 Coefficient 1 Lower Byte Table 279. Bit Descriptions for EQ4_COEF1_LO Bits [7:0] Bit Name EQ4_COEF1_LO Settings Description EQ4 Coefficient. Equalizer 4 Coefficient 1 Lower Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ4_COEF2_HI REGISTER Address: 0xA2, Reset: 0x00, Name: EQ4_COEF2_HI Equalizer 4 Coefficient 2 Upper Byte Table 280. Bit Descriptions for EQ4_COEF2_HI Bits [7:0] Bit Name EQ4_COEF2_HI Settings Description EQ4 Coefficient. Equalizer 4 Coefficient 2 Upper Byte. EQ4_COEF2_LO REGISTER Address: 0xA3, Reset: 0x00, Name: EQ4_COEF2_LO Equalizer 4 Coefficient 2 Lower Byte Table 281. Bit Descriptions for EQ4_COEF2_LO Bits [7:0] Bit Name EQ4_COEF2_LO Settings Description EQ4 Coefficient. Equalizer 4 Coefficient 2 Lower Byte. Rev. 0 | Page 282 of 296 ADAU1373 EQ4_COEF3_HI REGISTER Address: 0xA4, Reset: 0x00, Name: EQ4_COEF3_HI Equalizer 4 Coefficient 3 Upper Byte Table 282. Bit Descriptions for EQ4_COEF3_HI Bits [7:0] Bit Name EQ4_COEF3_HI Settings Description EQ4 Coefficient. Equalizer 4 Coefficient 3 Upper Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ4_COEF3_LO REGISTER Address: 0xA5, Reset: 0x00, Name: EQ4_COEF3_LO Equalizer 4 Coefficient 3 Lower Byte Table 283. Bit Descriptions for EQ4_COEF3_LO Bits [7:0] Bit Name EQ4_COEF3_LO Settings Description EQ4 Coefficient. Equalizer 4 Coefficient 3 Lower Byte. EQ4_COEF4_HI REGISTER Address: 0xA6, Reset: 0x00, Name: EQ4_COEF4_HI Equalizer 4 Coefficient 4 Upper Byte Table 284. Bit Descriptions for EQ4_COEF4_HI Bits [7:0] Bit Name EQ4_COEF4_HI Settings Description EQ4 Coefficient. Equalizer 4 Coefficient 4 Upper Byte. Rev. 0 | Page 283 of 296 ADAU1373 EQ4_COEF4_LO REGISTER Address: 0xA7, Reset: 0x00, Name: EQ4_COEF4_LO Equalizer 4 Coefficient 4 Lower Byte Table 285. Bit Descriptions for EQ4_COEF4_LO Bits [7:0] Bit Name EQ4_COEF4_LO Settings Description EQ4 Coefficient. Equalizer 4 Coefficient 4 Lower Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ5_COEF0_HI REGISTER Address: 0xA8, Reset: 0x00, Name: EQ5_COEF0_HI Equalizer 5 Coefficient 0 Upper Byte Table 286. Bit Descriptions for EQ5_COEF0_HI Bits [7:0] Bit Name EQ5_COEF0_HI Settings Description EQ5 Coefficient. Equalizer 5 Coefficient 0 Upper Byte. EQ5_COEF0_LO REGISTER Address: 0xA9, Reset: 0x00, Name: EQ5_COEF0_LO Equalizer 5 Coefficient 0 Lower Byte Table 287. Bit Descriptions for EQ5_COEF0_LO Bits [7:0] Bit Name EQ5_COEF0_LO Settings Description EQ5 Coefficient. Equalizer 5 Coefficient 0 Lower Byte. Rev. 0 | Page 284 of 296 ADAU1373 EQ5_COEF1_HI REGISTER Address: 0xAA, Reset: 0x00, Name: EQ5_COEF1_HI Equalizer 5 Coefficient 1 Upper Byte Table 288. Bit Descriptions for EQ5_COEF1_HI Bits [7:0] Bit Name EQ5_COEF1_HI Settings Description EQ5 Coefficient. Equalizer 5 Coefficient 1 Upper Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ5_COEF1_LO REGISTER Address: 0xAB, Reset: 0x00, Name: EQ5_COEF1_LO Equalizer 5 Coefficient 1 Lower Byte Table 289. Bit Descriptions for EQ5_COEF1_LO Bits [7:0] Bit Name EQ5_COEF1_LO Settings Description EQ5 Coefficient. Equalizer 5 Coefficient 1 Lower Byte. EQ5_COEF2_HI REGISTER Address: 0xAC, Reset: 0x00, Name: EQ5_COEF2_HI Equalizer 5 Coefficient 2 Upper Byte Table 290. Bit Descriptions for EQ5_COEF2_HI Bits [7:0] Bit Name EQ5_COEF2_HI Settings Description EQ5 Coefficient. Equalizer 5 Coefficient 2 Upper Byte. Rev. 0 | Page 285 of 296 ADAU1373 EQ5_COEF2_LO REGISTER Address: 0xAD, Reset: 0x00, Name: EQ5_COEF2_LO Equalizer 5 Coefficient 2 Lower Byte Table 291. Bit Descriptions for EQ5_COEF2_LO Bits [7:0] Bit Name EQ5_COEF2_LO Settings Description EQ5 Coefficient. Equalizer 5 Coefficient 2 Lower Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ5_COEF3_HI REGISTER Address: 0xAE, Reset: 0x00, Name: EQ5_COEF3_HI Equalizer 5 Coefficient 3 Upper Byte Table 292. Bit Descriptions for EQ5_COEF3_HI Bits [7:0] Bit Name EQ5_COEF3_HI Settings Description EQ5 Coefficient. Equalizer 5 Coefficient 3 Upper Byte. EQ5_COEF3_LO REGISTER Address: 0xAF, Reset: 0x00, Name: EQ5_COEF3_LO Equalizer 5 Coefficient 3 Lower Byte Table 293. Bit Descriptions for EQ5_COEF3_LO Bits [7:0] Bit Name EQ5_COEF3_LO Settings Description EQ5 Coefficient. Equalizer 5 Coefficient 3 Lower Byte. Rev. 0 | Page 286 of 296 ADAU1373 EQ5_COEF4_HI REGISTER Address: 0xB0, Reset: 0x00, Name: EQ5_COEF4_HI Equalizer 5 Coefficient 4 Upper Byte Table 294. Bit Descriptions for EQ5_COEF4_HI Bits [7:0] Bit Name EQ5_COEF4_HI Settings Description EQ5 Coefficient. Equalizer 5 Coefficient 4 Upper Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ5_COEF4_LO REGISTER Address: 0xB1, Reset: 0x00, Name: EQ5_COEF4_LO Equalizer 5 Coefficient 4 Lower Byte Table 295. Bit Descriptions for EQ5_COEF4_LO Bits [7:0] Bit Name EQ5_COEF4_LO Settings Description EQ5 Coefficient. Equalizer 5 Coefficient 4 Lower Byte. EQ6_COEF0_HI REGISTER Address: 0xB2, Reset: 0x00, Name: EQ6_COEF0_HI Equalizer 6 Coefficient 0 Upper Byte Table 296. Bit Descriptions for EQ6_COEF0_HI Bits [7:0] Bit Name EQ6_COEF0_HI Settings Description EQ6 Coefficient. Equalizer 6 Coefficient 0 Upper Byte. Rev. 0 | Page 287 of 296 ADAU1373 EQ6_COEF0_LO REGISTER Address: 0xB3, Reset: 0x00, Name: EQ6_COEF0_LO Equalizer 6 Coefficient 0 Lower Byte Table 297. Bit Descriptions for EQ6_COEF0_LO Bits [7:0] Bit Name EQ6_COEF0_LO Settings Description EQ6 Coefficient. Equalizer 6 Coefficient 0 Lower Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ6_COEF1_HI REGISTER Address: 0xB4, Reset: 0x00, Name: EQ6_COEF1_HI Equalizer 6 Coefficient 1 Upper Byte Table 298. Bit Descriptions for EQ6_COEF1_HI Bits [7:0] Bit Name EQ6_COEF1_HI Settings Description EQ6 Coefficient. Equalizer 6 Coefficient 1 Upper Byte. EQ6_COEF1_LO REGISTER Address: 0xB5, Reset: 0x00, Name: EQ6_COEF1_LO Equalizer 6 Coefficient 1 Lower Byte Table 299. Bit Descriptions for EQ6_COEF1_LO Bits [7:0] Bit Name EQ6_COEF1_LO Settings Description EQ6 Coefficient. Equalizer 6 Coefficient 1 Lower Byte. Rev. 0 | Page 288 of 296 ADAU1373 EQ6_COEF2_HI REGISTER Address: 0xB6, Reset: 0x00, Name: EQ6_COEF2_HI Equalizer 6 Coefficient 2 Upper Byte Table 300. Bit Descriptions for EQ6_COEF2_HI Bits [7:0] Bit Name EQ6_COEF2_HI Settings Description EQ6 Coefficient. Equalizer 6 Coefficient 2 Upper Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ6_COEF2_LO REGISTER Address: 0xB7, Reset: 0x00, Name: EQ6_COEF2_LO Equalizer 6 Coefficient 2 Lower Byte Table 301. Bit Descriptions for EQ6_COEF2_LO Bits [7:0] Bit Name EQ6_COEF2_LO Settings Description EQ6 Coefficient. Equalizer 6 Coefficient 2 Lower Byte. EQ7_COEF0_HI REGISTER Address: 0xB8, Reset: 0x00, Name: EQ7_COEF0_HI Equalizer 7 Coefficient 0 Upper Byte Table 302. Bit Descriptions for EQ7_COEF0_HI Bits [7:0] Bit Name EQ7_COEF0_HI Settings Description EQ7 Coefficient. Equalizer 7 Coefficient 0 Upper Byte. Rev. 0 | Page 289 of 296 ADAU1373 EQ7_COEF0_LO REGISTER Address: 0xB9, Reset: 0x00, Name: EQ7_COEF0_LO Equalizer 7 Coefficient 0 Lower Byte Table 303. Bit Descriptions for EQ7_COEF0_LO Bits [7:0] Bit Name EQ7_COEF0_LO Settings Description EQ7 Coefficient. Equalizer 7 Coefficient 0 Lower Byte. Reset 0x00 Access RW Reset 0x00 Access RW Reset 0x00 Access RW EQ7_COEF1_HI REGISTER Address: 0xBA, Reset: 0x00, Name: EQ7_COEF1_HI Equalizer 7 Coefficient 1 Upper Byte Table 304. Bit Descriptions for EQ7_COEF1_HI Bits [7:0] Bit Name EQ7_COEF1_HI Settings Description EQ7 Coefficient. Equalizer 7 Coefficient 1 Upper Byte. EQ7_COEF1_LO REGISTER Address: 0xBB, Reset: 0x00, Name: EQ7_COEF1_LO Equalizer 7 Coefficient 1 Lower Byte Table 305. Bit Descriptions for EQ7_COEF1_LO Bits [7:0] Bit Name EQ7_COEF1_LO Settings Description EQ7 Coefficient. Equalizer 7 Coefficient 1 Lower Byte. Rev. 0 | Page 290 of 296 ADAU1373 EQ7_COEF2_HI REGISTER Address: 0xBC, Reset: 0x00, Name: EQ7_COEF2_HI Equalizer 7 Coefficient 2 Upper Byte Table 306. Bit Descriptions for EQ7_COEF2_HI Bits [7:0] Bit Name EQ7_COEF2_HI Settings Description EQ7 Coefficient. Equalizer 7 Coefficient 2 Upper Byte. Reset 0x00 Access RW Reset 0x00 Access RW EQ7_COEF2_LO REGISTER Address: 0xBD, Reset: 0x00, Name: EQ7_COEF2_LO Equalizer 7 Coefficient 2 Lower Byte Table 307. Bit Descriptions for EQ7_COEF2_LO Bits [7:0] Bit Name EQ7_COEF2_LO Settings Description EQ7 Coefficient. Equalizer 7 Coefficient 2 Lower Byte. Rev. 0 | Page 291 of 296 ADAU1373 APPLICATIONS CIRCUIT 0.1µF 10µF BATTERY 1µF FM 1µF – + – L R 0.1µF IOVDD4 DMIC1_2_DATA DMIC3_4_DATA AIN3P AIN3N MICBIAS2 (1.8V TO 2.8V, 0.2V STEP) AIN2N 2kΩ 2.2µF EXTERNAL MICROPHONE AIN4P AIN2P 2.2µF AIN4N AIN1L HPL AIN1R HPR IOVDD3 (1.8V TO 3.3V) EARPHONE SGND GPIO4 BT INTERNAL DIGITAL MICROPHONE DMIC_CLK CONNECTOR 22nF DVDD (1.08V TO 2.0V) 22nF AVDD (1.5V TO 1.8V) 22nF + INTERNAL ANALOG MICROPHONE 2.2µF DVDD MICBIAS1 (1.8V TO 2.8V, 0.2V STEP) 2kΩ 22nF HPVDD (1.62V TO 2.0V) 2kΩ SPKVDD (2.5V TO 5.5V) CM RESERVED 1µF 2.2µF 2.2µF HPVDD AVDD JACKDET BCLKC 2.2µF CPVDD LRCLKC CF1 SDATAOUTC CF2 SDATAINC 2.2µF 2.2µF CPVSS IOVDD2 (1.8V TO 3.3V) GPIO2 EPP ADAU1373 RECEIVER EPN BCLKB AP SPKLP LRCLKB SDATAOUTB BEAD 2 SDATAINB SPKRP MCLK21 RIGHT SPEAKER SPKRN IOVDD1 (1.8V TO 3.3V) LOUT1L/ LOUTLP GPIO1 MCLK11 BB LEFT SPEAKER SPKLN LOUT1R/ LOUTRP BCLKA LOUT2L/ LOUTLN LRCLKA SDATAOUTA LOUT2R/ LOUTRN SDATAINA 1µF 1µF 1µF 1µF DOCKING 2.2µF LN1FBIN IOVDD5 (1.8V TO 3.3V) 2.2µF GPIO3 EXCEED 4 INCHES. THE OUTPUT SPEAKER TRACE PLUS THE CABLE LENGTH Figure 123. Typical Stereo Class-D Applications Circuit Rev. 0 | Page 292 of 296 08975-109 1SELECT EITHER MCLK1 OR MCLK2 BY CONTROL. 2REQUIRED FOR EMI SENSITIVE APPLICATIONS WHERE DGND SD AGND SDA HPGND SCL SPKGND BB OR AP LN2FBIN ADAU1373 OUTLINE DIMENSIONS 4.085 4.045 4.005 9 8 7 6 5 4 3 2 1 A B BALL A1 IDENTIFIER C 3.860 3.820 3.780 3.20 BSC SQ D E F G H 0.40 BALL PITCH TOP VIEW (BALL SIDE DOWN) SEATING PLANE SIDE VIEW (BALL SIDE UP) 0.330 0.300 0.270 COPLANARITY 0.05 0.300 0.260 0.220 0.230 0.200 0.170 02-01-2010-A 0.560 0.500 0.440 J BOTTOM VIEW Figure 124. 81-Ball Wafer Level Chip Scale Package [WLCSP] (CB-81-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADAU1373BCBZ-R7 ADAU1373BCBZ-RL EVAL-ADAU1373Z 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 81-Ball WLCSP 81-Ball WLCSP Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 293 of 296 Package Option CB-81-1 CB-81-1 ADAU1373 NOTES Rev. 0 | Page 294 of 296 ADAU1373 NOTES Rev. 0 | Page 295 of 296 ADAU1373 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08975-0-5/11(0) Rev. 0 | Page 296 of 296