ADAU1381BCPZ-RL

Low Noise Stereo Codec with Enhanced Recording and Playback Processing ADAU1381 FEATURES GENERAL DESCRIPTION 24-bit stereo audio ADC and DAC 400 mW speaker amplifier (into 8 Ω load) Built-in sound engine for audio processing Wind noise detection and autofiltering Enhanced stereo capture (ESC) Dual-band automatic level control (ALC) 6-band equalizer, including notch filter Sampling rates from 8 kHz to 96 kHz Stereo pseudo differential microphone input Optional stereo digital microphone input pulse-density modulation (PDM) Stereo line output PLL supporting a range of input clock rates Analog and digital I/O 1.8 V to 3.3 V Software control via SigmaStudio graphical user interface Software-controllable, clickless mute Software register and hardware pin standby mode 32-lead, 5 mm × 5 mm LFCSP or 30-ball, 6 × 5 bump WLCSP The ADAU1381 is a low power, 24-bit stereo audio codec. The low noise DAC and ADC support sample rates from 8 kHz to 96 kHz. Low current draw and power saving modes make the ADAU1381 ideal for battery-powered audio applications. A configurable sound engine provides enhanced record and playback processing to improve overall audio quality. The record path includes two digital stereo microphone inputs and an analog stereo input path. The analog inputs can be configured for either a pseudo differential or a single-ended stereo source. A dedicated analog beep input signal can be mixed into any output path. The ADAU1381 includes a stereo line output and speaker driver, which makes the device capable of supporting dynamic speakers. The serial control bus supports the I2C® or SPI protocols, and the serial audio bus is programmable for I2S, left-justified, rightjustified, or TDM mode. A programmable PLL supports flexible clock generation for all standard rates and available master clocks from 11 MHz to 20 MHz. APPLICATIONS Digital still cameras Digital video cameras AGND2 AVDD2 AGND1 AVDD1 DVDDOUT DGND IOVDD CM FUNCTIONAL BLOCK DIAGRAM ADAU1381 REGULATOR BEEP PGA SOUND ENGINE LMIC/LMICN/ MICD1 PGA LMICP AOUTL DECIMATION FILTERS LEFT ADC AOUTR LEFT DAC WIND NOISE OUTPUT MIXER NOTCH FILTER EQUALIZER RMIC/RMICN/ MICD2 PGA RMICP RIGHT ADC SPP RIGHT DAC SPN AUTOMATIC LEVEL CONTROL 08313-001 SDA/COUT SCL/CCLK ADDR0/CDATA DAC_SDATA/ GPIO0 LRCLK/GPIO3 ADDR1/CLATCH I2C/SPI CONTROL PORT SERIAL DATA INPUT/OUTPUT PORTS BCLK/GPIO2 PLL MCKI MICROPHONE BIAS ADC_SDATA/ GPIO1 PDN MICBIAS DIGITAL VOLUME CONTROL Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved. ADAU1381 TABLE OF CONTENTS Features .............................................................................................. 1 Input Signal Path ........................................................................ 30 Applications....................................................................................... 1 Analog-to-Digital Converters................................................... 31 General Description ......................................................................... 1 Digital Dual-Band Automatic Level Control (ALC) ............. 31 Functional Block Diagram .............................................................. 1 Playback Signal Path ...................................................................... 32 Revision History ............................................................................... 3 Output Signal Paths ................................................................... 32 Specifications..................................................................................... 4 Digital-to-Analog Converters................................................... 32 Record Side Performance Specifications................................... 4 Line Outputs ............................................................................... 32 Output Side Performance Specifications................................... 6 Speaker Output........................................................................... 32 Power Supply Specifications........................................................ 8 Control Ports................................................................................... 33 Typical Power Management Measurements ............................. 9 I2C Port ........................................................................................ 33 Digital Filters................................................................................. 9 SPI Port ........................................................................................ 36 Digital Input/Output Specifications......................................... 10 Memory and Register Access.................................................... 36 Digital Timing Specifications ................................................... 11 Serial Data Input/Output Ports .................................................... 38 Absolute Maximum Ratings.......................................................... 14 TDM Modes................................................................................ 38 Thermal Resistance .................................................................... 14 General-Purpose Input/Outputs .................................................. 40 ESD Caution................................................................................ 14 Sound Engine.................................................................................. 41 Pin Configuration and Function Descriptions........................... 15 Signal Processing........................................................................ 41 Typical Performance Characteristics ........................................... 17 Processing Flow .......................................................................... 41 System Block Diagrams ................................................................. 20 Programming.............................................................................. 41 Theory of Operation ...................................................................... 24 Parameter Memory .................................................................... 41 Startup, Initialization, and Power ................................................. 25 Applications Information .............................................................. 42 Power-Up Sequence ................................................................... 25 Power Supply Bypass Capacitors.............................................. 42 Clock Generation and Management........................................ 26 GSM Noise Filter ........................................................................ 42 Enabling Digital Power to Functional Subsystems ................ 26 Grounding ................................................................................... 42 Setting Up the Sound Engine.................................................... 26 Speaker Driver Supply Trace (AVDD2) .................................. 42 Power Reduction Modes............................................................ 26 Exposed Pad PCB Design ......................................................... 42 Power-Down Sequence.............................................................. 26 Control Register Map..................................................................... 43 Clocking and Sampling Rates ....................................................... 27 Clock Management, Internal Regulator, and PLL Control... 44 Core Clock................................................................................... 27 Record Path Configuration....................................................... 48 Sampling Rates............................................................................ 27 Serial Port Configuration .......................................................... 53 PLL ............................................................................................... 28 Audio Converter Configuration............................................... 58 Record Signal Path.......................................................................... 30 Playback Path Configuration.................................................... 63 Rev. B | Page 2 of 84 ADAU1381 Pad Configuration.......................................................................70 Outline Dimensions........................................................................84 Digital Subsystem Configuration..............................................77 Ordering Guide ...........................................................................84 REVISION HISTORY 1/11—Rev. A to Rev. B Changes to Pin PDN Description in Table 10 .............................16 Changes to Power-Down Pin (PDN) Section..............................26 Changes to Table 23 ........................................................................36 3/10—Rev. 0 to Rev. A Changes to Output Side Performance Specifications Section Condition Statement.....................................................................6 Added Endnote 1 to Table 3.............................................................8 Changes to Figure 23 ......................................................................20 Changes to Figure 24 ......................................................................21 Changes to Figure 25 ......................................................................22 Changes to Figure 26 ......................................................................23 Changes to Table 27 ........................................................................43 Added Register 16434 (0x4032), Dejitter Control Section ........76 Changes to Ordering Guide...........................................................84 10/09—Revision 0: Initial Version Rev. B | Page 3 of 84 ADAU1381 SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages AVDD = AVDD1 = AVDD2 = I/O supply = 3.3 V, digital supply = 1.5 V, unless otherwise noted; temperature = 25°C; master clock (MCLK) = 12.288 MHz (fS = 48 kHz, 256 × fS mode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz; word width = 24 bits; load capacitance (digital output) = 20 pF; load current (digital output) = 2 mA; high level input voltage = 0.7 × IOVDD; and low level input voltage = 0.3 × IOVDD. All power management registers are set to their default states. RECORD SIDE PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). Table 1. Parameter ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Digital Attenuation Step Digital Attenuation Range INPUT RESISTANCE Noninverting Inputs PGA (LMICP, RMICP) Inverting Inputs PGA (LMICN, RMICN) Beep Input PGA SINGLE-ENDED MICROPHONE INPUT TO ADC PATH Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Test Conditions/Comments Min Typ Max Unit All ADCs 24 0.375 95 Bits dB dB All gain settings 500 kΩ 0 dB gain 6 dB gain 10 dB gain 14 dB gain 17 dB gain 20 dB gain 26 dB gain 32 dB gain 0 dB 6 dB 10 dB 14 dB −23 dB 20 dB 26 dB 32 dB 62 32 22 14 10 8 5 4 20 9 6 3.5 50 2 2 2 kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ Scales linearly with AVDD AVDD = 1.8 V AVDD = 3.3 V −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V −3 dBFS AVDD = 1.8 V AVDD = 3.3 V AVDD/3.3 0.55 (1.56) 1.0 (2.83) V rms V rms (V p-p) V rms (V p-p) 96 99.2 92 96.5 dB dB dB dB −88 −90 dB dB 96 100 92 97 dB dB dB dB AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Rev. B | Page 4 of 84 94 92 ADAU1381 Parameter Left/Right Microphone PGA Gain Range Left/Right Microphone PGA Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio DIFFERENTIAL MICROPHONE INPUT TO ADC PATH Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Left/Right Microphone PGA Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation Common-Mode Rejection Ratio BEEP TO LINE OUTPUT PATH Full-Scale Input Voltage (0 dB) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Test Conditions/Comments AVDD = 3.3 V Min 0 AVDD = 3.3 V; mute set by Register 0x400E, Bit 1, and Register 0x400F, Bit 1 AVDD = 3.3 V AVDD = 3.3 V AVDD = 3.3 V AVDD = 3.3 V CM capacitor = 10 μF AVDD = 3.3 V, 100 mV p-p at 217 Hz AVDD = 3.3 V, 100 mV p-p at 1 kHz Scales linearly with AVDD AVDD = 1.8 V AVDD = 3.3 V −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V −3 dBFS AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 3.3 V; mute set by Register 0x400E, Bit 1, and Register 0x400F, Bit 1 AVDD = 3.3 V AVDD = 3.3 V AVDD = 3.3 V AVDD = 3.3 V AVDD = 3.3 V, 100 mV rms, 1 kHz AVDD = 3.3 V, 100 mV rms, 20 kHz 94 92 Typ Max 32 Unit dB −98 dB 50 0.25 −1 −98 mdB mV % dB −55 −55 dB dB AVDD/3.3 0.55 (1.56) 1.0 (2.83) V rms V rms (V p-p) V rms (V p-p) 96 99.2 92 96.5 dB dB dB dB −84 −85 dB dB 96 100 92 97 −98 dB dB dB dB dB 50 0.25 −1 −85 −60 −45 mdB mV % dB dB dB Scales linearly with AVDD AVDD = 1.8 V AVDD = 3.3 V −3 dBFS input, measured at AOUTL pin, beep gain set to 0 dB AVDD = 1.8 V AVDD = 3.3 V AVDD/3.3 0.55 (1.56) 1.0 (2.83) V rms V rms (V p-p) V rms (V p-p) −88 −88 dB dB AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V 99 105 96 102 dB dB dB dB Rev. B | Page 5 of 84 ADAU1381 Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Beep Input Mute Attenuation Offset Error Gain Error Interchannel Gain Mismatch Beep Input PGA Gain Range Beep Playback Mixer Gain Range Power Supply Rejection Ratio MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.90 × AVDD Bias Current Source Noise in the Signal Bandwidth Test Conditions/Comments −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 3.3 V; mute set by Register 0x4008, Bit 3 AVDD = 3.3 V AVDD = 3.3 V Min AVDD = 3.3 V AVDD = 3.3 V CM capacitor = 10 μF AVDD = 3.3 V, 100 mV p-p at 217 Hz AVDD = 3.3 V, 100 mV p-p at 1 kHz Microphone bias enabled −23 −15 AVDD = 1.8 V, low bias AVDD = 3.3 V, low bias AVDD = 1.8 V, high bias AVDD = 3.3 V, high bias AVDD = 3.3 V, high bias, high performance AVDD = 3.3 V, 20 Hz to 20 kHz High bias, high performance High bias, low performance Low bias, high performance Low bias, low performance AVDD = 1.8 V, 20 Hz to 20 kHz High bias, high performance High bias, low performance Low bias, high performance Low bias, low performance Typ Max Unit 99 105 96 102 −90 dB dB dB dB dB 10 −0.3 30 mV dB mdB dB dB +32 +6 −58 −72 dB dB 1.17 2.145 1.62 2.97 V V V V mA 5 39 78 25 35 nV√Hz nV√Hz nV√Hz nV√Hz 35 45 23 23 nV√Hz nV√Hz nV√Hz nV√Hz OUTPUT SIDE PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). The output load for the speaker output path is an 8 Ω, 400 mW speaker. Table 2. Parameter DIGITAL-TO-ANALOG CONVERTERS DAC Resolution Digital Attenuation Step Digital Attenuation Range DAC TO LINE OUTPUT PATH Full-Scale Output Voltage (0 dB) Line Output Mute Attenuation, DAC to Mixer Path Muted Line Output Mute Attenuation, Line Output Muted Test Conditions/Comments Min Typ Max Unit All DACs 24 0.375 95 Bits dB dB Scales linearly with AVDD AVDD = 1.8 V AVDD = 3.3 V AVDD = 3.3 V; mute set by Register 0x401C, Bit 5, and Register 0x401E, Bit 6 AVDD = 3.3 V; mute set by Register 0x4025, Bit 1, and Register 0x4026, Bit 1 AVDD/3.3 0.55 (1.56) 1.0 (2.83) −85 V rms V rms (V p-p) V rms (V p-p) dB −85 dB Rev. B | Page 6 of 84 ADAU1381 Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Gain Error Interchannel Gain Mismatch Offset Error DAC TO SPEAKER OUTPUT PATH Differential Full-Scale Output Voltage (0 dB) Total Harmonic Distortion + Noise 4 Ω Load 8 Ω Load Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Differential Offset Error Mono Mixer Mute Attenuation, DAC to Mixer Path Muted BEEP TO SPEAKER OUTPUT PATH Differential Full-Scale Output Voltage (0 dB) Test Conditions/Comments −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V −3 dBFS AVDD = 1.8 V AVDD = 3.3 V Min Typ Unit −88 −88 dB dB dB dB dB dB dB 99 103 97 100 dB dB dB dB −55 −63 −1 50 10 dB dB dB mdB mV AVDD/1.65 V rms AVDD = 1.8 V AVDD = 3.3 V 1.1 (3.12) 2.0 (5.66) V rms (V p-p) V rms (V p-p) AVDD = 1.8 V, PO = 50 mW AVDD = 3.3 V, PO = 175 mW AVDD = 1.8 V, PO = 50 mW AVDD = 3.3 V, PO = 175 mW AVDD = 3.3 V, PO = 330 mW AVDD = 3.3 V, PO = 440 mW −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V −60 −60 −60 −60 −60 −16 dB dB dB dB dB dB 100 105 98 103 dB dB dB dB 94 92 AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V CM capacitor = 10 μF AVDD = 3.3 V, 100 mV p-p at 217 Hz AVDD = 3.3 V, 100 mV p-p at 1 kHz AVDD = 3.3 V AVDD = 3.3 V AVDD = 3.3 V PO = output power Scales linearly with AVDD 94 92 99 103 97 100 Max AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V CM capacitor = 10 μF AVDD = 3.3 V,100 mV p-p at 217 Hz AVDD = 3.3 V, 100 mV p-p at 1 kHz AVDD = 3.3 V Mute set by Register 0x401F, Bit 0 100 105 98 103 dB dB dB dB −55 −55 2 −90 dB dB mV dB PO = output power Scales linearly with AVDD AVDD/1.65 V rms AVDD = 1.8 V AVDD = 3.3 V 1.1 (3.12) 2.0 (5.66) V rms (V p-p) V rms (V p-p) Rev. B | Page 7 of 84 ADAU1381 Parameter Total Harmonic Distortion + Noise Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Differential Offset Error Mono Mixer Mute Attenuation, Beep to Mixer Path Muted REFERENCE (CM PIN) Common-Mode Reference Output Test Conditions/Comments Min Typ Max Unit 8 Ω, 1 nF load, AVDD = 1.8 V, PO = 50 mW AVDD = 3.3 V, PO = 175 mW −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V −60 −60 dB dB 97 103 94 100 dB dB dB dB AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V CM capacitor = 10 μF 100 mV p-p at 217 Hz 100 mV p-p at 1 kHz 98 103 96 101 dB dB dB dB −57 −60 2 −90 dB dB mV dB AVDD/2 V Mute set by Register 0x401F, Bit 0 POWER SUPPLY SPECIFICATIONS AVDD1 and AVDD2 must always be equal. Power supply measurements are taken with the sound engine processing path enabled. Table 3. Parameter AVDD1, AVDD2 IOVDD Digital I/O Current (IOVDD = 3.3 V) Slave Mode, Analog I/O, 12.288 MHz External MCLK Input Master Mode, MCKO Disabled Digital I/O Current (IOVDD = 1.8 V) Slave Mode, Analog I/O, 12.288 MHz External MCLK Input Master Mode, MCKO Disabled Analog Current (AVDD) 1 Test Conditions/Comments 20 pF capacitive load on all digital pins fS = 48 kHz Min 1.8 1 1.63 Typ 3.3 3.3 Max 3.65 3.65 Unit V V 0.20 mA fS = 96 kHz fS = 8 kHz fS = 48 kHz fS = 96 kHz fS = 8 kHz 20 pF capacitive load on all digital pins fS = 48 kHz 0.35 0.04 1.25 2.50 0.22 mA mA mA mA mA 0.10 mA fS = 96 kHz fS = 8 kHz fS = 48 kHz fS = 96 kHz fS = 8 kHz See Table 4 0.18 0.02 0.68 1.33 0.12 mA mA mA mA mA The zero-cross detection of the beep path is not supported at AVDD1, AVDD2 < 2.2 V. Rev. B | Page 8 of 84 ADAU1381 TYPICAL POWER MANAGEMENT MEASUREMENTS Master clock = 12.288 MHz, PLL is active in integer mode at a 256 × fS input rate for fS = 48 kHz, analog and digital input tones are −1 dBFS with a frequency of 1 kHz. Analog input and output are simultaneously active. Pseudo differential stereo input is routed to ADCs, and DACs are routed to stereo line output with a 16 kΩ load. ADC input at −1 dBFS, DAC input at 0 dBFS. The speaker output is disabled. The serial port is configured in slave mode. The beep path is disabled. The sound engine processing path is enabled. Current measurements are given in units of mA rms. Table 4. Mixer Boost and Power Management Conditions Operating Voltage AVDD = IOVDD = 3.3 V Power Management Mode 1 Normal (default) Extreme power saving Enhanced performance Power saving AVDD = IOVDD = 1.8 V Normal (default) Extreme power saving Enhanced performance Power saving 1 2 Mixer Boost Mode 2 Normal operation Boost Level 1 Boost Level 2 Boost Level 3 Normal operation Boost Level 1 Boost Level 2 Boost Level 3 Normal operation Boost Level 1 Boost Level 2 Boost Level 3 Normal operation Boost Level 1 Boost Level 2 Boost Level 3 Normal operation Boost Level 1 Boost Level 2 Boost Level 3 Normal operation Boost Level 1 Boost Level 2 Boost Level 3 Normal operation Boost Level 1 Boost Level 2 Boost Level 3 Normal operation Boost Level 1 Boost Level 2 Boost Level 3 Typical AVDD Current Consumption (mA) 16.84 16.88 16.92 17.00 15.66 15.68 15.70 15.75 17.43 17.50 17.53 17.63 16.25 16.28 16.31 16.38 15.15 15.19 15.23 15.30 14.03 14.05 14.07 14.12 15.71 15.76 15.81 15.89 14.59 14.62 14.65 14.71 Typical ADC THD + N (dB) 88.5 88.5 88.5 88.5 88.0 88.0 88.0 88.0 88.5 88.5 88.5 88.5 89.0 89.0 89.0 89.0 88.5 88.5 88.5 88.5 86.5 86.5 86.5 86.5 88.5 88.5 88.5 88.5 88.0 88.0 88.0 88.0 Typical Line Output THD + N (dB) 93.0 93.0 93.0 93.0 87.5 87.5 87.5 87.5 94.5 94.5 94.5 94.5 90.5 90.5 90.5 90.5 89.5 89.5 89.5 89.5 85.5 85.5 85.5 85.5 90.5 90.5 90.5 90.5 88.0 88.0 88.0 88.0 Set by Register 0x4009, Bits[4:1], and Register 0x4029, Bits[5:2]. Set by Register 0x4009, Bits[6:5]. DIGITAL FILTERS Table 5. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode All modes, typ value is for 48 kHz Factor Min 0.4375 × fS Typ 21 ±0.015 24 27 0.5 × fS 0.5625 × fS 70 22.9844/fS Rev. B | Page 9 of 84 479 Max Unit kHz dB kHz kHz dB μs ADAU1381 Parameter DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode Factor Min Typ 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 48 kHz mode, typ value is for 48 kHz 96 kHz mode, typ value is for 96 kHz 0.4535 × fS 0.3646 × fS 35 22 69 Max ±0.01 ±0.05 0.5 × fS 0.5 × fS 0.5465 × fS 0.6354 × fS 24 48 26 61 70 70 25/fS 11/fS 521 115 Unit kHz kHz dB dB kHz kHz kHz kHz dB dB μs μs DIGITAL INPUT/OUTPUT SPECIFICATIONS −25°C < TA < +85°C, IOVDD = 1.62 V to 3.63 V, unless otherwise specified. Table 6. Parameter HIGH LEVEL INPUT VOLTAGE (VIH) LOW LEVEL INPUT VOLTAGE (VIL) INPUT LEAKAGE HIGH LEVEL OUTPUT VOLTAGE (VOH) LOW LEVEL OUTPUT VOLTAGE (VOL) Conditions/Comments IOVDD ≥ 2.97 V 1.8 V ≤ IOVDD ≤ 2.97 V IOVDD < 1.8 V IIH at VIH = 2.4 V IIL at VIL = 0.8 V IIL of MCKI IIH with internal pull-up IIL with internal pull-down IIH with internal pull-up IIL with internal pull-down For low drive strength, IOH = 2 mA and IOL = 2 mA at IOVDD = 3.3 V, IOH = 0.6 mA and IOL = 0.6 mA at IOVDD = 1.8 V; for high drive strength, IOH = 3 mA and IOL = 3 mA at IOVDD = 3.3 V, IOH = 0.9 mA and IOL = 0.9 mA at IOVDD = 1.8 V For low drive strength, IOH = 2 mA and IOL = 2 mA at IOVDD = 3.3 V, IOH = 0.6 mA and IOL = 0.6 mA at IOVDD = 1.8 V; for high drive strength, IOH = 3 mA and IOL = 3 mA at IOVDD = 3.3 V, IOH = 0.9 mA and IOL = 0.9 mA at IOVDD = 1.8 V INPUT CAPACITANCE Rev. B | Page 10 of 84 Min 0.7 × IOVDD Typ Max 0.3 × IOVDD 0.2 × IOVDD 0.1 × IOVDD ±0.17 ±0.17 −7 ±0.7 −7 5 ±0.18 IOVDD − 0.4 Unit V V V V μA μA μA μA μA μA μA V 0.4 V 5 pF ADAU1381 DIGITAL TIMING SPECIFICATIONS −25°C < TA < +85°C, IOVDD = 1.62 V to 3.63 V, unless otherwise specified. Table 7. Digital Timing Parameter MASTER CLOCK tMP Duty Cycle SERIAL PORT tBIL tBIH tLIS tLIH tSIS tSIH tSODM SPI PORT fCCLK,R fCCLK,R fCCLK,W fCCLK,W tCCPL tCCPH tCLS tCLH tCLPH tCDS tCDH tCOD I2C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tSCR tSCF tSDR tSDF tBFT DIGITAL MICROPHONE tDCF tDCR tDDV tDDH tMIN 50 30 Limit tMAX Unit Description 90.9 70 ns % Master clock (MCLK) period (that is, period of the signal input to MCKI). 70 ns ns ns ns ns ns ns BCLK pulse width low. BCLK pulse width high. LRCLK setup. Time to BCLK rising. LRCLK hold. Time from BCLK rising. DAC_SDATA setup. Time to BCLK rising. DAC_SDATA hold. Time from BCLK rising. ADC_SDATA delay. Time from BCLK falling in master mode. MHz MHz MHz MHz ns ns ns ns ns ns ns CCLK frequency, read operation, IOVDD = 1.8 V ± 10%. CCLK frequency, read operation, IOVDD = 3.3 V ± 10%. CCLK frequency, write operation, IOVDD = 1.8 V ± 10%. CCLK frequency, write operation, IOVDD = 3.3 V ± 10%. CCLK pulse width low. CCLK pulse width high. CLATCH setup. Time to CCLK rising. CLATCH hold. Time from CCLK rising. CLATCH pulse width high. CDATA setup. Time to CCLK rising. CDATA hold. Time from CCLK rising. COUT delay from CCLK edge to valid data, IOVDD = 1.8 V ± 10%. COUT delay from CCLK edge to valid data, IOVDD = 3.3 V ± 10%. 10 10 5 5 5 5 5 10 25 25 10 10 10 5 10 5 5 70 40 400 0.6 1.3 0.6 0.6 100 300 300 300 300 0.6 22 0 10 10 30 12 ns kHz μs μs μs μs ns ns ns ns ns μs ns ns ns ns SCL frequency. SCL high. SCL low. Setup time; relevant for repeated start condition. Hold time. After this period, the first clock is generated. Data setup time. SCL rise time. SCL fall time. SDA rise time. SDA fall time. Bus-free time. Time between stop and start. RL = 1 MΩ, CL = 14 pF. Digital microphone clock fall time. Digital microphone clock rise time. Digital microphone delay time for valid data. Digital microphone delay time for data three-stated. Rev. B | Page 11 of 84 ADAU1381 Digital Timing Diagrams tLIH tBIH BCLK tBIL tLIS LRCLK tSIS DAC_SDATA LEFT-JUSTIFIED MODE MSB MSB – 1 tSIH tSIS DAC_SDATA I2S MODE MSB tSIH tSIS tSIS DAC_SDATA RIGHT-JUSTIFIED MODE LSB MSB tSIH tSIH 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 08313-002 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 2. Serial Input Port Timing tBIH BCLK tBIL LRCLK ADC_SDATA LEFT-JUSTIFIED MODE tSODM MSB MSB – 1 tSODM ADC_SDATA I2S MODE MSB tSODM ADC_SDATA RIGHT-JUSTIFIED MODE MSB LSB 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 08313-003 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 3. Serial Output Port Timing Rev. B | Page 12 of 84 ADAU1381 tCLS tCLH tCLPH tCCPL tCCPH CLATCH CCLK CDATA tCDH tCDS COUT 08313-004 tCOD Figure 4. SPI Port Timing tSDR tSCH tDS tSCH SDA tSDF tSCR SCL tSCLL tSCS tSCF tBFT 2 Figure 5. I C Port Timing tDCF tDCR CLK DATA1/ DATA2 DATA1 DATA2 tDDH tDDV tDDV DATA1 DATA2 Figure 6. Digital Microphone Timing Rev. B | Page 13 of 84 08313-106 tDDH 08313-005 tSCLH ADAU1381 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Power Supply (AVDD1 = AVDD2) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +3.9 V ±20 mA –0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −25°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. In Table 9, θJA is the junction-to-ambient thermal resistance, θJB is the junction-to-board thermal resistance, θJC is the junction-to-case thermal resistance, ψJB is the in-use junction-to-top of package thermal resistance, and ψJT is the in-use junction-to-board thermal resistance. All characteristics are for a 4-layer board. Table 9. Thermal Resistance Package Type 32-Lead LFCSP 30-Ball WLCSP ESD CAUTION Rev. B | Page 14 of 84 θJA 35 39 θJB 19 7 θJC 2.5 0.5 ψJB 18 ψJT 0.3 Unit °C/W °C/W ADAU1381 32 31 30 29 28 27 26 25 MICBIAS BEEP LMIC/LMICN/MICD1 LMICP RMICP RMIC/RMICN/MICD2 AOUTL AOUTR PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADAU1381 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 NC AGND2 SPP NC SPN AVDD2 MCKO MCKI NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1381 GROUNDS. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. 08313-007 SDA/COUT ADDR0/CDATA ADDR1/CLATCH IOVDD DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 9 10 11 12 13 14 15 16 CM PDN AGND1 AVDD1 DVDDOUT DGND GPIO SCL/CCLK 1 2 3 4 5 6 A AGND2 AOUTL RMICP LMIC/ LIMICN/ MICD1 MICBIAS CM B SPP AOUTR RMIC/ RMICN/ MICD2 LMICP BEEP AGND1 C SPN LRCLK/ GPIO3 ADDR0/ CDATA SCL/ CCLK PDN AVDD1 D AVDD2 MCKO ADC_ SDATA/ GPIO1 ADDR1/ CLATCH GPIO DVDDOUT E MCKI BCLK/ GPIO2 DAC_ SDATA/ GPIO0 IOVDD SDA/ COUT DGND TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 8. 30-Ball, 6 × 5 WLCSP Pin Configuration (Bottom View) Rev. B | Page 15 of 84 08313-008 Figure 7. 32-Lead LFCSP Pin Configuration ADAU1381 Table 10. Pin Function Descriptions Pin No. LFCSP 1 WLCSP A6 Mnemonic CM Type 1 A_OUT 2 C5 PDN A_IN 3 4 5 B6 C6 D6 AGND1 AVDD1 DVDDOUT PWR PWR PWR 6 7 8 9 10 11 12 E6 D5 C4 E5 C3 D4 E4 DGND GPIO SCL/CCLK SDA/COUT ADDR0/CDATA ADDR1/CLATCH IOVDD PWR D_IO D_IN D_IO D_IN D_IN PWR 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 E3 D3 E2 C2 E1 D2 D1 C1 N/A B1 A1 N/A B2 A2 B3 DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 MCKI MCKO AVDD2 SPN NC SPP AGND2 NC AOUTR AOUTL RMIC/RMICN/MICD2 D_IO D_IO D_IO D_IO D_IN D_OUT PWR A_OUT 28 29 30 A3 B4 A4 RMICP LMICP LMIC/LMICN/MICD1 A_IN A_IN A_IN 31 32 B5 A5 BEEP MICBIAS THERM_PAD (Exposed Pad) A_IN PWR 1 A_OUT PWR A_OUT A_OUT A_IN Description VDD/2 V Common-Mode Reference. A 10 μF to 47 μF decoupling capacitor should be connected between this pin and ground to reduce crosstalk between the ADCs and DACs. The material of the capacitors is not critical. This pin can be used to bias external analog circuits, as long as they are not drawing current from CM (for example, the noninverting input of an op amp). Power-Down. Connecting this pin to GND powers down the chip. Resides in AVDD1 domain. Analog Ground. Analog Power Supply. Should be equivalent to AVDD2. Digital Core Supply Decoupling Point. The digital supply is generated from an onboard regulator and does not require an external supply. DVDDOUT should be decoupled to DGND with a 100 nF capacitor. Digital Ground. Dedicated General-Purpose Input/Output. I2C Clock/SPI Clock. I2C Data/SPI Data Output. I2C Address 0/SPI Data Input. I2C Address 1/SPI Latch Signal. Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD, which sets the highest allowed input voltage for the digital input pins. The current draw of this pin is variable because it is dependent on the loads of the digital outputs. IOVDD should be decoupled to DGND with a 100 nF capacitor. DAC Serial Input Data/General-Purpose Input and Output. ADC Serial Output Data/General-Purpose Input and Output. Serial Data Port Bit Clock/General-Purpose Input and Output. Serial Data Port Frame Clock/General-Purpose Input and Output. Master Clock Input. Master Clock Output. Analog Power Supply. Should be equivalent to AVDD1. Speaker Amplifier Negative Signal Output. No Connect. Speaker Amplifier Positive Signal Output. Speaker Amplifier Ground. No Connect. Line Output Amplifier, Right Channel. Line Output Amplifier, Left Channel. Right Channel Input from Single-Ended Source/Right Channel Input from Negative Pseudo Differential Source/Digital Microphone Input 2. Right Channel Input from Positive Pseudo Differential Source. Left Channel Input from Positive Pseudo Differential Source. Left Channel Input from Single-Ended Source/Left Channel Input from Negative Pseudo Differential Source/Digital Microphone Input 1. Beep Signal Input. Microphone Bias. Exposed Pad. The exposed pad is connected internally to the ADAU1381 grounds. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the ground plane. A_OUT = analog output, A_IN = analog input, PWR = power, D_IO = digital input/output, D_OUT = digital output, and D_IN = digital input. Rev. B | Page 16 of 84 ADAU1381 0 0.10 –10 0.08 –20 0.06 –30 0.04 MAGNITUDE (dBFS) –40 –50 –60 –70 0.02 0 –0.02 –0.04 –80 –0.06 –90 –0.08 –0.10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (NORMALIZED TO fS) 08313-009 –100 Figure 9. ADC Decimation Filter, 64× Oversampling, Normalized to fS 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 08313-012 MAGNITUDE (dBFS) TYPICAL PERFORMANCE CHARACTERISTICS 0.50 FREQUENCY (NORMALIZED TO fS) Figure 12. ADC Decimation Filter Pass-Band Ripple, 128× Oversampling, Normalized to fS 0 0.04 –10 –20 –30 MAGNITUDE (dBFS) MAGNITUDE (dBFS) 0.02 0 –0.02 –0.04 –40 –50 –60 –70 –80 –0.06 –90 0.10 0.15 0.20 0.25 0.30 0.35 0.40 FREQUENCY (NORMALIZED TO fS) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FREQUENCY (NORMALIZED TO fS) 1.0 08313-013 0.05 08313-010 0 –100 Figure 13. ADC Decimation Filter, Double-Rate Mode, Normalized to fS Figure 10. ADC Decimation Filter Pass-Band Ripple, 64× Oversampling, Normalized to fS 0 0.04 –10 0.02 MAGNITUDE (dBFS) –30 –40 –50 –60 –70 0 –0.02 –0.04 –80 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FREQUENCY (NORMALIZED TO fS) Figure 11. ADC Decimation Filter, 128× Oversampling, Normalized to fS 1.0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 FREQUENCY (NORMALIZED TO fS) 0.40 08313-014 –0.06 –90 08313-011 MAGNITUDE (dBFS) –20 Figure 14. ADC Decimation Filter Pass-Band Ripple, Double-Rate Mode, Normalized to fS Rev. B | Page 17 of 84 0 0.05 –10 0.04 –20 0.03 –30 0.02 MAGNITUDE (dBFS) –40 –50 –60 –70 0.01 0 –0.01 –0.02 –80 –0.03 –90 –0.04 –0.05 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (NORMALIZED TO fS) 08313-015 –100 Figure 15. DAC Interpolation Filter, 64× Oversampling, Normalized to fS 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 FREQUENCY (NORMALIZED TO fS) 08313-018 MAGNITUDE (dBFS) ADAU1381 Figure 18. DAC Interpolation Filter Pass-Band Ripple, 128× Oversampling, Normalized to fS 0.20 0 –10 0.15 –20 MAGNITUDE (dBFS) MAGNITUDE (dBFS) 0.10 0.05 0 –0.05 –30 –40 –50 –60 –70 –0.10 –80 –0.15 –90 0.10 0.15 0.20 0.25 0.30 0.35 0.40 FREQUENCY (NORMALIZED TO fS) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 08313-019 0.05 0.40 08313-020 –100 0 08313-016 –0.20 FREQUENCY (NORMALIZED TO fS) Figure 16. DAC Interpolation Filter Pass-Band Ripple, 64× Oversampling, Normalized to fS Figure 19. DAC Interpolation Filter, Double-Rate Mode, Normalized to fS 0 0.20 –10 0.15 –20 MAGNITUDE (dBFS) –40 –50 –60 –70 0.05 0 –0.05 –0.10 –80 –0.15 –90 –100 –0.20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FREQUENCY (NORMALIZED TO fS) Figure 17. DAC Interpolation Filter, 128× Oversampling, Normalized to fS 1.0 08313-017 MAGNITUDE (dBFS) 0.10 –30 0 0.05 0.10 0.15 0.20 0.25 0.30 FREQUENCY (NORMALIZED TO fS) 0.35 Figure 20. DAC Interpolation Filter Pass-Band Ripple, Double-Rate Mode, Normalized to fS Rev. B | Page 18 of 84 ADAU1381 0 0 –10 –20 –20 –40 THD + N (dB) THD + N (dB) –30 –50 –60 –40 –60 –70 –80 –80 –90 1 10 100 SPEAKER OUTPUT POWER (mW) 600 Figure 21. THD + N vs. Speaker Output Power, 8 Ω Load, 3.3 V Supply 1 10 SPEAKER OUTPUT POWER (mW) 100 08313-122 –100 08313-121 –100 Figure 22. THD + N vs. Speaker Output Power, 8 Ω Load, 1.8 V Supply Rev. B | Page 19 of 84 ADAU1381 SYSTEM BLOCK DIAGRAMS IOVDD 10µF AVDD1 10µF 10µF + + 0.1µF 0.1µF + AVDD2 47µF 0.1µF + MICBIAS 8Ω SPEAKER OUT – 0.1µF 0.1µF 49.9kΩ AVDD2 AVDD1 DVDDOUT 10µF IOVDD DIFFERENTIAL INPUT (LEFT) MICBIAS + 100pF LMIC/LMICN/MICD1 SPN LMICP SPP 10kΩ 10kΩ 10Ω 220µF AOUTL 10µF STEREO SINGLE-ENDED HEADPHONE OUTPUT 49.9kΩ 10kΩ ADAU1381 100pF DIFFERENTIAL INPUT (RIGHT) 10µF 10kΩ RMIC/RMICN/MICD2 49.9kΩ LEFT_OUT + AOUTR 10kΩ 10kΩ 10Ω 220µF + RMICP CM 10µF 100nF + RIGHT_OUT 10µF 49.9kΩ GPIO 10µF STEREO HEADPHONE AMPLIFIER GPIO BEEP DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 EXTERNAL BEEP INPUT MCKI PDN PDN 08313-021 MCKO SYSTEM CONTROLLER AGND2 49.9Ω AGND1 ADDR1/CLATCH ADDR0/CDATA SDA/COUT SCL/CCLK 2.2pF DGND MCKO 49.9Ω THERM_PAD (EXPOSED PAD) EXTERNAL MCLK SOURCE SERIAL DATA Figure 23. System Block Diagram with Differential Inputs Rev. B | Page 20 of 84 ADAU1381 IOVDD 10µF AVDD1 10µF 10µF + + 0.1µF 0.1µF + AVDD2 47µF 0.1µF + MICBIAS 8Ω SPEAKER OUT – 0.1µF 0.1µF 2kΩ AVDD2 AVDD1 DVDDOUT MICBIAS IOVDD MICBIAS + 100pF SPN 0.1µF 10kΩ SPP ANALOG MIC 1 LMIC/LMICN/MICD1 10µF 10kΩ LMICP AOUTR CM ADAU1381 ANALOG MIC 2 10kΩ 10kΩ 0.1µF 10kΩ 10kΩ 10Ω 220µF 10µF + RMIC/RMICN/MICD2 49.9kΩ LEFT_OUT 100pF MICBIAS 2kΩ 10Ω 220µF AOUTL CM + 49.9kΩ STEREO SINGLE-ENDED HEADPHONE OUTPUT CM CM RMICP 100nF + RIGHT_OUT 10µF GPIO 10µF STEREO HEADPHONE AMPLIFIER GPIO BEEP DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 EXTERNAL BEEP INPUT MCKI MCKO PDN 08313-022 PDN SYSTEM CONTROLLER AGND2 49.9Ω AGND1 ADDR1/CLATCH ADDR0/CDATA SDA/COUT SCL/CCLK 2.2pF DGND MCKO 49.9Ω THERM_PAD (EXPOSED PAD) EXTERNAL MCLK SOURCE SERIAL DATA Figure 24. System Block Diagram with Analog Microphone Inputs Rev. B | Page 21 of 84 ADAU1381 IOVDD 10µF AVDD1 10µF 10µF + + 0.1µF 0.1µF + AVDD2 47µF 0.1µF + MICBIAS 8Ω SPEAKER OUT – 0.1µF 0.1µF AVDD2 AVDD1 DVDDOUT IOVDD MICBIAS + 100pF SPN SINGLE-ENDED STEREO INPUT 10kΩ SPP 10kΩ 10µF CM 49.9kΩ 10Ω 220µF AOUTL LMIC/LMICN/MICD1 AOUTR LMICP LEFT_OUT + 1kΩ STEREO SINGLE-ENDED HEADPHONE OUTPUT 10kΩ CM ADAU1381 100pF 10µF 1kΩ RMIC/RMICN/MICD2 10kΩ CM 49.9kΩ 10kΩ 10kΩ 10Ω 220µF + RMICP CM 100nF + RIGHT_OUT 10µF GPIO 10µF STEREO HEADPHONE AMPLIFIER GPIO BEEP DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 EXTERNAL BEEP INPUT MCKI MCKO PDN 08313-023 PDN SYSTEM CONTROLLER AGND2 49.9Ω AGND1 ADDR1/CLATCH ADDR0/CDATA SDA/COUT SCL/CCLK 2.2pF DGND MCKO 49.9Ω THERM_PAD (EXPOSED PAD) EXTERNAL MCLK SOURCE SERIAL DATA Figure 25. System Block Diagram with Single-Ended Stereo Line Inputs Rev. B | Page 22 of 84 ADAU1381 IOVDD 10µF AVDD1 10µF 10µF + + 0.1µF 0.1µF + AVDD2 47µF 0.1µF + MICBIAS 8Ω SPEAKER OUT – 0.1µF 0.1µF AVDD2 AVDD1 DVDDOUT IOVDD MICBIAS + 100pF SPN BCLK OR MCLKO 10kΩ SPP 10kΩ 10Ω 220µF AOUTL LMIC/LMICN/MICD1 AOUTR LMICP 10kΩ ADAU1381 100pF RMIC/RMICN/MICD2 10kΩ 10kΩ RMICP 10kΩ 10Ω 220µF + 1kΩ LEFT_OUT + STEREO DIGITAL MIC INPUT STEREO SINGLE-ENDED HEADPHONE OUTPUT CM 100nF + RIGHT_OUT 10µF GPIO 10µF STEREO HEADPHONE AMPLIFIER GPIO BEEP DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 EXTERNAL BEEP INPUT MCKI MCKO PDN 08313-024 PDN SYSTEM CONTROLLER AGND2 49.9Ω AGND1 ADDR1/CLATCH ADDR0/CDATA SDA/COUT SCL/CCLK 2.2pF DGND MCKO BCLK 49.9Ω THERM_PAD (EXPOSED PAD) EXTERNAL MCLK SOURCE SERIAL DATA Figure 26. System Block Diagram with Stereo Digital Microphone Inputs Rev. B | Page 23 of 84 ADAU1381 THEORY OF OPERATION The ADAU1381 is a low power audio codec with an integrated, fixed-function audio processing sound engine. It is an all-in-one package that offers high quality audio, low power, small size, and many advanced features. The stereo ADC and stereo DAC each have a dynamic range (DNR) performance of at least 96.5 dB and a total harmonic distortion plus noise (THD + N) performance of at least −90 dB. The serial data port is compatible with I2S, leftjustified, right-justified, and TDM modes for interfacing to digital audio data. The operating voltage range is 1.8 V to 3.65 V, with an on-board regulator generating the internal digital supply voltage. The record path includes very flexible input configurations that can accept differential or single-ended analog microphone inputs as well as two stereo digital microphone inputs. There is also a beep input pin (BEEP) dedicated to analog beep signals that are common in digital still camera applications. A microphone bias pin that can power electrets-type microphones is also available. Each input signal has its own programmable gain amplifier (PGA) for input volume adjustment. An automatic level control (ALC) is built into the sound engine to maintain a constant input recording volume. The ADCs and DACs are high quality, 24-bit Σ-Δ converters that operate at selectable 64× or 128× oversampling rates. The base sampling rate of the converters is set by the input clock rate and can be further scaled with the converter control register settings. The converters can operate at sampling frequencies from 8 kHz to 96 kHz. The ADCs and DACs also include very fine-step digital volume controls. The playback path allows input signals and DAC outputs to be mixed into speaker and/or line outputs. The speaker driver is capable of driving 400 mW into an 8 Ω load. The fixed-function sound engine contains a digital audio processing flow optimized for digital still camera stereo audio processing. However, the flexibility offered by the built-in sound engine allows this codec to be used for a wide variety of low power applications. Signal processing blocks included in the sound engine include the following: • • • • • • • • Wind noise detection and autofiltering Dual-band compression with programmable crossover, compression curves, and timing Programmable multiband equalizer Configurable notch filter Enhanced stereo capture algorithm Automatic level control Digital volume control Multiplexers for signal routing The ADAU1381 can generate its internal clocks from a wide range of input clocks by using the on-board fractional PLL. The PLL accepts inputs from 11 MHz to 20 MHz. The ADAU1381 is provided in a small, 32-lead, 5 mm × 5 mm lead frame chip scale package (LFCSP) with an exposed bottom pad, or a 30-ball (6 × 5 bump), 3.4 mm × 2.64 mm wafer level chip scale package (WLCSP). Rev. B | Page 24 of 84 ADAU1381 STARTUP, INITIALIZATION, AND POWER POWER-UP SEQUENCE This section details the procedure for setting up the ADAU1381 properly. Figure 27 provides an overview of how to initialize the IC. If AVDD1 and AVDD2 are from the same supply, they can power up simultaneously. If AVDD1 and AVDD2 are from separate supplies, then AVDD1 should be powered up first. IOVDD should be applied simultaneously with AVDD1, if possible. START ARE AVDD1 AND AVDD2 SUPPLIED SEPARATELY? YES NO NO CAN AVDD1 AND AVDD2 BE SIMULTANEOUSLY SUPPLIED? The ADAU1381 uses a power-on reset (POR) circuit to reset the registers upon power-up. The POR monitors the DVDDOUT pin and generates a reset signal whenever power is applied to the chip. During the reset, the ADAU1381 is set to the default values documented in the register map (see the Control Register Map section). YES SUPPLY POWER TO AVDD1 SUPPLY POWER TO AVDD1/AVDD2 PINS SIMULTANEOUSLY SUPPLY POWER TO AVDD2 The POR is also used to prevent clicks and pops on the speaker driver output. The power-up sequencing and timing involved is described in Figure 28 in this section, and in Figure 36 and Figure 37 of the Speaker Output section. SUPPLY POWER TO IOVDD WAIT 14ms FOR POWER-ON RESET AND INITIALIZATION ROM BOOT A self-boot ROM initializes the memories after the POR has completed. When the self-boot sequence is complete, the control registers are accessible via the I2C/SPI control port and should then be configured as required for the application. Typically, with a 10 μF capacitor on AVDD1, the power supply ramp-up, POR, and self-boot combined take approximately 14 ms. CONFIGURE CLOCK GENERATION REGISTER 16384 (0x4000) AND REGISTER 16386 (0x4002) WAIT FOR PLL LOCK (2.4ms TO 3.5ms) ENABLE DIGITAL POWER TO FUNCTIONAL SUBSYSTEMS REGISTER 16512 (0x4080) AND REGISTER 16513 (0x4081) 08313-025 SET UP SOUND ENGINE REGISTERS FOR CUSTOMIZED SIGNAL PATH (INCLUDING VOLUME, SAMPLE RATES, FILTER COEFFICIENTS) INITIALIZATION COMPLETE Figure 27. Initialization Sequence MAIN SUPPLY ENABLED MAIN SUPPLY DISABLED AVDD1 1.5V AVDD2 1.5V DVDDOUT 1.35V POWER-UP (INTERNAL SIGNAL) 0.95V POR ACTIVE POR ACTIVATES POR COMPLETE/SELF-BOOT INITIATES SELF-BOOT COMPLETE/MEMORY IS ACCESSIBLE IOVDD 14ms INPUT/OUTPUT PINS HIGH-Z ACTIVE Figure 28. Power-Up and Power-Down Sequence Timing Diagram Rev. B | Page 25 of 84 HIGH-Z 08313-026 INTERNAL MCLK (NOT TO SCALE) ADAU1381 CLOCK GENERATION AND MANAGEMENT The ADAU1381 uses a flexible clocking scheme that enables the use of many different input clock rates. The PLL can be bypassed or used, resulting in two different approaches to clock management. For more information about clocking schemes, PLL configuration, and sampling rates, see the Clocking and Sampling Rates section. Case 1: PLL Is Bypassed If the PLL is bypassed, the core clock is derived directly from the master clock (MCLK) input. The rate of this clock must be set properly in Register 16384 (0x4000), clock control, Bits[2:1], input master clock frequency. When the PLL is bypassed, supported external clock rates are 256 × fS, 512 × fS, 768 × fS, and 1024 × fS, where fS is the base sampling rate. The core clock of the chip is off until Register 16384 (0x4000), clock control, Bit 0, core clock enable, is set to 1. Case 2: PLL Is Used The core clock to the entire chip is off during the PLL lock acquisition period. The user can poll the lock bit to determine when the PLL has locked. After lock is acquired, the ADAU1381 can be started by setting Register 16384 (0x4000), clock control, Bit 0, core clock enable, to 1.This bit enables the core clock to all the internal functional blocks of the ADAU1381. PLL Lock Acquisition During the lock acquisition period, only Register 16384 (0x4000), clock control, and Register 16386 (0x4002), PLL control, are accessible through the control port. Reading from or writing to any other address is prohibited until Register 16384 (0x4000), clock control, Bit 0, core clock enable, and Register 16386 (0x4002), PLL control, Bit 1, PLL lock, are set to 1. Register 16386 (0x4002), PLL control, is a 48-bit register for which all bits must be written with a single continuous write to the control port. The PLL lock time is dependent on the MCLK rate. Typical lock times are provided in Table 11. Table 11. PLL Lock Time PLL Mode Fractional Integer Fractional Fractional Fractional Fractional Fractional MCLK Frequency 12 MHz 12.288 MHz 13 MHz 14.4 MHz 19.2 MHz 19.68 MHz 19.8 MHz Lock Time (Typical) 3.0 ms 2.96 ms 2.4 ms 2.4 ms 2.98 ms 2.98 ms 2.98 ms ENABLING DIGITAL POWER TO FUNCTIONAL SUBSYSTEMS To power subsystems in the device, they must be enabled using Register 16512 (0x4080), Digital Power-Down 0, and Register 16513 (0x4081), Digital Power-Down 1. The exact settings depend on the application. However, to proceed with the initialization sequence and access the RAMs and registers of the ADAU1381, Register 16512 (0x4080), Digital Power-Down 0, Bit 6, memory controller, and Bit 0, sound engine, must be enabled. SETTING UP THE SOUND ENGINE After the PLL has locked, the ADAU1381 is in an operational state, and the control port can be used to configure the sound engine. For more information, see the Sound Engine section. POWER REDUCTION MODES Sections of the ADAU1381 chip can be turned on and off as needed to reduce power consumption. These include the ADCs, the DACs, and the PLL. In addition, some functions can be set in the registers to operate in power saving, normal, or enhanced performance operation. See the respective portions of the General-Purpose Input/Outputs section for more information. Each digital filter of the ADCs and DACs can be set to a 64× or 128× (default) oversampling ratio. Setting the oversampling ratio to 64× lowers power consumption with a minimal impact on performance. See the Typical Performance Characteristics section and the Typical Power Management Measurements section for specifications and graphs of the filters. Detailed information regarding individual power reduction control registers can be found in the Control Register Map section of this document. Power-Down Pin (PDN) The power-down pin provides a simple hardware-based method for initiating low power mode without requiring access via the control port. When the PDN pin is lowered to the same potential as ground, the internal digital regulator is disabled and the device ceases to function, with power consumption dropping to a very low level. The common-mode voltage sinks, and all internal memories and registers lose their contents. When the PDN pin is raised back to the same potential as AVDD1, the device reinitializes in its default state, as described in the Power-Up Sequence section. POWER-DOWN SEQUENCE When powering down the device, the IOVDD, AVDD1, and AVDD2 supplies should be disabled at the same time, if possible, but only after the analog and speaker outputs have been muted. If the supplies cannot be disabled simultaneously, the preferred sequence is IOVDD first, AVDD2 second, and AVDD1 last. Rev. B | Page 26 of 84 ADAU1381 CLOCKING AND SAMPLING RATES SOUND ENGINE FRAME RATE fS / 0.5, 1, 1.5, 2, 3, 4, 6 CORE CLOCK AUTOMATICALLY SET TO 1024 × fS WHEN PLL CLOCK SOURCE SELECTED CONVERTER SAMPLING RATE ADCs DACs fS / 0.5, 1, 1.5, 2, 3, 4, 6 SERIAL PORT SAMPLING RATE SERIAL DATA INPUT/OUTPUT PORTS ADC_SDATA/GPIO1 fS / 0.5, 1, 1.5, 2, 3, 4, 6 08313-027 INPUT DIVIDE 1, 2, 3, 4 INPUT MASTER CLOCK FREQUENCY 256 × fS, 512 × fS, 768 × fS, 1024 × fS DAC_SDATA/GPIO0 MCKI f × (R + N/M) INTEGER, NUMERATOR, DENOMINATOR BCLK/GPIO2 f/X CLOCK CONTROL LRCLK/GPIO3 PLL CONTROL SOUND ENGINE Figure 29. Clock Routing Diagram CORE CLOCK The core clock divider generates a core clock either from the PLL or directly from MCLK and can be set in Register 16384 (0x4000), clock control. The core clock is always in 256 × fS mode. Direct MCLK frequencies must correspond to a value listed in Table 12, where fS is the base sampling frequency. PLL outputs are always in 1024 × fS mode, and the clock control register automatically sets the core clock divider to f/4 when using the PLL. For example, if the input to Bit 3 = 49.152 MHz (from PLL), then Bits[2:1] = 1024 × fS; therefore, fS = 49.152 MHz/1024 = 48 kHz Table 13. Clock Control Register (Register 16384, 0x4000) Bits 3 Bit Name Clock source select [2:1] Input master clock frequency 0 Core clock enable Table 12. Core Clock Frequency Dividers Input Clock Rate 256 × fS 512 × fS 768 × fS 1024 × fS Core Clock Divider f/1 f/2 f/3 f/4 Core Clock 256 × fS Settings 0: direct from MCKI pin (default) 1: PLL clock 00: 256 × fS (default) 01: 512 × fS 10: 768 × fS 11: 1024 × fS 0: core clock disabled (default) 1: core clock enabled SAMPLING RATES Clocks for the converters, the serial ports, and the sound engine are derived from the core clock. The core clock can be derived directly from MCLK, or it can be generated by the PLL. Register 16384 (0x4000), clock control, Bit 3, clock source select, determines the clock source. Bits[2:1], input master clock frequency, should be set according to the expected input clock rate selected by Bit 3, clock source select. The clock source select value also determines the core clock rate and the base sampling frequency, fS. The ADCs, DACs, and serial port share a common sampling rate that is set in Register 16407 (0x4017), Converter Control 0. Bits[2:0], converter sampling rate, set the sampling rate as a ratio of the base sampling frequency. The sound engine sampling rate is set in Register 16619 (0x40EB), sound engine frame rate, Bits[3:0], sound engine frame rate, and the serial port sampling rate is set in Register 16632 (0x40F8), serial port sampling rate, Bits[2:0], serial port control sampling rate. It is strongly recommended that the sampling rates for the converters, serial ports, and sound engine be set to the same value, unless appropriate compensation filtering is done within the sound engine. Rev. B | Page 27 of 84 ADAU1381 Fractional Mode Table 14 and Table 15 list the sampling rate divisions for common base sampling rates. Fractional mode is used when the MCLK is a fractional (R + (N/M)) multiple of the PLL output. Table 14. Base Sampling Rate Divisions for fS = 48 kHz Base Sampling Frequency fS = 48 kHz For example, if MCLK = 12 MHz and fS = 48 kHz, then Sampling Rate Scaling fS/1 fS/6 fS/4 fS/3 fS/2 fS/1.5 fS/0.5 Sampling Rate 48 kHz 8 kHz 12 kHz 16 kHz 24 kHz 32 kHz 96 kHz Table 15. Base Sampling Rate Divisions for fS = 44.1 kHz Base Sampling Frequency fS = 44.1 kHz Sampling Rate Scaling fS/1 fS/6 fS/4 fS/3 fS/2 fS/1.5 fS/0.5 Sampling Rate 44.1 kHz 7.35 kHz 11.025 kHz 14.7 kHz 22.05 kHz 29.4 kHz 88.2 kHz PLL Required Output = 1024 × 48 kHz = 49.152 MHz R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125) Common fractional PLL parameter settings for 44.1 kHz and 48 kHz sampling rates can be found in Table 16 and Table 17. Table 16. Fractional PLL Parameter Settings for fS = 44.1 kHz1 MCLK Input (MHz) 12 13 14.4 19.2 19.68 19.8 1 Input Divider (X) 1 1 2 2 2 2 Integer (R) 3 3 6 4 4 4 Denominator (M) 625 8125 125 125 1025 1375 Numerator (N) 477 3849 34 88 604 772 Desired core clock = 11.2896 MHz, PLL output = 45.1584 MHz. Table 17. Fractional PLL Parameter Settings for fS = 48 kHz1 PLL The PLL uses the MCLK as a reference to generate the core clock. PLL settings are set in Register 16386 (0x4002), PLL control. Depending on the MCLK frequency, the PLL must be set for either integer or fractional mode. The PLL can accept input frequencies in the range of 11 MHz to 20 MHz. All six bytes in the PLL control register must be written with a single continuous write to the control port. MCKI ÷X × (R + N/M) 1 08313-028 TO PLL CLOCK DIVIDER MCLK Input (MHz) 12 13 14.4 19.2 19.68 19.8 Input Divider (X) 1 1 2 2 2 2 Integer (R) 4 3 6 5 4 4 Denominator (M) 125 1625 75 25 205 825 Numerator (N) 12 1269 62 3 204 796 Desired core clock = 12.288 MHz, PLL output = 49.152 MHz. The PLL outputs a clock in the range of 41 MHz to 54 MHz, which should be taken into account when calculating PLL values and MCLK frequencies. Figure 30. PLL Block Diagram Integer Mode Integer mode is used when the MCLK is an integer (R) multiple of the PLL output (1024 × fS). For example, if MCLK = 12.288 MHz and fS = 48 kHz, then PLL Required Output = 1024 × 48 kHz = 49.152 MHz R = 49.152 MHz/12.288 MHz = 4 In integer mode, the values set for N and M are ignored. Rev. B | Page 28 of 84 ADAU1381 The ADC and DAC sampling rate can be set in Register 16407 (0x4017), Converter Control 0, Bits[2:0], converter sampling rate. The sound engine sampling rate and serial port sampling rate are similarly set in Register 16619 (0x40EB), sound engine frame rate, Bits[3:0], sound engine frame rate, and Register 16632 (0x40F8), serial port sampling rate, Bits[2:0], serial port control sampling rate, respectively. Table 18. Sampling Rates for 256 × 48 kHz Core Clock Core Clock 12.288 MHz Table 18 and Table 19 depict example sampling rate settings. The (1 × 256) case is the base sampling rate. Sampling Rate Divider (1 × 256) (6 × 256) (4 × 256) (3 × 256) (2 × 256) (1.5 × 256) (0.5 × 256) Sampling Rate 48 kHz 8 kHz 12 kHz 16 kHz 24 kHz 32 kHz 96 kHz Table 19. Sampling Rates for 256 × 44.1 kHz Core Clock Core Clock 11.2896 MHz Rev. B | Page 29 of 84 Sampling Rate Divider (1 × 256) (6 × 256) (4 × 256) (3 × 256) (2 × 256) (1.5 × 256) (0.5 × 256) Sampling Rate 44.1 kHz 7.35 kHz 11.025 kHz 14.7 kHz 22.05 kHz 29.4 kHz 88.2 kHz ADAU1381 RECORD SIGNAL PATH Analog Beep Input BEEP PGA The BEEP pin is used for mono single-ended signals, such as a beep warning. This signal bypasses the ADCs and the sound engine and is mixed directly into any of the analog outputs. LMIC/LMICN/ MICD1 PGA LMICP A BEEP pin input can also be amplified or muted by a PGA, up to 32 dB in Register 16392 (0x4008), digital microphone and analog beep control. The beep input must be enabled in Register 16400 (0x4010), microphone bias control and beep enable. LEFT ADC DECIMATORS CM RMIC/RMICN/ MICD2 Microphone Bias The MICBIAS pin provides a voltage reference for electret microphones. Register 16400 (0x4010), microphone bias control and beep enable, sets the operation mode of this pin. RIGHT ADC CM 08313-029 PGA RMICP Example Configurations Figure 31. Record Signal Path Diagram TO DECIMATORS LMIC/LMICN/ MICD1 The ADAU1381 can be configured for three types of microphone inputs: single-ended, differential, or digital. The LMIC/LMICN/ MICD1 and RMIC/RMICN/MICD2 pins encompass all of these configurations. LMICP and RMICP are used only during differential configurations (see Figure 31, the record signal path diagram). Each analog input has individual gain controls (boost or cut). These signals are routed to their respective right or left channel ADC. PGA LMICP CM TO DECIMATORS RMIC/RMICN/ MICD2 PGA RMICP 08313-030 INPUT SIGNAL PATH CM Analog Microphone Inputs For differential inputs, RMICN and RMICP denote the negative and positive input for the right channel, respectively. LMICN and LMICP denote the negative and positive input for the left channel, respectively. Figure 32. Stereo Digital Microphone Input Configuration LMIC/LMICN/ MICD1 PGA LMICP LMIC and RMIC inputs are single-ended line inputs. Together, they can be used as a stereo single-ended input. TO LEFT ADC CM RMIC/RMICN/ MICD2 When a digital PDM microphone connected to the MICD1 or MICD2 pin is used, Register 16392 (0x4008), digital microphone and analog beep control, must be set appropriately to enable the microphone input of choice. The MCKO output clock provides the clock for the microphone and must be set accordingly in Register 16384 (0x4000), clock control, depending on the streaming PDM rate of the microphone. The digital microphone signal bypasses the ADCs and is routed directly into the decimation filters. The digital microphone and ADCs share these decimation filters; therefore, both cannot be used simultaneously. Rev. B | Page 30 of 84 PGA RMICP TO RIGHT ADC CM Figure 33. Single-Ended Input Configuration 08313-031 Digital Microphone Inputs ADAU1381 Digital ADC Volume Control LMIC/LMICN/ MICD1 PGA LMICP The ADC output (digital input) volume can be adjusted in Register 16410 (0x401A), left ADC attenuator, Bits[7:0], left ADC digital attenuator, for the left channel digital volume control and in Register 16411 (0x401B), right ADC attenuator, Bits[7:0], right ADC digital attenuator, for right channel digital volume control. TO LEFT ADC CM RMIC/RMICN/ MICD2 High-Pass Filter CM A high-pass filter is used in the ADC path to remove dc offsets and can be selected in Register 16409 (0x4019), ADC control, Bit 5, high-pass filter select, where it can be enabled or disabled. 08313-032 PGA RMICP TO RIGHT ADC Figure 34. Differential Input Configuration DIGITAL DUAL-BAND AUTOMATIC LEVEL CONTROL (ALC) ANALOG-TO-DIGITAL CONVERTERS The ADAU1381 uses two 24-bit Σ-Δ analog-to-digital converters (ADCs) with selectable oversampling rates of either 64× or 128×. The full-scale input to the ADCs depends on AVDD1. At 3.3 V, the full-scale input level is 1.0 V rms. Inputs greater than the full-scale value result in clipping and distortion. The ADAU1381 includes an automatic level control (ALC). The ALC adjusts the input gain continuously for a varying input signal as dictated by the user-defined ALC settings. This allows the input recording level to remain constant. Although this functionality relates mainly to the record signal path, it is implemented digitally in the sound engine. Rev. B | Page 31 of 84 ADAU1381 PLAYBACK SIGNAL PATH LEFT PLAYBACK MIXER beep signal. The mixer can be controlled in Register 16415 (0x401F), playback mono mixer control. LINE OUT AMPLIFIER LEFT DAC AOUTL LEFT PLAYBACK BEEP GAIN MONO PLAYBACK BEEP GAIN BEEP FROM RECORD PGA The drivers are low noise, Class AB mono amplifiers designed to drive 8 Ω, 400 mW speakers. The output is differential and does not require external capacitors. The gain settings for the speaker drivers can be set in Register 16423 (0x4027), playback speaker output control. In this register, the drivers can be set for any of the four gain settings: 0 dB, 2 dB, 4 dB, or 6 dB. Additionally, the speaker driver can be muted or powered down completely. MONO OUTPUT GAIN MONO PLAYBACK MIXER SPP RIGHT PLAYBACK BEEP GAIN –1 SPN MONO OUTPUT INVERTER RIGHT DAC 08313-033 AOUTR RIGHT PLAYBACK LINE OUT MIXER AMPLIFIER Figure 35. Playback Signal Path Diagram OUTPUT SIGNAL PATHS The outputs of the ADAU1381 include a left and right line output and speaker driver. The beep input signal can be mixed into any of these outputs, with separate gain control for each path. DIGITAL-TO-ANALOG CONVERTERS The ADAU1381 uses two 24-bit Σ-Δ digital-to-analog converters (DACs) with selectable oversampling rates of 64× or 128×. The full-scale output of the DACs depends on AVDD1. At 3.3 V, the full-scale output level is 1.0 V rms. For pop and click suppression, an internal precharge sequence with output gating/enabling occurs after the mono driver is enabled. The sequence lasts for 8 ms, and then the internal mute signal rising edge occurs (see Figure 36 for the power-up sequence timing diagram). The power-down sequence is essentially the reverse of the startup sequence, as depicted in Figure 37. SPEAKER OUTPUT ENABLE MONO OUTPUT MUTE 4ms SPP HIGH-Z SPN HIGH-Z 4ms VCM VCM Digital DAC Volume Control A de-emphasis filter is used in the DAC path to remove high frequency noise in an FM system. This filter can be enabled or disabled in Register 16426 (0x402A), DAC control.