ADAU1592ASVZ-RL

Class-D Audio Power Amplifier ADAU1592 FEATURES Integrated stereo modulator and power stage 0.005% THD + N 101 dB dynamic range PSRR > 65 dB RDS-ON < 0.3 Ω (per transistor) Efficiency > 90% (8 Ω) EMI-optimized modulator On/off-mute pop-noise suppression Short-circuit protection Overtemperature protection GENERAL DESCRIPTION The ADAU1592 is a 2-channel, bridge-tied load (BTL) switching audio power amplifier with an integrated Σ-Δ modulator. The modulator accepts an analog input signal and generates a switching output to drive speakers directly. A digital, microcontroller-compatible interface provides control of reset, mute and PGA gain as well as output signals for thermal and overcurrent error conditions. The output stage can operate from supply voltages ranging from 9 V to 18 V. The analog modulator and digital logic operate from a 3.3 V supply. APPLICATIONS Flat panel televisions PC audio systems Mini-components FUNCTIONAL BLOCK DIAGRAM PGA0 PGA1 PVDD AINL PGA A1 A2 OUTL+ PGND PVDD B1 SLC_TH SLICER Σ-Δ MODULATOR B2 OUTL– PGND PVDD C1 C2 AINR PGA OUTR+ PGND PVDD PGA0 AVDD PGA1 D1 D2 OUTR– PGND LEVEL SHIFT AND DEAD TIME CONTROL VREF AGND DVDD DGND VOLTAGE REFERENCE fCLK/2 CLOCK OSCILLATOR MODE CONTROL LOGIC TEMPERATURE/ OVERCURRENT PROTECTION XTI XTO MO/ST STDN MUTE ERR OTW Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. 06749-001 ADAU1592 ADAU1592 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Audio Performance ...................................................................... 3 DC Specifications ......................................................................... 4 Power Supplies .............................................................................. 4 Digital I/O ..................................................................................... 4 Digital Timing............................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 15 Overview...................................................................................... 15 Modulator.................................................................................... 15 Slicer ............................................................................................. 15 Power Stage ................................................................................. 16 Gain.............................................................................................. 16 Protection Circuits ..................................................................... 16 Thermal Protection.................................................................... 16 Overcurrent Protection ............................................................. 16 Undervoltage Protection ........................................................... 17 Clock Loss Detection ................................................................. 17 Automatic Recovery from Protections .................................... 17 MUTE and STDN ...................................................................... 17 Power-Up/Power-Down Sequence .......................................... 18 DC Offset and Pop Noise .......................................................... 19 Selecting Value for CREF and CIN ............................................... 19 Mono Mode................................................................................. 19 Power Supply Bypassing ............................................................ 19 External Protection for PVDD > 15 V .................................... 20 Clock ............................................................................................ 20 Applications Information .............................................................. 21 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23 REVISION HISTORY 5/07—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADAU1592 SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, PVDD = 15 V, ambient temperature = 25°C, load impedance = 6 Ω, clock frequency = 24.576 MHz, measurement bandwidth = 20 Hz to 20 kHz, unless otherwise specified. AUDIO PERFORMANCE Table 1. Parameter OUTPUT POWER1 Min Typ 12 15 14.5 18 19.5 24 87 0.28 0.25 135 150 6 5.1 1.0 0.5 0.25 0.125 0.005 101 101 −90 19 25 31 37 78 100 158 280 65 Max Unit W W W W W W % Ω Ω °C °C A V VRMS VRMS VRMS VRMS % dB dB dB dB dB dB dB PVDD = 15 V, 6 Ω μV μV μV μV dB Test Conditions/Comments 1 kHz 1% THD + N, 8 Ω 10% THD + N , 8 Ω 1% THD + N, 6 Ω 10% THD + N, 6 Ω 1% THD + N , 4 Ω 10% THD + N , 4 Ω @ 18 W, 6 Ω @ TCASE = 25°C @ 100 mA @ 100 mA Die temperature Die temperature Peak current Full-scale output @ 1% THD + N PGA gain = 0 dB PGA gain = 6 dB PGA gain = 12 dB PGA gain = 18 dB 1 kHz, POUT = 1 W, PGA gain = 0 dB A-weighted, referred to 1% THD + N output A-weighted, measured with −60 dBFS input @ full-scale output voltage, 1% THD + N, 1 kHz PVDD = 15 V, 6 Ω EFFICIENCY RDS-ON Per High-Side Transistor Per Low-Side Transistor THERMAL CHARACTERISTICS Thermal Warning Active2 Thermal Shutdown Active OVERCURRENT SHUTDOWN ACTIVE PVDD UNDERVOLTAGE SHUTDOWN INPUT LEVEL FOR FULL-SCALE OUTPUT 5 TOTAL HARMONIC DISTORTION + NOISE (THD+N) SIGNAL-TO-NOISE RATIO (SNR) DYNAMIC RANGE (DNR) CROSSTALK (LEFT TO RIGHT OR RIGHT TO LEFT) AMPLIFIER GAIN PGA = 0 dB PGA = 6 dB PGA = 12 dB PGA = 18 dB OUTPUT NOISE VOLTAGE PGA = 0 dB PGA = 6 dB PGA = 12 dB PGA = 18 dB POWER SUPPLY REJECTION RATIO (PSRR) 1 2 99 99 20 Hz to 20 kHz, 1.5 V p-p ripple, inputs ac-coupled to AGND Output powers above 12 W at 4 Ω and above 18 W at 6 Ω are not continuous and are thermally limited by the package dissipation. Thermal warning flag is for indication of device TJ reaching close to shutdown temperature. Rev. 0 | Page 3 of 24 ADAU1592 DC SPECIFICATIONS Table 2. Parameter INPUT IMPEDANCE OUTPUT DC OFFSET VOLTAGE Min Typ 20 ±3 Max Unit kΩ mV Test Conditions/Comments AINL/AINR POWER SUPPLIES Table 3. Parameter ANALOG SUPPLY VOLTAGE (AVDD) DIGITAL SUPPLY VOLTAGE (DVDD) POWER TRANSISTOR SUPPLY VOLTAGE (PVDD) POWER-DOWN CURRENT AVDD DVDD PVDD MUTE CURRENT AVDD DVDD PVDD OPERATING CURRENT AVDD DVDD PVDD Min 3.0 3.0 9 Typ 3.3 3.3 15 5 0.1 0.082 13 1.7 5.4 13 2.7 44 Max 3.6 3.6 18 60 0.24 0.25 20 3.2 8 30 4 65 Unit V V V μA mA mA MUTE held low mA mA mA STDN and MUTE held high, no input mA mA mA Test Conditions/Comments STDN held low DIGITAL I/O Table 4. Parameter INPUT VOLTAGE Input Voltage High Input Voltage Low OUTPUT VOLTAGE Output Voltage High Output Voltage Low LEAKAGE CURRENT ON DIGITAL INPUTS Min 2 0.8 2 0.4 10 Typ Max Unit V V V V μA @ 2 mA @ 2 mA Test Conditions/Comments Rev. 0 | Page 4 of 24 ADAU1592 DIGITAL TIMING Table 5. Parameter tWAIT tINT tHOLD tOUTx+/OUTx− SW tOUTx+/OUTx− MUTE 1 2 Min 0.011 101 Typ 10002 650 2503 200 200 Unit ms ms μs μs μs Test Conditions/Comments Wait time for unmute Internal mute time Wait time for shutdown Time delay after MUTE held high until output starts switching Time delay after MUTE held low until output stops switching tWAIT MIN and tHOLD MIN are the minimum times for fast turn-on and do not guarantee pop-and-click suppression. tWAIT TYP is the recommended value for minimum pop and click during the unmute of the amplifier. The recommended value is 1 sec. It is calculated using the input coupling capacitor value and the input resistance of the device. See the Power-Up/Power-Down Sequence section. 3 tHOLD TYP is the recommended value for minimum pop and click during the mute of the amplifier. STDN INTERNAL MUTE tINT tHOLD MIN tWAIT MIN MUTE OUTx+/OUTx– NOTES 1. INTERNAL MUTE IS INTERNAL TO CHIP. 06749-002 Figure 2 .Timing Diagram (Minimum) STDN INTERNAL MUTE MUTE OUTx+/OUTx– tINT tHOLD TYP tWAIT TYP NOTES 1. INTERNAL MUTE IS INTERNAL TO CHIP. Figure 3. Timing Diagram (Typical) Rev. 0 | Page 5 of 24 06749-003 tOUTx+/OUTx– SW tOUTx+/OUTx– MUTE ADAU1592 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter DVDD to DGND AVDD to AGND PVDD to PGND1 MUTE/STDN Inputs Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) 1 THERMAL RESISTANCE Rating −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +20.0 V DGND − 0.3 V to DVDD + 0.3 V −40°C to +85°C −65°C to +150°C 150°C θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance Package Type LFCSP-48 TQFP-48 1 2 θJA1 24.6 24.7 θJC1,2 2.0 1.63 ΨJB 8.05 11 ΨJT 0.18 0.8 Unit °C/W °C/W With exposed pad (ePAD) soldered to 4-layer JEDEC standard PCB. Through the bottom (ePAD) surface. 260°C 215°C 220°C ESD CAUTION Includes any induced voltage due to inductive load. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 6 of 24 ADAU1592 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 PGND PGND PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PGND PGND OUTL– 1 OUTL– 2 OUTL– 3 OUTL+ 4 OUTL+ 5 OUTL+ 6 TEST1 7 TEST0 8 ERR 9 OTW 10 MO/ST 11 TEST3 12 PIN 1 INDICATOR ADAU1592 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 OUTR– OUTR– OUTR– OUTR+ OUTR+ OUTR+ TEST13 TEST12 AINR AINL TEST9 TEST8 NOTES 1. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO PGND, DGND, AND AGND FOR TQFP-48. 2. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO PGND AND DGND FOR LFCSP-48. PGA1 PGA0 MUTE STDN XTI XTO DGND DVDD AVDD AGND VREF SLC_TH 13 14 15 16 17 18 19 20 21 22 23 24 Figure 4. Pin Configuration Table 8. Pin Function Descriptions Pin Number 1, 2, 3 4, 5, 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31, 32, 33 Mnemonic OUTL− OUTL+ TEST1 TEST0 ERR OTW MO/ST TEST3 PGA1 PGA0 MUTE STDN XTI XTO DGND DVDD AVDD AGND VREF SLC_TH TEST8 TEST9 AINL AINR TEST12 TEST13 OUTR+ Type1 O O I I O O I I I I I I I O P P P P I I I I I I I I O Description Output of High Power Transistors, Left Channel Negative Polarity. Output of High Power Transistors, Left Channel Positive Polarity. Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Error Indicator (Active Low, Open-Drain Output). Overtemperature Warning Indicator (Active Low, Open-Drain Output). Mono/Stereo Mode Setting Pin for Stereo. Connect to DGND (for mono mode, connect to DVDD). Reserved for Internal Use. Connect to DVDD. Programmable Gain Amplifier Select, MSB. Programmable Gain Amplifier Select, LSB. Mute (Active Low Input). Shutdown/Reset Input (Active Low Input). Quartz Crystal Connection/External Clock Input. Quartz Crystal Connection/Clock Output. Digital Ground for Digital Circuitry. Internally connected to exposed pad (ePAD). Positive Supply for Digital Circuitry. Positive Supply for Analog Circuitry. (Can be tied to DVDD.) Analog Ground for Analog Circuitry. (See the notes in Figure 4 for connection to ePAD.) AVDD/2 Voltage Reference Connection for External Filter. Slicer Threshold Adjust. (Connect to AGND via a resistor for slicer operation.) Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Analog Input Left Channel. Analog Input Right Channel. Reserved for Internal Use. Connect to DGND. Reserved for Internal Use. Connect to DGND. Output of High Power Transistors, Right Channel Positive Polarity. Rev. 0 | Page 7 of 24 06749-004 ADAU1592 Pin Number 34, 35, 36 37, 38, 47, 48 39, 40, 41, 42, 43, 44, 45, 46 1 Mnemonic OUTR− PGND PVDD Type1 O P P Description Output of High Power Transistors. Right Channel Negative Polarity. Power Ground for High Power Transistors. Internally connected to ePAD. Positive Power Supply for High Power Transistors. I = input, O = output, P = power. Rev. 0 | Page 8 of 24 ADAU1592 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 0 –10 –20 –30 THD OR THD + N (dB) THD OR THD + N (dB) –40 –50 –60 –70 –80 –90 –100 –110 100m 1 10 06749-005 –40 –50 –60 –70 –80 –90 –100 –110 06749-008 THD + N THD + N THD THD –120 10m –120 10m 100m 1 10 OUTPUT POWER (W) OUTPUT POWER (W) Figure 5. THD or THD + N vs. Output Power, 4 Ω, PVDD = 9 V 0 –10 –20 –30 Figure 8. THD or THD + N vs. Output Power, 4 Ω, PVDD = 12 V 0 –10 –20 –30 THD OR THD + N (dB) THD OR THD + N (dB) –40 –50 –60 –70 –80 –90 –100 –110 06749-006 –40 –50 –60 –70 –80 –90 THD THD + N THD + N THD –100 –110 100m 1 10 100m 1 10 OUTPUT POWER (W) OUTPUT POWER (W) Figure 6. THD or THD + N vs. Output Power, 6 Ω, PVDD = 9 V 0 –10 –20 –30 Figure 9. THD or THD + N vs. Output Power, 6 Ω, PVDD = 12 V 0 –10 –20 –30 THD OR THD + N (dB) THD OR THD + N (dB) –40 –50 –60 –70 –80 –90 –100 –110 100m 1 10 06749-007 –40 –50 –60 –70 –80 –90 THD THD + N THD + N THD –100 –110 100m 1 10 OUTPUT POWER (W) OUTPUT POWER (W) Figure 7. THD or THD + N vs. Output Power, 8 Ω, PVDD = 9 V Figure 10. THD or THD + N vs. Output Power, 8 Ω, PVDD = 12 V Rev. 0 | Page 9 of 24 06749-010 –120 10m –120 10m 06749-009 –120 10m –120 10m ADAU1592 0 –10 –20 –30 30 POWER LIMITED DUE TO PACKAGE DISSIPATION 25 OUTPUT POWER (W) 4Ω THD OR THD + N (dB) –40 –50 –60 –70 –80 –90 –100 –110 THD THD + N 20 6Ω 15 8Ω 10 5 6 7 8 9 10 11 12 13 14 15 16 17 18 OUTPUT POWER (W) PVDD (V) Figure 11. THD or THD + N vs. Output Power, 4 Ω, PVDD = 15 V 30 Figure 14. Output Power vs. PVDD @ 0.1% THD + N 0 –10 –20 –30 THD OR THD + N (dB) OUTPUT POWER (W) POWER LIMITED DUE TO PACKAGE DISSIPATION 25 4Ω 6Ω 20 8Ω 15 –40 –50 –60 –70 –80 –90 –100 –110 100m 1 10 06749-012 THD + N 10 THD 5 OUTPUT POWER (W) PVDD (V) Figure 12. THD or THD + N vs. Output Power, 6 Ω, PVDD = 15 V 0 –10 –20 –30 THD OR THD + N (dB) OUTPUT POWER (W) Figure 15. Output Power vs. PVDD @ 1% THD + N 40 POWER LIMITED DUE TO PACKAGE DISSIPATION 35 30 6Ω 25 8Ω 20 15 10 THD 5 0 4Ω –40 –50 –60 –70 –80 –90 –100 –110 06749-013 THD + N 100m 1 10 6 7 8 9 10 11 12 13 14 15 16 17 18 OUTPUT POWER (W) PVDD (V) Figure 13. THD or THD + N vs. Output Power, 8 Ω, PVDD = 15 V Figure 16. Output Power vs. PVDD @ 10% THD + N Rev. 0 | Page 10 of 24 06749-016 –120 10m 06749-015 –120 10m 0 6 7 8 9 10 11 12 13 14 15 16 17 18 06749-014 100m 1 10 06749-011 –120 10m 0 ADAU1592 0 –10 –20 –30 –40 –50 OUTPUT (dBr) OUTPUT (dBr) 0dBr = 15W 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 06749-017 0dBr = 15W –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 22 FREQUENCY (kHz) FREQUENCY (kHz) Figure 17. FFT @ 1 W, 6 Ω, PVDD = 15 V, PGA = 0 dB, 1 kHz Sine 0 –10 –20 –30 –40 OUTPUT (dBr) Figure 20. FFT @ 1 W, 6 Ω, PVDD = 15 V, PGA = 0 dB, 19 kHz and 20 kHz Sine 0 –10 –20 –30 –40 OUTPUT (dB) 0dBr = 15W –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –50 –60 –70 –80 –90 –100 –110 LEFT TO RIGHT RIGHT TO LEFT 06749-018 0 2 4 6 8 10 12 14 16 18 20 100 1k FREQUENCY (Hz) 10k FREQUENCY (kHz) Figure 18. FFT @ −60 dBFS, 6 Ω, PVDD = 15 V, PGA = 0 dB, 1 kHz Sine 0 –10 –20 –30 –40 OUTPUT (dBV) OUTPUT (dB) Figure 21. Crosstalk @ 1 W, 6 Ω, PVDD = 15 V, PGA = 0 dB 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 LEFT TO RIGHT RIGHT TO LEFT –50 –60 –70 –80 –90 –100 –110 –120 –130 0 2 4 6 8 10 12 14 16 18 20 06749-019 100 1k FREQUENCY (Hz) 10k FREQUENCY (kHz) Figure 19. FFT No Input, 6 Ω, PVDD = 15 V, PGA = 0 dB Figure 22. Crosstalk @ Full Scale, 6 Ω, PVDD = 15 V, PGA = 0 dB Rev. 0 | Page 11 of 24 06749-022 –140 –120 20 06749-021 –120 20 06749-020 –160 ADAU1592 0 –10 –20 –30 THD OR THD + N (dB) –40 –50 –60 –70 –80 –90 –100 –110 06749-023 THD + N THD 100 1k FREQUENCY (Hz) 10k FREQUENCY (Hz) Figure 23. THD or THD + N vs. Frequency @ 1 W, 4 Ω, PVDD = 15 V, PGA = 0 dB Figure 26. Frequency Response @ 1 W, 6 Ω, PVDD = 15 V, PGA = 0 dB 41 39 37 35 33 PGA 12dB PGA 18dB 0 –10 –20 –30 THD OR THD + N (dB) –40 GAIN (dB) –50 –60 –70 –80 –90 –100 –110 –120 20 100 THD THD + N 31 29 27 25 23 21 19 17 PGA 0dB PGA 6dB 06749-024 1k FREQUENCY (Hz) 10k 100 1k FREQUENCY (Hz) 10k Figure 24. THD or THD + N vs. Frequency @ 1 W, 6 Ω, PVDD = 15 V, PGA = 0 dB 0 –10 –20 –30 THD OR THD + N (dB) 0 –10 –20 –30 PSRR (dB) –40 –50 –60 –70 –80 Figure 27. Gain vs. Frequency @ 1 W, 6 Ω, PVDD = 15 V –40 –50 –60 –70 –80 –90 –100 –110 –120 20 100 THD THD + N –90 06749-025 1k FREQUENCY (Hz) 10k 100 1k FREQUENCY (Hz) 10k Figure 25. THD or THD + N vs. Frequency @ 1 W, 8 Ω, PVDD = 15 V, PGA = 0 dB Figure 28. PSRR vs. Frequency, No Input Signal, Ripple = 1.5 V p-p, PVDD =15 V, 6 Ω Rev. 0 | Page 12 of 24 06749-028 –100 20 06749-027 15 20 06749-026 –120 20 100 1k 10k 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 –1.8 –2.0 20 OUTPUT (dBr) ADAU1592 90 80 70 12 11 10 POWER LIMITED DUE TO PACKAGE DISSIPATION EFFICIENCY (%) 60 50 40 30 20 10 POWER LIMITED DUE TO PACKAGE DISSIPATION 06749-029 POWER DISSIPATION (W) 0 5 10 15 20 25 30 9 8 7 6 5 4 3 2 1 06749-032 06749-034 06749-033 0 0 0 5 10 15 20 25 OUTPUT POWER (W) OUTPUT POWER PER CHANNEL, STEREO MODE (W) Figure 29. Efficiency vs. Output Power, 15 V, 4 Ω Figure 32. Power Dissipation vs. Output Power, 15 V, 4 Ω, Stereo Mode, Both Channels Driven 6 100 90 5 80 70 POWER DISSIPATION (W) EFFICIENCY (%) 4 60 50 40 30 20 10 06749-030 3 2 1 POWER LIMITED DUE TO PACKAGE DISSIPATION 0 5 10 15 20 25 POWER LIMITED DUE TO PACKAGE DISSIPATION 0 0 5 10 15 20 25 0 OUTPUT POWER (W) OUTPUT POWER PER CHANNEL, STEREO MODE (W) Figure 30. Efficiency vs. Output Power, 15 V, 6 Ω 100 90 80 70 Figure 33. Power Dissipation vs. Output Power, 15 V, 6 Ω, Stereo Mode, Both Channels Driven 4 60 50 40 30 20 10 06749-031 POWER DISSIPATION (W) 3 EFFICIENCY (%) 2 1 0 0 0 5 10 15 20 25 OUTPUT POWER (W) 0 5 10 15 20 OUTPUT POWER PER CHANNEL, STEREO MODE (W) Figure 31. Efficiency vs. Output Power, 15 V, 8 Ω Figure 34. Power Dissipation vs. Output Power, 15 V, 8 Ω, Stereo Mode, Both Channels Driven Rev. 0 | Page 13 of 24 ADAU1592 6 30 3Ω 25 4Ω 5 OUTPUT POWER (W) 4 20 6Ω 8Ω PDISS MAX (W) 3 15 2 10 1 5 POWER LIMITED DUE TO PACKAGE DISSIPATION 9 10 11 12 13 14 15 16 17 18 06749-038 06749-040 06749-039 06749-035 0 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 TAMBIENT (°C) PVDD (V) Figure 35. Power Dissipation Derating vs. Ambient Temperature 40 POWER LIMITED DUE TO PACKAGE DISSIPATION 35 3Ω 30 4Ω Figure 38. Output Power vs. PVDD, Mono Mode, 60 dB THD + N 90 80 70 EFFICIENCY (%) OUTPUT POWER (W) 25 20 15 10 5 0 6Ω 8Ω 60 50 40 30 20 10 POWER LIMITED DUE TO PACKAGE DISSIPATION 9 10 11 12 13 14 15 16 17 18 06749-036 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 OUTPUT POWER (W) PVDD (V) Figure 36. Output Power vs. PVDD, Mono Mode, 20 dB THD + N 30 3Ω 4Ω Figure 39. Efficiency vs. Output Power, Mono Mode, 15 V, 3 Ω 90 80 70 25 OUTPUT POWER (W) 8Ω 15 EFFICIENCY (%) 06749-037 20 6Ω 60 50 40 30 20 10 5 10 POWER LIMITED DUE TO PACKAGE DISSIPATION 0 9 10 11 12 13 14 15 16 17 18 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 OUTPUT POWER (W) PVDD (V) Figure 37. Output Power vs PVDD, Mono Mode, 40 dB THD + N Figure 40. Efficiency vs. Output Power, Mono Mode, 15 V, 4 Ω Rev. 0 | Page 14 of 24 ADAU1592 THEORY OF OPERATION OVERVIEW The ADAU1592 is a 2-channel high performance switching audio power amplifier. Each of the two Σ-Δ modulators converts a single-ended analog input into a 2-level PDM output. This PDM pulse stream is output from the internal full differential power stage. The ADAU1592 has built-in circuits to suppress the turn-on and turn-off pop and click. The ADAU1592 also offers extensive thermal and overcurrent protection circuits. feature allows the user to adjust the slicer to the desired value and to limit the output power. For input signals higher than the set threshold, the slicer clips the input signal to the modulator. This adds distortion due to clipping of the signal input to the modulator. This is especially helpful in applications where the output power available needs to be reduced instead of reducing the supply voltage. Figure 41 is a plot showing THD + N vs. the input level at 0 dB PGA, 15 V, and 6 Ω, and demonstrates the difference between a device with and without the slicer. 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 SLICER 1.1V SLICER 1.17V SLICER 1.24V SLICER 1.32V SLICER DISABLED MODULATOR The modulator is a 5th-order Σ-Δ with feedback from the power stage connected internally. This helps reduce the external connections. The 5th order modulator switches to a lower order near full-scale inputs. The modulator gain is optimized at 19 dB for 15 V operation. The Σ-Δ modulator outputs a pulse density modulation (PDM) 1-bit stream, which does not produce distinct sharp peaks and harmonics in the AM band like conventional fixed-frequency PWM. The Σ-Δ modulators require feedback to generate PDM stream with respect to the input. The feedback for the modulators comes from the power stage. This helps reduce the nonlinearity in the power stages and achieve excellent THD + N performance. The feedback also helps in achieving good PSRR. In the ADAU1592, the feedback from the power stage is internally connected. This helps reduce the external connections for ease in PCB layout. The Σ-Δ modulators operate in a discrete time domain and Nyquist frequency limit, which is half the sampling frequency. The modulator uses the master clock of 12.288 MHz. This is generated by dividing the external clock input by 2. This sets the fS/2 around 6.144 MHz. This is sufficient for the audio bandwidth of 22 kHz. The modulator shapes the quantization noise and transfers it outside the audio band. The noise floor rises sharply above 20 kHz. This ensures very good signal-tonoise ratio (SNR) in the audio band of 20 kHz. The 6.144 MHz bandwidth allows the modulator order to be set around the 5th order. The modulator uses proprietary dynamic hysteresis to reduce the switching rate or frequency to around 700 kHz. This reduces the switching losses and achieves good efficiency. The dynamic hysteresis helps the modulator to continuously track the change in PVDD and the input level to keep the modulator stable. THD + N (dB) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 INPUT (V rms) Figure 41. THD + N vs. Input Level @ PGA = 0 dB, 15 V Figure 42 depicts the typical output power vs input at different slicer settings. 25 20 OUTPUT POWER (W) 15 SLICER DISABLED SLICER 1.32V SLICER 1.24V SLICER 1.17V SLICER 1.10V 10 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 INPUT (V rms) Figure 42. Typical Output Power vs. Input, at Different Slicer Settings SLICER The ADAU1592 has a built-in slicer block following the PGA and before the modulator. The slicer block is essentially a hard limiter included for limiting the input signal to the modulator. This, in turn, limits the output power at a given supply voltage. The slicer in the ADAU1592 is normally inactive at lower input levels but is activated as soon as the peak input voltage exceeds the set threshold. The threshold can be set externally by connecting a resistor from SLC_TH (Pin 24) to ground. This From Figure 42, it can be seen that the slicer effectively reduces the output power depending on its setting. Internally, the slicer block receives the input from the PGA. Figure 43 shows the block for slicer threshold adjust, SLC_TH (Pin 24). Rev. 0 | Page 15 of 24 06749-042 0 06749-041 ADAU1592 VCM with PGA set to 0 dB. PGA0 (Pin 14) and PGA1 (Pin 13) are used for setting the desired gain. 50kΩ SLICER_LEVEL The gain can be set according to Table 10. Note that the amplifier full-scale input level changes as per the PGA gain setting. PIN 24 (SLC_TH) VTH Table 10. Gain Settings PGA1 (Pin 13) 0 0 1 1 PGA0 (Pin 14) 0 1 0 1 PGA Gain (dB) 0 6 12 18 Amplifier Gain (dB) 19 25 31 37 Full-Scale Input Level (VRMS) 1 0.5 0.25 0.125 REXTERNAL Figure 43. Block for Slicer Threshold Adjust, SLC_TH 06749-043 The slicer threshold can be set externally using a resistor as follows: VTH = (AVDD/2) × (50 kΩ/50 kΩ + REXTERNAL) where: AVDD = 3.3 V typical. VTH is the voltage threshold at which the slicer is activated. The following equation can be used to calculate the input signal at which the slicer becomes active: PROTECTION CIRCUITS The ADAU1592 includes comprehensive protection circuits. It includes thermal warning, thermal overheat, and overcurrent or short-circuit protection on the outputs. The ERR and OTW outputs are open drain and require external pull-up resistors. The outputs are capable of sinking 10 mA. The open-drain outputs are useful in multichannel applications where more than one ADAU1592 is used. The error outputs of multiple ADAU1592s can be OR’ed to simplify the system design. The logic outputs of the error flags ease the system design of using a microcontroller. VIN RMS = VTH 1.414 × 0.9 Therefore, for AVDD = 3.3 V typical and VTH = 1.1 V, REXTERNAL = 24.9 kΩ VIN RMS = 0.864 V Thus, the slicer is activated at and above 0.864 VIN RMS. This feature allows the user to set the slicer and, in turn, reduces the output power at a given supply voltage.To disable the slicer, SLC_TH should be connected to AGND. Table 9 shows the typical values for REXTERNAL. Table 9. Typical REXTERNAL Values VTH ( V) 1.1 1.17 1.24 1.32 REXTERNAL (kΩ) 24.9 20.5 16.5 12.4 VIN RMS (V) 0.864 0.919 0.974 1.037 THERMAL PROTECTION Thermal protection in the ADAU1592 is categorized into two error flags: one as thermal warning and the other as thermal shutdown. When the device junction temperature reaches near 135°C (±5°C), the ADAU1592 outputs a thermal warning error flag by pulling OTW (Pin 10) low. This flag can be used by the microcontroller in the system for indication to the user or can be used to lower the input level to the amplifier to prevent thermal shutdown. The device continues operation until shutdown temperature is reached. When the device junction temperature exceeds 150°C, the device outputs an error flag by pulling ERR (Pin 9) low. This error flag is latched. To restore the operation, MUTE (Pin 15) needs to be toggled to low and then to high again. OVERCURRENT PROTECTION The overcurrent protection in the ADAU1592 is set internally at a 5 A peak output current. The device protects the output devices against excessive output current by pulling ERR (Pin 9) low. This error flag is latched. To restore the normal operation, MUTE (Pin 15) needs to be toggled to low and then to high again. The error flag is useful for the microcontroller in the system to indicate abnormal operation and to initiate the audio MUTE sequence. The device senses the short-circuit condition on the outputs after the LC filter. Typical short-circuit conditions include shorting of the output load and shorting to either PVDD or PGND. POWER STAGE The ADAU1592 power stage comprises a high-side PMOS and a low-side NMOS. The typical RDS-ON is ~ 300 mΩ. The PMOSNMOS stage does not need an external bootstrap capacitor and simplifies the high-side driver design. The power stage also has comprehensive protection circuits to detect the faults in typical applications. See the Protection Circuits section for further details. GAIN The gain of the amplifier is set internally using feedback resistors optimized for 15 V nominal operation. The typical gain values are tabulated in Table 1. The typical gain is 19 dB Rev. 0 | Page 16 of 24 ADAU1592 UNDERVOLTAGE PROTECTION The ADAU1592 is also comprised of an undervoltage protection circuit, which senses the undervoltage on PVDD. When the PVDD supply goes below the operating threshold, the output FETs are turned to a high-Z condition. In addition, the device issues an error flag by pulling ERR low. This condition is latched. To restore the operation, MUTE (Pin 15) needs to be toggled to low and then to high again. Option 2: Using ERR Option 2 is similar to Option 1 except the ERR pin is tied to MUTE instead of OTW. See the circuit in Figure 45. ADAU1592 DVDD R1 100k Ω ERR 9 C1 47µF MUTE 15 D1 1N4148 TO MUTE LOGIC INPUT The ADAU1592 includes a clock loss detection circuit. In case the master clock to the part is lost, the ERR flag is set. This condition is latched. To restore operation, MUTE needs to be toggled low and high again. Figure 45. Option 2 Schematic for Autorecovery AUTOMATIC RECOVERY FROM PROTECTIONS In certain applications, it is desired for the amplifier to recover itself from thermal protection without the need for system microcontroller intervention. The ADAU1592 thermal protection circuit issues two error signals for this purpose: one a thermal warning (OTW) and the other a thermal shutdown (ERR). With the two error signals, there are two options available for using the protections: • • In this case, the part goes into shutdown mode due to any of the error generating events like output overcurrent, overtemperature, missing PVDD or DVDD, or clock loss. The part recovers itself based on the same circuit operation in Figure 44. However, if the part goes into error mode due to overtemperature, then the device would have reached its maximum limit of 150°C (15°C to 20°C higher than Option 1). If it goes into error mode due to an overcurrent from a short circuit on the speaker outputs, then the part keeps itself recycling on and off until the short circuit is removed. It is possible that, with this operation, the part is subjected to a much higher temperature and current stress continuously. This, in turn, reduces the part’s reliability in the long term. Therefore, using Option 1 for autorecovery from thermal protection and using the system microcontroller to indicate to the user of an error condition is recommended. Option 1: Using OTW Option 2: Using ERR The following sections provide further details of these two options. Option 1: Using OTW The OTW pin is pulled low when the die temperature reaches 130°C to 135°C. This pin can be wired to MUTE as shown in Figure 44, using an RC circuit. ADAU1592 DVDD R1 100k Ω OTW 10 C1 47µF MUTE 15 MUTE AND STDN The MUTE and STDN pins are 3.3 V logic-compatible inputs used to control the turn-on/turn-off for ADAU1592. The STDN input is active low when the STDN pin is pulled low and the device is in its energy saving mode. The modulator is inactive and the power stage is in high-Z state. The high logic level input on the STDN pin wakes up the device. The modulator is running internally but the power stage is still in high-Z state. When the MUTE pin is pulled high, the power stage becomes active with a soft turn-on to avoid the pop and clicks. The low level on the MUTE pin disables the power stage and is recommended to be used to mute the audio output. See the Power-Up/Power-Down Sequence section for more details. D1 1N4148 TO MUTE LOGIC INPUT Figure 44. Option 1 Schematic for Autorecovery The low logic level on OTW also pulls down the MUTE pin. The bridge is shut down and starts cooling or the die temperature starts reducing. When it reaches around 120°C, the OTW signal starts going high. While this pin is tied to a capacitor with a resistor pulled to DVDD, the voltage on this pin starts rising slowly towards DVDD. When it reaches the CMOS threshold, MUTE is deasserted and the amplifier starts functioning again. This cycle repeats itself depending on the input signal conditions and the temperature of the die. This option allows device operation that is safely below the shutdown temperature of 150°C and allows the amplifier to recover itself without the need for microcontroller intervention. 06749-044 Rev. 0 | Page 17 of 24 06749-045 CLOCK LOSS DETECTION ADAU1592 POWER-UP/POWER-DOWN SEQUENCE Figure 46 shows the recommended power-up sequence for the ADAU1592. AVDD/DVDD STDN PVDD AVDD/DVDD PVDD tINT INTERNAL MUTE tWAIT STDN MUTE tINT INTERNAL MUTE OUTx+/OUTx– PVDD/2 tWAIT MUTE PVDD/2 OUTx+/OUTx– AVDD/2 AINx tPDL-H AINx AVDD/2 tINT = 650ms @ 24.576MHz CLOCK tWAIT < TINT NOTES 1. INTERNAL MUTE IS INTERNAL TO CHIP. 06749-047 NOTES 1. INTERNAL MUTE IS INTERNAL TO CHIP. Figure 46. Recommended Power-Up Sequence The ADAU1592 has a special turn-on sequence that consists of a fixed internal mute time during which the power stage does not start switching. This internal mute time depends on the master clock frequency and is 650 ms for a 24.576 MHz clock. Also, the internal mute overrides the external MUTE and ensures that the power stage does not switch on immediately even if the external MUTE signal is pulled high in less than 650 ms after STDN. The power stage starts switching only after 650 ms plus a small propagation delay of 200 μs has elapsed and after MUTE is deasserted. Therefore, it is recommended to ensure that tWAIT > tINT to prevent the pop and click during power-on. Ensure that the MUTE signal is delayed by at least tWAIT seconds after STDN. This time is approximately 10 times the charging time constant of the input coupling capacitor. For example, if the input coupling capacitor is 4.7 μF, the time constant is T = R × C = 20 kΩ × 4.7 μF = 94 ms Therefore, tWAIT = 10 × T = 940 ms ~ 1 sec. tWAIT is needed to ensure that the input capacitors are charged to AVDD/2 before turning on the power stage. When tWAIT < tINT, the power stage does not start switching until 650 ms has elapsed after STDN (see Figure 47). However, note that this method does not ensure pop-and-click suppression because of less than recommended or insufficient tWAIT 06749-046 tINT = 650ms @ 24.576MHz CLOCK tPDL-H = 200µs tWAIT = 10 × RIN × CIN Figure 47. Power-Up Sequence, tWAIT < tINT The ADAU1592 uses three separate supplies: AVDD (3.3 V analog for PGA and modulator), DVDD (3.3 V digital for control logic and clock oscillator), and PVDD (9 V to 18 V power stage and level shifter). Separate pins are provided for the AVDD, DVDD, and PVDD supply connections, as well as AGND, DGND, and PGND. In addition, the ADAU1592 incorporates a built-in undervoltage lockout logic on DVDD as well as PVDD. This helps detect undervoltage operation and eliminates the need to have an external mechanism to sense the supplies. The ADAU1592 monitors the DVDD and PVDD supply voltages and prevents the power stage from turning on if either of the supplies are not present or are below the operating threshold. Therefore, if DVDD is missing or below the operating threshold, for example, the power stage does not turn on, even if PVDD is present, or vice versa. Because this protection is only present on DVDD and PVDD and not on AVDD, shorting both AVDD and DVDD externally or generating AVDD and DVDD from one power source is recommended. This ensures that both AVDD and DVDD supplies are tracking each other and avoids the need to monitor the sequence with respect to PVDD. This also ensures minimal pop and click during power-up. When using separate AVDD and DVDD supplies, ensure that both supplies are stable before unmuting or turning on the power stage. Similarly, during shutdown, pulling MUTE to logic low before pulling STDN down is recommended. However, where a fault event occurs, the power stage shuts down to protect the part. In this case, depending on the signal level, there is some pop at the speaker. Rev. 0 | Page 18 of 24 ADAU1592 To shut down the power supplies, it is highly recommended to mute the amplifier before shutting down any of the supplies. After MUTE is shut down, shut down the supplies in the following order: PVDD, DVDD, then AVDD. Where AVDD and DVDD are generated from a single source, turn PVDD off before DVDD and AVDD, and after issuing MUTE. The amount of pop at the turn-on depends on tWAIT, which in turn depends on the values of CREF and CIN. The following section describes how to select the value for the CREF and CIN. SELECTING VALUE FOR CREF AND CIN The CREF is the capacitor used for filtering the noise from AVDD on VREF. VREF is used for the biasing of the internal analog amplifier as well as the modulator. Therefore, care must be taken to ensure that the recommended minimum value is used. The minimum recommended value for CREF is 4.7 μF. CIN is the input coupling capacitor and is used to decouple the inputs from the external dc. The CIN value determines the low corner frequency of the amplifier. It can be determined from the following equation: f LOW = 1 2 × π × R IN × C IN DC OFFSET AND POP NOISE This section describes the cause of dc offset and pop noise during turn-on/turn-off. The turn-on/turn-off pop in amplifiers depend mainly on the dc offset, therefore, care must be taken to reduce the dc offset at the output. The first stage of ADAU1592 has an inverting PGA amplifier, as shown in Figure 48. CHANGES WITH PGA SETTING RFB CIN AINx RIN TO NEXT STAGE VREF CREF VMIS 06749-048 RSOURCE where: fLOW is the low corner frequency (−3 dB). RIN is the input resistance (20 kΩ). CIN is the input coupling capacitor. Note that RIN = 20 kΩ, provided that RSOURCE is 15 V As the PVDD supply voltage approaches 15 V and above, the available headroom with maximum PVDD reduces. As with any switching amplifier, the outputs swing to full rail and the amount of overshoots due to parasitic elements of the package/board would be significant. Therefore, for reliable and safe operation it is recommended to add external protection circuits for applications requiring supply voltages >15 V. The use of an RC snubber or a Schottky diode on the outputs should be considered. The RC snubber should be connected between the OUTx+ and OUTx− pins for each channel. The typical recommended values are 10 Ω and 680 pF. Also, both of these components must be placed close to the output pins. For two channels, two resistors and two capacitors are needed. If Schottky diodes are preferred, the diodes must be from each OUTx−/OUTx+ pin to PVDD/PGND. So in total eight diodes are needed for two channels. The Schottky diodes need to be placed close to the output pins to be effective. Option 2: Using a Ceramic Resonator The ADAU1592 can also be used with ceramic resonators similar to crystal by using the XTI and XTO pins. Option 3: Using an External Clock The ADAU1592 can be provided with an external clock of 24.576 MHz at the XTI pin. The logic level for the clock input should be in the range of 3.3 V and 50% typical duty cycle. For systems using multiple ADAU1592s, it is recommended to use only one clock source if the ADAU1592s share the same power supply to prevent the beat frequencies of asynchronous clocks from appearing in the audio band. Multiple ADAU1592s can be connected in a daisy chain by providing or generating a master clock from one ADAU1592 and subsequently connecting its XTO output to the XTI input of the next ADAU1592, and so on. However, using a simple logic buffer between the XTO pin of one ADAU1592 to the XTI pin of the next ADAU1592 is recommended. Because the clock output is now buffered, it can be connected to the XTI inputs of the remaining ADAU1592s, depending on the fanout capability of the logic buffer used. Rev. 0 | Page 20 of 24 ADAU1592 APPLICATIONS INFORMATION For applications with PVDD > 15 V, add components R1 and R2 = 10 Ω typical, C5 and C6 = 680 pF typical, and D1 through D8 = CRS01/02. 3.3V PVDD 100nF 100nF 100nF 100nF 1µF 470µF TEST3 AVDD DVDD PVDD ANALOG INPUT LEFT 2.2µF AINL 100kΩ OUTL+ PVDD D1 D2 PVDD SLC_TH D3 D4 PVDD VREF OUTR+ D5 D6 R2 10Ω C6 680pF L3 C3 R1 10Ω C5 680pF L1 C1 L2 C2 R3 OUTL– 4.7µF 100nF ADAU1592 ANALOG INPUT RIGHT 2.2µF AINR 100k Ω OUTR– PVDD D7 D8 L4 C4 STDN SYSTEM LOGIC MICROCONTROLLER MUTE ERR OTW TEST12 TEST13 MO/ST TEST0 TEST1 TEST8 TEST9 AGND DGND PGND XTO 24.576MHz CRYSTAL OR RESONATOR XTI Figure 49. Typical Stereo Application Circuit Table 11. R3—Slicer Threshold Resistor VTH ( V) 1.1 1.17 1.24 1.32 R3 (kΩ) 24.9 20.5 16.5 12.4 Table 12. Output Filter Component Values Load Impedance (Ω) 4 6 8 Inductance L1 to L4 (μH) 10 15 22 Capacitance C1 to C4 (μF) 1.5 1 0.68 Rev. 0 | Page 21 of 24 06749-049 ADAU1592 3.3V PVDD 100nF 100nF 100nF 100nF 1µF 470µF MO/ST TEST3 AVDD DVDD PVDD ANALOG INPUT LEFT 2.2µF AINL 100kΩ OUTL+ PVDD D1 D2 PVDD SLC_TH D3 D4 R1 10Ω C5 680pF L1 C1 L2 C2 R3 OUTL– VREF 4.7µF 100nF OUTR+ ADAU1592 ANALOG INPUT RIGHT 2.2µF AINR 100k Ω OUTR– STDN SYSTEM LOGIC MICROCONTROLLER MUTE ERR OTW TEST12 TEST13 TEST0 TEST1 TEST8 TEST9 AGND DGND PGND XTO 24.576MHz CRYSTAL OR RESONATOR XTI Figure 50. Typical Mono Application Circuit For component values, refer to the stereo application circuit in Figure 49. Rev. 0 | Page 22 of 24 06749-050 ADAU1592 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 0.30 0.23 0.18 48 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 6.75 BSC SQ EXPOSED PAD (BOTTOM VIEW) 5.25 5.10 SQ 4.95 0.50 0.40 0.30 25 24 12 13 0.25 MIN 5.50 REF 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 51. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters 0.75 0.60 0.45 1.00 REF SEATING PLANE 1.20 MAX 48 1 9.20 9.00 SQ 8.80 37 36 PIN 1 37 36 BOTTOM VIEW (PINS UP) 48 1 TOP VIEW (PINS DOWN) EXPOSED PAD 12 13 25 24 25 24 12 13 5.10 SQ 1.05 1.00 0.95 7.20 7.00 SQ 6.80 0.20 0.09 7° 3.5° 0° VIEW A 0.15 0.05 0.50 BSC LEAD PITCH 0.08 MAX COPLANARITY 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ABC Figure 52. 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-48-5) Dimensions shown in millimeters ORDERING GUIDE Model ADAU1592ACPZ1 ADAU1592ACPZ-RL1 ADAU1592ACPZ-RL71 ADAU1592ASVZ1 ADAU1592ASVZ-RL1 ADAU1592ASVZ-RL71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 042507-A VIEW A Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 13” Tape and Reel 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP], 13” Tape and Reel 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP], 7” Tape and Reel Package Option CP-48-1 CP-48-1 CP-48-1 SV-48-5 SV-48-5 SV-48-5 Z = RoHS Compliant Part. Rev. 0 | Page 23 of 24 ADAU1592 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06749-0-5/07(0) Rev. 0 | Page 24 of 24