ADAU1777BCBZ

Four-ADC, Two-DAC, Low Power Codec with Audio Processor ADAU1777 Data Sheet FEATURES APPLICATIONS Programmable audio processing engine Fast (up to 768 kHz) and slow processing paths Biquad filters, limiters, volume controls, and mixing Low latency, 24-bit ADCs and DACs 102 dB SNR (through PGA and ADC with A weighted filter) 108 dB combined SNR (through DAC and headphone with A weighted filter) Serial port sampling rate from 8 kHz to 192 kHz 5 μs analog-to-analog latency 4 single-ended analog inputs, configurable as microphone or line inputs Dual stereo digital microphone inputs Stereo analog audio output, single-ended or differential, configurable as either line output or headphone driver PLL supporting any input clock rate from 8 MHz to 27 MHz Full duplex, asynchronous sample rate converters (ASRCs) Power supplies Analog and digital input/output of 1.8 V to 3.3 V Digital signal processing (DSP) core of 1.1 V to 1.8 V Low power I2C and SPI control interfaces, self boot from I2C EEPROM 7 multipurpose (MPx) pins for digital controls and outputs Noise canceling handsets, headsets, and headphones Bluetooth® active noise canceling (ANC) handsets, headsets, and headphones Personal navigation devices Digital still and video cameras GENERAL DESCRIPTION The ADAU1777 is a codec with four inputs and two outputs that incorporates a digital processing engine to perform filtering, level control, signal level monitoring, and mixing. The path from the analog input to the DSP core to the analog output is optimized for low latency and is ideal for noise canceling headsets. With the addition of just a few passive components, a crystal, and an EEPROM for booting, the ADAU1777 provides a complete headset solution. Note that throughout this data sheet, multifunction pins, such as SCL/SCLK, are referred to either by the entire pin name or by a single function of the pin, for example, SCLK, when only that function is relevant. MICBIAS0 MICBIAS1 AIN0 MICROPHONE BIAS GENERATORS POWER MANAGEMENT IOVDD AVDD AVDD AVDD REG_OUT DVDD PD FUNCTIONAL BLOCK DIAGRAM LDO REGULATOR ADAU1777 ADC_SDATA1/CLKOUT/MP6 PGA PLL ADC CLOCK OSCILLATOR XTALI/MCLKIN XTALO PGA DMIC0_1/MP4 DMIC2_3/MP5 INPUT/OUTPUT SIGNAL ROUTING DIGITAL MICROPHONE INPUTS HPOUTLP/LOUTLP DAC ADC HPOUTLN/LOUTLN STEREO PDM MODULATOR HPOUTRP/LOUTRP DAC DAC_SDATA/MP0 ADC_SDATA0/PDMOUT/MP1 BCLK/MP2 LRCLK/MP3 SDA/MISO ADDR0/SS I2C/SPI CONTROL INTERFACE AND SELF BOOT ADDR1/MOSI AGND DGND CM AGND ADC DSP CORE: BIQUAD FILTERS, LIMITERS, VOLUME CONTROLS, MIXING AGND PGA BIDIRECTIONAL ASRCS SERIAL INPUT/ OUTPUT PORT SCL/SCLK ADC AIN3 HPOUTRN/LOUTRN PGA SELFBOOT AIN2 14796-001 AIN1 Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADAU1777 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Burst Mode Communication .................................................... 35 Applications ....................................................................................... 1 I2C Port ........................................................................................ 35 General Description ......................................................................... 1 SPI Port ........................................................................................ 38 Functional Block Diagram .............................................................. 1 Self Boot ....................................................................................... 39 Revision History ............................................................................... 3 Multipurpose Pins .......................................................................... 40 Specifications..................................................................................... 4 Push-Button Volume Controls ................................................. 40 Analog Performance Specifications ........................................... 4 Limiter Compression Enable .................................................... 40 Crystal Amplifier Specifications................................................. 8 Parameter Bank Switching ........................................................ 40 Digital Input/Output Specifications........................................... 8 Mute ............................................................................................. 40 Power Supply Specifications........................................................ 8 DSP Bypass Mode ...................................................................... 41 Typical Power Management Settings ......................................... 9 Serial Data Input/Output Ports .................................................... 42 Digital Filters Specifications ....................................................... 9 Tristating Unused Channels ..................................................... 42 Digital Timing Specifications ................................................... 10 Applications Information .............................................................. 45 Absolute Maximum Ratings .......................................................... 14 Power Supply Bypass Capacitors .............................................. 45 Thermal Resistance .................................................................... 14 Layout .......................................................................................... 45 ESD Caution ................................................................................ 14 Grounding ................................................................................... 45 Pin Configuration and Function Descriptions ........................... 15 PCB Stackup ................................................................................ 45 Typical Performance Characteristics ........................................... 17 Low Latency Register Settings ...................................................... 46 Theory of Operation ...................................................................... 24 Register Summary .......................................................................... 49 System Clocking and Power-Up ................................................... 25 Register Details ............................................................................... 52 Clock Initialization ..................................................................... 25 Clock Control Register .............................................................. 52 PLL................................................................................................ 25 PLL Denominator MSB Register .............................................. 53 Clock Output............................................................................... 26 PLL Denominator LSB Register ............................................... 53 Power Sequencing ...................................................................... 26 PLL Numerator MSB Register .................................................. 53 Signal Routing ................................................................................. 27 PLL Numerator LSB Register.................................................... 54 Input Signal Paths ........................................................................... 28 PLL Integer Setting Register ..................................................... 54 Analog Inputs .............................................................................. 28 PLL Lock Flag Register .............................................................. 55 Digital Microphone Input ......................................................... 29 CLKOUT Setting Selection Register........................................ 55 Analog-to-Digital Converters (ADCs) .................................... 29 Regulator Control Register ....................................................... 56 Output Signal Paths ........................................................................ 30 Core Control Register ................................................................ 56 Analog Outputs........................................................................... 30 Sleep on Program Address Count Register............................. 57 Digital-to-Analog Converters (DACs) .................................... 30 Filter Engine and Limiter Control Register ............................ 59 PDM Output ............................................................................... 30 DB Value Register 0 Read.......................................................... 59 Asynchronous Sample Rate Converters .................................. 31 DB Value Register 1 Read.......................................................... 60 Signal Levels ................................................................................ 31 DB Value Register 2 Read.......................................................... 60 Signal Processing ............................................................................ 32 Core Channel 0/Core Channel 1 Input Select Register......... 61 Instructions ................................................................................. 32 Core Channel 2/Core Channel 3 Input Select Register......... 62 Data Memory .............................................................................. 32 DAC Input Select Register ........................................................ 63 Parameters ................................................................................... 32 PDM Modulator Input Select Register .................................... 64 Control Port..................................................................................... 35 Rev. 0 | Page 2 of 108 Data Sheet ADAU1777 Serial Data Output 0/Serial Data Output 1 Input Select Register .........................................................................................65  Serial Port Control 0 Register.................................................... 85  Serial Data Output 2/Serial Data Output 3 Input Select Register .........................................................................................66  TDM Output Channel Disable Register .................................. 87  Serial Data Output 4/Serial Data Output 5 Input Select Register .........................................................................................67  PDM Pattern Setting Register ................................................... 89  Serial Data Output 6/Serial Data Output 7 Input Select Register .........................................................................................68  Serial Port Control 1 Register.................................................... 86  PDM Enable Register ................................................................. 88  MP0 Function Setting Register ................................................. 89  MP1 Function Setting Register ................................................. 90  ADC_SDATA0/ADC_SDATA1 Channel Select Register ......69  MP2 Function Setting Register ................................................. 91  Output ASRC0/Output ASRC1 Source Register.....................69  MP3 Function Setting Register ................................................. 91  Output ASRC2/Output ASRC3 Source Register.....................70  MP4 Function Setting Register ................................................. 92  Input ASRC Channel Select Register ........................................71  MP5 Function Setting Register ................................................. 93  ADC0/ADC1 Control 0 Register ..............................................72  MP6 Function Setting Register ................................................. 94  ADC2/ADC3 Control 0 Register ..............................................73  Push-Button Volume Settings Register .................................... 94  ADC0/ADC1 Control 1 Register ..............................................74  Push-Button Volume Control Assignment Register .............. 95  ADC2/ADC3 Control 1 Register ..............................................75  Debounce Modes Register ......................................................... 96  ADC0 Volume Control Register ...............................................75  Headphone Line Output Select Register .................................. 97  ADC1 Volume Control Register ...............................................76  Decimator Power Control Register .......................................... 97  ADC2 Volume Control Register ...............................................76  ADC3 Volume Control Register ...............................................77  ASRC Interpolator and DAC Modulator Power Control Register ......................................................................................... 99  PGA Control 0 Register..............................................................77  Analog Bias Control 0 Register ................................................. 99  PGA Control 1 Register..............................................................78  Analog Bias Control 1 Register ...............................................100  PGA Control 2 Register..............................................................78  Digital Pin Pull-Up Control 0 Register ..................................101  PGA Control 3 Register..............................................................79  Digital Pin Pull-Up Control 1 Register ..................................102  PGA Slew Control Register........................................................80  Digital Pin Pull-Down Control 0 Register ............................103  PGA 10 dB Gain Boost Register................................................80  Digital Pin Pull-Down Control 1 Register ............................103  Input and Output Capacitor Charging Register .....................81  Digital Pin Drive Strength Control 0 Register ......................104  DSP Bypass Path Register ..........................................................82  Digital Pin Drive Strength Control 1 Register ......................105  DSP Bypass Gain for PGA0 Register ........................................82  Fast Rate Control Register .......................................................105  DSP Bypass Gain for PGA1 Register ........................................82  DAC Interpolation Control Register ......................................106  MICBIAS0_1 Control Register..................................................83  Volume Control Bypass Register ............................................107  DAC Control Register ................................................................83  Outline Dimensions ......................................................................108  DAC0 Volume Control Register................................................84  Ordering Guide .........................................................................108  DAC1 Volume Control Register................................................84  Headphone Output Mutes Register ..........................................85  REVISION HISTORY 12/2016—Revision 0: Initial Version Rev. 0 | Page 3 of 108 ADAU1777 Data Sheet SPECIFICATIONS Master clock = 12.288 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, TA = 25°C, outputs line loaded with 10 kΩ. ANALOG PERFORMANCE SPECIFICATIONS AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted. Phase-locked loop (PLL) disabled, direct master clock. Table 1. Parameter ANALOG-TO-DIGITAL CONVERTERS (ADCs) ADC Resolution Digital Attenuation Step Digital Attenuation Range INPUT RESISTANCE Single-Ended Line Input Programmable Gain Amplifier (PGA) Inputs LINE INPUT Full-Scale Input Voltage Dynamic Range 1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Signal-to-Noise Ratio (SNR) 2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch Total Harmonic Distortion + Noise (THD + N) Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio (PSRR) PGA INPUT Full-Scale Input Voltage Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Test Conditions/Comments Min All ADCs Gain settings do not include 10 dB gain from PGA_x_BOOST settings; this additional gain does not affect input impedance; PGA_POP_DISx = 1 0 dB gain −12 dB gain 0 dB gain +35.25 dB gain PGA_ENx = 0, PGA_x_BOOST = 0, PGA_POP_DISx = 1 Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 3.3 V 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Typ Bits dB dB 14.3 32.0 20 0.68 kΩ kΩ kΩ kΩ AVDD/3.3 0.55 1.54 1.00 2.83 V rms V rms V p-p V rms V p-p 95 99 92 96 97 102 94 99 dB dB dB dB 96 100 92 96 0 98 103 96 100 40 dB dB dB dB mdB −90 −94 200 95 55 dB dB mV dB dB dB AVDD/3.3 0.55 1.54 1.00 2.83 V rms V rms V p-p V rms V p-p 94 102 92 98 dB dB dB dB −0.11 −0.4 Rev. 0 | Page 4 of 108 Unit 24 0.375 95 20 Hz to 20 kHz, −1 dB from full-scale input AVDD = 1.8 V AVDD = 3.3 V CM capacitor = 22 μF CM capacitor = 22 μF, 100 mV p-p at 1 kHz PGA_ENx = 1, PGA_x_BOOST = 0 Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 3.3 V 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Max −83 −87 +0.12 +0.2 Data Sheet Parameter THD + N SNR2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter PGA Gain Variation With −12 dB Setting With +35.25 dB Setting PGA Boost PGA Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation PSRR MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.90 × AVDD Bias Current Source Output Impedance MICBIASx Isolation Noise in the Signal Bandwidth AVDD = 1.8 V AVDD = 3.3 V DIGITAL-TO-ANALOG CONVERTERS (DACs) Resolution Digital Attenuation Step Digital Attenuation Range DAC SINGLE-ENDED OUTPUT Full-Scale Output Voltage Mute Attenuation Line Output Mode Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter ADAU1777 Test Conditions/Comments 20 Hz to 20 kHz, −1 dB from full-scale input AVDD = 1.8 V AVDD = 3.3 V Min AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Standard deviation PGA_x_BOOST PGA_MUTEx Typ dB dB 94 102 93 98 dB dB dB dB 0.05 0.15 10 −63 0.04 dB dB dB dB dB mV dB dB dB 1.14 2.10 1.61 2.95 MIC_GAINx = 0 MIC_GAINx = 1 20 Hz to 20 kHz, 4.7 µF decoupling capacitor, 5.0 kΩ load on the MICBIASx pins MIC_GAINx = 0 MIC_GAINx = 1 MIC_GAINx = 0 MIC_GAINx = 1 All DACs Single-ended operation, HPOUTLP/LOUTLP and HPOUTRP/LOUTRP pins Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 3.3 V 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Rev. 0 | Page 5 of 108 +0.12 −0.05 100 63 CM capacitor = 20 μF, 100 mV p-p at 1 kHz MIC_ENx = 1 97 102 95 99 Unit −88 −90 −0.12 AVDD = 1.8 V, MIC_GAINx = 1 AVDD = 3.3 V, MIC_GAINx = 1 AVDD = 1.8 V, MIC_GAINx = 0 AVDD = 3.3 V, MIC_GAINx = 0 Max 1.16 2.12 1.63 2.97 1.17 2.14 1.65 2.99 3 1 95 99 V V V V mA Ω dB dB 27 16 35 19 nV/√Hz nV/√Hz nV/√Hz nV/√Hz 24 0.375 95 Bits dB dB AVDD/3.4 0.53 1.5 0.97 2.74 −72 V rms V rms V p-p V rms V p-p dB 100 104 97 101 dB dB dB dB ADAU1777 Parameter SNR2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch THD + N Gain Error Headphone Mode Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter SNR2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch THD + N 32 Ω Load 24 Ω Load 16 Ω Load Gain Error Headphone Output Power 32 Ω Load 24 Ω Load 16 Ω Load Offset Error Interchannel Isolation PSRR DAC DIFFERENTIAL OUTPUT Full-Scale Output Voltage Mute Attenuation Line Output Mode Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Data Sheet Test Conditions/Comments 20 Hz to 20 kHz AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Min Typ 98 102 96 99 0 100 104 98 102 50 20 Hz to 20 kHz, −1 dBFS input AVDD = 1.8 V AVDD = 3.3 V −93 −94 −0.13 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V 20 Hz to 20 kHz AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V 200 dB dB dB dB mdB dB dB dB dB −89 −90 +0.13 100 104 97 101 dB dB dB dB 98 102 96 100 0 100 104 98 102 50 230 dB dB dB dB mdB −67 −67 −65 −64 −61 −67 +0.13 dB dB dB dB dB dB dB −79 −84 −79 −80 −74 −77 −0.13 AVDD = 1.8 V,