ADAU1787BCBZRL

Four ADC, Two DAC, Low Power Codec with Audio DSPs ADAU1787 Data Sheet FEATURES Programmable FastDSP audio processing engine Up to 768 kHz sample rate Biquad filters, limiters, volume controls, mixing 28-bit SigmaDSP audio processing core Visually programmable using SigmaStudio Up to 50 MIPS performance Low latency, 24-bit ADCs and DACs 96 dB SNR (signal through PGA and ADC with A-weighted filter) 105 dB combined SNR (signal through DAC and headphone with A-weighted filter) Serial port fSYNC frequency from 8 kHz to 768 kHz 5 μs group delay (fS = 768 kHz) analog in to analog out with FastDSP bypass (zero instructions) 4 single-ended analog inputs, configurable as microphone or line inputs 8 digital microphone inputs 2 analog differential audio outputs, configurable as either line output or headphone driver PLL supporting any input clock rate from 30 kHz to 27 MHz Full-duplex, 4-channel ASRCs 2, 16-channel serial audio ports supporting I2S, left justified, or up to TDM16 8 interpolators and 8 decimators with flexible routing Power supplies Analog AVDD at 1.8 V typical Digital I/O IOVDD at 1.1 V to 1.98 V Rev. A Digital DVDD at 0.9 V typical Low power (11.079 mW for typical stereo ANC settings) I2C and SPI control interfaces, self boot from I2C EEPROM Flexible GPIO 42-ball, 0.35 mm pitch, 2.695 mm × 2.320 mm WLCSP APPLICATIONS Noise cancelling handsets, headsets, and headphones Bluetooth ANC handsets, headsets, and headphones Personal navigation devices Digital still and video cameras Musical instrument effect processors Multimedia speaker systems Smartphones GENERAL DESCRIPTION The ADAU1787 is a codec with four inputs and two outputs that incorporates two digital signal processors (DSPs). The path from the analog input to the DSP core to the analog output is optimized for low latency and is ideal for noise cancelling headsets. With the addition of just a few passive components, the ADAU1787 provides a complete headset solution. Note that throughout this data sheet, multifunction pins, such as BCLK_0/MP1, are referred to either by the entire pin name or by a single function of the pin, for example, BCLK_0, when only that function is relevant. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2019-2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADAU1787 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Interpolation and Decimation Blocks ..................................... 39  Applications ....................................................................................... 1  Signal Levels ................................................................................ 39  General Description ......................................................................... 1  FastDSP Core .................................................................................. 40  Revision History ............................................................................... 5  Instructions ................................................................................. 40  Functional Block Diagram .............................................................. 6  Filter Precision ............................................................................ 40  Specifications..................................................................................... 7  Flags and Conditional Execution ............................................. 40  Analog Performance Specifications ........................................... 7  Input Sources .............................................................................. 40  Crystal Amplifier Specifications................................................. 9  Power and Run Control ............................................................. 41  Digital Input and Output Specifications ................................... 9  Data Memory .............................................................................. 41  Power Supply Specifications...................................................... 10  Parameters ................................................................................... 41  Power-Down Current ................................................................ 10  Parameter Bank Switching ........................................................ 41  Typical Power Consumption..................................................... 10  Parameter Bank Copying .......................................................... 41  Digital Filters ............................................................................... 11  Parameter Memory Access........................................................ 42  Digital Timing Specifications ................................................... 12  FastDSP Parameter Safeload ..................................................... 42  Absolute Maximum Ratings.......................................................... 16  SigmaDSP Core .............................................................................. 43  Thermal Resistance .................................................................... 16  Read/Write Data Formats ......................................................... 44  ESD Caution ................................................................................ 16  Software Safeload ....................................................................... 45  Pin Configuration and Function Descriptions ........................... 17  FastDSP Safeload ........................................................................ 45  Typical Performance Characteristics ........................................... 20  Program RAM, Parameter RAM, and Data RAM ..................... 46  System Block Diagram ................................................................... 27  Program RAM ............................................................................ 46  Theory of Operation ...................................................................... 28  Parameter RAM .......................................................................... 46  System Clocking and Power-Up ................................................... 29  Data RAM ................................................................................... 46  Power-Down Operation and Options ..................................... 29  Power Saving Options .................................................................... 47  Example ADC to DAC Power-up ............................................. 30  Control Port .................................................................................... 49  DVDD LDO Regulator .............................................................. 30  Burst Mode Communication .................................................... 49  Clock Initialization ..................................................................... 30  Reading and Writing to Memories .......................................... 50  PLL ............................................................................................... 31  I2C Port ........................................................................................ 50  Multichip Phase Synchronization ............................................ 32  SPI Port ........................................................................................ 53  Clock Output............................................................................... 32  Self Boot ....................................................................................... 54  Power Supply Sequencing ......................................................... 32  Multipurpose Pins ...................................................................... 56  Signal Routing ................................................................................. 33  Serial Data Ports ............................................................................. 57  Input Signal Paths ........................................................................... 34  Applications Information .............................................................. 59  Analog Inputs .............................................................................. 34  Power Supply Bypass Capacitors .............................................. 59  Digital Microphone Inputs ........................................................ 35  Layout .......................................................................................... 59  ADCs ............................................................................................ 36  Grounding ................................................................................... 59  Output Signal Paths ........................................................................ 37  PCB Stackup ................................................................................ 59  Analog Outputs........................................................................... 37  Register Summary .......................................................................... 60  DACs ............................................................................................ 37  Register Details ............................................................................... 67  PDM Outputs .............................................................................. 38  ADI Vendor ID Register ............................................................ 67  ASRCs .......................................................................................... 38  Device ID Registers .................................................................... 67  Rev. A | Page 2 of 280 Data Sheet ADAU1787 Revision Code Register ..............................................................67  PGA Channel 3 Gain Control LSBs Register .......................... 92  ADC, DAC, Headphone Power Controls Register .................68  PGA Slew Rate and Gain Link Register ................................... 93  PLL, Microphone Bias, and PGA Power Controls Register ..69  Microphone Bias Level and Current Register ......................... 93  Digital Microphone Power Controls Register .........................70  Digital Microphone Clock Rate Control Register .................. 94  Serial Port, PDM Output, and Digital Microphone CLK Power Controls Register .............................................................71  Digital Microphone Channel 0 and Channel 1 Rate, Order, Mapping, and Edge Control Register .......................................... 95  DSP Power Controls Register ....................................................72  Digital Microphone Channel 2 and Channel 3 Rate, Order, Mapping, and Edge Control Register .......................................... 96  ASRC Power Controls Register .................................................72  Interpolator Power Controls Register ......................................73  Decimator Power Controls Register .........................................74  Digital Microphone Channel 4 and Channel 5 Rate, Order, Mapping, and Edge Control Register .......................................... 97  State Retention Controls Register .............................................75  Digital Microphone Channel 6 and Channel 7 Rate, Order, Mapping, and Edge Control Register .......................................... 98  Chip Power Control Register.....................................................76  Digtial Microphone Volume Options Register ....................... 99  Clock Control Register ...............................................................77  Digital Microphone Channel Mute Controls Register.........100  PLL Input Divider Register ........................................................78  Digital Microphone Channel 0 Volume Control Register...101  PLL Feedback Integer Divider (LSBs Register) .......................78  Digital Microphone Channel 1 Volume Control Register...102  PLL Feedback Integer Divider (MSBs Register) .....................78  Digital Microphone Channel 2 Volume Control Register...103  PLL Fractional Numerator Value (LSBs Register) ..................78  Digital Microphone Channel 3 Volume Control Register...104  PLL Fractional Numerator Value (MSBs Register) ................79  Digital Microphone Channel 4 Volume Control Register...105  PLL Fractional Denominator (LSBs Register).........................79  Digital Microphone Channel 5 Volume Control Register...106  PLL Fractional Denominator (MSBs Register) .......................79  Digital Microphone Channel 6 Volume Control Register...107  PLL Update Register ...................................................................79  Digital Microphone Channel 7 Volume Control Register...108  ADC Sample Rate Control Register .........................................80  DAC Sample Rate, Filtering, and Power Controls Register......109  ADC IBIAS Controls Register .......................................................81  ADC HPF Control Register .......................................................81  DAC Volume Link, High-Pass Filter (HPF), and Mute Controls Register.......................................................................110  ADC Mute and Compensation Control Register ...................82  DAC Channel 0 Volume Register ...........................................111  Analog Input Precharge Time Register ....................................83  DAC Channel 1 Volume Register ...........................................112  ADC Channel Mutes Register ...................................................84  DAC Channel 0 Routing Register ...........................................113  ADC Channel 0 Volume Control Register ..............................85  DAC Channel 1 Routing Register ...........................................115  ADC Channel 1 Volume Control Register ..............................86  Headphone Control Register ...................................................117  ADC Channel 2 Volume Control Register ..............................87  ADC Channel 3 Volume Control Register ..............................88  Fast to Slow Decimator Sample Rates Channel 0 and Channel 1 Register........................................................................................117  PGA Channel 0 Gain Control MSBs, Mute, Boost, Slew Register .........................................................................................89  Fast to Slow Decimator Sample Rates Channel 2 and Channel 3 Register........................................................................................118  PGA Channel 0 Gain Control LSBs Register ..........................89  Fast to Slow Decimator Sample Rates Channel 4 and Channel 5 Register........................................................................................119  PGA Channel 1 Gain Control MSBs, Mute, Boost, Slew Register .........................................................................................90  PGA Channel 1 Gain Control LSBs Register ..........................90  PGA Channel 2 Gain Control MSBs, Mute, Boost, Slew Register .........................................................................................91  PGA Channel 2 Gain Control LSBs Register ..........................91  PGA Channel 3 Gain Control MSBs, Mute, Boost, Slew Register .........................................................................................92  Fast to Slow Decimator Sample Rates Channel 6 and Channel 7 Register........................................................................................120  Fast to Slow Decimator Channel 0 Input Routing Register .....121  Fast to Slow Decimator Channel 1 Input Routing Register .....122  Fast to Slow Decimator Channel 2 Input Routing Register .....124  Fast to Slow Decimator Channel 3 Input Routing Register .....125  Fast to Slow Decimator Channel 4 Input Routing Register .....127  Rev. A | Page 3 of 280 ADAU1787 Data Sheet Fast to Slow Decimator Channel 5 Input Routing Register ..... 128  Fast to Slow Decimator Channel 6 Input Routing Register ..... 130  FastDSP Modulo N Counter for Lower Rate Conditional Execution Register ................................................................... 167  Fast to Slow Decimator Channel 7 Input Routing Register ..... 131  FastDSP Generic Conditional Execution Registers ............. 168  Slow to Fast Interpolator Sample Rates Channel 0 and Channel 1 Register ................................................................... 133  FastDSP Safeload Address Register........................................ 169  FastDSP Safeload Parameter 0 Value Registers .................... 169  Slow to Fast Interpolator Sample Rates Channel 2 and Channel 3 Register ................................................................... 134  FastDSP Safeload Parameter 1 Value Registers .................... 170  Slow to Fast Interpolator Sample Rates Channel 4 and Channel 5 Register ................................................................... 135  FastDSP Safeload Parameter 3 Value Registers .................... 172  Slow to Fast Interpolator Sample Rates Channel 6 and Channel 7 Register ................................................................... 136  FastDSP Safeload Update Register ......................................... 174  Slow to Fast Interpolator Channel 0 Input Routing Register ..................................................................................................... 137  FastDSP Safeload Parameter 2 Value Registers .................... 171  FastDSP Safeload Parameter 4 Value Registers .................... 173  SigmaDSP Frame Rate Source Select Register ..................... 174  SigmaDSP Run Register .......................................................... 175  Slow to Fast Interpolator Channel 1 Input Routing Register ..................................................................................................... 139  SigmaDSP Watchdog Controls Register................................ 176  Slow to Fast Interpolator Channel 2 Input Routing Register ..................................................................................................... 141  SigmaDSP Modulo Data Memory Start Position Registers 177  Slow to Fast Interpolator Channel 3 Input Routing Register ..................................................................................................... 143  SigmaDSP Set Interrupts Register.......................................... 178  Slow to Fast Interpolator Channel 4 Input Routing Register ..................................................................................................... 145  SigmaDSP Watchdog Value Registers ................................... 176  SigmaDSP Fixed Frame Rate Divisor Registers ................... 177  MultiPurpose Pin 0 and Pin 1 Mode Select Register........... 179  MultiPurpose Pin 2 and Pin 3 Mode Select Register........... 180  Slow to Fast Interpolator Channel 5 Input Routing Register ..................................................................................................... 147  MultiPurpose Pin 4 and Pin 5 Mode Select Register........... 181  Slow to Fast Interpolator Channel 6 Input Routing Register ..................................................................................................... 149  MultiPurpose Pin 8 and Pin 9 Mode Select Register........... 183  Slow to Fast Interpolator Channel 7 Input Routing Register ..................................................................................................... 151  Input ASRC Control, Source, and Rate Selection Register . 153  Input ASRC Channel 0 and Channel 1 Input Routing Register ..................................................................................................... 154  Input ASRC Channel 2 and Channel 3 Input Routing Register ..................................................................................................... 155  MultiPurpose Pin 6 and Pin 7 Mode Select Register........... 182  MultiPurpose Pin 10 and Pin 11 Mode Select Register ...... 184  General-Purpose Input Debounce Control and Master Clock Output Rate Selection Register............................................... 185  General-Purpose Outputs Control Pin 0 to Pin 7 Register ..... 186  General-Purpose Outputs Control Pin 8 to Pin 10 Register ... 187  FSYNC_0 Pin Controls Register ............................................ 188  BCLK_0 Pin Controls Register ............................................... 189  Output ASRC Control Register .............................................. 156  SDATAO_0 Pin Control Register ........................................... 189  Output ASRC Channel 0 Input Routing Register ................ 157  SDATAI_0 Pin Controls Register ........................................... 190  Output ASRC Channel 1 Input Routing Register ................ 158  FSYNC_1 Pin Controls Register ............................................ 191  Output ASRC Channel 2 Input Routing Register ................ 160  BCLK_1 Pin Controls Register ............................................... 192  Output ASRC Channel 3 Input Routing Register ................ 161  SDATAO_1 Pin Controls Register ......................................... 193  FastDSP Run Register .............................................................. 163  SDATAI_1 Pin Controls Register ........................................... 194  FastDSP Current Bank and Bank Ramping Controls Register ..................................................................................................... 163  DMIC_CLK0 Pin Controls Register ...................................... 195  FastDSP Bank Ramping Stop Point Register ........................ 164  DMIC01 Pin Controls Register .............................................. 197  FastDSP Bank Copying Register ............................................ 165  DMIC23 Pin Controls Register .............................................. 198  FastDSP Frame Rate Source Register..................................... 166  SDA/MISO Pin Controls Register ......................................... 198  FastDSP Fixed Rate Division MSBs Register ........................ 166  IRQ Signaling and Clearing Register ..................................... 199  FastDSP Fixed Rate Division LSBs Register ......................... 167  IRQ1 Masking Registers .......................................................... 200  DMIC_CLK1 Pin Controls Register ...................................... 196  Rev. A | Page 4 of 280 Data Sheet ADAU1787 IRQ2 Masking Registers .......................................................... 203  Serial Port 0 Output Routing Slot 15 Register ......................241  Chip Resets Register ................................................................ 205  Serial Port 1 Control 1 Register ..............................................243  FastDSP Current Lambda Register ........................................ 206  Serial Port 1 Control 2 Register ..............................................244  Chip Status 1 Register .............................................................. 207  Serial Port 1 Output Routing Slot 0 (Left Register)..............245  Chip Status 2 Register .............................................................. 208  Serial Port 1 Output Routing Slot 1 (Right Register) ...........246  General-Purpose Input Read 0 to Input Read 7 Register ... 209  Serial Port 1 Output Routing Slot 2 Register.........................248  General-Purpose Input Read 8 to Input Read 10 Register ...... 210  Serial Port 1 Output Routing Slot 3 Register.........................249  DSP Status Register .................................................................. 210  Serial Port 1 Output Routing Slot 4 Register.........................251  IRQ1 Status 1 Register ............................................................. 211  Serial Port 1 Output Routing Slot 5 Register.........................252  IRQ1 Status 2 Register ............................................................. 212  Serial Port 1 Output Routing Slot 6 Register.........................254  IRQ1 Status 3 Register ............................................................. 213  Serial Port 1 Output Routing Slot 7 Register.........................255  IRQ2 Status 1 Register ............................................................. 214  Serial Port 1 Output Routing Slot 8 Register.........................257  IRQ2 Status 2 Register ............................................................. 215  Serial Port 1 Output Routing Slot 9 Register.........................258  IRQ2 Status 3 Register ............................................................. 216  Serial Port 1 Output Routing Slot 10 Register ......................260  Serial Port 0 Control 1 Register .............................................. 217  Serial Port 1 Output Routing Slot 11 Register ......................261  Serial Port 0 Control 2 Register .............................................. 218  Serial Port 1 Output Routing Slot 12 Register ......................263  Serial Port 0 Output Routing Slot 0 (Left Register) ............. 219  Serial Port 1 Output Routing Slot 13 Register ......................264  Serial Port 0 Output Routing Slot 1 (Right Register) .......... 220  Serial Port 1 Output Routing Slot 14 Register ......................266  Serial Port 0 Output Routing Slot 2 Register ........................ 222  Serial Port 1 Output Routing Slot 15 Register ......................267  Serial Port 0 Output Routing Slot 3 Register ........................ 223  MP12 Pin Control Register......................................................269  Serial Port 0 Output Routing Slot 4 Register ........................ 225  SELFBOOT Pin Controls Register .........................................270  Serial Port 0 Output Routing Slot 5 Register ........................ 226  SW_EN Pin Controls Register ................................................271  Serial Port 0 Output Routing Slot 6 Register ........................ 228  PDM Sample Rate and Filtering Control Register ...............272  Serial Port 0 Output Routing Slot 7 Register ........................ 229  PDM Muting, High-Pass, and Volume Options Register ....273  Serial Port 0 Output Routing Slot 8 Register ........................ 231  PDM Output Channel 0 Volume Register .............................274  Serial Port 0 Output Routing Slot 9 Register ........................ 232  PDM Output Channel 1 Volume Register .............................275  Serial Port 0 Output Routing Slot 10 Register ...................... 234  PDM Output Channel 0 Routing Register ............................276  Serial Port 0 Output Routing Slot 11 Register ...................... 235  PDM Output Channel 1 Routing Register ............................278  Serial Port 0 Output Routing Slot 12 Register ...................... 237  Outline Dimensions ......................................................................280  Serial Port 0 Output Routing Slot 13 Register ...................... 238  Ordering Guide .........................................................................280  Serial Port 0 Output Routing Slot 14 Register ...................... 240  REVISION HISTORY 1/2020—Rev. 0 to Rev. A Changes to Features Section ............................................................ 1 Changes to Typical Power Consumption Section and Table 6 .......................................................................................10 Changes to Table 7 and Added Note 1 to Table 8 .......................11 Added Note 1 to Table 9, Renumbered Sequentially ..................12 Changes to Figure 7.........................................................................15 Changes to Table 10 ........................................................................16 Changes to Analog Input Precharge Time Register Section and Table 67 ....................................................................................83 4/2019—Revision 0: Initial Revision Rev. A | Page 5 of 280 ADAU1787 Data Sheet XTALO XTALI/MCLKIN SAI_0 SAI_0 SAI_1 SAI_1 SAI_1 ADC DECIMATION 4 8kHz TO DMIC 768kHz ADC OUTPUT ASRCI ADC SigmaDSP 16 DMIC 50 MIPs SDSP ASRCI ADC FastDSP 16 ASRCI 64 INSTRUCTIONS FDSP FDSP FDSP SDSP SDSP ADC SAI_0 ROUTE INPUT 4 ASYNCHRONOUS SAMPLE RATE ASRCI CONVERTER ROUTE 16 16 SERIAL AUDIO PORT 0 MASTER OR SLAVE SERIAL AUDIO PORT 1 MASTER OR SLAVE DAC OUTPUT ASYNCHRONOUS SAMPLE RATE CONVERTER 4 I2C OR SPI CONTROL PORT HPOUTP1/ LOUTP1 HPOUTN1/ LOUTN1 4 ASRCO ADAU1787 20127-001 SDA/MISO SCL/SCLK ADDR0/SS ADDR1/MOSI SDATAI_1/MP6 SELFBOOT/MP11 NOTES 1. SAI_0 IS THE SERIAL AUDIO INTERFACE 0. 2. SAI_1 IS THE SERIAL AUDIO INTERFACE 1. 3. DMIC IS THE DIGITAL MICROPHONE. 4. ASRCI IS THE INPUT ASYNCHRONOUS SAMPLE RATE CONVERTER. 5. ASRCO IS THE OUTPUT ASYNCHRONOUS SAMPLE RATE CONVERTER. 6. FDSP IS FastDSP. 7. SDSP IS SigmaDSP. SADATAO_1/MP5 FSYNC_1/MP3 SDATAI_0/MP2 SADATAO_0 FSYNC_0/MP0 BCLK_0/MP1 SW_EN/MP12 DGND AGND AGND HPOUTN0/ LOUTN0 ROUTE DMIC4_5 DMIC6_7 HPGND HPOUTP0/ LOUTP0 ROUTE SAI_0 16 ROUTE DIGITAL MICROPHONE 8 DECIMATION 8kHz TO DMIC 768kHz OUTPUT 4 DAC HP CM IOVDD HPVDD AVDD AVDD SAI_0 SAI_1 DMIC_CLK0/ MP7 DMIC_CLK1/ MP8 DMIC01/ MP9 DMIC23/ MP10 BCLK_1 FSYNC_1 HP ADC MASTER CLOCK PLL PD ADC CLK OSCILATOR SAI_1 AIN3 CM GENERATOR 16 PGA AIN2 LDO ADC PGA AIN1 PGA AIN0 BCLK_0 FSYNC_0 BCLK_1/MP4 MICBIAS1 MICROPHONE BIAS GENERATOR PGA MICBIAS0 DVDD REG_EN FUNCTIONAL BLOCK DIAGRAM Figure 1. Rev. A | Page 6 of 280 Data Sheet ADAU1787 SPECIFICATIONS Master clock input = 24.576 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, ambient temperature (TA) = 25°C, and line output load = 10 kΩ, unless otherwise noted. ANALOG PERFORMANCE SPECIFICATIONS Supply voltages AVDD = IOVDD = 1.8 V and DVDD = 0.9 V, unless otherwise noted. Table 1. Parameter ANALOG-TO-DIGITAL CONVERTERS (ADCs) ADC Resolution Digital Gain Step Digital Gain Range INPUT RESISTANCE Single-Ended Line Input Programmable Gain Amplifier (PGA) Inputs SINGLE-ENDED LINE INPUT Full-Scale Input Voltage Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Signal-to-Noise Ratio (SNR)2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch Total Harmonic Distortion + Noise (THD + N) Level Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio (PSRR) SINGLE-ENDED PGA INPUT Full-Scale Input Voltage Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter THD + N Level SNR2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter PGA Gain Variation With 0 dB Setting With 35.25 dB Setting PGA Boost Interchannel Gain Mismatch Test Conditions/Comments Min All ADCs Typ Max Unit +24 Bits dB dB 24 0.375 −71 0 dB gain 32 dB gain PGAx_EN = 0, PGAx_BOOST = 0, PGAx_SLEW_DIS = 1 0 dBFS 0 dBFS 20 Hz to 20 kHz, −60 dB input 14.3 20.26 kΩ kΩ 0.97 kΩ 0.49 1.38 V rms V p-p 97 94 dB dB 98 96 40 dB dB mdB −90 ±0.1 ±0.2 100 dBFS mV dB dB 60 40 dB dB 0.49 1.38 V rms V p-p 96 94 −88 dB dB dBFS 96 94 dB dB 0.05 0.15 10 0.005 dB dB dB dB 20 Hz to 20 kHz, −1 dB full-scale output CM capacitor = 10 μF CM capacitor = 10 μF 100 mV p-p at 1 kHz 100 mV p-p at 10 kHz PGAx_EN = 1, PGA_x_BOOST = 0 0 dBFS 20 Hz to 20 kHz, −60 dB input 20 Hz to 20 kHz, −1 dBFS output Standard deviation PGA_x_BOOST Rev. A | Page 7 of 280 ADAU1787 Parameter Offset Error Gain Error Interchannel Isolation PSRR MICROPHONE BIAS Bias Voltage Data Sheet Test Conditions/Comments Min CM capacitor = 10 μF, 100 mV p-p at 1 kHz 100 mV p-p at 1 kHz MBIASx_EN = 1, 1 μF load MBIASx_LEVEL = 1 MBIASx_LEVEL = 0 Bias Current Source Output Impedance MICBIASx Isolation Noise3 CONVERTERS DIGITAL Internal Converter Resolution Digital Gain Step Range Ramp Rate DAC DIFFERENTIAL OUTPUT Full-Scale Output Voltage Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter SNR2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch THD + N Level Gain Error Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter SNR2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch THD + N Level 32 Ω Load 24 Ω Load 16 Ω Load Headphone Output Power 32 Ω Load 24 Ω Load 16 Ω Load Typ 0 ±0.2 83 70 49 Max 1.18 1.63 1 95 99 V V mA Ω dB dB 3.5 3.5 μV μV 24 Bits 2 MBIASx_LEVEL = 0 MBIASx_LEVEL = 1 AVDD = 1.8 V, 20 Hz to 20 kHz, A-weighted MBIASx_LEVEL = 0 MBIASx_LEVEL = 1 All digital-to-analog converters (DACs)/ADCs Unit mV dB dB dB dB 0.375 4.5 dB dB dB/ms 1.0 V rms 105 102 dB dB 105 102 20 −93 dB dB mdB dBV % 105 101 dB dB Headphone mode Headphone mode −1 dBFS, output power (POUT) = 27 mW POUT = 1 mW −2 dBFS, POUT = 28 mW −3 dBFS, POUT = 33 mW 105 101 75 dB dB mdB −75 −82 −75 −75 dBV dBV dBV dBV AVDD = 1.8 V, 25 MIPs operation of the SigmaDSP is not needed, there is no downside to bypassing the PLL. DAC Bias Current Control Table 21 PLL_BIAS Power Comparison The DACs provide a mechanism to modify the bias current level used, allowing performance vs. power consumption options for the user. Four possible settings can be set via the DAC_IBIAS control bit. PLL_BYPASS 0 1 PLL Operation Used Bypassed Relative Power Consumption (mW) 0 −0.55 Table 22. ADCxx_IBIAS Power and Performance Options ADCxx_IBIAS Setting 010 000 011 001 Description Enhanced performance Normal operation Power saving Extreme power saving Change in Digital Noise Reduction (DNR), A-Weighted (dB) 0 0 −0.7 −0.7 Change in THD + N Level at 1 kHz(dB) 0 0 9 11.5 Change in Power Consumption per ADC Channel (mW) +0.12 0 −0.27 −0.39 Table 23. DAC_IBIAS Power and Performance Options in Headphone Mode DAC_IBIAS Setting 010 000 011 001 Description Enhanced performance Normal operation Power saving Extreme power saving Change in DNR, A-Weighted (dB) 0 0 −0.5 −1.0 Change in THD + N Level at 1 kHz (dB) −1 0 +4 +7 Change in Power Consumption per DAC Channel (mW) +0.22 0 −0.51 −0.73 Table 24. DAC Low Power and Performance Options in Line Output Mode Mode Default DAC_LPM = 1 DAC_LPM_II = 1 Relative THD + N at 1 kHz, −6 dB 0 dB 0 dB 8 dB DNR A-Weighted (dB) 105.5 105.5 105.8 Rev. A | Page 47 of 280 Relative Power per Channel (mW) 0 −0.041 −0.058 ADAU1787 Data Sheet SigmaDSP Clock Speed Control By default, SDSP_SPEED is set to 0 and the SigmaDSP receives a 24.576 MHz clock. If the PLL is used and SDSP_SPEED is set to 1, the SigmaDSP receives a 49.152 MHz clock and is able to run twice as many instructions. If this extra processing power is not needed, keeping SDSP_SPEED = 0 saves power. Table 25. SDSP_SPEED Power Comparison SDSP_SPEED 1 0 SigmaDSP Clock Rate (MHz) 49.152 24.576 Asynchronous Sample Rate Converters Low Power Modes The ASRCs offer two separate, selectable low power operating modes. These modes allow power vs. performance trade-offs when using the ASRCs. Generally, if the data being sourced or sinked to the ASRCs is from or to the ADC or DAC using the ASRCx_LPM_II setting provides the lowest power consumption and does not degrade the performance of the converters. Relative Power Consumption (mW) 0 −0.076 Table 26. Input ASRC Power and Performance Options for 44.1 kHz to 48 kHz Conversion Mode Default ASRCI_LPM = 1 ASRCI_LPM_II = 1 THD + N at 1 kHz (dB) 123 120 112 THD + N at 20 kHz 123 118 108 DNR AW (dB) 130 130 130 Relative Power per Channel (mW) 0 −0.041 −0.058 Table 27. Output ASRC Power and Performance Options for 48 kHz to 44.1 kHz Conversion Mode Default ASRCO_LPM = 1 ASRCO_LPM_II = 1 THD + N at 1 kHz (dB) 123 120 112 THD + N at 20 kHz 123 118 108 DNR AW (dB) 130 130 130 Rev. A | Page 48 of 280 Relative Power per Channel (mW) 0 −0.045 −0.070 Data Sheet ADAU1787 CONTROL PORT Registers and bits shown as reserved in the register map read back 0s. The ADAU1787 has a 4-wire SPI control port and a 2-wire I2C bus control port. Each port can set the memories and registers. The IC defaults to I2C mode but can be put into SPI control mode by pulling the SS pin low three times. When in I2C mode, the unused control pins determine the I2C device address. The IC can be put into I2C and/or SPI mode by tying the SW_EN pin to DGND. The control port pins are multifunctional, depending on the mode in which the device is operating. Table 28 describes these multiple functions. Table 28. Control Port Pin Functions I2C Mode SCL—input SDA—open-collector output I2C Address Bit 1—input I2C Address Bit 0—input Pin SCL/SCLK SDA/MISO ADDR1/MOSI ADDR0/SS The control port is capable of full read/write operation for all addressable memories and registers. Most signal processing parameters are controlled by writing new values to the parameter memories using the control port. Other functions, such as mute and input/output mode control, are programmed through the registers. SPI Mode SCLK—input MISO—output MOSI—input SS—input BURST MODE COMMUNICATION All addresses can be accessed in either single address mode or burst mode. The first byte (Byte 0) of a control port write contains the 7-bit IC address plus the R/W bit. The next two bytes (Byte 1 and Byte 2) are the 16-bit subaddress of the memory or register location within the ADAU1787. All subsequent bytes (starting with Byte 3) contain the data, such as the register, program, or parameter data. The exact formats for specific types of writes are shown in Figure 61 and Figure 62. Burst mode addressing, in which the subaddresses are automatically incremented at word boundaries, can be used for writing large amounts of data to contiguous memory locations. This increment happens automatically after a single-word write unless the control port communication is stopped (that is, a stop condition is issued for I2C, or SS is brought high for SPI). The registers and RAMs in the ADAU1787 range in width from one byte to five bytes, so the auto-increment feature knows the mapping between subaddresses and the word length of the destination register (or memory location). If large blocks of data must be downloaded to the ADAU1787 DSP cores, the output of the cores can be disabled, new data can be loaded, and the core can then be restarted. This restart is typically done during the booting sequence at start-up or when loading a new program into memory. Table 29. Control Pins Function Setup List Mode I2C IOVDD (V) 1.2 to 1.8 I2C Address 0x28 BCLK0 Pin BCLK0 SDATAO_0 Pin SDATAO_0 ADDR1/ MOSI Pin 0 ADDR0/ SS Pin 0 SCL/ SCLK Pin SCL SDA/ MISO Pin SDA SW_EN Pin 0 I2C 1.2 to 1.8 0x29 BCLK0 SDATAO_0 0 1 SCL SDA 0 2 IC 1.2 to 1.8 0x2A BCLK0 SDATAO_0 1 0 SCL SDA 0 I2C 1.2 to 1.8 0x2B BCLK0 SDATAO_0 1 1 SCL SDA 0 SPI 1.2 to 1.8 Not applicable BCLK0 SDATAO_0 MOSI SS SCLK MISO 0 Table 30. I2C/SPI Control Data Word Sizes and Address Ranges Base Address 0x0000 0x2000 0x5000 0x7800 0xC000 0xD000 0xD100 0xE000 End Address 0x0F00 0x3FFF 0x77FF 0x97FF 0xC0E1 0xD0FF 0xDFFF 0xE3FF Description Reserved SigmaDSP parameter RAM SigmaDSP program RAM SigmaDSP data RAM Control registers FastDSP program FastDSP parameter FastDSP state Width per Address Not applicable 8 8 8 8 8 8 8 Rev. A | Page 49 of 280 Write Modes Not applicable Direct, safeload Direct Direct Direct Direct Direct safeload Direct Writes Needed for Update Not applicable 4 5 4 1 4 4 4 ADAU1787 Data Sheet READING AND WRITING TO MEMORIES All SigmaDSP and FastDSP memory locations are larger than a single byte. While each byte occupies a single address when communicating over a control interface (I2C or SPI), when writing to these memories, an entire memory word must be written starting with the lowest address and continuing sequentially to the highest address for a write to actually occur. Similarly, a read must begin at the lowest memory address. However, for reads, all locations must not be read. The mapping of bytes over the control interface is the most significant byte, or a memory location is written or read first, and the least significant byte is written or read last. The memories can be read or written in burst mode or single byte mode so that the proceeding requirements are met. Table 31. Example Write to SigmaDSP Program RAM Word 0 Address 0x5000 0x5001 0x5002 0x5003 0x5004 Data Data, Bits[39:32] Data, Bits[31:24] Data, Bits[23:16] Data, Bits[15:8] Data, Bits[7:0], the memory is written to after this write I2C PORT The ADAU1787 supports a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. I2C uses two pins, serial data (SDA) and serial clock (SCL), to carry data between the ADAU1787 and the system I2C master controller. In I2C mode, the ADAU1787 is always a slave on the bus, except when the IC is self booting. See the Self Boot section for details about using the ADAU1787 in self boot mode. The device supports fast mode plus I2C operation, but for most bus capacitances, the SDA_MISO_DRIVE bit must be set to 1 to support these operating speeds. Each slave device is recognized by a unique 7-bit device address. The ADAU1787 I2C address format is shown in Table 32. The LSB of this first byte sent from the I2C master sets either a read or write operation. Logic Level 1 corresponds to a read operation, and Logic Level 0 corresponds to a write operation. Pin ADDR0 and Pin ADDR1 set the LSBs of the I2C address (see Table 33). Therefore, each ADAU1787 can be set to one of four unique addresses, allowing multiple ICs to exist on the same I2C bus without address contention. The 7-bit I2C addresses are shown in Table 33. An I2C data transfer is always terminated by a stop condition. Both SDA and SCL must have 2.0 kΩ pull-up resistors on the lines connected to these pins. The voltage on these signal lines cannot be higher than IOVDD. Table 32. I2C Address Format Bit 6 0 Bit 5 1 Bit 4 0 Bit 3 1 Bit 2 0 Bit 1 ADDR1 Bit 0 ADDR0 Table 33. I2C Addresses ADDR1 (MOSI) 0 0 1 1 ADDR0 (SS) 0 1 0 1 Slave Address 0x28 0x29 0x2A 0x2B Addressing Initially, each device on the I2C bus is in an idle state and monitoring the SDA and SCL lines for a start condition and the proper address. The I2C master initiates a data transfer by establishing a start condition, defined by a high to low transition on SDA while SCL remains high, indicating that an address/data stream follows. All devices on the bus respond to the start condition and shift the next eight bits (the 7-bit address plus the R/W bit) MSB first. The device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This ninth bit is known as an acknowledge bit. All other devices withdraw from the bus at this point and return to the idle condition. The R/W bit determines the direction of the data. A Logic 0 on the LSB of the first byte indicates that the master writes information to the peripheral, whereas a Logic 1 indicates that the master reads information from the peripheral after writing the subaddress and repeating the start address. A data transfer takes place until a stop condition is encountered. A stop condition occurs when SDA transitions from low to high while SCL is held high. Figure 59 shows the timing of an I2C write, and Figure 60 shows an I2C read. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, the ADAU1787 immediately jumps to the idle condition. During a given SCL high period, the user can only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. A noacknowledge condition is where the SDA line is not pulled low on the ninth clock pulse on SCL. If an invalid subaddress is issued by the user, the ADAU1787 issues an acknowledge, but no data write occurs, and a read returns zeros. If the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded to any subaddress register. Rev. A | Page 50 of 280 Data Sheet ADAU1787 SCL 0 SDA 1 0 START BY MASTER 1 0 ADDR1 ADDR0 R/W ACKNOWLEDGE BY ADAU1787 FRAME 1 CHIP ADDRESS BYTE FRAME 2 SUBADDRESS BYTE 1 ACKNOWLEDGE BY ADAU1787 SCL (CONTINUED) FRAME 3 SUBADDRESS BYTE 2 ACKNOWLEDGE BY ADAU1787 ACKNOWLEDGE BY ADAU1787 FRAME 4 DATA BYTE 1 STOP BY MASTER 20127-064 SDA (CONTINUED) Figure 59. I2C Write to ADAU1787 Clocking SCL SDA 0 1 0 1 0 ADDR1 ADDR0 R/W ACKNOWLEDGE BY ADAU1787 ACKNOWLEDGE BY ADAU1787 START BY MASTER FRAME 1 CHIP ADDRESS BYTE FRAME 2 SUBADDRESS BYTE 1 SCL (CONTINUED) SDA (CONTINUED) 0 FRAME 3 SUBADDRESS BYTE 2 ACKNOWLEDGE BY ADAU1787 1 REPEATED START BY MASTER 0 1 0 ADDR1 ADDR0 R/W ACKNOWLEDGE BY ADAU1787 FRAME 4 CHIP ADDRESS BYTE SCL (CONTINUED) ACKNOWLEDGE BY ADAU1787 FRAME 5 READ DATA BYTE 1 ACKNOWLEDGE STOP BY BY ADAU1787 MASTER FRAME 6 READ DATA BYTE 2 Figure 60. I2C Read from ADAU1787 Clocking Rev. A | Page 51 of 280 20127-065 SDA (CONTINUED) ADAU1787 Data Sheet I2C Read and Write Operations back to the master. The master then responds every ninth pulse with an acknowledge pulse to the ADAU1787. Figure 61 shows the timing of a single-word write operation. Every ninth clock pulse, the ADAU1787 issues an acknowledge by pulling SDA low. Figure 64 shows the timing of a burst mode read sequence. Figure 64 shows an example where the target read words are two bytes. The ADAU1787 increments its subaddress every two bytes because the requested subaddress corresponds to a register or memory area with word lengths of two bytes. Other address ranges may have a variety of word lengths, ranging from one byte to four bytes. The ADAU1787 always decodes the subaddress and sets the auto-increment circuit so that the address increments after the appropriate number of bytes. Figure 62 shows the timing of a burst mode write sequence. Figure 62 shows an example where the target destination words are two bytes, such as the program memory. The ADAU1787 knows to increment its subaddress register every two bytes because the requested subaddress corresponds to a register or memory area with a 2-byte word length. The timing of a single-word read operation is shown in Figure 63. Note that the first R/W bit is 0, indicating a write operation because the subaddress still must be written to set up the internal address. After the ADAU1787 acknowledges the receipt of the subaddress, the master must issue a repeated start command, followed by the chip address byte with the R/W set to 1 (read), causing the ADAU1787 SDA to reverse and begin driving data I2C ADDRESS, R/W = 0 AS SUBADDRESS HIGH     SUBADDRESS LOW AS AS S is the start bit. P is the stop bit. AM is acknowledge by master. AS is acknowledge by slave. DATA BYTE 1 AS ... AS DATA BYTE N P 20127-066 S Figure 61 to Figure 64 use the following abbreviations: DATA-WORD 2, BYTE 1 AS DATA-WORD 2 BYTE 2 AS ... DATA BYTE 2 I2C ADDRESS, R/W = 0 AS SUBADDRESS HIGH AS SUBADDRESS LOW DATA-WORD 1, BYTE 1 AS AS DATA-WORD 1, BYTE 2 AS P S I2C ADDRESS, R/W = 0 AS SUBADDRESS HIGH AS SUBADDRESS LOW AS S I2C ADDRESS, R/W = 1 AS DATA BYTE 1 AM DATA BYTE 2 ... AM DATA BYTE N P Figure 63. Single-Word I2C Read Format S I2C ADDRESS, R/W = 0 AS SUBADDRESS HIGH AS SUBADDRESS LOW AS S I2C ADDRESS, R/W = 1 AS DATA-WORD 1 AM BYTE 1 Figure 64. Burst Mode I2C Read Format Rev. A | Page 52 of 280 DATA-WORD 1 AM BYTE 2 ... P 20127-068 Figure 62. Burst Mode I2C Write Format 20127-069 S 20127-067 Figure 61. Single-Word I2C Write Format Data Sheet ADAU1787 SPI PORT R/W 2 By default, the ADAU1787 is in I C mode, but the device can be put in SPI control mode by pulling SS low three times by issuing three SPI writes, which are in turn ignored by the ADAU1787. The next (fourth) SPI write is then latched in the SPI port. The first byte of an SPI transaction indicates whether the communication is a read or a write with the R/W bit. The LSB of this first byte determines whether the SPI transaction is a read (Logic Level 1) or a write (Logic Level 0). The SPI port uses a 4-wire interface, consisting of SS, SCLK, MOSI, and MISO signals, and is always a slave port. The SS signal must go low at the beginning of a transaction and high at the end of a transaction. The SCLK signal latches MOSI on a low to high transition. MISO data is shifted out of the ADAU1787 on the falling edge of SCLK and must be clocked to a receiving device, such as a microcontroller, on the SCLK rising edge. The MOSI signal carries the serial input data, and the MISO signal is the serial output data. The MISO signal remains tristated until a read operation is requested, allowing other SPI-compatible peripherals to share the same readback line. The 16-bit subaddress word is decoded into a location in one of the memories or registers. This subaddress is the location of the appropriate memory location or register. Subaddress It is necessary to add an unused byte of zeros after the subaddress to effectively make the subaddress 24 bits with the actual address placed in the 16 MSBs. Data Bytes The number of data bytes varies according to the register or memory being accessed. During a burst mode write, an initial subaddress is written followed by a continuous sequence of data for consecutive memory and/or register locations. All SPI transactions have the same basic format shown in Table 34. The timing diagrams for SPI write and SPI read are shown in Figure 65 and Figure 66, respectively. All data must be written MSB first. The ADAU1787 can only be taken out of SPI mode by pulling the PD pin low or by powering down the IC. A sample timing diagram for a single-write SPI operation to the parameter RAM is shown in Figure 65. A sample timing diagram of a single-read SPI operation is shown in Figure 66. The MISO pin goes from tristate to being driven at the beginning of Byte 3. In this example, Byte 0 to Byte 2 contain the addresses and the R/W bit and subsequent bytes carry the data. Table 34. Generic SPI Word Format Byte 0 0000000, R/W Byte 2 Register/memory address, Bits[7:0] Byte 3 Zeros, Bits[7:0] (dummy) Byte 4 Data Byte 51 Data Continues to end of data. SS SCLK BYTE 0 BYTE 1 BYTE 2 REGISTER ADDRESS BYTE 4 BYTE 3 DUMMY DATA 20127-070 MOSI DATA Figure 65. SPI Write to ADAU1787 Clocking (Single-Write Mode) SS SCLK REGISTER ADDRESS MOSI MISO BYTE 0 BYTE 1 BYTE 2 HIGH-Z DUMMY DATA BYTE 3 ZERO DATA Figure 66. SPI Read from ADAU1787 Clocking (Single-Read Mode) Rev. A | Page 53 of 280 DUMMY DATA BYTE 4 VALID DATA HIGH-Z 20127-071 1 Byte 1 Register/memory address, Bits[15:8] ADAU1787 Data Sheet Table 35. EEPROM Self Boot Instructions Instruction Byte ID 0x00 0x01 0x02 0x03 0x04 0x05 Instruction Byte Description End self boot Write multibyte length minus two bytes, starting at target address Delays by the 16-bit setting × 2048 clock cycles No operation Wait for PLL lock Write single byte to target address Following Bytes Cyclical redundancy check (CRC) Length (high byte), length (low byte), address (high byte), address (low byte), data (0), data (1), … , data (length – 3) Delay (high byte), delay (low byte) None None Address (high byte), address (low byte), data 0x02 0x00 0x04 0x01 0x00 0x05 0x00 0x80 DELAY DELAY (HIGH BYTE) DELAY (LOW BYTE) WRITE LENGTH (HIGH BYTE) LENGTH (LOW BYTE) ADDRESS (HIGH BYTE) ADDRESS (LOW BYTE) DELAY LENGTH 0x2B DATA (1) 0x3C DATA (LENGTH – 3) 0x04 PLL LOCK 0x03 NO OP PROGRAM RAM ADDRESS 0x00 END 20127-072 0x1A DATA (0) LENGTH PROGRAM RAM DATA Figure 67. Example of Self Boot EEPROM Instructions SELF BOOT The ADAU1787 boots up from an EEPROM over the I2C bus when the SELFBOOT pin is set high at power-up and the PD pin is set high. The state of the SELFBOOT pin is checked internally only when the ADAU1787 comes out of a reset via the PD pin going high or by applying power with PD already set high. When the device comes out of reset and there is a MCLK source present, the state of the SELFBOOT pin is registered to determine whether to self boot. At reset, the state is set not to self boot. Therefore, if a master clock at the MCLKIN pin is not present, the self boot does not occur. The EEPROM is not used after a self boot completes. During booting, ensure that there is a stable DVDD in the system. The PD pin must remain high during self boot operation. If the SELFBOOT pin is not used for a multipurpose pin function, tie the pin to either IOVDD or DGND. The master SCL clock output from the ADAU1787 is derived from the input clock on XTALI/MCLKIN. A divide by 64 circuit ensures that the SCL output frequency during self boot operation is never greater than 400 kHz for most input clock frequencies. With the external master clock to the ADAU1787 being between 11.264 MHz and 27 MHz, the SCL frequency ranges from 176 kHz to 422 kHz. If the self-boot EEPROM is not rated for operation above 400 kHz, use a master clock that is no faster than 25.6 MHz. Table 35 details the list of instructions that are possible during an ADAU1787 self boot. The 0x01 and 0x05 instruction bytes are used to load the register, program, and parameter settings. EEPROM Size The self-boot circuit is compatible with an EEPROM that has a 2-byte address. For most EEPROM families, a 2-byte address is used on devices that are 32 kB or larger. The EEPROM must be set to Address 0x50. Examples of two compatible EEPROMs include Atmel AT24C256C and STMicroelectronics M24256. Table 36 lists the maximum necessary EEPROM size, assuming that there is 100% utilization. There is inherently some overhead for instructions to control the self boot procedure. CRC An 8-bit CRC validates the content of the EEPROM. This CRC is strong enough to detect single error bursts of up to eight bits in size. The terminate self boot instruction (0x00 instruction byte) must be followed by a CRC byte. The CRC is generated using all of the EEPROM bytes from Address 0x0000 to the last 0x00 instruction byte. The polynomial for the CRC is x8 + x2 + x + 1. If the CRC is incorrect or if an unrecognized instruction byte is read during self boot, the boot process is immediately stopped and restarted after a 250 ms delay (for a 12.288 MHz input clock). When SigmaStudio is used, the CRC byte is generated automatically when a configuration is downloaded to the EEPROM. Delay The delay instruction (0x02 instruction byte) delays by the 16-bit setting × 2048 clock cycles. Boot Time The time to self boot the ADAU1787 from an EEPROM can be calculated by the following equation: Self Boot Time = 64/MCLK Frequency × Total Bytes + Wait Time The self boot operation starts after 16,568 clock cycles are seen on the XTALI/MCLKIN pin after PD is set high. With a 12.288 MHz clock, this wait time corresponds to approximately a 1.35 ms wait time from power-up. This delay ensures that the crystal used for generating the master clock has ramped up to a stable oscillation. Rev. A | Page 54 of 280 ADAU1787 Data Sheet Table 36. Maximum EEPROM Size ADAU1787 Memory Blocks Program FastDSP Bank A Parameters FastDSP Bank B Parameters FastDSP Bank C Parameters Registers SigmaDSP Program SigmaDSP Parameter Total Bytes Word Size (Bytes per Word) 4 4 4 4 1 5 4 Not applicable Words 64 320 (64 × 5) 320 320 512 2048 2048 Not applicable Rev. A | Page 55 of 280 Total EEPROM Space Requirement (Bytes) 256 1280 1280 1280 512 10240 8192 23040 ADAU1787 Data Sheet MULTIPURPOSE PINS Table 37. Multipurpose Pin Functions The ADAU1787 has thirteen multipurpose (MPx) pins that can be used for serial data I/O, digital microphone inputs, clock outputs, PDM outputs, and interrupts. Each pin can be individually set to either its default or MPx setting. The function of each of these pins is set in using the MPx_MODE bits. By default, each pin is configured as its normal function. MPx Pin Function1 Digital Microphone Channel 4 to Channel 5 Input (DMIC45) Digital Microphone Channel 6 to Channel 7 Input (DMIC67) General-Purpose Input (GPI) General-Purpose Output from GPIOx_OUT Bits (GPO_REG) General-Purpose Output from SigmaDSP (GPO_SDSP) MCLK Output (MCLKO) IRQ1 Output (IRQ1) IRQ2 Output (IRQ2) Care must be taken when using SELFBOOT/MP11 and SW_EN/MP12 as multipurpose pins. The states of these pins at power-up (later of either PD pin going high or power being applied with PD pin already high) determine whether the device self boots, which must still be followed even if the pins are used for another multipurpose function later. When an MPx pin is set as a general-purpose input, the MPx pin can be read via all control interfaces via the GPIOx_IN bits, the pin can also be read and acted upon by the SigmaDSP core, and the pin can be used to conditionally execute instructions or trigger the compressor in the FastDSP. When an MPx pin is set as general-purpose output, the state of the pin can be set via all control interfaces using the GPIOx_OUT bits or by the SigmaDSP core. The GPIO maps to the corresponding MPx pin, for example, GPIO1 maps to MP1/BCLK_0. Any MPx pin can be used as the digital microphone input for Digital Microphone Channel 4/ Digital Microphone Channel 5 or Digital Microphone Channel 6/ Digital Microphone Channel 7. If multiple pins are assigned to this function, the lowest number MPx pin is used, and the other pins have no function. Any MPx pin can be used as a master clock output. The rate of the master clock output is determined by the MCLKO_RATE bits. Multiple pins can be used as this function if desired. Any MPx pin can be used to output the PDM clock or data signal for the PDM output interface. Any MPx pin can be used to output the interrupt status from the two interrupt sources. 1 Direction In In In Out Out Out Out Out These functions are enumeration options in Register 0xC08B through Register 0xC090 that any of the MPx pins can be set to. Interrupts Each multipurpose pin can be used to output one of two interrupts that have various sources when selected for this function. The sources for the interrupts are for DAC and ADC channels clipping, PLL locking or unlocking, input and output ASRCs locking or unlocking, the generic SigmaDSP interrupts, and the AVDD undervoltage warning. Each interrupt source can be individually masked with their respective IRQx_MASKx registers. Each interrupt output can be set to active low or active high output on the pin selected for the interrupt output via the IRQx_FUNC bits. The status of each interrupt source can be read via the IRQ status registers (IRQx_STATUSx). When an interrupt source is masked, if that interrupt becomes true, the interrupt is shown in the interrupt status registers but does not cause the MPx pin (if set as IRQx) to show an interrupt. All sources of each interrupt are cleared via a write of 1 to the IRQx_CLEAR bits. The interrupt status bits are sticky, such that if an interrupt source becomes true, the status reads 1 until a clear occurs, even if that interrupt source is no longer true. The SigmaDSP interrupts are initiated by the SigmaDSP writing to the SDSP_INTx bits. Pin Controls Each pin that can be used as a multipurpose pin has several control selections to set various setting. When the pin is used as an output, the drive strength can be selected at 2 mA, 4 mA, 8 mA, or 12 mA. In addition, a weak pull-up or pull-down can be selected. These settings are in their respective pin control register. These pin control settings affect the pins operation in both normal functional mode and when used in all multipurpose pin modes. Rev. A | Page 56 of 280 Data Sheet ADAU1787 SERIAL DATA PORTS The serial data input and output ports of the ADAU1787 can be set to accept or transmit data in a 2-channel format such as I2S or up to 16 channels in a time division multiplexing (TDM) stream to interface to external ADCs, DACs, DSPs, and system on chips (SOCs). Data is processed in twos complement, MSB first format. The left channel data field always precedes the right channel data field in 2-channel streams. When using a high bit clock rate (12.288 MHz or higher), it is recommended to increase the drive strength settings for the output signal pins. The high drive strength effectively speeds up the transition times of the waveforms, thereby improving the signal integrity of the clock and data lines. The drive strength can be set in the pad drive strength registers (Register 0xC094 through Register 0xC0A0). The serial data clocks do not need to be synchronous with the ADAU1787 master clock input, but the frame clock and bit clock must be synchronous to each other. The FSYNC_x and BCLK_x pins are used to clock both the serial input and output ports. The pins can also be used as a source to the PLL to provide the main chip clock. Each serial port can be set to be either the master or the slave in a system. Because there is only one set of serial data clocks, the input and output of a single port must always both be either master or slave. Table 38 describes the proper serial port settings for standard audio data formats. More information about the settings in Table 38 can be found in the SPTx_CTRLx register descriptions. The SPTx_SAI_MODE bits set whether the serial port is operating in stereo mode or TDM mode. In stereo modes, both edges of frame clock determine where data is placed, and the left channel maps to the output for Channel 0, while the right channel maps to the output for Channel 1. In TDM mode only, the rising edge of frame clock determine where data is placed. In TDM mode, each channel of data receives a slot that can be either 16, 24, or 32 BCLKs wide. The width of each slot is determined by the SPTx_SLOT_WIDTH bits. The serial data control registers allow control of the clock polarity and the data input modes. The valid data formats are I2S (delay by 1), left justified (delay by 0), or right justified (delay by 8, 12, or 16 BCLKs). The delay indicates the number of bit clocks BCLKs from the rising/falling edge of frame clock FSYNC_x where the MSB of the data is placed in stereo modes, and the number of bit clocks BCLKs from the rising of frame clock in TDM mode. In all modes except for the right justified mode, the serial port inputs an arbitrary number of bits up to a limit of 24. Extra bits do not cause an error, but the bits are ignored. The serial port can operate with an arbitrary number of bit clock BCLK_x transitions in each frame clock frame. The polarity of both frame clock and bit clock can be inverted via the SPTx_LRCLK_POL and SPTx_BCLK_POL bits. These bits do not need to be used to support the typical formats shown in Table 38. Setting either SPTx_LRCLK_POL or SPTx_BCLK_POL to 1 places an inverter at the input to the serial port on its respective signal. For example, while serial data and frame clock are normally sampled on the rising edge of bit clock, setting SPTx_BCLK_POL = 1 samples on the falling edge of bit clock. Each serial port can be set to be a master, in which case BCLK_x and FSYNC_x are driven as outputs. The output rate and direction of these two signals are set via the SPTx_LRCLK_SRC and SPTx_BCLK_SRC bits. A bit clock rate higher than 24.576 MHz cannot be generated. Therefore, the settings of these registers that request this rate result in no bit clock. Unused bit slots can be tristated so that multiple ICs can drive a single serial data bus, which is controlled via the SPTx_TRI_ STATE bit. For example, in a 32-bit TDM frame with 24-bit data, the eight unused bits are tristated. Inactive channels are also tristated for one full frame each. Serial output channels are disabled when the SPTx_OUT_ROUTEy bits are set to 0x3E. Note that the timing for serial data output changes based on the minimum IOVDD voltage. While the serial ports can work for inputting a signal on SDATAI_x for any IOVDD and bit clock rate within the specification, the delay on SDATAO_x at 1.1 V excludes operating at higher bit clock rates. Table 38. Serial Port Data Format Settings Format I2S (See Figure 68) Left Justified (See Figure 68) Right Justified (See Figure 68) TDM (See Figure 69) 1 Frame Clock Mode, Bit (SPTx_SAI_MODE) 0 (50 % duty cycle) 0 0 0 0 1 (single bit clock wide pulse) Sets the Slot Width per Channel, Bit (SPTx_SLOT_WIDTH)1 XX XX XX XX XX XX X = don’t care. Rev. A | Page 57 of 280 Sets the MSB Position from Start of Frame Clock, Bit (SPTx_DATA_FORMAT) 000 (One bit clock delay) 001 (No delay) 010 (delay by 8 bit clocks) 011 (delay by 12 bit clocks) 100 (delay by 16 bit clocks) 000 ADAU1787 Data Sheet BCLK_x SDATAx I2S LEFT CHANNEL RIGHT CHANNEL SDATAx_x LEFT JUSTIFIED LEFT CHANNEL RIGHT CHANNEL SDATAx_x RIGHT JUSTIFIED LEFT CHANNEL 20127-073 FSYNC_x RIGHT CHANNEL Figure 68. Stereo Modes: I2S, Left Justified, and Right Justified Modes, 16 Bits to 24 Bits per Channel, Any Number of BCLKs Are Allowed BCLK_x SDATAx_x 29 30 31 0 1 2 3 25 26 27 28 29 30 31 0 CHANNEL 0 1 2 3 4 26 CHANNEL 7 Figure 69. 8-Channel TDM Mode, Default Settings, Except SPTx_SAI_MODE = 1 Rev. A | Page 58 of 280 27 28 29 30 31 0 20127-074 FSYNC_x Data Sheet ADAU1787 APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT Bypass each analog and digital power supply pin to its nearest appropriate ground pin with a single 0.1 μF capacitor. The connections to each side of the capacitor must be as short as possible, and the trace must be routed on a single layer with no vias. For maximum effectiveness, locate the capacitor equidistant from the power and ground pins or slightly closer to the power pin if equidistant placement is not possible. Thermal connections to the ground planes must be made on the far side of the capacitor. The HPVDD supply is for the headphone amplifiers. If the headphone amplifiers are enabled, the PCB trace to this pin must be wider than the traces to other pins to increase the current carrying capacity. A wider trace must also be used for the headphone output lines. Each supply signal on the board must also be bypassed with a single bulk capacitor (10 μF to 47 μF). AVDD PIN AGND PIN Use a single ground plane in the application layout. Place the components in the analog signal path away from the digital signals. PCB STACKUP Figure 71 shows the PCB stackup. TO AGND 20127-075 CAPACITOR FROM AVDD GROUNDING Figure 70. Recommended Power Supply Bypass Capacitor Layout VIA L1 TO L4 SILKSCREEN AND SOLDER MASK (0.8 MIL THICK) LAYER 1 TOP SIDE 1.5OZ CU FINISHED (2 MIL THICK) LAMINATE (8.7 MIL THICK) LAYER 2 GROUND PLANE CU (0.6 MIL THICK) CORE (8 MIL THICK) LAYER 3 POWER PLANE 1 CU (0.6 MIL THICK) PREPREG (8.45 MIL THICK) LAYER 4 SIGNAL (CU 0.6 MIL THICK) PREPREG (3.9 MIL THICK) LAYER 5 BLANK (NO COPPER) PREPREG (8.45 MIL THICK) LAYER 5 (CU 0.6 MIL THICK) CORE (8 MIL THICK) LAYER 5 (GROUND PLANE CU 0.6 MIL THICK) PREPREG (8.7 MIL THICK) LAYER 6 BOTTOM SIDE 1.5 0Z CU FINISHED (2 MIL THICK) SCREEN AND SOLDER MASK 0.8 MIL THICK VIA L1 TO L6 0.062 ± 0.005 Figure 71. PCB Stackup Rev. A | Page 59 of 280 20127-171 6 LAYER CONSTRUCTION DETAIL SCALE: NONE ADAU1787 Data Sheet REGISTER SUMMARY Table 39. Reg (Hex) C000 C001 C002 C003 C004 Bits [7:0] [7:0] [7:0] [7:0] [7:0] Bit 7 [7:0] PGA3_EN [7:0] [7:0] DMIC7_EN PDM1_EN C008 C009 C00A C00B C00C C00D Name VENDOR_ID DEVICE_ID1 DEVICE_ID2 REVISION ADC_DAC_ HP_PWR PLL_MB_ PGA_PWR DMIC_PWR SAI_CLK_ PWR DSP_PWR ASRC_PWR FINT_PWR FDEC_PWR KEEPS CHIP_PWR C00E C00F C010 C011 C012 C013 C014 C015 C016 C017 CLK_CTRL1 CLK_CTRL2 CLK_CTRL3 CLK_CTRL4 CLK_CTRL5 CLK_CTRL6 CLK_CTRL7 CLK_CTRL8 CLK_CTRL9 ADC_CTRL1 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] C018 C019 ADC_CTRL2 ADC_CTRL3 [7:0] [7:0] C01A ADC_CTRL4 [7:0] C01B C01C ADC_CTRL5 ADC_MUTES [7:0] [7:0] C01D C01E C01F C020 C021 ADC0_VOL ADC1_VOL ADC2_VOL ADC3_VOL PGA0_ CTRL1 PGA0_ CTRL2 PGA1_ CTRL1 PGA1_ CTRL2 PGA2_ CTRL1 PGA2_ CTRL2 PGA3_ CTRL1 PGA3_ CTRL2 PGA_CTRL MBIAS_ CTRL DMIC_ CTRL1 [7:0] [7:0] [7:0] [7:0] [7:0] C005 C006 C007 C022 C023 C024 C025 C026 C027 C028 C029 C02A C02B [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit 6 Bit 5 Bit 4 PB1_EN PB0_EN PGA2_EN PGA1_EN PGA0_EN DMIC6_EN PDM0_EN DMIC5_EN DMIC_ CLK1_EN DMIC4_EN DMIC_CLK0_EN RESERVED RESERVED ASRCO2_EN FINT6_EN FDEC6_EN RESERVED RESERVED Bit 3 VENDOR DEVICE1 DEVICE2 REV ADC3_EN Bit 2 Bit 1 Bit 0 ADC2_EN ADC1_EN MBIAS1_EN MBIAS0_EN DMIC3_EN SPT1_ OUT_EN DMIC2_EN SPT1_IN_EN PGA1_ SLEW_DIS PGA2_GAIN[10:5] PGA3_GAIN[10:5] [7:0] PGA3_ BOOST RESERVED [7:0] [7:0] RESERVED RESERVED PGA2_ SLEW_DIS [7:0] [7:0] PLL_EN 0x02 R/W DMIC1_EN SPT0_ OUT_EN DMIC0_EN SPT0_IN_EN 0x00 0x00 R/W R/W 0x00 0x00 0x00 0x00 0x10 0x10 R/W R/W R/W R/W R/W R/W 0xC8 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x22 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00 0x00 R/W R/W 0x40 R/W 0x06 0x00 R/W R/W 0x40 0x40 0x40 0x40 0x00 R/W R/W R/W R/W R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 0x00 R/W R/W 0x33 R/W SDSP_EN ASRCO0_EN FINT4_EN FDEC4_EN CM_KEEP_ALIVE DLDO_CTRL PGA2_ BOOST RESERVED [7:0] [7:0] XTAL_EN ASRCO1_EN FINT5_EN FDEC5_EN PGA1_GAIN[10:5] [7:0] R/W R R R R R/W RESERVED FDSP_EN ASRCI3_EN ASRCI2_EN ASRCI1_EN ASRCI0_EN FINT3_EN FINT2_EN FINT1_EN FINT0_EN FDEC3_EN FDEC2_EN FDEC1_EN FDEC0_EN RESERVED KEEP_SDSP KEEP_FDSP RESERVED CM_ MASTER_ POWER_EN STARTUP_ BLOCK_EN OVER SYNC_SOURCE PLL_BYPASS PLL_TYPE XTAL_MODE PLL_SOURCE RESERVED PLL_INPUT_PRESCALER RESERVED PLL_INTEGER_DIVIDER[12:8] PLL_INTEGER_DIVIDER[7:0] PLL_NUMERATOR[15:8] PLL_NUMERATOR[7:0] PLL_DENOMINATOR[15:8] PLL_DENOMINATOR[7:0] RESERVED PLL_UPDATE ADC01_ ADC23_ ADC23_FS ADC01_FS DEC_ORDER DEC_ORDER RESERVED ADC23_IBIAS RESERVED ADC01_IBIAS ADC3_ ADC2_ ADC1_ ADC0_ RESERVED HPF_EN HPF_EN HPF_EN HPF_EN RESERVED ADC_ ADC_ ADC_ RESERVED ADC23_ ADC01_ VOL_ZC VOL_LINK HARD_VOL FCOMP FCOMP RESERVED DIFF_INPUT ADC_AIN_CHRG_TIME ADC3_ ADC2_ ADC1_ ADC0_ RESERVED MUTE MUTE MUTE MUTE ADC0_VOL ADC1_VOL ADC2_VOL ADC3_VOL PGA0_ PGA0_ PGA0_GAIN[10:5] SLEW_DIS BOOST RESERVED PGA0_GAIN[4:0] ASRCO3_EN FINT7_EN FDEC7_EN PGA1_ BOOST RESERVED [7:0] ADC0_EN Reset 0x41 0x17 0x87 0x01 0x00 PGA3_ SLEW_DIS RESERVED PGA1_GAIN[4:0] PGA2_GAIN[4:0] PGA3_GAIN[4:0] PGA_GAIN_LINK MBIAS_IBIAS DMIC_CLK1_RATE RESERVED RESERVED RESERVED Rev. A | Page 60 of 280 PGA_SLEW_RATE MBIAS1_ MBIAS0_ LEVEL LEVEL DMIC_CLK0_RATE Data Sheet Reg (Hex) C02C ADAU1787 Bits [7:0] C032 C033 C034 C035 C036 C037 C038 C039 C03A Name DMIC_ CTRL2 DMIC_ CTRL3 DMIC_ CTRL4 DMIC_ CTRL5 DMIC_ CTRL6 DMIC_ MUTES DMIC_VOL0 DMIC_VOL1 DMIC_VOL2 DMIC_VOL3 DMIC_VOL4 DMIC_VOL5 DMIC_VOL6 DMIC_VOL7 DAC_CTRL1 C03B DAC_CTRL2 [7:0] C03C C03D C03E DAC_VOL0 DAC_VOL1 DAC_ ROUTE0 DAC_ ROUTE1 HP_CTRL FDEC_ CTRL1 FDEC_ CTRL2 FDEC_ CTRL3 FDEC_ CTRL4 FDEC_ ROUTE0 FDEC_ ROUTE1 FDEC_ ROUTE2 FDEC_ ROUTE3 FDEC_ ROUTE4 FDEC_ ROUTE5 FDEC_ ROUTE6 FDEC_ ROUTE7 FINT_CTRL1 FINT_CTRL2 FINT_CTRL3 FINT_CTRL4 [7:0] [7:0] [7:0] RESERVED DMIC3_ MUTE DMIC0_VOL DMIC1_VOL DMIC2_VOL DMIC3_VOL DMIC4_VOL DMIC5_VOL DMIC6_VOL DMIC7_VOL DAC_ FCOMP DAC_ LPM_II DAC0_VOL DAC1_VOL DAC0_ROUTE [7:0] RESERVED DAC1_ROUTE [7:0] [7:0] RESERVED HP1_MODE FDEC01_OUT_FS RESERVED [7:0] RESERVED FDEC23_OUT_FS [7:0] RESERVED [7:0] RESERVED C02D C02E C02F C030 C031 C03F C040 C041 C042 C043 C044 C045 C046 C047 C048 C049 C04A C04B C04C C04D C04E C04F C050 [7:0] [7:0] [7:0] Bit 7 DMIC01_ MAP DMIC23_ MAP DMIC45_ MAP DMIC67_ MAP Bit 6 DMIC01_ EDGE DMIC23_ EDGE DMIC45_ EDGE DMIC67_ EDGE [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] DMIC7_ MUTE DMIC6_ MUTE DAC_ MORE_FILT DAC1_MUTE Bit 5 DMIC01_ FCOMP DMIC23_ FCOMP DMIC45_ FCOMP DMIC67_ FCOMP RESERVED Bit 4 DMIC01_ DEC_ORDER DMIC23_ DEC_ORDER DMIC45_ DEC_ORDER DMIC67_ DEC_ORDER DMIC5_ MUTE DMIC4_ MUTE Reset 0x01 R/W R/W DMIC23_FS 0x01 R/W DMIC45_FS 0x01 R/W DMIC67_FS 0x01 R/W 0x04 R/W 0x00 R/W 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x02 R/W R/W R/W R/W R/W R/W R/W R/W R/W 0xC4 R/W 0x40 0x40 0x00 R/W R/W R/W 0x01 R/W FDEC01_IN_FS 0x00 0x25 R/W R/W RESERVED FDEC23_IN_FS 0x25 R/W FDEC45_OUT_FS RESERVED FDEC45_IN_FS 0x25 R/W FDEC67_OUT_FS RESERVED FDEC67_IN_FS 0x25 R/W DAC_LPM DAC0_ MUTE RESERVED DAC_IBIAS DAC1_ HPF_EN DAC0_ HPF_EN Bit 3 DMIC01_ HPF_EN DMIC23_ HPF_EN DMIC45_ HPF_EN DMIC67_ HPF_EN Bit 2 DMIC_ VOL_ZC DMIC2_ MUTE Bit 1 DMIC01_FS DMIC_ VOL_LINK DMIC1_ MUTE Bit 0 DMIC_ HARD_VOL DMIC0_ MUTE DAC_FS DAC_ VOL_ZC DAC_ HARD_VOL RESERVED DAC_ VOL_LINK HP0_MODE [7:0] RESERVED FDEC0_ROUTE 0x00 R/W [7:0] RESERVED FDEC1_ROUTE 0x00 R/W [7:0] RESERVED FDEC2_ROUTE 0x00 R/W [7:0] RESERVED FDEC3_ROUTE 0x00 R/W [7:0] RESERVED FDEC4_ROUTE 0x00 R/W [7:0] RESERVED FDEC5_ROUTE 0x00 R/W [7:0] RESERVED FDEC6_ROUTE 0x00 R/W [7:0] RESERVED FDEC7_ROUTE 0x00 R/W 0x52 0x52 0x52 0x52 R/W R/W R/W R/W [7:0] [7:0] [7:0] [7:0] RESERVED RESERVED RESERVED RESERVED FINT01_OUT_FS FINT23_OUT_FS FINT45_OUT_FS FINT67_OUT_FS RESERVED RESERVED RESERVED RESERVED Rev. A | Page 61 of 280 FINT01_IN_FS FINT23_IN_FS FINT45_IN_FS FINT67_IN_FS ADAU1787 Reg (Hex) C051 C052 C053 C054 C055 C056 C057 C058 C059 C05A C05B C05C C05D C05E C05F C060 C061 C062 C063 C064 C065 C066 C067 C068 C069 C06A C06B C06C C06D C06E C06F C070 Data Sheet Name FINT_ ROUTE0 FINT_ ROUTE1 FINT_ ROUTE2 FINT_ ROUTE3 FINT_ ROUTE4 FINT_ ROUTE5 FINT_ ROUTE6 FINT_ ROUTE7 ASRCI_CTRL Bits [7:0] Bit 7 RESERVED Reset 0x00 R/W R/W [7:0] RESERVED FINT1_ROUTE 0x00 R/W [7:0] RESERVED FINT2_ROUTE 0x00 R/W [7:0] RESERVED FINT3_ROUTE 0x00 R/W [7:0] RESERVED FINT4_ROUTE 0x00 R/W [7:0] RESERVED FINT5_ROUTE 0x00 R/W [7:0] RESERVED FINT6_ROUTE 0x00 R/W [7:0] RESERVED FINT7_ROUTE 0x00 R/W [7:0] ASRCI_ MORE_FILT ASRCI_ ROUTE01 ASRCI_ ROUTE23 ASRCO_ CTRL ASRCO_ ROUTE0 ASRCO_ ROUTE1 ASRCO_ ROUTE2 ASRCO_ ROUTE3 FDSP_RUN FDSP_ CTRL1 [7:0] ASRCI_ LPM ASRCI1_ROUTE 0x02 R/W ASRCI0_ROUTE 0x00 R/W [7:0] ASRCI3_ROUTE ASRCI2_ROUTE 0x00 R/W 0x02 R/W 0x00 R/W FDSP_ CTRL2 FDSP_ CTRL3 FDSP_ CTRL4 FDSP_ CTRL5 FDSP_ CTRL6 FDSP_ CTRL7 FDSP_ CTRL8 FDSP_SL_ ADDR FDSP_SL_ P0_3 FDSP_SL_ P0_2 FDSP_SL_ P0_1 FDSP_SL_ P0_0 FDSP_SL_ P1_3 FDSP_SL_ P1_2 [7:0] RESERVED [7:0] RESERVED [7:0] [7:0] Bit 6 Bit 5 ASRCI_ VFILT ASRCO_ ASRCO_ MORE_FILT VFILT RESERVED ASRCO_ LPM Bit 4 Bit 3 FINT0_ROUTE ASRCI_ SOURCE Bit 2 Bit 1 ASRCI_ LPM_II ASRCO_SAI_ SEL Bit 0 ASRCI_OUT_FS ASRCO_ LPM_II ASRCO0_ROUTE ASRCO_IN_FS [7:0] RESERVED ASRCO1_ROUTE 0x00 R/W [7:0] RESERVED ASRCO2_ROUTE 0x00 R/W [7:0] RESERVED ASRCO3_ROUTE 0x00 R/W 0x00 0x70 R/W R/W 0x3F R/W 0x00 W 0x00 R/W 0x00 R/W 0x7F R/W 0x00 R/W 0x00 R/W 0x00 R/W [7:0] [7:0] [7:0] RESERVED FDSP_RAMP_RATE FDSP_ COPY_CB RESERVED [7:0] [7:0] FDSP_ FDSP_ COPY_CA COPY_BC FDSP_EXP_ ATK_SPEED FDSP_RATE_DIV[15:8] FDSP_RUN FDSP_BANK_SEL FDSP_ FDSP_ COPY_BA COPY_AC FDSP_RATE_SOURCE FDSP_ COPY_AB FDSP_RATE_DIV[7:0] [7:0] RESERVED [7:0] FDSP_REG_ FDSP_REG_ COND7 COND6 RESERVED [7:0] FDSP_ FDSP_ ZERO_ RAMP_ STATE MODE FDSP_LAMBDA FDSP_MOD_N FDSP_REG_ COND5 FDSP_REG_ COND4 FDSP_REG_ FDSP_REG_ COND3 COND2 FDSP_SL_ADDR FDSP_REG_ COND1 FDSP_REG_ COND0 [7:0] FDSP_SL_P0[31:24] 0x00 R/W [7:0] FDSP_SL_P0[23:16] 0x00 R/W [7:0] FDSP_SL_P0[15:8] 0x00 R/W [7:0] FDSP_SL_P0[7:0] 0x00 R/W [7:0] FDSP_SL_P1[31:24] 0x00 R/W [7:0] FDSP_SL_P1[23:16] 0x00 R/W Rev. A | Page 62 of 280 Data Sheet Reg (Hex) C071 C072 C073 0xC074 C075 C076 C077 C078 C079 C07A C07B C07C C07D C07E C07F C080 C081 C082 C083 C084 C085 C086 C087 C088 C089 C08A C08B C08C C08D C08E C08F C090 C091 C092 C093 Name FDSP_SL_ P1_1 FDSP_SL_ P1_0 FDSP_SL_ P2_3 FDSP_SL_ P2_2 FDSP_SL_ P2_1 FDSP_SL_ P2_0 FDSP_SL_ P3_3 FDSP_SL_ P3_2 FDSP_SL_ P3_1 FDSP_SL_ P3_0 FDSP_SL_ P4_3 FDSP_SL_ P4_2 FDSP_SL_ P4_1 FDSP_SL_ P4_0 FDSP_SL_ UPDATE SDSP_ CTRL1 SDSP_ CTRL2 SDSP_ CTRL3 SDSP_ CTRL4 SDSP_ CTRL5 SDSP_ CTRL6 SDSP_ CTRL7 SDSP_ CTRL8 SDSP_ CTRL9 SDSP_ CTRL10 SDSP_ CTRL11 MP_CTRL1 MP_CTRL2 MP_CTRL3 MP_CTRL4 MP_CTRL5 MP_CTRL6 MP_CTRL7 MP_CTRL8 MP_CTRL9 ADAU1787 Bits [7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 FDSP_SL_P1[15:8] Bit 2 Bit 1 Bit 0 Reset 0x00 R/W R/W [7:0] FDSP_SL_P1[7:0] 0x00 R/W [7:0] FDSP_SL_P2[31:24] 0x00 R/W [7:0] FDSP_SL_P2[23:16] 0x00 R/W [7:0] FDSP_SL_P2[15:8] 0x00 R/W [7:0] FDSP_SL_P2[7:0] 0x00 R/W [7:0] FDSP_SL_P3[31:24] 0x00 R/W [7:0] FDSP_SL_P3[23:16] 0x00 R/W [7:0] FDSP_SL_P3[15:8] 0x00 R/W [7:0] FDSP_SL_P3[7:0] 0x00 R/W [7:0] FDSP_SL_P4[31:24] 0x00 R/W [7:0] FDSP_SL_P4[23:16] 0x00 R/W [7:0] FDSP_SL_P4[15:8] 0x00 R/W [7:0] FDSP_SL_P4[7:0] 0x00 R/W 0x00 W 0x00 R/W SDSP_RUN 0x00 R/W SDSP_ WDOG_EN 0x00 R/W 0x00 R/W [7:0] FDSP_SL_ UPDATE RESERVED [7:0] RESERVED [7:0] SDSP_SPEED SDSP_RATE_SOURCE RESERVED [7:0] RESERVED [7:0] SDSP_ WDOG_MUTE SDSP_WDOG_VAL[23:16] [7:0] SDSP_WDOG_VAL[15:8] 0x00 R/W [7:0] SDSP_WDOG_VAL[7:0] 0x00 R/W 0x07 R/W [7:0] RESERVED RESERVED SDSP_MOD_DATA_MEM[11:8] [7:0] SDSP_MOD_DATA_MEM[7:0] 0xF4 R/W [7:0] SDSP_RATE_DIV[15:8] 0x07 R/W [7:0] SDSP_RATE_DIV[7:0] 0xFF R/W SDSP_INT0 0x00 W GPIO0_OUT GPIO8_OUT 0x00 0x00 0x00 0x00 0x00 0x00 0x10 0x00 0x00 R/W R/W R/W R/W R/W R/W R/W R/W R/W [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] RESERVED RESERVED GPIO7_OUT MP1_MODE MP3_MODE MP5_MODE MP7_MODE MP9_MODE MP11_MODE MCLKO_RATE GPIO6_OUT GPIO5_OUT GPIO4_OUT RESERVED GPIO12_OUT SDSP_INT3 SDSP_INT2 RESERVED GPIO3_OUT GPIO11_ OUT MP0_MODE MP2_MODE MP4_MODE MP6_MODE MP8_MODE MP10_MODE GPI_DB GPIO2_OUT GPIO1_OUT GPIO10_ GPIO9_OUT OUT Rev. A | Page 63 of 280 SDSP_INT1 ADAU1787 Reg (Hex) C094 Data Sheet Name FSYNC0_ CTRL BCLK0_ CTRL SDATAO0_ CTRL SDATAI0_ CTRL FSYNC1_ CTRL BCLK1_ CTRL SDATAO1_ CTRL SDATAI1_ CTRL DMIC_ CLK0_CTRL Bits [7:0] C09D C09E C095 C096 C097 [7:0] Bit 7 Bit 6 RESERVED RESERVED [7:0] Bit 5 FSYNC0_ PULL_SEL BCLK0_ PULL_SEL RESERVED Bit 4 FSYNC0_ PULL_EN BCLK0_ PULL_EN SDATAI0_ PULL_SEL FSYNC1_ PULL_SEL BCLK1_ PULL_SEL SDATAO1_ PULL_SEL SDATAI1_ PULL_SEL DMIC_ CLK0_ PULL_SEL DMIC_ CLK1_ PULL_SEL DMIC01_ PULL_SEL DMIC23_ PULL_SEL SDATAI0_ PULL_EN FSYNC1_ PULL_EN BCLK1_ PULL_EN SDATAO1_ PULL_EN SDATAI1_ PULL_EN DMIC_CLK0_ PULL_EN Bit 3 RESERVED RESERVED [7:0] RESERVED [7:0] RESERVED [7:0] RESERVED [7:0] RESERVED [7:0] RESERVED [7:0] RESERVED DMIC_ CLK1_CTRL [7:0] RESERVED DMIC01_ CTRL DMIC23_ CTRL I2C_SPI_ CTRL IRQ_CTRL1 [7:0] RESERVED [7:0] RESERVED C0A2 IRQ1_ MASK1 [7:0] IRQ1_ADC3_ CLIP_MASK IRQ1_ADC2_ CLIP_MASK C0A3 IRQ1_ MASK2 [7:0] IRQ1_ ASRCO_ UNLOCKED_ MASK C0A4 IRQ1_ MASK3 [7:0] IRQ1_ ASRCO_ LOCKED_ MASK RESERVED C0A5 IRQ2_ MASK1 [7:0] IRQ2_ADC3_ CLIP_MASK IRQ2_ADC2_ CLIP_MASK IRQ2_ ADC1_ CLIP_MASK IRQ2_ADC0_ CLIP_MASK C0A6 IRQ2_ MASK2 [7:0] IRQ2_ ASRCO_ UNLOCKED_ MASK IRQ2_ ASRCI_ UNLOCKED_ MASK IRQ2_ASRCI_ LOCKED_MASK IRQ2_ PRAMP_ MASK C0A7 IRQ2_ MASK3 [7:0] IRQ2_ ASRCO_ LOCKED_ MASK RESERVED IRQ2_ SDSP3_ MASK C0A8 RESETS [7:0] RESERVED IRQ2_ POWER_UP_ COMPLETE_ MASK SOFT_RESET C0A9 [7:0] C0AA C0AB READ_ LAMBDA STATUS1 STATUS2 C0AC C0AD GPI1 GPI2 [7:0] [7:0] C098 C099 C09A C09B C09C C09F C0A0 C0A1 [7:0] [7:0] [7:0] [7:0] RESERVED DMIC_ CLK1_ PULL_EN DMIC01_ PULL_EN DMIC23_ PULL_EN RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED IRQ2_FUNC IRQ1_FUNC RESERVED IRQ1_ ADC1_ CLIP_MASK IRQ1_ ASRCI_ UNLOCKED_ MASK IRQ1_ADC0_ CLIP_MASK RESERVED IRQ1_ ASRCI_ LOCKED_ MASK IRQ1_POWER_ UP_COMPLETE_ MASK IRQ1_ PRAMP_ MASK IRQ1_ SDSP3_ MASK IRQ1_ AVDD_ UVW_ MASK IRQ1_ SDSP2_ MASK RESERVED IRQ2_ AVDD_ UVW_ MASK IRQ2_ SDSP2_ MASK Bit 1 Bit 0 FSYNC0_DRIVE Reset 0x05 R/W R/W BCLK0_DRIVE 0x05 R/W SDATAO0_ DRIVE SDATAI0_DRIVE 0x04 R/W 0x05 R/W FSYNC1_DRIVE 0x05 R/W BCLK1_DRIVE 0x05 R/W SDATAO1_DRIVE 0x05 R/W SDATAI1_DRIVE 0x05 R/W DMIC_CLK0_DRIVE 0x05 R/W DMIC_CLK1_DRIVE 0x05 R/W DMIC01_DRIVE 0x05 R/W DMIC23_DRIVE 0x05 R/W RESERVED SCL_SCLK_ DRIVE IRQ2_ CLEAR IRQ1_ DAC1_ CLIP_MASK IRQ1_ PLL_ UNLOCKED_ MASK IRQ1_ SDSP1_ MASK SDA_MISO_ DRIVE IRQ1_ CLEAR IRQ1_ DAC0_ CLIP_MASK IRQ1_ PLL_ LOCKED_ MASK IRQ1_ SDSP0_ MASK 0x00 R/W 0x00 R/W 0xF3 R/W 0xFF R/W 0x1F R/W IRQ2_ DAC1_ CLIP_MASK 0xF3 R/W IRQ2_PLL_ UNLOCKED_ MASK IRQ2_ DAC0_ CLIP_ MASK IRQ2_PLL_ LOCKED_ MASK 0xFF R/W IRQ2_ SDSP1 _MASK IRQ2_ SDSP0_ MASK 0x1F R/W SOFT_ FULL_ RESET 0x00 W 0x3F R DAC0_CLIP PLL_LOCK 0x00 0x00 R R GPIO0_IN GPIO8_IN 0x00 0x00 R R RESERVED RESERVED ADC3_CLIP POWER_UP_ COMPLETE GPIO7_IN Bit 2 FSYNC0_ SLEW BCLK0_ SLEW SDATAO0_ SLEW SDATAI0_ SLEW FSYNC1_ SLEW BCLK1_ SLEW SDATAO1_ SLEW SDATAI1_ SLEW DMIC_ CLK0_ SLEW DMIC_ CLK1_ SLEW DMIC01_ SLEW DMIC23_ SLEW FDSP_CURRENT_LAMBDA ADC2_CLIP SYNC_LOCK ADC1_CLIP SPT1_LOCK ADC0_CLIP SPT0_LOCK GPIO6_IN RESERVED GPIO5_IN GPIO4_IN GPIO12_IN RESERVED ASRCO_ ASRCI_ LOCK LOCK GPIO3_IN GPIO2_IN GPIO11_IN GPIO10_IN Rev. A | Page 64 of 280 DAC1_CLIP AVDD_ UVW GPIO1_IN GPIO9_IN Data Sheet Reg (Hex) C0AE ADAU1787 Name DSP_ STATUS Bits [7:0] Bit 7 Bit 6 Bit 5 Bit 4 RESERVED C0AF IRQ1_ STATUS1 [7:0] IRQ1_ STATUS2 [7:0] IRQ1_ ADC1_ CLIP IRQ1_ ASRCI_ UNLOCKED C0B1 IRQ1_ STATUS3 IRQ2_ STATUS1 IRQ2_ STATUS2 [7:0] IRQ1_ ADC2_ CLIP IRQ1_ ASRCO_ LOCKED RESERVED IRQ1_ADC0_ CLIP C0B0 IRQ1_ ADC3_ CLIP IRQ1_ ASRCO_ UNLOCKED IRQ2_ ADC1_CLIP IRQ2_ ASRCI_ UNLOCKED C0B4 IRQ2_ STATUS3 [7:0] IRQ2_ ADC2_CLIP IRQ2_ ASRCO_ LOCKED RESERVED C0B5 SPT0_ CTRL1 SPT0_ CTRL2 SPT0_ ROUTE0 SPT0_ ROUTE1 SPT0_ ROUTE2 SPT0_ ROUTE3 SPT0_ ROUTE4 SPT0_ ROUTE5 SPT0_ ROUTE6 SPT0_ ROUTE7 SPT0_ ROUTE8 SPT0_ ROUTE9 SPT0_ ROUTE10 SPT0_ ROUTE11 SPT0_ ROUTE12 SPT0_ ROUTE13 SPT0_ ROUTE14 SPT0_ ROUTE15 SPT1_ CTRL1 SPT1_ CTRL2 [7:0] RESERVED [7:0] [7:0] SPT0_ LRCLK_POL RESERVED [7:0] RESERVED [7:0] C0B2 C0B3 C0B6 C0B7 C0B8 C0B9 C0BA C0BB C0BC C0BD C0BE C0BF C0C0 C0C1 C0C2 C0C3 C0C4 C0C5 C0C6 C0C7 C0C8 Bit 0 SDSP_ WDOG_ ERROR IRQ1_ DAC0_CLIP Reset 0x00 R/W R 0x00 R IRQ1_PLL_ LOCKED 0x00 R IRQ1_ SDSP1 IRQ2_ DAC1_CLIP IRQ2_PLL_ UNLOCKED IRQ1_ SDSP0 IRQ2_ DAC0_CLIP IRQ2_PLL_ LOCKED 0x00 R 0x00 R 0x00 R IRQ2_ SDSP1 IRQ2_ SDSP0 0x00 R SPT0_ SAI_MODE 0x00 R/W 0x00 R/W 0x10 R/W SPT0_OUT_ROUTE1 0x11 R/W RESERVED SPT0_OUT_ROUTE2 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE3 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE4 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE5 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE6 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE7 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE8 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE9 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE10 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE11 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE12 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE13 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE14 0x3F R/W [7:0] RESERVED SPT0_OUT_ROUTE15 0x3F R/W 0x00 R/W 0x00 R/W [7:0] [7:0] IRQ2_ ADC3_CLIP IRQ2_ ASRCO_ UNLOCKED [7:0] RESERVED [7:0] SPT1_ LRCLK_POL SPT0_ TRI_STATE SPT1_ TRI_STATE Bit 3 RESERVED IRQ1_ASRCI_ LOCKED IRQ1_ PRAMP IRQ1_POWER_ UP_COMPLETE IRQ2_ ADC0_CLIP IRQ2_ASRCI_ LOCKED IRQ1_ SDSP3 IRQ2_ POWER_UP_ COMPLETE SPT0_SLOT_WIDTH SPT0_LRCLK_SRC Bit 2 IRQ1_ AVDD_ UVW IRQ1_ SDSP2 RESERVED IRQ2_PRAMP IRQ2_SDSP3 IRQ1_ DAC1_ CLIP IRQ1_PLL_ UNLOCKED SPT0_DATA_FORMAT SPT0_ BCLK_POL SPT0_OUT_ROUTE0 SPT1_SLOT_WIDTH SPT1_LRCLK_SRC IRQ2_ AVDD_ UVW IRQ2_ SDSP2 Bit 1 SPT0_BCLK_SRC SPT1_DATA_FORMAT SPT1_ BCLK_POL Rev. A | Page 65 of 280 SPT1_BCLK_SRC SPT1_ SAI_MODE ADAU1787 Reg (Hex) C0C9 Data Sheet Bits [7:0] C0DC Name SPT1_ ROUTE0 SPT1_ ROUTE1 SPT1_ ROUTE2 SPT1_ ROUTE3 SPT1_ ROUTE4 SPT1_ ROUTE5 SPT1_ ROUTE6 SPT1_ ROUTE7 SPT1_ ROUTE8 SPT1_ ROUTE9 SPT1_ ROUTE10 SPT1_ ROUTE11 SPT1_ ROUTE12 SPT1_ ROUTE13 SPT1_ ROUTE14 SPT1_ ROUTE15 MP_ CTRL10 SELFBOOT_ CTRL SW_EN_ CTRL PDM_CTRL1 C0DD PDM_CTRL2 [7:0] C0DE C0DF C0E0 PDM_VOL0 PDM_VOL1 PDM_ ROUTE0 PDM_ ROUTE1 [7:0] [7:0] [7:0] [7:0] C0CA C0CB C0CC C0CD C0CE C0CF C0D0 C0D1 C0D2 C0D3 C0D4 C0D5 C0D6 C0D7 C0D8 C0D9 C0DA C0DB C0E1 Bit 7 Bit 6 RESERVED Bit 5 Bit 4 Bit 3 Bit 2 SPT1_OUT_ROUTE0 Bit 1 Bit 0 Reset 0x10 R/W R/W [7:0] RESERVED SPT1_OUT_ROUTE1 0x11 R/W [7:0] RESERVED SPT1_OUT_ROUTE2 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE3 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE4 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE5 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE6 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE7 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE8 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE9 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE10 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE11 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE12 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE13 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE14 0x3F R/W [7:0] RESERVED SPT1_OUT_ROUTE15 0x3F R/W 0x00 R/W [7:0] RESERVED [7:0] RESERVED [7:0] RESERVED [7:0] PDM_ MORE_FILT PDM1_MUTE MP12_MODE SELFBOOT_ SELFBOOT_ SLEW PULL_SEL SWEN_ SWEN_ SLEW PULL_SEL RESERVED SELFBOOT_ PULL_EN SWEN_ PULL_EN PDM_RATE RESERVED SELFBOOT_DRIVE 0x45 R/W RESERVED SWEN_DRIVE 0x45 R/W 0x02 R/W PDM0_ MUTE PDM0_ HPF_EN 0xC4 R/W RESERVED PDM0_VOL PDM1_VOL PDM0_ROUTE 0x40 0x40 0x00 R/W R/W R/W RESERVED PDM1_ROUTE 0x01 R/W PDM1_ HPF_EN PDM_FCOMP RESERVED Rev. A | Page 66 of 280 PDM_FS PDM_ VOL_ZC PDM_ HARD_VOL PDM_ VOL_LINK Data Sheet ADAU1787 REGISTER DETAILS ADI VENDOR ID REGISTER Address: 0xC000, Reset: 0x41, Name: VENDOR_ID 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 1 [ 7 : 0 ] V EN D O R ( R ) AD I Ve n d o r ID Table 40. Bit Descriptions for VENDOR_ID Bits [7:0] Bit Name VENDOR Settings Description ADI Vendor ID Reset 0x41 Access R DEVICE ID REGISTERS Address: 0xC001, Reset: 0x17, Name: DEVICE_ID1 7 6 5 4 3 2 1 0 0 0 0 1 0 1 1 1 [ 7 : 0 ] D EV I C E1 ( R ) D e v ic e ID 1 Table 41. Bit Descriptions for DEVICE_ID1 Bits [7:0] Bit Name DEVICE1 Settings Description Device ID 1 Reset 0x17 Access R Reset 0x87 Access R Reset 0x1 Access R Address: 0xC002, Reset: 0x87, Name: DEVICE_ID2 7 6 5 4 3 2 1 0 1 0 0 0 0 1 1 1 [ 7 : 0 ] D EV I C E2 ( R ) D e v ic e ID 2 Table 42. Bit Descriptions for DEVICE_ID2 Bits [7:0] Bit Name DEVICE2 Settings Description Device ID 2 REVISION CODE REGISTER Address: 0xC003, Reset: 0x01, Name: REVISION 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [ 7 : 0 ] R EV ( R ) Re v is io n ID Table 43. Bit Descriptions for REVISION Bits [7:0] Bit Name REV Settings Description Revision ID Rev. A | Page 67 of 280 ADAU1787 Data Sheet ADC, DAC, HEADPHONE POWER CONTROLS REGISTER Address: 0xC004, Reset: 0x00, Name: ADC_DAC_HP_PWR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5] PB1_EN (R/W) Playback Path (DAC/Headphone) Channel 1 Enable 0: DAC and Headphone/Line Output Channel 1 Powered Off. 1: DAC and Headphone/Line Output Channel 1 Powered On. [4] PB0_EN (R/W) Playback Path (DAC/Headphone) Channel 0 Enable 0: DAC and Headphone/Line Output Channel 0 Powered Off. 1: DAC and Headphone/Line Output Channel 0 Powered On. [0] ADC0_EN (R/W) ADC Channel 0 Enable 0: ADC Channel 0 Powered Off. 1: ADC Channel 0 Powered On. [1] ADC1_EN (R/W) ADC Channel 1 Enable 0: ADC Channel 1 Powered Off. 1: ADC Channel 1 Powered On. [2] ADC2_EN (R/W) ADC Channel 2 Enable 0: ADC Channel 2 Powered Off. 1: ADC Channel 2 Powered On. [3] ADC3_EN (R/W) ADC Channel 3 Enable 0: ADC Channel 3 Powered Off. 1: ADC Channel 3 Powered On. Table 44. Bit Descriptions for ADC_DAC_HP_PWR Bits [7:6] 5 Bit Name RESERVED PB1_EN Settings 0 1 4 PB0_EN 0 1 3 ADC3_EN 0 1 2 ADC2_EN 0 1 1 ADC1_EN 0 1 0 ADC0_EN 0 1 Description Reserved. Playback Path (DAC/Headphone) Channel 1 Enable. DAC and Headphone/Line Output Channel 1 Powered Off. DAC and Headphone/Line Output Channel 1 Powered On. Playback Path (DAC/Headphone) Channel 0 Enable. DAC and Headphone/Line Output Channel 0 Powered Off. DAC and Headphone/Line Output Channel 0 Powered On. ADC Channel 3 Enable. ADC Channel 3 Powered Off. ADC Channel 3 Powered On. ADC Channel 2 Enable. ADC Channel 2 Powered Off. ADC Channel 2 Powered On. ADC Channel 1 Enable. ADC Channel 1 Powered Off. ADC Channel 1 Powered On. ADC Channel 0 Enable. ADC Channel 0 Powered Off. ADC Channel 0 Powered On. Rev. A | Page 68 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet ADAU1787 PLL, MICROPHONE BIAS, AND PGA POWER CONTROLS REGISTER Address: 0xC005, Reset: 0x02, Name: PLL_MB_PGA_PWR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 [7] PGA3_EN (R/W) Select Line or Microphone Input 0: AIN3 used as a single-ended line input. PGA powered down. 1: AIN3 used as a single-ended m icrophone input. PGA powered up with slewing. [6] PGA2_EN (R/W) Select Line or Microphone Input 0: AIN2 used as a single-ended line input. PGA powered down. 1: AIN2 used as a single-ended m icrophone input. PGA powered up with slewing. [5] PGA1_EN (R/W) Select Line or Microphone Input 0: AIN1 used as a single-ended line input. PGA powered down. 1: AIN1 used as a single-ended m icrophone input. PGA powered up with slewing. [0] PLL_EN (R/W) PLL Enable 0: PLL Powered Off. 1: PLL Powered On. [1] XTAL_EN (R/W) Crystal Oscillator Enable 0: Crystal oscillator powered off. 1: Crystal oscillator powered on. [2] MBIAS0_EN (R/W) Microphone Bias 0 Enable 0: Microphone Bias 0 Powered Off. 1: Microphone Bias 0 Powered On. [3] MBIAS1_EN (R/W) Microphone Bias 1 Enable 0: Microphone Bias 1 Powered Off. 1: Microphone Bias 1 Powered On. [4] PGA0_EN (R/W) Select Line or Microphone Input 0: AIN0 used as a single-ended line input. PGA powered down. 1: AIN0 used as a single-ended m icrophone input. PGA powered up with slewing. Table 45. Bit Descriptions for PLL_MB_PGA_PWR Bits 7 Bit Name PGA3_EN Settings 0 1 6 PGA2_EN 0 1 5 PGA1_EN 0 1 4 PGA0_EN 0 1 3 MBIAS1_EN 0 1 2 MBIAS0_EN 0 1 1 XTAL_EN 0 1 0 PLL_EN 0 1 Description Select Line or Microphone Input. The PGA inverts the signal going through the bit. AIN3 used as a single-ended line input. PGA powered down. AIN3 used as a single-ended microphone input. PGA powered up with slewing. Select Line or Microphone Input. The PGA inverts the signal going through the bit. AIN2 used as a single-ended line input. PGA powered down. AIN2 used as a single-ended microphone input. PGA powered up with slewing. Select Line or Microphone Input. The PGA inverts the signal going through the bit. AIN1 used as a single-ended line input. PGA powered down. AIN1 used as a single-ended microphone input. PGA powered up with slewing. Select Line or Microphone Input. The PGA inverts the signal going through the bit. AIN0 used as a single-ended line input. PGA powered down. AIN0 used as a single-ended microphone input. PGA powered up with slewing. Microphone Bias 1 Enable. Microphone Bias 1 Powered Off. Microphone Bias 1 Powered On. Microphone Bias 0 Enable. Microphone Bias 0 Powered Off. Microphone Bias 0 Powered On. Crystal Oscillator Enable. Crystal oscillator powered off. Crystal oscillator powered on. PLL Enable. PLL Powered Off. PLL Powered On. Rev. A | Page 69 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x0 R/W ADAU1787 Data Sheet DIGITAL MICROPHONE POWER CONTROLS REGISTER Address: 0xC006, Reset: 0x00, Name: DMIC_PWR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] DMIC7_EN (R/W) Digital Microphone Channel 7 Enable 0: Digital Microphone Channel 7 Powered Off. 1: Digital Microphone Channel 7 Powered On. [0] DMIC0_EN (R/W) Digital Microphone Channel 0 Enable 0: Digital Microphone Channel 0 Powered Off. 1: Digital Microphone Channel 0 Powered On. [6] DMIC6_EN (R/W) Digital Microphone Channel 6 Enable 0: Digital Microphone Channel 6 Powered Off. 1: Digital Microphone Channel 6 Powered On. [1] DMIC1_EN (R/W) Digital Microphone Channel 1 Enable 0: Digital Microphone Channel 1 Powered Off. 1: Digital Microphone Channel 1 Powered On. [5] DMIC5_EN (R/W) Digital Microphone Channel 5 Enable 0: Digital Microphone Channel 5 Powered Off. 1: Digital Microphone Channel 5 Powered On. [2] DMIC2_EN (R/W) Digital Microphone Channel 2 Enable 0: Digital Microphone Channel 2 Powered Off. 1: Digital Microphone Channel 2 Powered On. [4] DMIC4_EN (R/W) Digital Microphone Channel 4 Enable 0: Digital Microphone Channel 4 Powered Off. 1: Digital Microphone Channel 4 Powered On. [3] DMIC3_EN (R/W) Digital Microphone Channel 3 Enable 0: Digital Microphone Channel 3 Powered Off. 1: Digital Microphone Channel 3 Powered On. Table 46. Bit Descriptions for DMIC_PWR Bits 7 Bit Name DMIC7_EN Settings 0 1 6 DMIC6_EN 0 1 5 DMIC5_EN 0 1 4 DMIC4_EN 0 1 3 DMIC3_EN 0 1 2 DMIC2_EN 0 1 1 DMIC1_EN 0 1 0 DMIC0_EN 0 1 Description Digital Microphone Channel 7 Enable. Digital Microphone Channel 7 Powered Off. Digital Microphone Channel 7 Powered On. Digital Microphone Channel 6 Enable. Digital Microphone Channel 6 Powered Off. Digital Microphone Channel 6 Powered On. Digital Microphone Channel 5 Enable. Digital Microphone Channel 5 Powered Off. Digital Microphone Channel 5 Powered On. Digital Microphone Channel 4 Enable. Digital Microphone Channel 4 Powered Off. Digital Microphone Channel 4 Powered On. Digital Microphone Channel 3 Enable. Digital Microphone Channel 3 Powered Off. Digital Microphone Channel 3 Powered On. Digital Microphone Channel 2 Enable. Digital Microphone Channel 2 Powered Off. Digital Microphone Channel 2 Powered On. Digital Microphone Channel 1 Enable. Digital Microphone Channel 1 Powered Off. Digital Microphone Channel 1 Powered On. Digital Microphone Channel 0 Enable. Digital Microphone Channel 0 Powered Off. Digital Microphone Channel 0 Powered On. Rev. A | Page 70 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet ADAU1787 SERIAL PORT, PDM OUTPUT, AND DIGITAL MICROPHONE CLK POWER CONTROLS REGISTER Address: 0xC007, Reset: 0x00, Name: SAI_CLK_PWR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] PDM1_EN (R/W) PDM Output Channel 1 Enable 0: PDM Output Channel 1 Powered Off. 1: PDM Output Channel 1 Powered On. [0] SPT0_IN_EN (R/W) Serial Audio Port 0 Input Side Enable 0: Serial Audio Port 0 Input Side Powered Off. 1: Serial Audio Port 0 Input Side Powered On. [6] PDM0_EN (R/W) PDM Output Channel 0 Enable 0: PDM Output Channel 0 Powered Off. 1: PDM Output Channel 0 Powered On. [1] SPT0_OUT_EN (R/W) Serial Audio Port 0 Output Side Enable 0: Serial Audio Port 0 Output Side Powered Off. 1: Serial Audio Port 0 Output Side Powered On. [5] DMIC_CLK1_EN (R/W) Digital Microphone Clock 1 Enable 0: Digital Microphone Clock 1 Powered Off. 1: Digital Microphone Clock 1 Powered On. [2] SPT1_IN_EN (R/W) Serial Audio Port 1 Input Side Enable 0: Serial Audio Port 1 Input Side Powered Off. 1: Serial Audio Port 1 Input Side Powered On. [4] DMIC_CLK0_EN (R/W) Digital Microphone Clock 0 Enable 0: Digital Microphone Clock 0 Powered Off. 1: Digital Microphone Clock 0 Powered On. [3] SPT1_OUT_EN (R/W) Serial Audio Port 1 Output Side Enable 0: Serial Audio Port 1 Output Side Powered Off. 1: Serial Audio Port 1 Output Side Powered On. Table 47. Bit Descriptions for SAI_CLK_PWR Bits 7 Bit Name PDM1_EN Settings 0 1 6 PDM0_EN 0 1 5 DMIC_CLK1_EN 0 1 4 DMIC_CLK0_EN 0 1 3 SPT1_OUT_EN 0 1 2 SPT1_IN_EN 0 1 1 SPT0_OUT_EN 0 1 0 SPT0_IN_EN 0 1 Description PDM Output Channel 1 Enable. PDM Output Channel 1 Powered Off. PDM Output Channel 1 Powered On. PDM Output Channel 0 Enable. PDM Output Channel 0 Powered Off. PDM Output Channel 0 Powered On. Digital Microphone Clock 1 Enable. Digital Microphone Clock 1 Powered Off. Digital Microphone Clock 1 Powered On. Digital Microphone Clock 0 Enable. Digital Microphone Clock 0 Powered Off. Digital Microphone Clock 0 Powered On. Serial Audio Port 1 Output Side Enable. Serial Audio Port 1 Output Side Powered Off. Serial Audio Port 1 Output Side Powered On. Serial Audio Port 1 Input Side Enable. Serial Audio Port 1 Input Side Powered Off. Serial Audio Port 1 Input Side Powered On. Serial Audio Port 0 Output Side Enable. Serial Audio Port 0 Output Side Powered Off. Serial Audio Port 0 Output Side Powered On. Serial Audio Port 0 Input Side Enable. Serial Audio Port 0 Input Side Powered Off. Serial Audio Port 0 Input Side Powered On. Rev. A | Page 71 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W ADAU1787 Data Sheet DSP POWER CONTROLS REGISTER Address: 0xC008, Reset: 0x00, Name: DSP_PWR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 : 5 ] R ES ER V ED [ 0 ] F D S P _EN ( R / W ) Fa s tD SP En a b le 0 : Fa s tD SP Po w e r e d O ff. 1 : Fa s tD SP Po w e r e d O n . [ 4 ] S D S P _EN ( R /W ) Sig m a D SP En a b le 0 : Sig m a D SP Po w e r e d O ff. 1 : Sig m a D SP Po w e r e d O n . [ 3 : 1 ] R ES ER V ED Table 48. Bit Descriptions for DSP_PWR Bits [7:5] 4 Bit Name RESERVED SDSP_EN Settings 0 1 [3:1] 0 RESERVED FDSP_EN 0 1 Description Reserved. SigmaDSP Enable. SigmaDSP Powered Off. SigmaDSP Powered On. Reserved. FastDSP Enable. FastDSP Powered Off. FastDSP Powered On. Reset 0x0 0x0 Access R R/W 0x0 0x0 R R/W ASRC POWER CONTROLS REGISTER Address: 0xC009, Reset: 0x00, Name: ASRC_PWR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] A S R C O 3 _EN ( R /W ) O u tp u t As y n c h r o n o u s Sa m p le Ra t e Co n v e r te r Ch a n n e l 3 En a b le 0 : O u tp u t As y n c h r o n o u s Sa m p le Ra te Co n v e r te r Ch a n n e l 3 Po w e r e d O ff. 1 : O u tp u t As y n c h r o n o u s Sa m p le Ra te Co n v e r te r Ch a n n e l 3 Po w e r e d O n . [ 0 ] A S R C I0 _EN ( R / W ) In p u t As y n c h r o n o u s Sa m p le Ra te Co n v e r t e r Ch a n n e l 0 En a b le 0 : In p u t As y n c h r o n o u s Sa m p le Ra te Co n v e r t e r Ch a n n e l 0 Po w e r e d O ff . 1 : In p u t As y n c h r o n o u s Sa m p le Ra te Co n v e r t e r Ch a n n e l 0 Po w e r e d O n . [ 6 ] A S R C O 2 _EN ( R /W ) O u tp u t As y n c h r o n o u s Sa m p le Ra t e Co n v e r te r Ch a n n e l 2 En a b le 0 : O u tp u t As y n c h r o n o u s Sa m p le Ra te Co n v e r te r Ch a n n e l 2 Po w e r e d O ff. 1 : O u tp u t As y n c h r o n o u s Sa m p le Ra te Co n v e r te r Ch a n n e l 2 Po w e r e d O n . [ 1 ] A S R C I1 _EN ( R /W ) In p u t As y n c h r o n o u s Sa m p le Ra te Co n v e r t e r Ch a n n e l 1 En a b le 0 : In p u t As y n c h r o n o u s Sa m p le Ra te Co n v e r t e r Ch a n n e l 1 Po w e r e d O ff. 1 : In p u t As y n c h r o n o u s Sa m p le Ra te Co n v e r t e r Ch a n n e l 1 Po w e r e d O n . [ 5 ] A S R C O 1 _EN ( R /W ) O u tp u t As y n c h r o n o u s Sa m p le Ra t e Co n v e r te r Ch a n n e l 1 En a b le 0 : O u tp u t As y n c h r o n o u s Sa m p le Ra te Co n v e r te r Ch a n n e l 1 Po w e r e d O ff. 1 : O u tp u t As y n c h r o n o u s Sa m p le Ra te Co n v e r te r Ch a n n e l 1 Po w e r e d O n . [ 2 ] A S R C I2 _EN ( R /W ) In p u t As y n c h r o n o u s Sa m p le Ra te Co n v e r t e r Ch a n n e l 2 En a b le 0 : In p u t As y n c h r o n o u s Sa m p le Ra te Co n v e r t e r Ch a n n e l 2 Po w e r e d O ff . 1 : In p u t As y n c h r o n o u s Sa m p le Ra te Co n v e r t e r Ch a n n e l 2 Po w e r e d O n . [ 4 ] A S R C O 0 _EN ( R / W ) O u tp u t As y n c h r o n o u s Sa m p le Ra t e Co n v e r te r Ch a n n e l 0 En a b le 0 : O u tp u t As y n c h r o n o u s Sa m p le Ra te Co n v e r te r Ch a n n e l 0 Po w e r e d O ff. 1 : O u tp u t As y n c h r o n o u s Sa m p le Ra te Co n v e r te r Ch a n n e l 0 Po w e r e d O n . [ 3 ] A S R C I3 _EN ( R /W ) In p u t As y n c h r o n o u s Sa m p le Ra te Co n v e r t e r Ch a n n e l 3 En a b le 0 : In p u t As y n c h r o n o u s Sa m p le Ra te Co n v e r t e r Ch a n n e l 3 Po w e r e d O ff . 1 : In p u t As y n c h r o n o u s Sa m p le Ra te Co n v e r t e r Ch a n n e l 3 Po w e r e d O n . Table 49. Bit Descriptions for ASRC_PWR Bits 7 Bit Name ASRCO3_EN Settings 0 1 6 ASRCO2_EN 0 1 Description Output Asynchronous Sample Rate Converter Channel 3 Enable. Output Asynchronous Sample Rate Converter Channel 3 Powered Off. Output Asynchronous Sample Rate Converter Channel 3 Powered On. Output Asynchronous Sample Rate Converter Channel 2 Enable. Output Asynchronous Sample Rate Converter Channel 2 Powered Off. Output Asynchronous Sample Rate Converter Channel 2 Powered On. Rev. A | Page 72 of 280 Reset 0x0 Access R/W 0x0 R/W Data Sheet Bits 5 Bit Name ASRCO1_EN ADAU1787 Settings 0 1 4 ASRCO0_EN 0 1 3 ASRCI3_EN 0 1 2 ASRCI2_EN 0 1 1 ASRCI1_EN 0 1 0 ASRCI0_EN 0 1 Description Output Asynchronous Sample Rate Converter Channel 1 Enable. Output Asynchronous Sample Rate Converter Channel 1 Powered Off. Output Asynchronous Sample Rate Converter Channel 1 Powered On. Output Asynchronous Sample Rate Converter Channel 0 Enable. Output Asynchronous Sample Rate Converter Channel 0 Powered Off. Output Asynchronous Sample Rate Converter Channel 0 Powered On. Input Asynchronous Sample Rate Converter Channel 3 Enable. Input Asynchronous Sample Rate Converter Channel 3 Powered Off. Input Asynchronous Sample Rate Converter Channel 3 Powered On. Input Asynchronous Sample Rate Converter Channel 2 Enable. Input Asynchronous Sample Rate Converter Channel 2 Powered Off. Input Asynchronous Sample Rate Converter Channel 2 Powered On. Input Asynchronous Sample Rate Converter Channel 1 Enable. Input Asynchronous Sample Rate Converter Channel 1 Powered Off. Input Asynchronous Sample Rate Converter Channel 1 Powered On. Input Asynchronous Sample Rate Converter Channel 0 Enable. Input Asynchronous Sample Rate Converter Channel 0 Powered Off. Input Asynchronous Sample Rate Converter Channel 0 Powered On. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W INTERPOLATOR POWER CONTROLS REGISTER Address: 0xC00A, Reset: 0x00, Name: FINT_PWR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] F IN T 7 _EN ( R /W ) In t e r p o la t io n Ch a n n e l 7 En a b le 0 : In te r p o la tio n Ch a n n e l 7 Po w e r e d O ff . 1 : In te r p o la tio n Ch a n n e l 7 Po w e r e d O n . [ 0 ] F IN T 0 _EN ( R /W ) In te r p o la tio n Ch a n n e l 0 En a b le 0 : In te r p o la tio n Ch a n n e l 0 Po w e r e d O f f. 1 : In te r p o la tio n Ch a n n e l 0 Po w e r e d O n . [ 6 ] F IN T 6 _EN ( R /W ) In t e r p o la t io n Ch a n n e l 6 En a b le 0 : In te r p o la tio n Ch a n n e l 6 Po w e r e d O ff . 1 : In te r p o la tio n Ch a n n e l 6 Po w e r e d O n . [ 1 ] F IN T 1 _EN ( R / W ) In te r p o la tio n Ch a n n e l 1 En a b le 0 : In te r p o la tio n Ch a n n e l 1 Po w e r e d O ff . 1 : In te r p o la tio n Ch a n n e l 1 Po w e r e d O n . [ 5 ] F I N T 5 _EN ( R /W ) In t e r p o la t io n Ch a n n e l 5 En a b le 0 : In te r p o la tio n Ch a n n e l 5 Po w e r e d O ff . 1 : In te r p o la tio n Ch a n n e l 5 Po w e r e d O n . [ 2 ] F IN T 2 _EN ( R / W ) In te r p o la tio n Ch a n n e l 2 En a b le 0 : In te r p o la tio n Ch a n n e l 2 Po w e r e d O f f. 1 : In te r p o la tio n Ch a n n e l 2 Po w e r e d O n . [ 4 ] F IN T 4 _EN ( R /W ) In t e r p o la t io n Ch a n n e l 4 En a b le 0 : In te r p o la tio n Ch a n n e l 4 Po w e r e d O ff . 1 : In te r p o la tio n Ch a n n e l 4 Po w e r e d O n . [ 3 ] F IN T 3 _EN ( R / W ) In te r p o la tio n Ch a n n e l 3 En a b le 1 : In te r p o la tio n Ch a n n e l 3 Po w e r e d O n . 0 : In te r p o la tio n Ch a n n e l 3 Po w e r e d O f f. Table 50. Bit Descriptions for FINT_PWR Bits 7 Bit Name FINT7_EN Settings 0 1 6 FINT6_EN 0 1 5 FINT5_EN 0 1 4 FINT4_EN 0 1 Description Interpolation Channel 7 Enable. Interpolation Channel 7 Powered Off. Interpolation Channel 7 Powered On. Interpolation Channel 6 Enable. Interpolation Channel 6 Powered Off. Interpolation Channel 6 Powered On. Interpolation Channel 5 Enable. Interpolation Channel 5 Powered Off. Interpolation Channel 5 Powered On. Interpolation Channel 4 Enable. Interpolation Channel 4 Powered Off. Interpolation Channel 4 Powered On. Rev. A | Page 73 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W ADAU1787 Bits 3 Bit Name FINT3_EN Data Sheet Settings Description Interpolation Channel 3 Enable. Interpolation Channel 3 Powered On. Interpolation Channel 3 Powered Off. Interpolation Channel 2 Enable. Interpolation Channel 2 Powered Off. Interpolation Channel 2 Powered On. Interpolation Channel 1 Enable. Interpolation Channel 1 Powered Off. Interpolation Channel 1 Powered On. Interpolation Channel 0 Enable. Interpolation Channel 0 Powered Off. Interpolation Channel 0 Powered On. 1 0 2 FINT2_EN 0 1 1 FINT1_EN 0 1 0 FINT0_EN 0 1 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W DECIMATOR POWER CONTROLS REGISTER Address: 0xC00B, Reset: 0x00, Name: FDEC_PWR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] F D EC 7 _EN ( R / W ) D e c im a tio n Ch a n n e l 7 En a b le 0 : D e c im a to r Ch a n n e l 7 Po w e r e d O ff. 1 : D e c im a to r Ch a n n e l 7 Po w e r e d O n . [ 0 ] F D EC 0 _EN ( R / W ) D e c im a tio n Ch a n n e l 0 En a b le 0 : D e c im a to r Ch a n n e l 0 Po w e r e d O f f. 1 : D e c im a to r Ch a n n e l 0 Po w e r e d O n . [ 6 ] F D EC 6 _EN ( R / W ) D e c im a tio n Ch a n n e l 6 En a b le 0 : D e c im a to r Ch a n n e l 6 Po w e r e d O ff. 1 : D e c im a to r Ch a n n e l 6 Po w e r e d O n . [ 1 ] F D EC 1 _EN ( R /W ) D e c im a tio n Ch a n n e l 1 En a b le 0 : D e c im a to r Ch a n n e l 1 Po w e r e d O ff . 1 : D e c im a to r Ch a n n e l 1 Po w e r e d O n . [ 5 ] F D EC 5 _EN ( R /W ) D e c im a tio n Ch a n n e l 5 En a b le 0 : D e c im a to r Ch a n n e l 5 Po w e r e d O ff. 1 : D e c im a to r Ch a n n e l 5 Po w e r e d O n . [ 2 ] F D EC 2 _EN ( R /W ) D e c im a tio n Ch a n n e l 2 En a b le 0 : D e c im a to r Ch a n n e l 2 Po w e r e d O f f. 1 : D e c im a to r Ch a n n e l 2 Po w e r e d O n . [ 4 ] F D EC 4 _EN ( R / W ) D e c im a tio n Ch a n n e l 4 En a b le 0 : D e c im a to r Ch a n n e l 4 Po w e r e d O ff. 1 : D e c im a to r Ch a n n e l 4 Po w e r e d O n . [ 3 ] F D EC 3 _EN ( R /W ) D e c im a tio n Ch a n n e l 3 En a b le 0 : D e c im a to r Ch a n n e l 3 Po w e r e d O f f. 1 : D e c im a to r Ch a n n e l 3 Po w e r e d O n . Table 51. Bit Descriptions for FDEC_PWR Bits 7 Bit Name FDEC7_EN Settings 0 1 6 FDEC6_EN 0 1 5 FDEC5_EN 0 1 4 FDEC4_EN 0 1 3 FDEC3_EN 0 1 Description Decimation Channel 7 Enable. Decimator Channel 7 Powered Off. Decimator Channel 7 Powered On. Decimation Channel 6 Enable. Decimator Channel 6 Powered Off. Decimator Channel 6 Powered On. Decimation Channel 5 Enable. Decimator Channel 5 Powered Off. Decimator Channel 5 Powered On. Decimation Channel 4 Enable. Decimator Channel 4 Powered Off. Decimator Channel 4 Powered On. Decimation Channel 3 Enable. Decimator Channel 3 Powered Off. Decimator Channel 3 Powered On. Rev. A | Page 74 of 280 Data Sheet Bits 2 Bit Name FDEC2_EN ADAU1787 Settings 0 1 1 FDEC1_EN 0 1 0 FDEC0_EN 0 1 Description Decimation Channel 2 Enable. Decimator Channel 2 Powered Off. Decimator Channel 2 Powered On. Decimation Channel 1 Enable. Decimator Channel 1 Powered Off. Decimator Channel 1 Powered On. Decimation Channel 0 Enable. Decimator Channel 0 Powered Off. Decimator Channel 0 Powered On. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W STATE RETENTION CONTROLS REGISTER Address: 0xC00C, Reset: 0x10, Name: KEEPS 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 [7:5] RESERVED [4] CM_KEEP_ALIVE (R/W) Com mon-Mode (CM) Output Keep Alive During Power-Down 0: CM output turns off when POWER_EN = 0, which allows lower shutdown power but longer start-up tim ing. 1: CM output stays on when POWER_EN = 0, which allows faster start-up timing but greater shutdown power. [3:2] RESERVED [0] KEEP_FDSP (R/W) State Retention Control for FastDSP Memories 1: During software full chip power-down, the state of FastDSP m em ories are maintained. 0: During software full chip power-down, the state of FastDSP m em ories are not m aintained. [1] KEEP_SDSP (R/W) State Retention Control for Sigm aDSP Memories 0: During software full chip power-down, the state of Sigm aDSP m em ories are not m aintained. 1: During software full chip power-down, the state of Sigm aDSP m em ories are m aintained. Table 52. Bit Descriptions for KEEPS Bits [7:5] 4 Bit Name RESERVED CM_KEEP_ALIVE Settings 0 1 [3:2] 1 RESERVED KEEP_SDSP 0 1 0 KEEP_FDSP 1 0 Description Reserved. Common-Mode (CM) Output Keep Alive During Power-Down. CM output turns off when POWER_EN = 0, which allows lower shutdown power but longer start-up timing. CM output stays on when POWER_EN = 0, which allows faster start-up timing but greater shutdown power. Reserved. State Retention Control for SigmaDSP Memories. During software full chip power-down, the state of SigmaDSP memories are not maintained. During software full chip power-down, the state of SigmaDSP memories are maintained. State Retention Control for FastDSP Memories. During software full chip power-down, the state of FastDSP memories are maintained. During software full chip power-down, the state of FastDSP memories are not maintained. Rev. A | Page 75 of 280 Reset 0x0 0x1 Access R R/W 0x0 0x0 R R/W 0x0 R/W ADAU1787 Data Sheet CHIP POWER CONTROL REGISTER Address: 0xC00D, Reset: 0x10, Name: CHIP_PWR 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 [7:6] RESERVED [5:4] DLDO_CTRL (R/W) DVDD LDO Regulator Output Voltage 00: Reserved. 01: DVDD regulator is set to 0.9 V. 10: Reserved. 11: Reserved. [3] RESERVED [0] POWER_EN (R/W) Controls Internal DVDD Power Gating 0: Disables internal DVDD supply. 1: Enables internal DVDD supply. Allows block enabling of PLL, FDSP, and SDSP. [1] MASTER_BLOCK_EN (R/W) Master Block Level Enable. Gates block level enabling of all blocks except PLL, crystal, FDSP, and SDSP. 0: All blocks are disabled. 1: All blocks that have their respective block enable set are enabled. [2] CM_STARTUP_OVER (R/W) Disables High Power CM Start-Up Boost Mode 0: CM pin fast charge is enabled. 1: CM pin fast charge is disabled. Table 53. Bit Descriptions for CHIP_PWR Bits [7:6] [5:4] Bit Name RESERVED DLDO_CTRL Settings 00 01 10 11 3 2 RESERVED CM_STARTUP_OVER 0 1 1 MASTER_BLOCK_EN 0 1 0 POWER_EN 0 1 Description Reserved. DVDD LDO Regulator Output Voltage. Reserved. DVDD regulator is set to 0.9 V. Reserved. Reserved. Reserved. Disables High Power CM Start-Up Boost Mode. CM pin fast charge is enabled. CM pin fast charge is disabled. Master Block Level Enable. Gates block level enabling of all blocks except PLL, crystal, FDSP, and SDSP. All blocks are disabled. All blocks that have their respective block enable set are enabled. Controls Internal DVDD Power Gating. Disables internal DVDD supply. Enables internal DVDD supply. Allows block enabling of PLL, FDSP, and SDSP. Rev. A | Page 76 of 280 Reset 0x0 0x1 Access R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W Data Sheet ADAU1787 CLOCK CONTROL REGISTER Address: 0xC00E, Reset: 0xC8, Name: CLK_CTRL1 7 6 5 4 3 2 1 0 1 1 0 0 1 0 0 0 [7:6] SYNC_SOURCE (R/W) Source for Phase Synchronization Signal to Phase Align Multiple Chips. 0: FSYNC_0 signal used for phase synchronization. 1: FSYNC_1 signal used for phase synchronization. 10: Input ASRC used for phase synchronization signal. Used when fram e clock signal is asynchronous to core clock. 11: Phase synchronization signal internally generated. [2:0] PLL_SOURCE (R/W) PLL Source Clock Selection 0: MCLKIN pin or crystal is PLL source. 1: FSYNC_0 pin is PLL source. 10: BCLK_0 pin is PLL source. 11: FSYNC_1 pin is PLL source. 100: BCLK_1 pin is PLL source. [3] XTAL_MODE (R/W) Master Clock/Crystal Oscillator Mode 0: Logic level m aster clock input used. 1: Crystal oscillator used. [5] PLL_BYPASS (R/W) PLL Bypass Control 0: PLL output is source of main chip clock. 1: PLL is bypassed. Main chip clock sourced directly from PLL_SOURCE setting and m ust be 24.576 MHz. [4] PLL_TYPE (R/W) Type of PLL (Integer/Fractional). 0: Integer PLL. 1: Fractional PLL. Table 54. Bit Descriptions for CLK_CTRL1 Bits [7:6] Bit Name SYNC_SOURCE Settings 0 1 10 11 5 PLL_BYPASS 0 1 4 PLL_TYPE 0 1 3 XTAL_MODE 0 1 [2:0] PLL_SOURCE 0 1 10 11 100 Description Source for Phase Synchronization Signal to Phase Align Multiple Chips. FSYNC_0 signal used for phase synchronization. FSYNC_1 signal used for phase synchronization. Input ASRC used for phase synchronization signal. Used when LRCLK signal is async to core clock. Phase synchronization signal internally generated. PLL Bypass Control. PLL output is source of main chip clock. PLL is bypassed. Main chip clock sourced directly from PLL_SOURCE setting and must be 24.576 MHz. Type of PLL (Integer/Fractional). Integer PLL. Fractional PLL. Master Clock/Crystal Oscillator Mode. Logic level master clock input used. Crystal oscillator used. PLL Source Clock Selection. MCLKIN pin or crystal is PLL source. FSYNC_0 pin is PLL source. BCLK_0/SW_CLK pin is PLL source. FSYNC_1 pin is PLL source. BCLK_1 pin is PLL source. Rev. A | Page 77 of 280 Reset 0x3 Access R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x0 R/W ADAU1787 Data Sheet PLL INPUT DIVIDER REGISTER Address: 0xC00F, Reset: 0x00, Name: CLK_CTRL2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:3] RESERVED [2:0] PLL_INPUT_PRESCALER (R/W) PLL_INPUT_PRESCALER is the input divider rate Table 55. Bit Descriptions for CLK_CTRL2 Bits [7:3] [2:0] Bit Name RESERVED PLL_INPUT_PRESCALER Settings Description Reserved. PLL_INPUT_PRESCALER is the input divider rate. Reset 0x0 0x0 Access R R/W PLL FEEDBACK INTEGER DIVIDER (LSBs REGISTER) Address: 0xC010, Reset: 0x00, Name: CLK_CTRL3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4:0] PLL_INTEGER_DIVIDER[12:8] (R/W) Feedback Divider Rate (Integer Mode). Table 56. Bit Descriptions for CLK_CTRL3 Bits [7:5] [4:0] Bit Name RESERVED PLL_INTEGER_DIVIDER[12:8] Settings Description Reserved Feedback Divider Rate (Integer Mode) Reset 0x0 0x0 Access R R/W Reset 0x2 Access R/W PLL FEEDBACK INTEGER DIVIDER (MSBs REGISTER) Address: 0xC011, Reset: 0x02, Name: CLK_CTRL4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 [7:0] PLL_INTEGER_DIVIDER[7:0] (R/W) Feedback Divider Rate (Integer Mode). Table 57. Bit Descriptions for CLK_CTRL4 Bits [7:0] Bit Name PLL_INTEGER_DIVIDER[7:0] Settings Description Feedback Divider Rate (Integer Mode) PLL FRACTIONAL NUMERATOR VALUE (LSBs REGISTER) Address: 0xC012, Reset: 0x00, Name: CLK_CTRL5 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] PLL_NUMERATOR[15:8] (R/W) PLL Numerator Table 58. Bit Descriptions for CLK_CTRL5 Bits [7:0] Bit Name PLL_NUMERATOR[15:8] Settings Description PLL Numerator Rev. A | Page 78 of 280 Reset 0x0 Access R/W Data Sheet ADAU1787 PLL FRACTIONAL NUMERATOR VALUE (MSBs REGISTER) Address: 0xC013, Reset: 0x00, Name: CLK_CTRL6 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] PLL_NUMERATOR[7:0] (R/W) PLL Numerator Table 59. Bit Descriptions for CLK_CTRL6 Bits [7:0] Bit Name PLL_NUMERATOR[7:0] Settings Description PLL Numerator Reset 0x0 Access R/W PLL FRACTIONAL DENOMINATOR (LSBs REGISTER) Address: 0xC014, Reset: 0x00, Name: CLK_CTRL7 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] PLL_DENOMINATOR[15:8] (R/W) PLL Denom inator Table 60. Bit Descriptions for CLK_CTRL7 Bits [7:0] Bit Name PLL_DENOMINATOR[15:8] Settings Description PLL Denominator Reset 0x0 Access R/W Reset 0x0 Access R/W PLL FRACTIONAL DENOMINATOR (MSBs REGISTER) Address: 0xC015, Reset: 0x00, Name: CLK_CTRL8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] PLL_DENOMINATOR[7:0] (R/W) PLL Denom inator Table 61. Bit Descriptions for CLK_CTRL8 Bits [7:0] Bit Name PLL_DENOMINATOR[7:0] Settings Description PLL Denominator PLL UPDATE REGISTER Address: 0xC016, Reset: 0x00, Name: CLK_CTRL9 [7:1] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [0] PLL_UPDATE (R/W1T) Update PLL Configuration 0: Write of 0 does nothing. 1: Write of 1 updates all PLL configuration settings. Table 62. Bit Descriptions for CLK_CTRL9 Bits [7:1] 0 Bit Name RESERVED PLL_UPDATE Settings 0 1 Description Reserved. Update PLL Configuration. Write of 0 does nothing. Write of 1 updates all PLL configuration settings. Rev. A | Page 79 of 280 Reset 0x0 0x0 Access R R/W1T ADAU1787 Data Sheet ADC SAMPLE RATE CONTROL REGISTER Address: 0xC017, Reset: 0x22, Name: ADC_CTRL1 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 0 [7] ADC23_DEC_ORDER (R/W) ADC Channel 2 and Channel 3 Decimation Filter Order 0: Lower Order Decimation Filter: Lower Delay. 1: Higher Order Decimation Filter: Higher Delay. [6:4] ADC23_FS (R/W) ADC Channel 2 and Channel 3 Sam ple Rate Selection 000: 12 kHz Sample Rate. 001: 24 kHz Sample Rate. 010: 48 kHz Sample Rate. 011: 96 kHz Sample Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. 110: 768 kHz Sam ple Rate. [2:0] ADC01_FS (R/W) ADC Channel 0 and Channel 1 Sam ple Rate Selection 000: 12 kHz Sample Rate. 001: 24 kHz Sample Rate. 010: 48 kHz Sample Rate. 011: 96 kHz Sample Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. 110: 768 kHz Sam ple Rate. [3] ADC01_DEC_ORDER (R/W) ADC Channel 0 and Channel 1 Decimation Filter Order 0: Lower Order Decimation Filter: Lower Delay. 1: Higher Order Decimation Filter: Higher Delay. Table 63. Bit Descriptions for ADC_CTRL1 Bits 7 Bit Name ADC23_DEC_ORDER Settings 0 1 [6:4] ADC23_FS 000 001 010 011 100 101 110 3 ADC01_DEC_ORDER 0 1 [2:0] ADC01_FS 000 001 010 011 100 101 110 Description ADC Channel 2 and Channel 3 Decimation Filter Order. Lower Order Decimation Filter: Lower Delay. Higher Order Decimation Filter: Higher Delay. ADC Channel 2 and Channel 3 Sample Rate Selection. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. ADC Channel 0 and Channel 1 Decimation Filter Order. Lower Order Decimation Filter: Lower Delay. Higher Order Decimation Filter: Higher Delay. ADC Channel 0 and Channel 1 Sample Rate Selection. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Rev. A | Page 80 of 280 Reset 0x0 Access R/W 0x2 R/W 0x0 R/W 0x2 R/W Data Sheet ADAU1787 ADC IBIAS CONTROLS REGISTER Address: 0xC018, Reset: 0x00, Name: ADC_CTRL2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [2:0] ADC01_IBIAS (R/W) ADC Channel 0 and Channel 1 Bias Current Setting 000: Normal Operation (Default). 001: Extrem e Power Saving. 010: Enhanced Perform ance. 011: Power Saving. [6:4] ADC23_IBIAS (R/W) ADC Channel 2 and Channel 3 Bias Current Setting 000: Norm al Operation (Default). 001: Extreme Power Saving. 010: Enhanced Performance. 011: Power Saving. [3] RESERVED Table 64. Bit Descriptions for ADC_CTRL2 Bits 7 [6:4] Bit Name RESERVED ADC23_IBIAS Settings 000 001 010 011 3 [2:0] RESERVED ADC01_IBIAS 000 001 010 011 Description Reserved. ADC Channel 2 and Channel 3 Bias Current Setting. Higher bias currents result in higher performance. Normal Operation (Default). Extreme Power Saving. Enhanced Performance. Power Saving. Reserved. ADC Channel 0 and Channel 1 Bias Current Setting. Higher bias currents result in higher performance. Normal Operation (Default). Extreme Power Saving. Enhanced Performance. Power Saving. Reset 0x0 0x0 Access R R/W 0x0 0x0 R R/W ADC HPF CONTROL REGISTER Address: 0xC019, Reset: 0x00, Name: ADC_CTRL3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] RESERVED [3] ADC3_HPF_EN (R/W) ADC Channel 3 Enable High-Pass Filter 0: ADC High-Pass Filter Off. 1: ADC High-Pass Filter On. [2] ADC2_HPF_EN (R/W) ADC Channel 2 Enable High-Pass Filter 0: ADC High-Pass Filter Off. 1: ADC High-Pass Filter On. [0] ADC0_HPF_EN (R/W) ADC Channel 0 Enable High-Pass Filter 0: ADC High-Pass Filter Off. 1: ADC High-Pass Filter On. [1] ADC1_HPF_EN (R/W) ADC Channel 1 Enable High-Pass Filter 0: ADC High-Pass Filter Off. 1: ADC High-Pass Filter On. Table 65. Bit Descriptions for ADC_CTRL3 Bits [7:4] 3 Bit Name RESERVED ADC3_HPF_EN Settings 0 1 2 ADC2_HPF_EN 0 1 Description Reserved. ADC Channel 3 Enable High-Pass Filter. ADC High-Pass Filter Off. ADC High-Pass Filter On. ADC Channel 2 Enable High-Pass Filter. ADC High-Pass Filter Off. ADC High-Pass Filter On. Rev. A | Page 81 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W ADAU1787 Bits 1 Bit Name ADC1_HPF_EN Data Sheet Settings 0 1 0 ADC0_HPF_EN 0 1 Description ADC Channel 1 Enable High-Pass Filter. ADC High-Pass Filter Off. ADC High-Pass Filter On. ADC Channel 0 Enable High-Pass Filter. ADC High-Pass Filter Off. ADC High-Pass Filter On. Reset 0x0 Access R/W 0x0 R/W ADC MUTE AND COMPENSATION CONTROL REGISTER Address: 0xC01A, Reset: 0x40, Name: ADC_CTRL4 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7] RESERVED [6] ADC_VOL_ZC (R/W) ADC Volum e Zero Cross Control 0: Volum e change occurs at any tim e. 1: Volum e change only occurs at zero crossing. [5] ADC_VOL_LINK (R/W) ADC Volum e Link 0: Each ADC channel uses its respective volume value. 1: All ADC channels use Channel 0 volume value. [4] ADC_HARD_VOL (R/W) ADC Hard Volum e 0: Soft Volum e Ramping. 1: Hard/Im m ediate Volum e Change. [0] ADC01_FCOMP (R/W) ADC Channel 0 and Channel 1 Frequency Response Com pensation 0: High frequency response is not com pensated (lower delay). 1: High frequency response is com pensated (higher delay). [1] ADC23_FCOMP (R/W) ADC Channel 2 and Channel 3 Frequency Response Com pensation 0: High frequency response is not com pensated (lower delay). 1: High frequency response is com pensated (higher delay). [3:2] RESERVED Table 66. Bit Descriptions for ADC_CTRL4 Bits 7 6 Bit Name RESERVED ADC_VOL_ZC Settings 0 1 5 ADC_VOL_LINK 0 1 4 ADC_HARD_VOL 0 1 [3:2] 1 RESERVED ADC23_FCOMP 0 1 0 ADC01_FCOMP 0 1 Description Reserved. ADC Volume Zero Cross Control. Volume change occurs at any time. Volume change only occurs at zero crossing. ADC Volume Link. Each ADC channel uses its respective volume value. All ADC channels use Channel 0 volume value. ADC Hard Volume. Soft Volume Ramping. Hard/Immediate Volume Change. Reserved. ADC Channel 2 and Channel 3 Frequency Response Compensation. High frequency response not compensated (lower delay). High frequency response compensated (higher delay). ADC Channel 0 and Channel 1 Frequency Response Compensation. High frequency response not compensated (lower delay). High frequency response compensated (higher delay). Rev. A | Page 82 of 280 Reset 0x0 0x1 Access R R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W Data Sheet ADAU1787 ANALOG INPUT PRECHARGE TIME REGISTER Address: 0xC01B, Reset: 0x26, Name: ADC_CTRL5 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 0 [7:5] RESERVED [4] DIFF_INPUT (R/W) Configures the ADCs for differential operation [3:0] ADC_AIN_CHRG_TIME (R/W) Analog Inputs Precharge Tim e Selection. 0x0: No Precharge. 0x1: 5 m s Precharge. 0x2: 10 m s Precharge. ... 0xD: 250 ms Precharge. 0xE: 300 ms Precharge. 0xF: 400 ms Precharge. Table 67. Bit Descriptions for ADC_CTRL5 Bits [7:5] 4 [3:0] Bit Name RESERVED DIFF_INPUT ADC_AIN_CHRG_TIME Settings 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Description Reserved. Configures the ADCs for differential operation. Analog Inputs Precharge Time Selection. These bits control the amount of time the precharge circuit is used to charge up the coupling capacitors. The time used depends on the value of the capacitor used and the required start-up time of the ADC. No Precharge. 5 ms Precharge. 10 ms Precharge. 20 ms Precharge. 30 ms Precharge. 40 ms Precharge. 50 ms Precharge. 60 ms Precharge. 80 ms Precharge 100 ms Precharge 125 ms Precharge. 150 ms Precharge. 200 ms Precharge. 250 ms Precharge. 300 ms Precharge. 400 ms Precharge. Rev. A | Page 83 of 280 Reset 0x1 0x0 0x6 Access R R/W R/W ADAU1787 Data Sheet ADC CHANNEL MUTES REGISTER Address: 0xC01C, Reset: 0x00, Name: ADC_MUTES 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 : 4 ] R ES ER V ED [ 3 ] A D C 3 _M U T E ( R /W ) AD C Ch a n n e l 3 M u t e Co n tr o l 0 : AD C U n m u t e d . 1 : AD C M u te d . [ 2 ] A D C 2 _M U T E ( R /W ) AD C Ch a n n e l 2 M u t e Co n tr o l 0 : AD C U n m u t e d . 1 : AD C M u te d . [ 0 ] A D C 0 _M U T E ( R /W ) AD C Ch a n n e l 0 M u te Co n tr o l 0 : AD C U n m u te d . 1 : AD C M u te d . [ 1 ] A D C 1 _M U T E ( R / W ) AD C Ch a n n e l 1 M u te Co n t r o l 0 : AD C U n m u te d . 1 : AD C M u te d . Table 68. Bit Descriptions for ADC_MUTES Bits [7:4] 3 Bit Name RESERVED ADC3_MUTE Settings 0 1 2 ADC2_MUTE 0 1 1 ADC1_MUTE 0 1 0 ADC0_MUTE 0 1 Description Reserved. ADC Channel 3 Mute Control. ADC Unmuted. ADC Muted. ADC Channel 2 Mute Control. ADC Unmuted. ADC Muted. ADC Channel 1 Mute Control. ADC Unmuted. ADC Muted. ADC Channel 0 Mute Control. ADC Unmuted. ADC Muted. Rev. A | Page 84 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet ADAU1787 ADC CHANNEL 0 VOLUME CONTROL REGISTER Address: 0xC01D, Reset: 0x40, Name: ADC0_VOL 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] ADC0_VOL (R/W) ADC Channel 0 Volum e Control. 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 69. Bit Descriptions for ADC0_VOL Bits [7:0] Bit Name ADC0_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description ADC Channel 0 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 85 of 280 Reset 0x40 Access R/W ADAU1787 Data Sheet ADC CHANNEL 1 VOLUME CONTROL REGISTER Address: 0xC01E, Reset: 0x40, Name: ADC1_VOL 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] ADC1_VOL (R/W) ADC Channel 1 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 70. Bit Descriptions for ADC1_VOL Bits [7:0] Bit Name ADC1_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description ADC Channel 1 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 86 of 280 Reset 0x40 Access R/W Data Sheet ADAU1787 ADC CHANNEL 2 VOLUME CONTROL REGISTER Address: 0xC01F, Reset: 0x40, Name: ADC2_VOL 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] ADC2_VOL (R/W) ADC Channel 2 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 71. Bit Descriptions for ADC2_VOL Bits [7:0] Bit Name ADC2_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description ADC Channel 2 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 87 of 280 Reset 0x40 Access R/W ADAU1787 Data Sheet ADC CHANNEL 3 VOLUME CONTROL REGISTER Address: 0xC020, Reset: 0x40, Name: ADC3_VOL 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] ADC3_VOL (R/W) ADC Channel 3 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 72. Bit Descriptions for ADC3_VOL Bits [7:0] Bit Name ADC3_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description ADC Channel 3 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 88 of 280 Reset 0x40 Access R/W Data Sheet ADAU1787 PGA CHANNEL 0 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER Address: 0xC021, Reset: 0x00, Name: PGA0_CTRL1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] PGA0_SLEW_DIS (R/W) PGA Channel 0 Gain Slew Disable 0: PGA slew enabled. 1: PGA slew disabled. [5:0] PGA0_GAIN[10:5] (R/W) PGA Channel 0 Gain Control 00000000000: 0 dB. 00000100000: 0.75 dB. 00001000000: 1.5 dB. ... 10110100000: 33.75 dB. 10111000000: 34.5 dB. 10111100000: 35.25 dB. [6] PGA0_BOOST (R/W) PGA Channel 0 Gain Boost Control 0: No additional PGA0 gain above setting in PGA0_GAIN. 1: Additional 10 dB gain above setting in PGA0_GAIN. Table 73. Bit Descriptions for PGA0_CTRL1 Bits 7 Bit Name PGA0_SLEW_DIS Settings 0 1 6 PGA0_BOOST 0 1 [5:0] PGA0_GAIN[10:5] 00000000000 00000100000 00001000000 … 10110100000 10111000000 10111100000 Description PGA Channel 0 Gain Slew Disable. PGA slew enabled. PGA slew disabled. PGA Channel 0 Gain Boost Control. No additional PGA0 gain above setting in PGA0_GAIN. Additional 10 dB gain above setting in in PGA0_GAIN. PGA Channel 0 Gain Control. 0 dB. 0.75 dB. 1.5 dB … 33.75 dB. 34.5 dB. 35.25 dB. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W PGA CHANNEL 0 GAIN CONTROL LSBs REGISTER Address: 0xC022, Reset: 0x00, Name: PGA0_CTRL2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4:0] PGA0_GAIN[4:0] (R/W) PGA Channel 0 Gain Control 00000000000: 0 dB. 00000100000: 0.75 dB. 00001000000: 1.5 dB. ... 10110100000: 33.75 dB. 10111000000: 34.5 dB. 10111100000: 35.25 dB. Table 74. Bit Descriptions for PGA0_CTRL2 Bits [7:5] [4:0] Bit Name RESERVED PGA0_GAIN[4:0] Settings 00000000000 00000100000 00001000000 … 10110100000 10111000000 10111100000 Description Reserved. PGA Channel 0 Gain Control. 0 dB. 0.75 dB. 1.5 dB. … 34.5 dB 34.5 dB. 35.25 dB. Rev. A | Page 89 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Data Sheet PGA CHANNEL 1 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER Address: 0xC023, Reset: 0x00, Name: PGA1_CTRL1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] PGA1_SLEW_DIS (R/W) PGA Channel 1 Gain Slew Disable 0: PGA slew enabled. 1: PGA slew disabled. [5:0] PGA1_GAIN[10:5] (R/W) PGA Channel 1 Gain Control 00000000000: 0 dB. 00000100000: 0.75 dB. 00001000000: 1.5 dB. ... 10110100000: 33.75 dB. 10111000000: 34.5 dB. 10111100000: 35.25 dB. [6] PGA1_BOOST (R/W) PGA Channel 1 Gain Boost Control 0: No additional PGA1 gain above setting in PGA1_GAIN. 1: Additional 10 dB gain above setting in PGA1_GAIN. Table 75. Bit Descriptions for PGA1_CTRL1 Bits 7 Bit Name PGA1_SLEW_DIS Settings 0 1 6 PGA1_BOOST 0 1 [5:0] PGA1_GAIN[10:5] 00000000000 00000100000 00001000000 … 10110100000 10111000000 10111100000 Description PGA Channel 1 Gain Slew Disable. PGA slew enabled. PGA slew disabled. PGA Channel 1 Gain Boost Control. No additional PGA1 gain above setting in PGA1_GAIN. Additional 10 dB gain above setting in in PGA1_GAIN. PGA Channel 1 Gain Control. 0 dB. 0.75 dB. 1.5 dB. … 33.75 dB. 34.5 dB 35.25 dB. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W PGA CHANNEL 1 GAIN CONTROL LSBs REGISTER Address: 0xC024, Reset: 0x00, Name: PGA1_CTRL2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4:0] PGA1_GAIN[4:0] (R/W) PGA Channel 1 Gain Control 00000000000: 0 dB. 00000100000: 0.75 dB. 00001000000: 1.5 dB. ... 10110100000: 33.75 dB. 10111000000: 34.5 dB. 10111100000: 35.25 dB. Table 76. Bit Descriptions for PGA1_CTRL2 Bits [7:5] [4:0] Bit Name RESERVED PGA1_GAIN[4:0] Settings 00000000000 00000100000 00001000000 … 10110100000 10111000000 10111100000 Description Reserved. PGA Channel 1 Gain Control. 0 dB. 0.75 dB. 1.5 dB. … 33.75 dB. 34.5 dB. 35.25 dB. Rev. A | Page 90 of 280 Reset 0x0 0x0 Access R R/W Data Sheet ADAU1787 PGA CHANNEL 2 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER Address: 0xC025, Reset: 0x00, Name: PGA2_CTRL1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] PGA2_SLEW_DIS (R/W) PGA Channel 2 Gain Slew Disable 0: PGA slew enabled. 1: PGA slew disabled. [5:0] PGA2_GAIN[10:5] (R/W) PGA Channel 2 Gain Control 00000000000: 0 dB. 00000100000: 0.75 dB. 00001000000: 1.5 dB. ... 10110100000: 33.75 dB. 10111000000: 34.5 dB. 10111100000: 35.25 dB. [6] PGA2_BOOST (R/W) PGA Channel 2 Gain Boost Control 0: No additional PGA2 gain above setting in PGA2_GAIN. 1: Additional 10 dB gain above setting in PGA2_GAIN. Table 77. Bit Descriptions for PGA2_CTRL1 Bits 7 Bit Name PGA2_SLEW_DIS Settings 0 1 6 PGA2_BOOST 0 1 [5:0] PGA2_GAIN[10:5] 00000000000 00000100000 00001000000 … 10111000000 10111000000 10111100000 Description PGA Channel 2 Gain Slew Disable. PGA slew enabled. PGA slew disabled. PGA Channel 2 Gain Boost Control. No additional PGA2 gain above setting in PGA2_GAIN. Additional 10 dB gain above setting in PGA2_GAIN. PGA Channel 2 Gain Control. 0 dB. 0.75 dB. 1.5 dB. … 33.75 dB. 34.5 dB. 35.25 dB. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W PGA CHANNEL 2 GAIN CONTROL LSBs REGISTER Address: 0xC026, Reset: 0x00, Name: PGA2_CTRL2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4:0] PGA2_GAIN[4:0] (R/W) PGA Channel 2 Gain Control 00000000000: 0 dB. 00000100000: 0.75 dB. 00001000000: 1.5 dB. ... 10110100000: 33.75 dB. 10111000000: 34.5 dB. 10111100000: 35.25 dB. Table 78. Bit Descriptions for PGA2_CTRL2 Bits [7:5] [4:0] Bit Name RESERVED PGA2_GAIN[4:0] Settings 00000000000 00000100000 00001000000 … 10110100000 10111000000 10111100000 Description Reserved. PGA Channel 2 Gain Control. 0 dB. 0.75 dB. 1.5 dB. … 33.75 dB. 34.5 dB. 35.25 dB. Rev. A | Page 91 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Data Sheet PGA CHANNEL 3 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER Address: 0xC027, Reset: 0x00, Name: PGA3_CTRL1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] PGA3_SLEW_DIS (R/W) PGA Channel 3 Gain Slew Disable 0: PGA slew enabled. 1: PGA slew disabled. [5:0] PGA3_GAIN[10:5] (R/W) PGA Channel 3 Gain Control 00000000000: 0 dB. 00000100000: 0.75 dB. 00001000000: 1.5 dB. ... 10110100000: 33.75 dB. 10111000000: 34.5 dB. 10111100000: 35.25 dB. [6] PGA3_BOOST (R/W) PGA Channel 3 Gain Boost Control 0: No additional PGA3 gain above setting in PGA3_GAIN. 1: Additional 10 dB gain above setting in PGA3_GAIN. Table 79. Bit Descriptions for PGA3_CTRL1 Bits 7 Bit Name PGA3_SLEW_DIS Settings Description PGA Channel 3 Gain Slew Disable. PGA slew enabled. PGA slew disabled. PGA Channel 3 Gain Boost Control. No additional PGA3 gain above setting in PGA3_GAIN. Additional 10 dB gain above setting in PGA3_GAIN. PGA Channel 3 Gain Control 0 dB. 0.75 dB. 1.5 dB. … 33.75 dB. 34.5 dB. 35.25 dB. 0 1 6 PGA3_BOOST 0 1 [5:0] PGA3_GAIN[10:5] 00000000000 00000100000 00001000000 … 10110100000 10111000000 10111100000 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W PGA CHANNEL 3 GAIN CONTROL LSBs REGISTER Address: 0xC028, Reset: 0x00, Name: PGA3_CTRL2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4:0] PGA3_GAIN[4:0] (R/W) PGA Channel 3 Gain Control 00000000000: 0 dB. 00000100000: 0.75 dB. 00001000000: 1.5 dB. ... 10110100000: 33.75 dB. 10111000000: 34.5 dB. 10111100000: 35.25 dB. Table 80. Bit Descriptions for PGA3_CTRL2 Bits [7:5] [4:0] Bit Name RESERVED PGA3_GAIN[4:0] Settings 00000000000 00000100000 00001000000 … 10110100000 10111000000 10111100000 Description Reserved. PGA Channel 3 Gain Control. 0 dB. 0.75 dB. 1.5 dB. … 33.75 dB. 34.5 dB. 35.25 dB. Rev. A | Page 92 of 280 Reset 0x0 0x0 Access R R/W Data Sheet ADAU1787 PGA SLEW RATE AND GAIN LINK REGISTER Address: 0xC029, Reset: 0x00, Name: PGA_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [1:0] PGA_SLEW_RATE (R/W) Controls how fast the PGA is slewed when changing gain. 00: 2.2 dB/m s. 01: 1.1 dB/m s. 10: 0.5 dB/m s. [4] PGA_GAIN_LINK (R/W) PGA Gain Link. 0: Each PGA channel uses its respective gain value. 1: All PGA channels use Channel 0 gain value. [3:2] RESERVED Table 81. Bit Descriptions for PGA_CTRL Bits [7:5] 4 Bit Name RESERVED PGA_GAIN_LINK Settings 0 1 [3:2] [1:0] RESERVED PGA_SLEW_RATE 00 01 10 Description Reserved. PGA Gain Link. Each PGA channel uses its respective gain value. All PGA channels use Channel 0 gain value. Reserved. Controls how fast the PGA is slewed when changing gain. 2.2 dB/ms. 1.1 dB/ms. 0.5 dB/ms. Reset 0x0 0x0 Access R R/W 0x0 0x0 R R/W MICROPHONE BIAS LEVEL AND CURRENT REGISTER Address: 0xC02A, Reset: 0x00, Name: MBIAS_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:4] MBIAS_IBIAS (R/W) Microphone Input Bias Current Setting 00: Normal Operation (Default). 01: Extrem e Power Saving. 10: Enhanced Perform ance. 11: Power Saving. [3:2] RESERVED [0] MBIAS0_LEVEL (R/W) Level of the MICBIAS0 Output 0: 0.9 × AVDD. 1: 0.65 × AVDD. [1] MBIAS1_LEVEL (R/W) Level of the MICBIAS1 Output 0: 0.9 × AVDD. 1: 0.65 × AVDD. Table 82. Bit Descriptions for MBIAS_CTRL Bits [7:6] [5:4] Bit Name RESERVED MBIAS_IBIAS Settings 00 01 10 11 [3:2] 1 RESERVED MBIAS1_LEVEL 0 1 0 MBIAS0_LEVEL 0 1 Description Reserved. Microphone Input Bias Current Setting. Higher bias currents result in higher performance. Normal Operation (Default). Extreme Power Saving. Enhanced Performance. Power Saving. Reserved. Level of the MICBIAS1 Output. 0.9 × AVDD. 0.65 × AVDD. Level of the MICBIAS0 Output. 0.9 × AVDD. 0.65 × AVDD. Rev. A | Page 93 of 280 Reset 0x0 0x0 Access R R/W 0x0 0x0 R R/W 0x0 R/W ADAU1787 Data Sheet DIGITAL MICROPHONE CLOCK RATE CONTROL REGISTER Address: 0xC02B, Reset: 0x33, Name: DMIC_CTRL1 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 1 [7] RESERVED [6:4] DMIC_CLK1_RATE (R/W) Digital Microphone Clock 1 Rate 0: 384 kHz Clock Rate. 1: 768 kHz Clock Rate. 10: 1536 kHz Clock Rate. 11: 3072 kHz Clock Rate. 100: 6144 kHz Clock Rate. [2:0] DMIC_CLK0_RATE (R/W) Digital Microphone Clock 0 Rate 0: 384 kHz Clock Rate. 1: 768 kHz Clock Rate. 10: 1536 kHz Clock Rate. 11: 3072 kHz Clock Rate. 100: 6144 kHz Clock Rate. [3] RESERVED Table 83. Bit Descriptions for DMIC_CTRL1 Bits 7 [6:4] Bit Name RESERVED DMIC_CLK1_RATE Settings 0 1 10 11 100 3 [2:0] RESERVED DMIC_CLK0_RATE 0 1 10 11 100 Description Reserved. Digital Microphone Clock 1 Rate. 384 kHz Clock Rate. 768 kHz Clock Rate. 1536 kHz Clock Rate. 3072 kHz Clock Rate. 6144 kHz Clock Rate. Reserved. Digital Microphone Clock 0 Rate. 384 kHz Clock Rate. 768 kHz Clock Rate. 1536 kHz Clock Rate. 3072 kHz Clock Rate. 6144 kHz Clock Rate. Rev. A | Page 94 of 280 Reset 0x0 0x3 Access R R/W 0x0 0x3 R R/W Data Sheet ADAU1787 DIGITAL MICROPHONE CHANNEL 0 AND CHANNEL 1 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER Address: 0xC02C, Reset: 0x01, Name: DMIC_CTRL2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7] DMIC01_MAP (R/W) Digital Microphone Channel 0 and Channel 1 Clock Mapping 0: Digital microphone channels use DMIC_CLK0. 1: Digital microphone channels use DMIC_CLK1. [6] DMIC01_EDGE (R/W) Selects clock edge for Channel 0 and Channel 1 0: 0 is rising edge, and 1 is falling edge. 1: 1 is rising edge, and 0 is falling edge. [5] DMIC01_FCOMP (R/W) Digital Microphone Channel 0 and Channel 1 Frequency Response Com pensation 0: High frequency response is not com pensated (lower delay). 1: High frequency response is com pensated (higher delay). [2:0] DMIC01_FS (R/W) Digital Microphone Channel 0 and Channel 1 Output Sam ple Rate 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sample Rate. 101: 384 kHz Sample Rate. 110: 768 kHz Sample Rate. [3] DMIC01_HPF_EN (R/W) Digital Microphone Channel 0 and Channel 1 High-Pass Filter Enable 0: High-Pass Filter Off. 1: High-Pass Filter On. [4] DMIC01_DEC_ORDER (R/W) Digital Microphone Channel 0 and Channel 1 Decimation Filter Order 0: Fourth-Order Decim ation Filter. 1: Fifth-Order Decim ation Filter. Table 84. Bit Descriptions for DMIC_CTRL2 Bits 7 Bit Name DMIC01_MAP Settings 0 1 6 DMIC01_EDGE 0 1 5 DMIC01_FCOMP 0 1 4 DMIC01_DEC_ORDER 0 1 3 DMIC01_HPF_EN 0 1 [2:0] DMIC01_FS 000 001 010 011 100 101 110 Description Digital Microphone Channel 0 and Channel 1 Clock Mapping. Digital microphone channels use DMIC_CLK0. Digital microphone channels use DMIC_CLK1. Selects clock edge for Channel 0 and Channel 1. 0 is rising edge, and 1 is falling edge. 1 is rising edge, and 0 is falling edge. Digital Microphone Channel 0 and Channel 1 Frequency Response Compensation. High frequency response is not compensated (lower delay). High frequency response is compensated (higher delay). Digital Microphone Channel 0 and Channel 1 Decimation Filter Order. Fourth-Order Decimation Filter. Fifth-Order Decimation Filter. Digital Microphone Channel 0 and Channel 1 High-Pass Filter Enable. High-Pass Filter Off. High-Pass Filter On. Digital Microphone Channel 0 and Channel 1 Output Sample Rate. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Rev. A | Page 95 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R/W ADAU1787 Data Sheet DIGITAL MICROPHONE CHANNEL 2 AND CHANNEL 3 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER Address: 0xC02D, Reset: 0x01, Name: DMIC_CTRL3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7] DMIC23_MAP (R/W) Digital Microphone Channel 2 and Channel 3 Clock Mapping 0: Digital microphone channels use DMIC_CLK0. 1: Digital microphone channels use DMIC_CLK1. [6] DMIC23_EDGE (R/W) Selects clock edge for Channel 2 and Channel 3 0: 0 is rising edge, and 1 is falling edge. 1: 1 is rising edge, and 0 is falling edge. [5] DMIC23_FCOMP (R/W) Digital Microphone Channel 2 and Channel 3 Frequency Response Com pensation 0: High frequency response is not com pensated (lower delay). 1: High frequency response is com pensated (higher delay). [2:0] DMIC23_FS (R/W) Digital Microphone Channel 2 and Channel 3 Output Sam ple Rate 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sample Rate. 101: 384 kHz Sample Rate. 110: 768 kHz Sample Rate. [3] DMIC23_HPF_EN (R/W) Digital Microphone Channel 2 and Channel 3 High-Pass Filter Enable 0: High-Pass Filter Off. 1: High-Pass Filter On. [4] DMIC23_DEC_ORDER (R/W) Digital Microphone Channel 2 and Channel 3 Decimation Filter Order 0: Fourth-Order Decim ation Filter. 1: Fifth-Order Decim ation Filter. Table 85. Bit Descriptions for DMIC_CTRL3 Bits 7 Bit Name DMIC23_MAP Settings 0 1 6 DMIC23_EDGE 0 1 5 DMIC23_FCOMP 0 1 4 DMIC23_DEC_ORDER 0 1 3 DMIC23_HPF_EN 0 1 [2:0] DMIC23_FS 000 001 010 011 100 101 110 Description Digital Microphone Channel 2 and Channel 3 Clock Mapping. Digital microphone channels use DMIC_CLK0. Digital microphone channels use DMIC_CLK1. Selects clock edge for Channel 2 and Channel 3. 0 is rising edge, and 1 is falling edge. 1 is rising edge, and 0 is falling edge. Digital Microphone Channel 2 and Channel 3 Frequency Response Compensation. High frequency response is not compensated (lower delay). High frequency response is compensated (higher delay). Digital Microphone Channel 2 and Channel 3 Decimation Filter Order. Fourth-Order Decimation Filter. Fifth-Order Decimation Filter. Digital Microphone Channel 2 and Channel 3 High-Pass Filter Enable. High-Pass Filter Off. High-Pass Filter On. Digital Microphone Channel 2 and Channel 3 Output Sample Rate. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Rev. A | Page 96 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R/W Data Sheet ADAU1787 DIGITAL MICROPHONE CHANNEL 4 AND CHANNEL 5 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER Address: 0xC02E, Reset: 0x01, Name: DMIC_CTRL4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7] DMIC45_MAP (R/W) Digital Microphone Channel 4 and Channel 5 Clock Mapping 0: Digital microphone channels use DMIC_CLK0. 1: Digital microphone channels use DMIC_CLK1. [6] DMIC45_EDGE (R/W) Selects clock edge for Channel 4 and Channel 5 0: 0 is rising edge, and 1 is falling edge. 1: 1 is rising edge, and 0 is falling edge. [5] DMIC45_FCOMP (R/W) Digital Microphone Channel 4 and Channel 5 Frequency Response Com pensation 0: High frequency response is not com pensated (lower delay). 1: High frequency response is com pensated (higher delay). [2:0] DMIC45_FS (R/W) Digital Microphone Channel 4 and Channel 5 Output Sam ple Rate 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sample Rate. 101: 384 kHz Sample Rate. 110: 768 kHz Sample Rate. [3] DMIC45_HPF_EN (R/W) Digital Microphone Channel 4 and Channel 5 High-Pass Filter Enable 0: High-Pass Filter Off. 1: High-Pass Filter On. [4] DMIC45_DEC_ORDER (R/W) Digital Microphone Channel 4 and Channel 5 Decimation Filter Order 0: Fourth-Order Decim ation Filter. 1: Fifth-Order Decim ation Filter. Table 86. Bit Descriptions for DMIC_CTRL4 Bits 7 Bit Name DMIC45_MAP Settings 0 1 6 DMIC45_EDGE 0 1 5 DMIC45_FCOMP 0 1 4 DMIC45_DEC_ORDER 0 1 3 DMIC45_HPF_EN 0 1 [2:0] DMIC45_FS 000 001 010 011 100 101 110 Description Digital Microphone Channel 4 and Channel 5 Clock Mapping. Digital microphone channels use DMIC_CLK0. Digital microphone channels use DMIC_CLK1. Selects clock edge for Channel 4 and Channel 5. 0 is rising edge, and 1 is falling edge. 1 is rising edge, and 0 is falling edge. Digital Microphone Channel 4 and Channel 5 Frequency Response Compensation. High frequency response is not compensated (lower delay). High frequency response is compensated (higher delay). Digital Microphone Channel 4 and Channel 5 Decimation Filter Order. Fourth-Order Decimation Filter. Fifth-Order Decimation Filter. Digital Microphone Channel 4 and Channel 5 High-Pass Filter Enable. High-Pass Filter Off. High-Pass Filter On. Digital Microphone Channel 4 and Channel 5 Output Sample Rate. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Rev. A | Page 97 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R/W ADAU1787 Data Sheet DIGITAL MICROPHONE CHANNEL 6 AND CHANNEL 7 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER Address: 0xC02F, Reset: 0x01, Name: DMIC_CTRL5 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7] DMIC67_MAP (R/W) Digital Microphone Channel 6 and Channel 7 Clock Mapping 0: Digital microphone channels use DMIC_CLK0. 1: Digital microphone channels use DMIC_CLK1. [6] DMIC67_EDGE (R/W) Selects clock edge for Channel 6 and Channel 7 0: 0 is rising edge, and 1 is falling edge. 1: 1 is rising edge, and 0 is falling edge. [5] DMIC67_FCOMP (R/W) Digital Microphone Channel 6 and Channel 7 Frequency Response Com pensation 0: High frequency response is not com pensated (lower delay). 1: High frequency response is com pensated (higher delay). [2:0] DMIC67_FS (R/W) Digital Microphone Channel 6 and Channel 7 Output Sam ple Rate 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sample Rate. 101: 384 kHz Sample Rate. 110: 768 kHz Sample Rate. [3] DMIC67_HPF_EN (R/W) Digital Microphone Channel 6 and Channel 7 High-Pass Filter Enable 0: High-Pass Filter Off. 1: High-Pass Filter On. [4] DMIC67_DEC_ORDER (R/W) Digital Microphone Channel 6 and Channel 7 Decimation Filter Order 0: Fourth-Order Decim ation Filter. 1: Fifth-Order Decim ation Filter. Table 87. Bit Descriptions for DMIC_CTRL5 Bits 7 Bit Name DMIC67_MAP Settings 0 1 6 DMIC67_EDGE 0 1 5 DMIC67_FCOMP 0 1 4 DMIC67_DEC_ORDER 0 1 3 DMIC67_HPF_EN 0 1 [2:0] DMIC67_FS 000 001 010 011 100 101 110 Description Digital Microphone Channel 6 and Channel 7 Clock Mapping. Digital microphone channels use DMIC_CLK0. Digital microphone channels use DMIC_CLK1. Selects clock edge for Channel 6 and Channel 7. 0 is rising edge, and 1 is falling edge. 1 is rising edge, and 0 is falling edge. Digital Microphone Channel 6 and Channel 7 Frequency Response Compensation. High frequency response is not compensated (lower delay). High frequency response is compensated (higher delay). Digital Microphone Channel 6 and Channel 7 Decimation Filter Order. Fourth-Order Decimation Filter. Fifth-Order Decimation Filter. Digital Microphone Channel 6 and Channel 7 High-Pass Filter Enable. High-Pass Filter Off. High-Pass Filter On. Digital Microphone Channel 6 and Channel 7 Output Sample Rate. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Rev. A | Page 98 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R/W Data Sheet ADAU1787 DIGTIAL MICROPHONE VOLUME OPTIONS REGISTER Address: 0xC030, Reset: 0x04, Name: DMIC_CTRL6 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 [7:3] RESERVED [2] DMIC_VOL_ZC (R/W) Digital Microphone Volume Zero Cross Control 0: Volum e change occurs at any tim e. 1: Volum e change only occurs at zero crossing. [0] DMIC_HARD_VOL (R/W) Digital Microphone Hard Volume 0: Soft Volum e Ram ping. 1: Hard/Im m ediate Volume Change. [1] DMIC_VOL_LINK (R/W) Digital Microphone Volume Link 0: Each digital m icrophone channel uses its respective volume value. 1: All digital microphone channels use Channel 0 volum e value. Table 88. Bit Descriptions for DMIC_CTRL6 Bits [7:3] 2 Bit Name RESERVED DMIC_VOL_ZC Settings 0 1 1 DMIC_VOL_LINK 0 1 0 DMIC_HARD_VOL 0 1 Description Reserved. Digital Microphone Volume Zero Cross Control. Volume change occurs at any time. Volume change only occurs at zero crossing. Digital Microphone Volume Link. Each digital microphone channel uses its respective volume value. All digital microphone channels use Channel 0 volume value. Digital Microphone Hard Volume. Soft Volume Ramping. Hard/Immediate Volume Change. Rev. A | Page 99 of 280 Reset 0x0 0x1 Access R R/W 0x0 R/W 0x0 R/W ADAU1787 Data Sheet DIGITAL MICROPHONE CHANNEL MUTE CONTROLS REGISTER Address: 0xC031, Reset: 0x00, Name: DMIC_MUTES 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] DMIC7_MUTE (R/W) Digital Microphone Channel 7 Mute Control 0: Digital Microphone Unm uted. 1: Digital Microphone Muted. [0] DMIC0_MUTE (R/W) Digital Microphone Channel 0 Mute Control 0: Digital Microphone Unm uted. 1: Digital Microphone Muted. [6] DMIC6_MUTE (R/W) Digital Microphone Channel 6 Mute Control 0: Digital Microphone Unm uted. 1: Digital Microphone Muted. [1] DMIC1_MUTE (R/W) Digital Microphone Channel 1 Mute Control 0: Digital Microphone Unm uted. 1: Digital Microphone Muted. [5] DMIC5_MUTE (R/W) Digital Microphone Channel 5 Mute Control 0: Digital Microphone Unm uted. 1: Digital Microphone Muted. [2] DMIC2_MUTE (R/W) Digital Microphone Channel 2 Mute Control 0: Digital Microphone Unm uted. 1: Digital Microphone Muted. [4] DMIC4_MUTE (R/W) Digital Microphone Channel 4 Mute Control 0: Digital Microphone Unm uted. 1: Digital Microphone Muted. [3] DMIC3_MUTE (R/W) Digital Microphone Channel 3 Mute Control 0: Digital Microphone Unm uted. 1: Digital Microphone Muted. Table 89. Bit Descriptions for DMIC_MUTES Bits 7 Bit Name DMIC7_MUTE Settings 0 1 6 DMIC6_MUTE 0 1 5 DMIC5_MUTE 0 1 4 DMIC4_MUTE 0 1 3 DMIC3_MUTE 0 1 2 DMIC2_MUTE 0 1 1 DMIC1_MUTE 0 1 0 DMIC0_MUTE 0 1 Description Digital Microphone Channel 7 Mute Control. Digital Microphone Unmuted. Digital Microphone Muted. Digital Microphone Channel 6 Mute Control. Digital Microphone Unmuted. Digital Microphone Muted. Digital Microphone Channel 5 Mute Control. Digital Microphone Unmuted. Digital Microphone Muted. Digital Microphone Channel 4 Mute Control. Digital Microphone Unmuted. Digital Microphone Muted. Digital Microphone Channel 3 Mute Control. Digital Microphone Unmuted. Digital Microphone Muted. Digital Microphone Channel 2 Mute Control. Digital Microphone Unmuted. Digital Microphone Muted. Digital Microphone Channel 1 Mute Control. Digital Microphone Unmuted. Digital Microphone Muted. Digital Microphone Channel 0 Mute Control. Digital Microphone Unmuted. Digital Microphone Muted. Rev. A | Page 100 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet ADAU1787 DIGITAL MICROPHONE CHANNEL 0 VOLUME CONTROL REGISTER Address: 0xC032, Reset: 0x40, Name: DMIC_VOL0 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] DMIC0_VOL (R/W) Digital Microphone Channel 0 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 90. Bit Descriptions for DMIC_VOL0 Bits [7:0] Bit Name DMIC0_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description Digital Microphone Channel 0 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 101 of 280 Reset 0x40 Access R/W ADAU1787 Data Sheet DIGITAL MICROPHONE CHANNEL 1 VOLUME CONTROL REGISTER Address: 0xC033, Reset: 0x40, Name: DMIC_VOL1 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] DMIC1_VOL (R/W) Digital Microphone Channel 1 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 91. Bit Descriptions for DMIC_VOL1 Bits [7:0] Bit Name DMIC1_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description Digital Microphone Channel 1 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 102 of 280 Reset 0x40 Access R/W Data Sheet ADAU1787 DIGITAL MICROPHONE CHANNEL 2 VOLUME CONTROL REGISTER Address: 0xC034, Reset: 0x40, Name: DMIC_VOL2 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] DMIC2_VOL (R/W) Digital Microphone Channel 2 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 92. Bit Descriptions for DMIC_VOL2 Bits [7:0] Bit Name DMIC2_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description Digital Microphone Channel 2 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 103 of 280 Reset 0x40 Access R/W ADAU1787 Data Sheet DIGITAL MICROPHONE CHANNEL 3 VOLUME CONTROL REGISTER Address: 0xC035, Reset: 0x40, Name: DMIC_VOL3 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] DMIC3_VOL (R/W) Digital Microphone Channel 3 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 93. Bit Descriptions for DMIC_VOL3 Bits [7:0] Bit Name DMIC3_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description Digital Microphone Channel 3 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 104 of 280 Reset 0x40 Access R/W Data Sheet ADAU1787 DIGITAL MICROPHONE CHANNEL 4 VOLUME CONTROL REGISTER Address: 0xC036, Reset: 0x40, Name: DMIC_VOL4 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] DMIC4_VOL (R/W) Digital Microphone Channel 4 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 94. Bit Descriptions for DMIC_VOL4 Bits [7:0] Bit Name DMIC4_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description Digital Microphone Channel 4 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 105 of 280 Reset 0x40 Access R/W ADAU1787 Data Sheet DIGITAL MICROPHONE CHANNEL 5 VOLUME CONTROL REGISTER Address: 0xC037, Reset: 0x40, Name: DMIC_VOL5 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] DMIC5_VOL (R/W) Digital Microphone Channel 5 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 95. Bit Descriptions for DMIC_VOL5 Bits [7:0] Bit Name DMIC5_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description Digital Microphone Channel 5 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 106 of 280 Reset 0x40 Access R/W Data Sheet ADAU1787 DIGITAL MICROPHONE CHANNEL 6 VOLUME CONTROL REGISTER Address: 0xC038, Reset: 0x40, Name: DMIC_VOL6 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] DMIC6_VOL (R/W) Digital Microphone Channel 6 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 96. Bit Descriptions for DMIC_VOL6 Bits [7:0] Bit Name DMIC6_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description Digital Microphone Channel 6 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 107 of 280 Reset 0x40 Access R/W ADAU1787 Data Sheet DIGITAL MICROPHONE CHANNEL 7 VOLUME CONTROL REGISTER Address: 0xC039, Reset: 0x40, Name: DMIC_VOL7 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] DMIC7_VOL (R/W) Digital Microphone Channel 7 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 97. Bit Descriptions for DMIC_VOL7 Bits [7:0] Bit Name DMIC7_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description Digital Microphone Channel 7 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 108 of 280 Reset 0x40 Access R/W Data Sheet ADAU1787 DAC SAMPLE RATE, FILTERING, AND POWER CONTROLS REGISTER Address: 0xC03A, Reset: 0x02, Name: DAC_CTRL1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 [7] DAC_MORE_FILT (R/W) DAC Additional Interpolation Filtering Selection 0: Less Interpolation Filtering: Lower Delay. 1: More Interpolation Filtering: Higher Delay. [6] DAC_LPM (R/W) DAC Low Power Mode Enable 0: DAC Low Power Mode Off (6.144 MHz). 1: DAC Low Power Mode On (3.072 MHz). [5:4] DAC_IBIAS (R/W) DAC Bias Current Select 00: Norm al Operation (Default). 01: Extrem e Power Saving. 10: Enhanced Performance. 11: Power Saving. [2:0] DAC_FS (R/W) DAC Path Sample Rate Selection 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sample Rate. 101: 384 kHz Sample Rate. 110: 768 kHz Sample Rate. [3] DAC_FCOMP (R/W) DAC Frequency Response Com pensation 0: High frequency response is not com pensated (lower delay). 1: High frequency response is com pensated for samples rates of 192 kHz or lower when DAC_MORE_FILT = 1 (higher delay). Table 98. Bit Descriptions for DAC_CTRL1 Bits 7 Bit Name DAC_MORE_FILT Settings 0 1 6 DAC_LPM 0 1 [5:4] DAC_IBIAS 00 01 10 11 3 DAC_FCOMP 0 1 [2:0] DAC_FS 000 001 010 011 100 101 110 Description DAC Additional Interpolation Filtering Selection. Less Interpolation Filtering: Lower Delay. More Interpolation Filtering: Higher Delay. DAC Low Power Mode Enable. DAC Low Power Mode Off (6.144 MHz). DAC Low Power Mode On (3.072 MHz). DAC Bias Current Select. Higher bias currents result in higher performance. Normal Operation (Default). Extreme Power Saving. Enhanced Performance. Power Saving. DAC Frequency Response Compensation. High frequency response is not compensated (lower delay). High frequency response is compensated for samples rates of 192 kHz or lower when DAC_MORE_FILT = 1 (higher delay). DAC Path Sample Rate Selection. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Rev. A | Page 109 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x2 R/W ADAU1787 Data Sheet DAC VOLUME LINK, HIGH-PASS FILTER (HPF), AND MUTE CONTROLS REGISTER Address: 0xC03B, Reset: 0xC4, Name: DAC_CTRL2 7 6 5 4 3 2 1 0 1 1 0 0 0 1 0 0 [7] DAC1_MUTE (R/W) DAC Channel 1 Mute Control 0: DAC Unm uted. 1: DAC Muted. [6] DAC0_MUTE (R/W) DAC Channel 0 Mute Control 0: DAC Unm uted. 1: DAC Muted. [5] DAC1_HPF_EN (R/W) DAC Channel 1 Enable High-Pass Filter 0: DAC High-Pass Filter Off. 1: DAC High-Pass Filter On. [4] DAC0_HPF_EN (R/W) DAC Channel 0 Enable High-Pass Filter 0: DAC High-Pass Filter Off. 1: DAC High-Pass Filter On. [0] DAC_VOL_LINK (R/W) DAC Volume Link 0: Each ADC channel uses its respective volum e value. 1: All ADC channels use Channel 0 volum e value. [1] DAC_HARD_VOL (R/W) DAC Hard Volume 0: Soft Volume Ram ping. 1: Hard/Imm ediate Volum e Change. [2] DAC_VOL_ZC (R/W) DAC Volume Zero Cross Control 0: Volume change occurs at any tim e. 1: Volume change only occurs at zero crossing. [3] DAC_LPM_II (R/W) DAC Low Power Mode 2 Enable 0: DAC Low Power Mode 2 Off. 1: DAC Low Power Mode 2 On. Reduced output activity. Table 99. Bit Descriptions for DAC_CTRL2 Bits 7 Bit Name DAC1_MUTE Settings 0 1 6 DAC0_MUTE 0 1 5 DAC1_HPF_EN 0 1 4 DAC0_HPF_EN 0 1 3 DAC_LPM_II 0 1 2 DAC_VOL_ZC 0 1 1 DAC_HARD_VOL 0 1 0 DAC_VOL_LINK 0 1 Description DAC Channel 1 Mute Control. DAC Unmuted. DAC Muted. DAC Channel 0 Mute Control. DAC Unmuted. DAC Muted. DAC Channel 1 Enable High-Pass Filter. ADC High-Pass Filter Off. ADC High-Pass Filter On. DAC Channel 0 Enable High-Pass Filter. ADC High-Pass Filter Off. ADC High-Pass Filter On. DAC Low Power Mode 2 Enable. DAC Low Power Mode 2 Off. DAC Low Power Mode 2 On. Reduced output activity. DAC Volume Zero Cross Control. Volume change occurs at any time. Volume change only occurs at zero crossing. DAC Hard Volume. Soft Volume Ramping. Hard/Immediate Volume Change. DAC Volume Link. Each ADC channel uses its respective volume value. All ADC channels use Channel 0 volume value. Rev. A | Page 110 of 280 Reset 0x1 Access R/W 0x1 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x0 R/W 0x0 R/W Data Sheet ADAU1787 DAC CHANNEL 0 VOLUME REGISTER Address: 0xC03C, Reset: 0x40, Name: DAC_VOL0 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] DAC0_VOL (R/W) DAC Channel 0 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 100. Bit Descriptions for DAC_VOL0 Bits [7:0] Bit Name DAC0_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description DAC Channel 0 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 111 of 280 Reset 0x40 Access R/W ADAU1787 Data Sheet DAC CHANNEL 1 VOLUME REGISTER Address: 0xC03D, Reset: 0x40, Name: DAC_VOL1 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] DAC1_VOL (R/W) DAC Channel 1 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 101. Bit Descriptions for DAC_VOL1 Bits [7:0] Bit Name DAC1_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description DAC Channel 1 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 112 of 280 Reset 0x40 Access R/W Data Sheet ADAU1787 DAC CHANNEL 0 ROUTING REGISTER Address: 0xC03E, Reset: 0x00, Name: DAC_ROUTE0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [6:0] DAC0_ROUTE (R/W) DAC Channel 0 Input Routing 0000000: Serial Port 0 Channel 0. 0000001: Serial Port 0 Channel 1. 0000010: Serial Port 0 Channel 2. ... 1001101: Digital Microphone Channel 5. 1001110: Digital Microphone Channel 6. 1001111: Digital Microphone Channel 7. Table 102. Bit Descriptions for DAC_ROUTE0 Bits 7 [6:0] Bit Name RESERVED DAC0_ROUTE Settings 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Description Reserved. DAC Channel 0 Input Routing. Serial Port 0 Channel 0. Serial Port 0 Channel 1. Serial Port 0 Channel 2. Serial Port 0 Channel 3. Serial Port 0 Channel 4. Serial Port 0 Channel 5. Serial Port 0 Channel 6. Serial Port 0 Channel 7. Serial Port 0 Channel 8. Serial Port 0 Channel 9. Serial Port 0 Channel 10. Serial Port 0 Channel 11. Serial Port 0 Channel 12. Serial Port 0 Channel 13. Serial Port 0 Channel 14. Serial Port 0 Channel 15. Serial Port 1 Channel 0. Serial Port 1 Channel 1. Serial Port 1 Channel 2. Serial Port 1 Channel 3. Serial Port 1 Channel 4. Serial Port 1 Channel 5. Serial Port 1 Channel 6. Serial Port 1 Channel 7. Serial Port 1 Channel 8. Serial Port 1 Channel 9. Serial Port 1 Channel 10. Serial Port 1 Channel 11. Serial Port 1 Channel 12. Serial Port 1 Channel 13. Serial Port 1 Channel 14. Serial Port 1 Channel 15. Rev. A | Page 113 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Description FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digital Microphone Channel 0. Digital Microphone Channel 1. Digital Microphone Channel 2. Digital Microphone Channel 3. Digital Microphone Channel 4. Digital Microphone Channel 5. Digital Microphone Channel 6. Digital Microphone Channel 7. Rev. A | Page 114 of 280 Reset Access Data Sheet ADAU1787 DAC CHANNEL 1 ROUTING REGISTER Address: 0xC03F, Reset: 0x01, Name: DAC_ROUTE1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7] RESERVED [6:0] DAC1_ROUTE (R/W) DAC Channel 1 Input Routing 0000000: Serial Port 0 Channel 0. 0000001: Serial Port 0 Channel 1. 0000010: Serial Port 0 Channel 2. ... 1001101: Digital Microphone Channel 5. 1001110: Digital Microphone Channel 6. 1001111: Digital Microphone Channel 7. Table 103. Bit Descriptions for DAC_ROUTE1 Bits 7 [6:0] Bit Name RESERVED DAC1_ROUTE Settings 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Description Reserved. DAC Channel 1 Input Routing. Serial Port 0 Channel 0. Serial Port 0 Channel 1. Serial Port 0 Channel 2. Serial Port 0 Channel 3. Serial Port 0 Channel 4. Serial Port 0 Channel 5. Serial Port 0 Channel 6. Serial Port 0 Channel 7. Serial Port 0 Channel 8. Serial Port 0 Channel 9. Serial Port 0 Channel 10. Serial Port 0 Channel 11. Serial Port 0 Channel 12. Serial Port 0 Channel 13. Serial Port 0 Channel 14. Serial Port 0 Channel 15. Serial Port 1 Channel 0. Serial Port 1 Channel 1. Serial Port 1 Channel 2. Serial Port 1 Channel 3. Serial Port 1 Channel 4. Serial Port 1 Channel 5. Serial Port 1 Channel 6. Serial Port 1 Channel 7. Serial Port 1 Channel 8. Serial Port 1 Channel 9. Serial Port 1 Channel 10. Serial Port 1 Channel 11. Serial Port 1 Channel 12. Serial Port 1 Channel 13. Serial Port 1 Channel 14. Serial Port 1 Channel 15. Rev. A | Page 115 of 280 Reset 0x0 0x1 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Description FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digital Microphone Channel 0. Digital Microphone Channel 1. Digital Microphone Channel 2. Digital Microphone Channel 3. Digital Microphone Channel 4. Digital Microphone Channel 5. Digital Microphone Channel 6. Digital Microphone Channel 7. Rev. A | Page 116 of 280 Reset Access Data Sheet ADAU1787 HEADPHONE CONTROL REGISTER Address: 0xC040, Reset: 0x00, Name: HP_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [0] HP0_MODE (R/W) Headphone Channel 0 Output Mode 0: HPOUTP0/HPOUTN0 in Line Output Mode. 1: HPOUTP0/HPOUTN0 in Headphone Mode. [4] HP1_MODE (R/W) Headphone Channel 1 Output Mode 0: HPOUTP0/HPOUTN0 in Line Output Mode. 1: HPOUTP0/HPOUTN0 in Headphone Mode. [3:1] RESERVED Table 104. Bit Descriptions for HP_CTRL Bits [7:5] 4 Bit Name RESERVED HP1_MODE Settings 0 1 [3:1] 0 RESERVED HP0_MODE 0 1 Description Reserved. Headphone Channel 1 Output Mode. HPOUTP0/HPOUTN0 in Line Output Mode. HPOUTP0/HPOUTN0 in Headphone Mode. Reserved. Headphone Channel 0 Output Mode. HPOUTP0/HPOUTN0 in Line Output Mode. HPOUTP0/HPOUTN0 in Headphone Mode. Reset 0x0 0x0 Access R R/W 0x0 0x0 R R/W FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER Address: 0xC041, Reset: 0x25, Name: FDEC_CTRL1 7 6 5 4 3 2 1 0 0 0 1 0 0 1 0 1 [7] RESERVED [6:4] FDEC01_OUT_FS (R/W) Decimator Channel 0/Channel 1 Output Sam pling Rate 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. [2:0] FDEC01_IN_FS (R/W) Decim ator Channel 0/Channel 1 Input Sam pling Rate 001: 24 kHz Sample Rate. 010: 48 kHz Sample Rate. 011: 96 kHz Sample Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. 110: 768 kHz Sam ple Rate. [3] RESERVED Table 105. Bit Descriptions for FDEC_CTRL1 Bits 7 [6:4] Bit Name RESERVED FDEC01_OUT_FS Settings 000 001 010 011 100 101 3 [2:0] RESERVED FDEC01_IN_FS 001 010 011 100 101 110 Description Reserved. Decimator Channel 0/Channel 1 Output Sampling Rate. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. Reserved. Decimator Channel 0/Channel 1 Input Sampling Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Rev. A | Page 117 of 280 Reset 0x0 0x2 Access R R/W 0x0 0x5 R R/W ADAU1787 Data Sheet FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER Address: 0xC042, Reset: 0x25, Name: FDEC_CTRL2 7 6 5 4 3 2 1 0 0 0 1 0 0 1 0 1 [7] RESERVED [6:4] FDEC23_OUT_FS (R/W) Decimator Channel 2/Channel 3 Output Sam pling Rate 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. [2:0] FDEC23_IN_FS (R/W) Decim ator Channel 2/Channel 3 Input Sam pling Rate 001: 24 kHz Sample Rate. 010: 48 kHz Sample Rate. 011: 96 kHz Sample Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. 110: 768 kHz Sam ple Rate. [3] RESERVED Table 106. Bit Descriptions for FDEC_CTRL2 Bits 7 [6:4] Bit Name RESERVED FDEC23_OUT_FS Settings 000 001 010 011 100 101 3 [2:0] RESERVED FDEC23_IN_FS 001 010 011 100 101 110 Description Reserved. Decimator Channel 2/Channel 3 Output Sampling Rate. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. Reserved. Decimator Channel 2/Channel 3 Input Sampling Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Rev. A | Page 118 of 280 Reset 0x0 0x2 Access R R/W 0x0 0x5 R R/W Data Sheet ADAU1787 FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER Address: 0xC043, Reset: 0x25, Name: FDEC_CTRL3 7 6 5 4 3 2 1 0 0 0 1 0 0 1 0 1 [7] RESERVED [6:4] FDEC45_OUT_FS (R/W) Decimator Channel 4/Channel 5 Output Sam pling Rate 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. [2:0] FDEC45_IN_FS (R/W) Decim ator Channel 4/Channel 5 Input Sam pling Rate 001: 24 kHz Sample Rate. 010: 48 kHz Sample Rate. 011: 96 kHz Sample Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. 110: 768 kHz Sam ple Rate. [3] RESERVED Table 107. Bit Descriptions for FDEC_CTRL3 Bits 7 [6:4] Bit Name RESERVED FDEC45_OUT_FS Settings 000 001 010 011 100 101 3 [2:0] RESERVED FDEC45_IN_FS 001 010 011 100 101 110 Description Reserved. Decimator Channel 4/Channel 5 Output Sampling Rate. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. Reserved. Decimator Channel 4/Channel 5 Input Sampling Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Rev. A | Page 119 of 280 Reset 0x0 0x2 Access R R/W 0x0 0x5 R R/W ADAU1787 Data Sheet FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER Address: 0xC044, Reset: 0x25, Name: FDEC_CTRL4 7 6 5 4 3 2 1 0 0 0 1 0 0 1 0 1 [7] RESERVED [6:4] FDEC67_OUT_FS (R/W) Decimator Channel 6/Channel 7 Output Sam pling Rate 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. [2:0] FDEC67_IN_FS (R/W) Decim ator Channel 6/Channel 7 Input Sam pling Rate 001: 24 kHz Sample Rate. 010: 48 kHz Sample Rate. 011: 96 kHz Sample Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. 110: 768 kHz Sam ple Rate. [3] RESERVED Table 108. Bit Descriptions for FDEC_CTRL4 Bits 7 [6:4] Bit Name RESERVED FDEC67_OUT_FS Settings 000 001 010 011 100 101 3 [2:0] RESERVED FDEC67_IN_FS 001 010 011 100 101 110 Description Reserved. Decimator Channel 6/Channel 7 Output Sampling Rate. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. Reserved. Decimator Channel 6/Channel 7 Input Sampling Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Rev. A | Page 120 of 280 Reset 0x0 0x2 Access R R/W 0x0 0x5 R R/W Data Sheet ADAU1787 FAST TO SLOW DECIMATOR CHANNEL 0 INPUT ROUTING REGISTER Address: 0xC045, Reset: 0x00, Name: FDEC_ROUTE0 [7:6] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [5:0] FDEC0_ROUTE (R/W) Fast to Slow Decimator Channel 0 Input Routing 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 101101: Digital Microphone Channel 5. 101110: Digital Microphone Channel 6. 101111: Digital Microphone Channel 7. Table 109. Bit Descriptions for FDEC_ROUTE0 Bits [7:6] [5:0] Bit Name RESERVED FDEC0_ROUTE Settings 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Description Reserved. Fast to Slow Decimator Channel 0 Input Routing. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. Rev. A | Page 121 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 36 37 38 39 40 41 42 43 44 45 46 47 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Reset Access Reset 0x0 0x0 Access R R/W FAST TO SLOW DECIMATOR CHANNEL 1 INPUT ROUTING REGISTER Address: 0xC046, Reset: 0x00, Name: FDEC_ROUTE1 [7:6] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [5:0] FDEC1_ROUTE (R/W) Fas t to Slow Decimator Channel 1 Input Routing 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 101101: Digital Microphone Channel 5. 101110: Digital Microphone Channel 6. 101111: Digital Microphone Channel 7. Table 110. Bit Descriptions for FDEC_ROUTE1 Bits [7:6] [5:0] Bit Name RESERVED FDEC1_ROUTE Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Description Reserved. Fast to Slow Decimator Channel 1 Input Routing. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. Rev. A | Page 122 of 280 Data Sheet Bits Bit Name ADAU1787 Settings 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Description SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Rev. A | Page 123 of 280 Reset Access ADAU1787 Data Sheet FAST TO SLOW DECIMATOR CHANNEL 2 INPUT ROUTING REGISTER Address: 0xC047, Reset: 0x00, Name: FDEC_ROUTE2 [7:6] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [5:0] FDEC2_ROUTE (R/W) Fas t to Slow Decimator Channel 2 Input Routing 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 101101: Digital Microphone Channel 5. 101110: Digital Microphone Channel 6. 101111: Digital Microphone Channel 7. Table 111. Bit Descriptions for FDEC_ROUTE2 Bits [7:6] [5:0] Bit Name RESERVED FDEC2_ROUTE Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Fast to Slow Decimator Channel 2 Input Routing. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. Rev. A | Page 124 of 280 Reset 0x0 0x0 Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Reset Access Reset 0x0 0x0 Access R R/W FAST TO SLOW DECIMATOR CHANNEL 3 INPUT ROUTING REGISTER Address: 0xC048, Reset: 0x00, Name: FDEC_ROUTE3 [7:6] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [5:0] FDEC3_ROUTE (R/W) Fas t to Slow Decimator Channel 3 Input Routing 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 101101: Digital Microphone Channel 5. 101110: Digital Microphone Channel 6. 101111: Digital Microphone Channel 7. Table 112. Bit Descriptions for FDEC_ROUTE3 Bits [7:6] [5:0] Bit Name RESERVED FDEC3_ROUTE Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Description Reserved. Fast to Slow Decimator Channel 3 Input Routing. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. Rev. A | Page 125 of 280 ADAU1787 Bits Bit Name Data Sheet Settings 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Description SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Rev. A | Page 126 of 280 Reset Access Data Sheet ADAU1787 FAST TO SLOW DECIMATOR CHANNEL 4 INPUT ROUTING REGISTER Address: 0xC049, Reset: 0x00, Name: FDEC_ROUTE4 [7:6] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [5:0] FDEC4_ROUTE (R/W) Fas t to Slow Decimator Channel 4 Input Routing 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 101101: Digital Microphone Channel 5. 101110: Digital Microphone Channel 6. 101111: Digital Microphone Channel 7. Table 113. Bit Descriptions for FDEC_ROUTE4 Bits [7:6] [5:0] Bit Name RESERVED FDEC4_ROUTE Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Fast to Slow Decimator Channel 4 Input Routing. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. Rev. A | Page 127 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Reset Access Reset 0x0 0x0 Access R R/W FAST TO SLOW DECIMATOR CHANNEL 5 INPUT ROUTING REGISTER Address: 0xC04A, Reset: 0x00, Name: FDEC_ROUTE5 [7:6] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [5:0] FDEC5_ROUTE (R/W) Fas t to Slow Decimator Channel 5 Input Routing 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 101101: Digital Microphone Channel 5. 101110: Digital Microphone Channel 6. 101111: Digital Microphone Channel 7. Table 114. Bit Descriptions for FDEC_ROUTE5 Bits [7:6] [5:0] Bit Name RESERVED FDEC5_ROUTE Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Description Reserved. Fast to Slow Decimator Channel 5 Input Routing. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. Rev. A | Page 128 of 280 Data Sheet Bits Bit Name ADAU1787 Settings 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Description SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Rev. A | Page 129 of 280 Reset Access ADAU1787 Data Sheet FAST TO SLOW DECIMATOR CHANNEL 6 INPUT ROUTING REGISTER Address: 0xC04B, Reset: 0x00, Name: FDEC_ROUTE6 [7:6] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [5:0] FDEC6_ROUTE (R/W) Fas t to Slow Decimator Channel 6 Input Routing 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 101101: Digital Microphone Channel 5. 101110: Digital Microphone Channel 6. 101111: Digital Microphone Channel 7. Table 115. Bit Descriptions for FDEC_ROUTE6 Bits [7:6] [5:0] Bit Name RESERVED FDEC6_ROUTE Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Fast to Slow Decimator Channel 6 Input Routing. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. Rev. A | Page 130 of 280 Reset 0x0 0x0 Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Reset Access Reset 0x0 0x0 Access R R/W FAST TO SLOW DECIMATOR CHANNEL 7 INPUT ROUTING REGISTER Address: 0xC04C, Reset: 0x00, Name: FDEC_ROUTE7 [7:6] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [5:0] FDEC7_ROUTE (R/W) Fas t to Slow Decimator Channel 7 Input Routing 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 101101: Digital Microphone Channel 5. 101110: Digital Microphone Channel 6. 101111: Digital Microphone Channel 7. Table 116. Bit Descriptions for FDEC_ROUTE7 Bits [7:6] [5:0] Bit Name RESERVED FDEC7_ROUTE Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Description Reserved. Fast to Slow Decimator Channel 7 Input Routing FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. Rev. A | Page 131 of 280 ADAU1787 Bits Bit Name Data Sheet Settings 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 Description SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Rev. A | Page 132 of 280 Reset Access Data Sheet ADAU1787 SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER Address: 0xC04D, Reset: 0x52, Name: FINT_CTRL1 7 6 5 4 3 2 1 0 0 1 0 1 0 0 1 0 [7] RESERVED [6:4] FINT01_OUT_FS (R/W) Interpolator Channel 0/Channel 1 Output Sam pling Rate 001: 24 kHz Sample Rate. 010: 48 kHz Sample Rate. 011: 96 kHz Sample Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. 110: 768 kHz Sam ple Rate. [2:0] FINT01_IN_FS (R/W) Interpolator Channel 0/Channel 1 Input Sam pling Rate 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sample Rate. 101: 384 kHz Sample Rate. [3] RESERVED Table 117. Bit Descriptions for FINT_CTRL1 Bits 7 [6:4] Bit Name RESERVED FINT01_OUT_FS Settings 001 010 011 100 101 110 3 [2:0] RESERVED FINT01_IN_FS 000 001 010 011 100 101 Description Reserved. Interpolator Channel 0/Channel 1 Output Sampling Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Reserved. Interpolator Channel 0/Channel 1 Input Sampling Rate. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. Rev. A | Page 133 of 280 Reset 0x0 0x5 Access R R/W 0x0 0x2 R R/W ADAU1787 Data Sheet SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER Address: 0xC04E, Reset: 0x52, Name: FINT_CTRL2 7 6 5 4 3 2 1 0 0 1 0 1 0 0 1 0 [7] RESERVED [6:4] FINT23_OUT_FS (R/W) Interpolator Channel 2/Channel 3 Output Sam pling Rate 001: 24 kHz Sample Rate. 010: 48 kHz Sample Rate. 011: 96 kHz Sample Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. 110: 768 kHz Sam ple Rate. [2:0] FINT23_IN_FS (R/W) Interpolator Channel 2/Channel 3 Input Sam pling Rate 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sample Rate. 101: 384 kHz Sample Rate. [3] RESERVED Table 118. Bit Descriptions for FINT_CTRL2 Bits 7 [6:4] Bit Name RESERVED FINT23_OUT_FS Settings 001 010 011 100 101 110 3 [2:0] RESERVED FINT23_IN_FS 000 001 010 011 100 101 Description Reserved. Interpolator Channel 2/Channel 3 Output Sampling Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Reserved. Interpolator Channel 2/Channel 3 Input Sampling Rate. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. Rev. A | Page 134 of 280 Reset 0x0 0x5 Access R R/W 0x0 0x2 R R/W Data Sheet ADAU1787 SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER Address: 0xC04F, Reset: 0x52, Name: FINT_CTRL3 7 6 5 4 3 2 1 0 0 1 0 1 0 0 1 0 [7] RESERVED [6:4] FINT45_OUT_FS (R/W) Interpolator Channel 4/Channel 5 Output Sam pling Rate 001: 24 kHz Sample Rate. 010: 48 kHz Sample Rate. 011: 96 kHz Sample Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. 110: 768 kHz Sam ple Rate. [2:0] FINT45_IN_FS (R/W) Interpolator Channel 4/Channel 5 Input Sam pling Rate 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sample Rate. 101: 384 kHz Sample Rate. [3] RESERVED Table 119. Bit Descriptions for FINT_CTRL3 Bits 7 [6:4] Bit Name RESERVED FINT45_OUT_FS Settings 001 010 011 100 101 110 3 [2:0] RESERVED FINT45_IN_FS 000 001 010 011 100 101 Description Reserved. Interpolator Channel 4/Channel 5 Output Sampling Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Reserved. Interpolator Channel 4/Channel 5 Input Sampling Rate. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. Rev. A | Page 135 of 280 Reset 0x0 0x5 Access R R/W 0x0 0x2 R R/W ADAU1787 Data Sheet SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER Address: 0xC050, Reset: 0x52, Name: FINT_CTRL4 7 6 5 4 3 2 1 0 0 1 0 1 0 0 1 0 [7] RESERVED [6:4] FINT67_OUT_FS (R/W) Interpolator Channel 6/Channel 7 Output Sam pling Rate 001: 24 kHz Sample Rate. 010: 48 kHz Sample Rate. 011: 96 kHz Sample Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. 110: 768 kHz Sam ple Rate. [2:0] FINT67_IN_FS (R/W) Interpolator Channel 6/Channel 7 Input Sam pling Rate 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sample Rate. 101: 384 kHz Sample Rate. [3] RESERVED Table 120. Bit Descriptions for FINT_CTRL4 Bits 7 [6:4] Bit Name RESERVED FINT67_OUT_FS Settings 001 010 011 100 101 110 3 [2:0] RESERVED FINT67_IN_FS 000 001 010 011 100 101 Description Reserved. Interpolator Channel 6/Channel 7 Output Sampling Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Reserved. Interpolator Channel 6/Channel 7 Input Sampling Rate. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. Rev. A | Page 136 of 280 Reset 0x0 0x5 Access R R/W 0x0 0x2 R R/W Data Sheet ADAU1787 SLOW TO FAST INTERPOLATOR CHANNEL 0 INPUT ROUTING REGISTER Address: 0xC051, Reset: 0x00, Name: FINT_ROUTE0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [6:0] FINT0_ROUTE (R/W) Slow to Fas t Interpolator Channel 0 Input Routing 0000000: Serial Port 0 Channel 0. 0000001: Serial Port 0 Channel 1. 0000010: Serial Port 0 Channel 2. ... 1001101: Digital Microphone Channel 5. 1001110: Digital Microphone Channel 6. 1001111: Digital Microphone Channel 7. Table 121. Bit Descriptions for FINT_ROUTE0 Bits 7 [6:0] Bit Name RESERVED FINT0_ROUTE Settings 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Description Reserved. Slow to Fast Interpolator Channel 0 Input Routing. Serial Port 0 Channel 0. Serial Port 0 Channel 1. Serial Port 0 Channel 2. Serial Port 0 Channel 3. Serial Port 0 Channel 4. Serial Port 0 Channel 5. Serial Port 0 Channel 6. Serial Port 0 Channel 7. Serial Port 0 Channel 8. Serial Port 0 Channel 9. Serial Port 0 Channel 10. Serial Port 0 Channel 11. Serial Port 0 Channel 12. Serial Port 0 Channel 13. Serial Port 0 Channel 14. Serial Port 0 Channel 15. Serial Port 1 Channel 0. Serial Port 1 Channel 1. Serial Port 1 Channel 2. Serial Port 1 Channel 3. Serial Port 1 Channel 4. Serial Port 1 Channel 5. Serial Port 1 Channel 6. Serial Port 1 Channel 7. Serial Port 1 Channel 8. Serial Port 1 Channel 9. Serial Port 1 Channel 10. Serial Port 1 Channel 11. Serial Port 1 Channel 12. Serial Port 1 Channel 13. Serial Port 1 Channel 14. Serial Port 1 Channel 15. Rev. A | Page 137 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Description FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Rev. A | Page 138 of 280 Reset Access Data Sheet ADAU1787 SLOW TO FAST INTERPOLATOR CHANNEL 1 INPUT ROUTING REGISTER Address: 0xC052, Reset: 0x00, Name: FINT_ROUTE1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [6:0] FINT1_ROUTE (R/W) Slow to Fas t Interpolator Channel 1 Input Routing 0000000: Serial Port 0 Channel 0. 0000001: Serial Port 0 Channel 1. 0000010: Serial Port 0 Channel 2. ... 1001101: Digital Microphone Channel 5. 1001110: Digital Microphone Channel 6. 1001111: Digital Microphone Channel 7. Table 122. Bit Descriptions for FINT_ROUTE1 Bits 7 [6:0] Bit Name RESERVED FINT1_ROUTE Settings 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Description Reserved. Slow to Fast Interpolator Channel 1 Input Routing. Serial Port 0 Channel 0. Serial Port 0 Channel 1. Serial Port 0 Channel 2. Serial Port 0 Channel 3. Serial Port 0 Channel 4. Serial Port 0 Channel 5. Serial Port 0 Channel 6. Serial Port 0 Channel 7. Serial Port 0 Channel 8. Serial Port 0 Channel 9. Serial Port 0 Channel 10. Serial Port 0 Channel 11. Serial Port 0 Channel 12. Serial Port 0 Channel 13. Serial Port 0 Channel 14. Serial Port 0 Channel 15. Serial Port 1 Channel 0. Serial Port 1 Channel 1. Serial Port 1 Channel 2. Serial Port 1 Channel 3. Serial Port 1 Channel 4. Serial Port 1 Channel 5. Serial Port 1 Channel 6. Serial Port 1 Channel 7. Serial Port 1 Channel 8. Serial Port 1 Channel 9. Serial Port 1 Channel 10. Serial Port 1 Channel 11. Serial Port 1 Channel 12. Serial Port 1 Channel 13. Serial Port 1 Channel 14. Serial Port 1 Channel 15. Rev. A | Page 139 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Description FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Rev. A | Page 140 of 280 Reset Access Data Sheet ADAU1787 SLOW TO FAST INTERPOLATOR CHANNEL 2 INPUT ROUTING REGISTER Address: 0xC053, Reset: 0x00, Name: FINT_ROUTE2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [6:0] FINT2_ROUTE (R/W) Slow to Fas t Interpolator Channel 2 Input Routing 0000000: Serial Port 0 Channel 0. 0000001: Serial Port 0 Channel 1. 0000010: Serial Port 0 Channel 2. ... 1001101: Digital Microphone Channel 5. 1001110: Digital Microphone Channel 6. 1001111: Digital Microphone Channel 7. Table 123. Bit Descriptions for FINT_ROUTE2 Bits 7 [6:0] Bit Name RESERVED FINT2_ROUTE Settings 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Description Reserved. Slow to Fast Interpolator Channel 2 Input Routing. Serial Port 0 Channel 0. Serial Port 0 Channel 1. Serial Port 0 Channel 2. Serial Port 0 Channel 3. Serial Port 0 Channel 4. Serial Port 0 Channel 5. Serial Port 0 Channel 6. Serial Port 0 Channel 7. Serial Port 0 Channel 8. Serial Port 0 Channel 9. Serial Port 0 Channel 10. Serial Port 0 Channel 11. Serial Port 0 Channel 12. Serial Port 0 Channel 13. Serial Port 0 Channel 14. Serial Port 0 Channel 15. Serial Port 1 Channel 0. Serial Port 1 Channel 1. Serial Port 1 Channel 2. Serial Port 1 Channel 3. Serial Port 1 Channel 4. Serial Port 1 Channel 5. Serial Port 1 Channel 6. Serial Port 1 Channel 7. Serial Port 1 Channel 8. Serial Port 1 Channel 9. Serial Port 1 Channel 10. Serial Port 1 Channel 11. Serial Port 1 Channel 12. Serial Port 1 Channel 13. Serial Port 1 Channel 14. Serial Port 1 Channel 15. Rev. A | Page 141 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Description FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Rev. A | Page 142 of 280 Reset Access Data Sheet ADAU1787 SLOW TO FAST INTERPOLATOR CHANNEL 3 INPUT ROUTING REGISTER Address: 0xC054, Reset: 0x00, Name: FINT_ROUTE3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [6:0] FINT3_ROUTE (R/W) Slow to Fas t Interpolator Channel 3 Input Routing 0000000: Serial Port 0 Channel 0. 0000001: Serial Port 0 Channel 1. 0000010: Serial Port 0 Channel 2. ... 1001101: Digital Microphone Channel 5. 1001110: Digital Microphone Channel 6. 1001111: Digital Microphone Channel 7. Table 124. Bit Descriptions for FINT_ROUTE3 Bits 7 [6:0] Bit Name RESERVED FINT3_ROUTE Settings 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Description Reserved. Slow to Fast Interpolator Channel 3 Input Routing. Serial Port 0 Channel 0. Serial Port 0 Channel 1. Serial Port 0 Channel 2. Serial Port 0 Channel 3. Serial Port 0 Channel 4. Serial Port 0 Channel 5. Serial Port 0 Channel 6. Serial Port 0 Channel 7. Serial Port 0 Channel 8. Serial Port 0 Channel 9. Serial Port 0 Channel 10. Serial Port 0 Channel 11. Serial Port 0 Channel 12. Serial Port 0 Channel 13. Serial Port 0 Channel 14. Serial Port 0 Channel 15. Serial Port 1 Channel 0. Serial Port 1 Channel 1. Serial Port 1 Channel 2. Serial Port 1 Channel 3. Serial Port 1 Channel 4. Serial Port 1 Channel 5. Serial Port 1 Channel 6. Serial Port 1 Channel 7. Serial Port 1 Channel 8. Serial Port 1 Channel 9. Serial Port 1 Channel 10. Serial Port 1 Channel 11. Serial Port 1 Channel 12. Serial Port 1 Channel 13. Serial Port 1 Channel 14. Serial Port 1 Channel 15. Rev. A | Page 143 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Description FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Rev. A | Page 144 of 280 Reset Access Data Sheet ADAU1787 SLOW TO FAST INTERPOLATOR CHANNEL 4 INPUT ROUTING REGISTER Address: 0xC055, Reset: 0x00, Name: FINT_ROUTE4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [6:0] FINT4_ROUTE (R/W) Slow to Fas t Interpolator Channel 4 Input Routing 0000000: Serial Port 0 Channel 0. 0000001: Serial Port 0 Channel 1. 0000010: Serial Port 0 Channel 2. ... 1001101: Digital Microphone Channel 5. 1001110: Digital Microphone Channel 6. 1001111: Digital Microphone Channel 7. Table 125. Bit Descriptions for FINT_ROUTE4 Bits 7 [6:0] Bit Name RESERVED FINT4_ROUTE Settings 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Description Reserved. Slow to Fast Interpolator Channel 4 Input Routing Serial Port 0 Channel 0. Serial Port 0 Channel 1. Serial Port 0 Channel 2. Serial Port 0 Channel 3. Serial Port 0 Channel 4. Serial Port 0 Channel 5. Serial Port 0 Channel 6. Serial Port 0 Channel 7. Serial Port 0 Channel 8. Serial Port 0 Channel 9. Serial Port 0 Channel 10. Serial Port 0 Channel 11. Serial Port 0 Channel 12. Serial Port 0 Channel 13. Serial Port 0 Channel 14. Serial Port 0 Channel 15. Serial Port 1 Channel 0. Serial Port 1 Channel 1. Serial Port 1 Channel 2. Serial Port 1 Channel 3. Serial Port 1 Channel 4. Serial Port 1 Channel 5. Serial Port 1 Channel 6. Serial Port 1 Channel 7. Serial Port 1 Channel 8. Serial Port 1 Channel 9. Serial Port 1 Channel 10. Serial Port 1 Channel 11. Serial Port 1 Channel 12. Serial Port 1 Channel 13. Serial Port 1 Channel 14. Serial Port 1 Channel 15. Rev. A | Page 145 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Description FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Rev. A | Page 146 of 280 Reset Access Data Sheet ADAU1787 SLOW TO FAST INTERPOLATOR CHANNEL 5 INPUT ROUTING REGISTER Address: 0xC056, Reset: 0x00, Name: FINT_ROUTE5 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [6:0] FINT5_ROUTE (R/W) Slow to Fas t Interpolator Channel 5 Input Routing 0000000: Serial Port 0 Channel 0. 0000001: Serial Port 0 Channel 1. 0000010: Serial Port 0 Channel 2. ... 1001101: Digital Microphone Channel 5. 1001110: Digital Microphone Channel 6. 1001111: Digital Microphone Channel 7. Table 126. Bit Descriptions for FINT_ROUTE5 Bits 7 [6:0] Bit Name RESERVED FINT5_ROUTE Settings 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Description Reserved. Slow to Fast Interpolator Channel 5 Input Routing. Serial Port 0 Channel 0. Serial Port 0 Channel 1. Serial Port 0 Channel 2. Serial Port 0 Channel 3. Serial Port 0 Channel 4. Serial Port 0 Channel 5. Serial Port 0 Channel 6. Serial Port 0 Channel 7. Serial Port 0 Channel 8. Serial Port 0 Channel 9. Serial Port 0 Channel 10. Serial Port 0 Channel 11. Serial Port 0 Channel 12. Serial Port 0 Channel 13. Serial Port 0 Channel 14. Serial Port 0 Channel 15. Serial Port 1 Channel 0. Serial Port 1 Channel 1. Serial Port 1 Channel 2. Serial Port 1 Channel 3. Serial Port 1 Channel 4. Serial Port 1 Channel 5. Serial Port 1 Channel 6. Serial Port 1 Channel 7. Serial Port 1 Channel 8. Serial Port 1 Channel 9. Serial Port 1 Channel 10. Serial Port 1 Channel 11. Serial Port 1 Channel 12. Serial Port 1 Channel 13. Serial Port 1 Channel 14. Serial Port 1 Channel 15. Rev. A | Page 147 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Description FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Rev. A | Page 148 of 280 Reset Access Data Sheet ADAU1787 SLOW TO FAST INTERPOLATOR CHANNEL 6 INPUT ROUTING REGISTER Address: 0xC057, Reset: 0x00, Name: FINT_ROUTE6 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [6:0] FINT6_ROUTE (R/W) Slow to Fas t Interpolator Channel 6 Input Routing 0000000: Serial Port 0 Channel 0. 0000001: Serial Port 0 Channel 1. 0000010: Serial Port 0 Channel 2. ... 1001101: Digital Microphone Channel 5. 1001110: Digital Microphone Channel 6. 1001111: Digital Microphone Channel 7. Table 127. Bit Descriptions for FINT_ROUTE6 Bits 7 [6:0] Bit Name RESERVED FINT6_ROUTE Settings 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Description Reserved. Slow to Fast Interpolator Channel 6 Input Routing. Serial Port 0 Channel 0. Serial Port 0 Channel 1. Serial Port 0 Channel 2. Serial Port 0 Channel 3. Serial Port 0 Channel 4. Serial Port 0 Channel 5. Serial Port 0 Channel 6. Serial Port 0 Channel 7. Serial Port 0 Channel 8. Serial Port 0 Channel 9. Serial Port 0 Channel 10. Serial Port 0 Channel 11. Serial Port 0 Channel 12. Serial Port 0 Channel 13. Serial Port 0 Channel 14. Serial Port 0 Channel 15. Serial Port 1 Channel 0. Serial Port 1 Channel 1. Serial Port 1 Channel 2. Serial Port 1 Channel 3. Serial Port 1 Channel 4. Serial Port 1 Channel 5. Serial Port 1 Channel 6. Serial Port 1 Channel 7. Serial Port 1 Channel 8. Serial Port 1 Channel 9. Serial Port 1 Channel 10. Serial Port 1 Channel 11. Serial Port 1 Channel 12. Serial Port 1 Channel 13. Serial Port 1 Channel 14. Serial Port 1 Channel 15. Rev. A | Page 149 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Description FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Rev. A | Page 150 of 280 Reset Access Data Sheet ADAU1787 SLOW TO FAST INTERPOLATOR CHANNEL 7 INPUT ROUTING REGISTER Address: 0xC058, Reset: 0x00, Name: FINT_ROUTE7 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [6:0] FINT7_ROUTE (R/W) Slow to Fas t Interpolator Channel 7 Input Routing 0000000: Serial Port 0 Channel 0. 0000001: Serial Port 0 Channel 1. 0000010: Serial Port 0 Channel 2. ... 1001101: Digital Microphone Channel 5. 1001110: Digital Microphone Channel 6. 1001111: Digital Microphone Channel 7. Table 128. Bit Descriptions for FINT_ROUTE7 Bits 7 [6:0] Bit Name RESERVED FINT7_ROUTE Settings 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Description Reserved. Slow to Fast Interpolator Channel 7 Input Routing. Serial Port 0 Channel 0. Serial Port 0 Channel 1. Serial Port 0 Channel 2. Serial Port 0 Channel 3. Serial Port 0 Channel 4. Serial Port 0 Channel 5. Serial Port 0 Channel 6. Serial Port 0 Channel 7. Serial Port 0 Channel 8. Serial Port 0 Channel 9. Serial Port 0 Channel 10. Serial Port 0 Channel 11. Serial Port 0 Channel 12. Serial Port 0 Channel 13. Serial Port 0 Channel 14. Serial Port 0 Channel 15. Serial Port 1 Channel 0. Serial Port 1 Channel 1. Serial Port 1 Channel 2. Serial Port 1 Channel 3. Serial Port 1 Channel 4. Serial Port 1 Channel 5. Serial Port 1 Channel 6. Serial Port 1 Channel 7. Serial Port 1 Channel 8. Serial Port 1 Channel 9. Serial Port 1 Channel 10. Serial Port 1 Channel 11. Serial Port 1 Channel 12. Serial Port 1 Channel 13. Serial Port 1 Channel 14. Serial Port 1 Channel 15. Rev. A | Page 151 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Description FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Rev. A | Page 152 of 280 Reset Access Data Sheet ADAU1787 INPUT ASRC CONTROL, SOURCE, AND RATE SELECTION REGISTER Address: 0xC059, Reset: 0x02, Name: ASRCI_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 [7] ASRCI_MORE_FILT (R/W) Input ASRC Additional Filtering Enable 0: No Additional Voice Band Filter. 1: Voice Band Filter On. [2:0] ASRCI_OUT_FS (R/W) Input ASRC Sample Rate Selection 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sam ple Rate. [6] ASRCI_VFILT (R/W) Input ASRC Voice Filter Enable 0: Voice Filter Off. 1: Voice Filter On. [5] ASRCI_LPM (R/W) Input ASRC Low Power Mode Selection 0: High Performance Mode. 1: Low Power Mode. [3] ASRCI_LPM_II (R/W) Input ASRC Low Power Mode Selection. Even lower power. 0: High Performance Mode. 1: Low Power Mode. [4] ASRCI_SOURCE (R/W) Input ASRC Source 0: Serial Audio Port 0 source for Input ASRC. 1: Serial Audio Port 1 source for Input ASRC. Table 129. Bit Descriptions for ASRCI_CTRL Bits 7 Bit Name ASRCI_MORE_FILT Settings 0 1 6 ASRCI_VFILT 0 1 5 ASRCI_LPM 0 1 4 ASRCI_SOURCE 0 1 3 ASRCI_LPM_II 0 1 [2:0] ASRCI_OUT_FS 000 001 010 011 100 Description Input ASRC Additional Filtering Enable. This bit can enable additional filtering within the ASRC that can provide higher performance under some conditions. No Additional Voice Band Filter. Voice Band Filter On. Input ASRC Voice Filter Enable. Voice Filter Off. Voice Filter On. Input ASRC Low Power Mode Selection. High Performance Mode. Low Power Mode. Input ASRC Source. Serial Audio Port 0 Source for Input ASRC. Serial Audio Port 1 Source for Input ASRC. Input ASRC Low Power Mode Selection. Even lower power. High Performance Mode. Low Power Mode. Input ASRC Sample Rate Selection. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. Rev. A | Page 153 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x2 R/W ADAU1787 Data Sheet INPUT ASRC CHANNEL 0 AND CHANNEL 1 INPUT ROUTING REGISTER Address: 0xC05A, Reset: 0x00, Name: ASRCI_ROUTE01 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] ASRCI1_ROUTE (R/W) Input ASRC Channel 1 Routing 0000: Serial Port Channel 0. 0001: Serial Port Channel 1. 0010: Serial Port Channel 2. ... 1101: Serial Port Channel 13. 1110: Serial Port Channel 14. 1111: Serial Port Channel 15. [3:0] ASRCI0_ROUTE (R/W) Input ASRC Channel 0 Routing 0000: Serial Port Channel 0. 0001: Serial Port Channel 1. 0010: Serial Port Channel 2. ... 1101: Serial Port Channel 13. 1110: Serial Port Channel 14. 1111: Serial Port Channel 15. Table 130. Bit Descriptions for ASRCI_ROUTE01 Bits [7:4] Bit Name ASRCI1_ROUTE Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] ASRCI0_ROUTE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Input ASRC Channel 1 Routing. Serial Port Channel 0. Serial Port Channel 1. Serial Port Channel 2. Serial Port Channel 3. Serial Port Channel 4. Serial Port Channel 5. Serial Port Channel 6. Serial Port Channel 7. Serial Port Channel 8. Serial Port Channel 9. Serial Port Channel 10. Serial Port Channel 11. Serial Port Channel 12. Serial Port Channel 13. Serial Port Channel 14. Serial Port Channel 15. Input ASRC Channel 0 Routing. Serial Port Channel 0. Serial Port Channel 1. Serial Port Channel 2. Serial Port Channel 3. Serial Port Channel 4. Serial Port Channel 5. Serial Port Channel 6. Serial Port Channel 7. Serial Port Channel 8. Serial Port Channel 9. Serial Port Channel 10. Serial Port Channel 11. Serial Port Channel 12. Serial Port Channel 13. Serial Port Channel 14. Serial Port Channel 15. Rev. A | Page 154 of 280 Reset 0x0 Access R/W 0x0 R/W Data Sheet ADAU1787 INPUT ASRC CHANNEL 2 AND CHANNEL 3 INPUT ROUTING REGISTER Address: 0xC05B, Reset: 0x00, Name: ASRCI_ROUTE23 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] ASRCI3_ROUTE (R/W) Input ASRC Channel 3 Routing 0000: Serial Port Channel 0. 0001: Serial Port Channel 1. 0010: Serial Port Channel 2. ... 1101: Serial Port Channel 13. 1110: Serial Port Channel 14. 1111: Serial Port Channel 15. [3:0] ASRCI2_ROUTE (R/W) Input ASRC Channel 2 Routing 0000: Serial Port Channel 0. 0001: Serial Port Channel 1. 0010: Serial Port Channel 2. ... 1101: Serial Port Channel 13. 1110: Serial Port Channel 14. 1111: Serial Port Channel 15. Table 131. Bit Descriptions for ASRCI_ROUTE23 Bits [7:4] Bit Name ASRCI3_ROUTE Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:0] ASRCI2_ROUTE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Input ASRC Channel 3 Routing. Serial Port Channel 0. Serial Port Channel 1. Serial Port Channel 2. Serial Port Channel 3. Serial Port Channel 4. Serial Port Channel 5. Serial Port Channel 6. Serial Port Channel 7. Serial Port Channel 8. Serial Port Channel 9. Serial Port Channel 10. Serial Port Channel 11. Serial Port Channel 12. Serial Port Channel 13. Serial Port Channel 14. Serial Port Channel 15. Input ASRC Channel 2 Routing. Serial Port Channel 0. Serial Port Channel 1. Serial Port Channel 2. Serial Port Channel 3. Serial Port Channel 4. Serial Port Channel 5. Serial Port Channel 6. Serial Port Channel 7. Serial Port Channel 8. Serial Port Channel 9. Serial Port Channel 10. Serial Port Channel 11. Serial Port Channel 12. Serial Port Channel 13. Serial Port Channel 14. Serial Port Channel 15. Rev. A | Page 155 of 280 Reset 0x0 Access R/W 0x0 R/W ADAU1787 Data Sheet OUTPUT ASRC CONTROL REGISTER Address: 0xC05C, Reset: 0x02, Name: ASRCO_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 [7] ASRCO_MORE_FILT (R/W) Output ASRC Additional Filtering Enable 0: No Additional Voice Band Filter. 1: Voice Band Filter On. [2:0] ASRCO_IN_FS (R/W) Output ASRC Input Sam ple Rate Selection 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sample Rate. [6] ASRCO_VFILT (R/W) Output ASRC Voice Filter Enable 0: Voice Filter Off. 1: Voice Filter On. [5] ASRCO_LPM (R/W) Output ASRC Low Power Mode Selection 0: High Perform ance Mode. 1: Low Power Mode. [3] ASRCO_LPM_II (R/W) Output ASRC Low Power Mode Selection. Even lower power. 0: High Perform ance Mode. 1: Low Power Mode. [4] ASRCO_SAI_SEL (R/W) Output ASRC Serial Port External Rate Source Selection 0: Use Serial Port 0 as Rate Source. 1: Use Serial Port 1 as Rate Source. Table 132. Bit Descriptions for ASRCO_CTRL Bits 7 Bit Name ASRCO_MORE_FILT Settings 0 1 6 ASRCO_VFILT 0 1 5 ASRCO_LPM 0 1 4 ASRCO_SAI_SEL 0 1 3 ASRCO_LPM_II 0 1 [2:0] ASRCO_IN_FS 000 001 010 011 100 Description Output ASRC Additional Filtering Enable. This bit can enable additional filtering within the ASRC that can provide higher performance under some conditions. No Additional Voice Band Filter. Voice Band Filter On. Output ASRC Voice Filter Enable. Voice Filter Off. Voice Filter On. Output ASRC Low Power Mode Selection. High Performance Mode. Low Power Mode. Output ASRC Serial Port External Rate Source Selection. Use Serial Port 0 as Rate Source. Use Serial Port 1 as Rate Source. Output ASRC Low Power Mode Selection. Even lower power. High Performance Mode. Low Power Mode. Output ASRC Input Sample Rate Selection. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. Rev. A | Page 156 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x2 R/W Data Sheet ADAU1787 OUTPUT ASRC CHANNEL 0 INPUT ROUTING REGISTER Address: 0xC05D, Reset: 0x00, Name: ASRCO_ROUTE0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] ASRCO0_ROUTE (R/W) Output ASRC Channel 0 Input Routing 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110001: Fast to Slow Decimator Channel 5. 110010: Fast to Slow Decimator Channel 6. 110011: Fast to Slow Decimator Channel 7. Table 133. Bit Descriptions for ASRCO_ROUTE0 Bits [7:6] [5:0] Bit Name RESERVED ASRCO0_ROUTE Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Output ASRC Channel 0 Input Routing. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Rev. A | Page 157 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 Description Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. Reset Access Reset 0x0 0x0 Access R R/W OUTPUT ASRC CHANNEL 1 INPUT ROUTING REGISTER Address: 0xC05E, Reset: 0x00, Name: ASRCO_ROUTE1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] ASRCO1_ROUTE (R/W) Output ASRC Channel 1 Input Routing 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110001: Fast to Slow Decimator Channel 5. 110010: Fast to Slow Decimator Channel 6. 110011: Fast to Slow Decimator Channel 7. Table 134. Bit Descriptions for ASRCO_ROUTE1 Bits [7:6] [5:0] Bit Name RESERVED ASRCO1_ROUTE Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Description Reserved. Output ASRC Channel 1 Input Routing. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. Rev. A | Page 158 of 280 Data Sheet Bits Bit Name ADAU1787 Settings 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 Description SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. Rev. A | Page 159 of 280 Reset Access ADAU1787 Data Sheet OUTPUT ASRC CHANNEL 2 INPUT ROUTING REGISTER Address: 0xC05F, Reset: 0x00, Name: ASRCO_ROUTE2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] ASRCO2_ROUTE (R/W) Output ASRC Channel 2 Input Routing 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110001: Fast to Slow Decimator Channel 5. 110010: Fast to Slow Decimator Channel 6. 110011: Fast to Slow Decimator Channel 7. Table 135. Bit Descriptions for ASRCO_ROUTE2 Bits [7:6] [5:0] Bit Name RESERVED ASRCO2_ROUTE Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Output ASRC Channel 2 Input Routing FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Rev. A | Page 160 of 280 Reset 0x0 0x0 Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 Description Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. Reset Access Reset 0x0 0x0 Access R R/W OUTPUT ASRC CHANNEL 3 INPUT ROUTING REGISTER Address: 0xC060, Reset: 0x00, Name: ASRCO_ROUTE3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] ASRCO3_ROUTE (R/W) Output ASRC Channel 3 Input Routing 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110001: Fast to Slow Decimator Channel 5. 110010: Fast to Slow Decimator Channel 6. 110011: Fast to Slow Decimator Channel 7. Table 136. Bit Descriptions for ASRCO_ROUTE3 Bits [7:6] [5:0] Bit Name RESERVED ASRCO3_ROUTE Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Description Reserved. Output ASRC Channel 3 Input Routing FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. Rev. A | Page 161 of 280 ADAU1787 Bits Bit Name Data Sheet Settings 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 Description SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. Rev. A | Page 162 of 280 Reset Access Data Sheet ADAU1787 FastDSP RUN REGISTER Address: 0xC061, Reset: 0x00, Name: FDSP_RUN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:1] RESERVED [0] FDSP_RUN (R/W) Allows FastDSP to run with go signal. 0: FastDSP has no go signal. Not running but m em ories can be loaded if FDSP_EN = 1. 1: FastDSP has go signal and is running. Table 137. Bit Descriptions for FDSP_RUN Bits [7:1] 0 Bit Name RESERVED FDSP_RUN Settings 0 1 Description Reserved. Allows FastDSP to run with go signal. FastDSP has no go signal. Not running but memories can be loaded if FDSP_EN = 1. FastDSP has go signal and is running. Reset 0x0 0x0 Access R R/W Reset 0x7 Access R/W FastDSP CURRENT BANK AND BANK RAMPING CONTROLS REGISTER Address: 0xC062, Reset: 0x70, Name: FDSP_CTRL1 7 6 5 4 3 2 1 0 0 1 1 1 0 0 0 0 [7:4] FDSP_RAMP_RATE (R/W) FastDSP Param eter Bank Ramp Rate of Change. Determines time to com plete full ram p from one bank to another. 0000: 0.02 sec Ram p. 0001: 0.04 sec Ram p. 0010: 0.06 sec Ram p. ... 1101: 1.5 s ec Ram p. 1110: 1.75 sec Ram p. 1111: 2 sec Ramp. [1:0] FDSP_BANK_SEL (R/W) FastDSP Current Parameter Bank Selection 0: FastDSP uses Parameter Bank A. 1: FastDSP uses Parameter Bank B. 10: FastDSP uses Parameter Bank C. [3] FDSP_ZERO_STATE (R/W) Zeroes the state of the FastDSP data m emory during bank switching 0: Do not zero state during bank switch. 1: Zero state during back switch. [2] FDSP_RAMP_MODE (R/W) FastDSP Param eter Bank Ramp Mode 0: Parameters linearly ram p when current bank is changed. 1: Parameters ins tantly change when current bank is changed. Table 138. Bit Descriptions for FDSP_CTRL1 Bits [7:4] Bit Name FDSP_RAMP_RATE Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Description FastDSP Parameter Bank Ramp Rate of Change. Determines time to complete full ramp from one bank to another. 0.02 sec Ramp. 0.04 sec Ramp. 0.06 sec Ramp. 0.08 sec Ramp. 0.1 sec Ramp. 0.15 sec Ramp. 0.2 sec Ramp. 0.25 sec Ramp. 0.3 sec Ramp. 0.5 sec Ramp. 0.75 sec Ramp. 1 sec Ramp. 1.25 sec Ramp. Rev. A | Page 163 of 280 ADAU1787 Bits Bit Name 3 FDSP_ZERO_STATE Data Sheet Settings 1101 1110 1111 0 1 2 FDSP_RAMP_MODE 0 1 [1:0] FDSP_BANK_SEL 0 1 10 Description 1.5 sec Ramp. 1.75 sec Ramp. 2 sec Ramp. Zeroes the state of the FastDSP data memory during bank switching. When switching active parameter banks between two settings, zeroing the state of the bank prevents the new filter settings from being active on old data that is recirculating in filters. Zeroing the state may prevent filter instability or unwanted noises upon bank switching. Do not zero state during bank switch. Zero state during back switch. FastDSP Parameter Bank Ramp Mode. Parameters linearly ramp when current bank is changed. Parameters instantly change when current bank is changed. FastDSP Current Parameter Bank Selection. FastDSP uses Parameter Bank A. FastDSP uses Parameter Bank B. FastDSP uses Parameter Bank C. Reset Access 0x0 R/W 0x0 R/W 0x0 R/W Reset 0x0 0x3F Access R R/W FastDSP BANK RAMPING STOP POINT REGISTER Address: 0xC063, Reset: 0x3F, Name: FDSP_CTRL2 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] FDSP_LAMBDA (R/W) FastDSP Bank Switch Ramp Stop Point 000000: Bank switch param eter ram p stops at 1/64 of full ram p. 000001: Bank switch param eter ram p stops at 2/64 of full ram p. 000010-111101: ... 111110: Bank switch param eter ram p stops at 63/64 of full ramp. 111111: Bank switch param eter ram p com pletes ramp to current bank. Table 139. Bit Descriptions for FDSP_CTRL2 Bits [7:6] [5:0] Bit Name RESERVED FDSP_LAMBDA Settings 000000 000001 000010 to 111101 111110 111111 Description Reserved. FastDSP Bank Switch Ramp Stop Point. Lambda is a 6-bit value representing the point along the linear interpolation curve between two banks at which the bank ramp switch stops. 0 = ((63/64) × A + (1/64) × B), 1 = ((62/64) × A + (2/64) × B), … , 62 = ((1/64) × A + (63/64) × B), and 63 = B (default) lambda can be updated on-the-fly via the control interface. To complete a bank switch, a value of 63 (default setting) must be set. Actual current ramp point (FDSP_CURRENT_LAMBDA: 0 to 63) can be read via a status register. When this point reaches 63, the bank switch is complete, and the current parameters used match the current bank. The actual step size of the linear interpolation is ~12 bits (4096 steps). Parameters in banks that are being ramped between must not change during a bank switch. Bank switch parameter ramp stops at 1/64 of full ramp. Bank switch parameter ramp stops at 2/64 of full ramp. … Bank switch parameter ramp stops at 63/64 of full ramp. Bank switch parameter ramp completes ramp to current bank. Rev. A | Page 164 of 280 Data Sheet ADAU1787 FastDSP BANK COPYING REGISTER Address: 0xC064, Reset: 0x00, Name: FDSP_CTRL3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5] FDSP_COPY_CB (W) FastDSP Copy Parameter Bank C to Bank B 0: Norm al Operation. 1: Writing of 1 copies bank. [4] FDSP_COPY_CA (W) FastDSP Copy Parameter Bank C to Bank A 0: Norm al Operation. 1: Writing of 1 copies bank. [3] FDSP_COPY_BC (W) FastDSP Copy Parameter Bank B to Bank C 0: Norm al Operation. 1: Writing of 1 copies bank. [0] FDSP_COPY_AB (W) FastDSP Copy Param eter Bank A to Bank B 0: Norm al Operation. 1: Writing of 1 copies bank. [1] FDSP_COPY_AC (W) FastDSP Copy Param eter Bank A to Bank C 0: Norm al Operation. 1: Writing of 1 copies bank. [2] FDSP_COPY_BA (W) FastDSP Copy Param eter Bank B to Bank A 0: Norm al Operation. 1: Writing of 1 copies bank. Table 140. Bit Descriptions for FDSP_CTRL3 Bits [7:6] 5 Bit Name RESERVED FDSP_COPY_CB Settings 0 1 4 FDSP_COPY_CA 0 1 3 FDSP_COPY_BC 0 1 2 FDSP_COPY_BA 0 1 1 FDSP_COPY_AC 0 1 0 FDSP_COPY_AB 0 1 Description Reserved. FastDSP Copy Parameter Bank C to Bank B. Normal Operation. Writing of 1 copies bank. FastDSP Copy Parameter Bank C to Bank A. Normal Operation. Writing of 1 copies bank. FastDSP Copy Parameter Bank B to Bank C. Normal Operation. Writing of 1 copies bank. FastDSP Copy Parameter Bank B to Bank A Normal Operation. Writing of 1 copies bank. FastDSP Copy Parameter Bank A to Bank C. Normal Operation. Writing of 1 copies bank. FastDSP Copy Parameter Bank A to Bank B. Normal Operation. Writing of 1 copies bank. Rev. A | Page 165 of 280 Reset 0x0 0x0 Access R W 0x0 W 0x0 W 0x0 W 0x0 W 0x0 W ADAU1787 Data Sheet FastDSP FRAME RATE SOURCE REGISTER Address: 0xC065, Reset: 0x00, Name: FDSP_CTRL4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [3:0] FDSP_RATE_SOURCE (R/W) FastDSP Fram e Rate Source Selection 0000: ADC Channel 0 and Channel 1. 0001: ADC Channel 2 and Channel 3. 0010: Digital Microphone Channel 0 and Channel 1. ... 1101: Interpolator Channel 6 and Channel 7. 1110: Input Asynchronous Sample Rate Converter. 1111: Fixed. [4] FDSP_EXP_ATK_SPEED (R/W) FastDSP Expander Attack/Ram p-Down Speed Table 141. Bit Descriptions for FDSP_CTRL4 Bits [7:5] 4 [3:0] Bit Name RESERVED FDSP_EXP_ATK_SPEED FDSP_RATE_SOURCE Settings 0000 0001 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 Description Reserved. FastDSP Expander Attack/Ramp-Down Speed. FastDSP Frame Rate Source. ADC Channel 0 and Channel 1. ADC Channel 2 and Channel 3. Digital Microphone Channel 0 and Channel 1. Digital Microphone Channel 2 and Channel 3. Digital Microphone Channel 4 and Channel 5. Digital Microphone Channel 6 and Channel 7. Serial Audio Interface 0. Serial Audio Interface 1. Interpolator Channel 0 and Channel 1. Interpolator Channel 2 and Channel 3. Interpolator Channel 4 and Channel 5. Interpolator Channel 6 and Channel 7. Input Asynchronous Sample Rate Converter. Fixed. Reset 0x0 0x0 0x0 Access R R/W R/W FastDSP FIXED RATE DIVISION MSBs REGISTER Address: 0xC066, Reset: 0x00, Name: FDSP_CTRL5 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_RATE_DIV[15:8] (R/W) FastDSP Go Signal Division. Num ber of 24.576 MHz clock cycles between go signal is FDSP_RATE_DIV m inus 1 when FDSP_RATE_SOURCE set to fixed. Table 142. Bit Descriptions for FDSP_CTRL5 Bits [7:0] Bit Name FDSP_RATE_DIV[15:8] Settings Description FastDSP Go Signal Division. Number of 24.576 MHz clock cycles between go signal is FDSP_RATE_DIV minus 1 when FDSP_RATE_SOURCE set to fixed. Rev. A | Page 166 of 280 Reset 0x0 Access R/W Data Sheet ADAU1787 FastDSP FIXED RATE DIVISION LSBs REGISTER Address: 0xC067, Reset: 0x7F, Name: FDSP_CTRL6 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 [7:0] FDSP_RATE_DIV[7:0] (R/W) FastDSP Go Signal Division. Num ber of 24.576 MHz clock cycles between go signal is FDSP_RATE_DIV m inus 1 when FDSP_RATE_SOURCE set to fixed. Table 143. Bit Descriptions for FDSP_CTRL6 Bits [7:0] Bit Name FDSP_RATE_DIV[7:0] Settings Description FastDSP Go Signal Division. Number of 24.576 MHz clock cycles between go signal is FDSP_RATE_DIV minus 1 when FDSP_RATE_SOURCE set to fixed. Reset 0x7F Access R/W FastDSP MODULO N COUNTER FOR LOWER RATE CONDITIONAL EXECUTION REGISTER Address: 0xC068, Reset: 0x00, Name: FDSP_CTRL7 [7:6] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [5:0] FDSP_MOD_N (R/W) FastDSP Modulo N Counter Reset for Conditional Execution. Table 144. Bit Descriptions for FDSP_CTRL7 Bits [7:6] [5:0] Bit Name RESERVED FDSP_MOD_N Settings Description Reserved. FastDSP Modulo N Counter Reset for Conditional Execution. Rev. A | Page 167 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Data Sheet FastDSP GENERIC CONDITIONAL EXECUTION REGISTERS Address: 0xC069, Reset: 0x00, Name: FDSP_CTRL8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] FDSP_REG_COND7 (R/W) FastDSP Generic Register for Conditional Execution 0: Conditional register is 0. 1: Conditional register is 1. [0] FDSP_REG_COND0 (R/W) FastDSP Generic Register for Conditional Execution 0: Conditional register is 0. 1: Conditional register is 1. [6] FDSP_REG_COND6 (R/W) FastDSP Generic Register for Conditional Execution 0: Conditional register is 0. 1: Conditional register is 1. [1] FDSP_REG_COND1 (R/W) FastDSP Generic Register for Conditional Execution 0: Conditional register is 0. 1: Conditional register is 1. [5] FDSP_REG_COND5 (R/W) FastDSP Generic Register for Conditional Execution 0: Conditional register is 0. 1: Conditional register is 1. [2] FDSP_REG_COND2 (R/W) FastDSP Generic Register for Conditional Execution 0: Conditional register is 0. 1: Conditional register is 1. [4] FDSP_REG_COND4 (R/W) FastDSP Generic Register for Conditional Execution 0: Conditional register is 0. 1: Conditional register is 1. [3] FDSP_REG_COND3 (R/W) FastDSP Generic Register for Conditional Execution 0: Conditional register is 0. 1: Conditional register is 1. Table 145. Bit Descriptions for FDSP_CTRL8 Bits 7 Bit Name FDSP_REG_COND7 Settings 0 1 6 FDSP_REG_COND6 0 1 5 FDSP_REG_COND5 0 1 4 FDSP_REG_COND4 0 1 3 FDSP_REG_COND3 0 1 2 FDSP_REG_COND2 0 1 1 FDSP_REG_COND1 0 1 0 FDSP_REG_COND0 0 1 Description FastDSP Generic Register for Conditional Execution. The value of this register can be used for conditional instruction execution in the FastDSP. Conditional register is 0. Conditional register is 1. FastDSP Generic Register for Conditional Execution. The value of this register can be used for conditional instruction execution in the FastDSP. Conditional register is 0. Conditional register is 1. FastDSP Generic Register for Conditional Execution. The value of this register can be used for conditional instruction execution in the FastDSP. Conditional register is 0. Conditional register is 1. FastDSP Generic Register for Conditional Execution. The value of this register can be used for conditional instruction execution in the FastDSP. Conditional register is 0. Conditional register is 1. FastDSP Generic Register for Conditional Execution. The value of this register can be used for conditional instruction execution in the FastDSP. Conditional register is 0. Conditional register is 1. FastDSP Generic Register for Conditional Execution. The value of this register can be used for conditional instruction execution in the FastDSP. Conditional register is 0. Conditional register is 1. FastDSP Generic Register for Conditional Execution. The value of this register can be used for conditional instruction execution in the FastDSP. Conditional register is 0. Conditional register is 1. FastDSP Generic Register for Conditional Execution. The value of this register can be used for conditional instruction execution in the FastDSP. Conditional register is 0. Conditional register is 1. Rev. A | Page 168 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet ADAU1787 FastDSP SAFELOAD ADDRESS REGISTER Address: 0xC06A, Reset: 0x00, Name: FDSP_SL_ADDR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 : 6 ] R ES ER V ED [ 5 : 0 ] F D S P _S L _A D D R ( R / W ) Fa s tD SP Sa fe lo a d In s tr u c tio n Nu m b e r Table 146. Bit Descriptions for FDSP_SL_ADDR Bits [7:6] [5:0] Bit Name RESERVED FDSP_SL_ADDR Settings Description Reserved. FastDSP Safeload Instruction Number. Reset 0x0 0x0 Access R R/W FastDSP SAFELOAD PARAMETER 0 VALUE REGISTERS Address: 0xC06B, Reset: 0x00, Name: FDSP_SL_P0_3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P0[31:24] (R/W) FastDSP Safeload Parameter 0 (B0 Coefficient) Value to Be Written Table 147. Bit Descriptions for FDSP_SL_P0_3 Bits [7:0] Bit Name FDSP_SL_P0[31:24] Settings Description FastDSP Safeload Parameter 0 (B0 Coefficient) Value to Be Written Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0xC06C, Reset: 0x00, Name: FDSP_SL_P0_2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P0[23:16] (R/W) FastDSP Safeload Parameter 0 (B0 Coefficient) Value to Be Written Table 148. Bit Descriptions for FDSP_SL_P0_2 Bits [7:0] Bit Name FDSP_SL_P0[23:16] Settings Description FastDSP Safeload Parameter 0 (B0 Coefficient) Value to Be Written Address: 0xC06D, Reset: 0x00, Name: FDSP_SL_P0_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P0[15:8] (R/W) FastDSP Safeload Param eter 0 (B0 Coefficient) Value to Be Written Table 149. Bit Descriptions for FDSP_SL_P0_1 Bits [7:0] Bit Name FDSP_SL_P0[15:8] Settings Description FastDSP Safeload Parameter 0 (B0 Coefficient) Value to Be Written Address: 0xC06E, Reset: 0x00, Name: FDSP_SL_P0_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P0[7:0] (R/W) FastDSP Safeload Param eter 0 (B0 Coefficient) Value to Be Written Table 150. Bit Descriptions for FDSP_SL_P0_0 Bits [7:0] Bit Name FDSP_SL_P0[7:0] Settings Description FastDSP Safeload Parameter 0 (B0 Coefficient) Value to Be Written Rev. A | Page 169 of 280 ADAU1787 Data Sheet FastDSP SAFELOAD PARAMETER 1 VALUE REGISTERS Address: 0xC06F, Reset: 0x00, Name: FDSP_SL_P1_3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P1[31:24] (R/W) FastDSP Safeload Parameter 1 (B1 Coefficient) Value to Be Written Table 151. Bit Descriptions for FDSP_SL_P1_3 Bits [7:0] Bit Name FDSP_SL_P1[31:24] Settings Description FastDSP Safeload Parameter 1 (B1 Coefficient) Value to Be Written Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0xC070, Reset: 0x00, Name: FDSP_SL_P1_2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P1[23:16] (R/W) FastDSP Safeload Parameter 1 (B1 Coefficient) Value to Be Written Table 152. Bit Descriptions for FDSP_SL_P1_2 Bits [7:0] Bit Name FDSP_SL_P1[23:16] Settings Description FastDSP Safeload Parameter 1 (B1 Coefficient) Value to Be Written Address: 0xC071, Reset: 0x00, Name: FDSP_SL_P1_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P1[15:8] (R/W) FastDSP Safeload Param eter 1 (B1 Coefficient) Value to Be Written Table 153. Bit Descriptions for FDSP_SL_P1_1 Bits [7:0] Bit Name FDSP_SL_P1[15:8] Settings Description FastDSP Safeload Parameter 1 (B1 Coefficient) Value to Be Written Address: 0xC072, Reset: 0x00, Name: FDSP_SL_P1_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P1[7:0] (R/W) FastDSP Safeload Param eter 1 (B1 Coefficient) Value to Be Written Table 154. Bit Descriptions for FDSP_SL_P1_0 Bits [7:0] Bit Name FDSP_SL_P1[7:0] Settings Description FastDSP Safeload Parameter 1 (B1 Coefficient) Value to Be Written Rev. A | Page 170 of 280 Data Sheet ADAU1787 FastDSP SAFELOAD PARAMETER 2 VALUE REGISTERS Address: 0xC073, Reset: 0x00, Name: FDSP_SL_P2_3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P2[31:24] (R/W) FastDSP Safeload Parameter 2 (B2 Coefficient) Value to Be Written Table 155. Bit Descriptions for FDSP_SL_P2_3 Bits [7:0] Bit Name FDSP_SL_P2[31:24] Settings Description FastDSP Safeload Parameter 2 (B2 Coefficient) Value to Be Written Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0xC074, Reset: 0x00, Name: FDSP_SL_P2_2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P2[23:16] (R/W) FastDSP Safeload Parameter 2 (B2 Coefficient) Value to Be Written Table 156. Bit Descriptions for FDSP_SL_P2_2 Bits [7:0] Bit Name FDSP_SL_P2[23:16] Settings Description FastDSP Safeload Parameter 2 (B2 Coefficient) Value to Be Written Address: 0xC075, Reset: 0x00, Name: FDSP_SL_P2_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P2[15:8] (R/W) FastDSP Safeload Param eter 2 (B2 Coefficient) Value to Be Written Table 157. Bit Descriptions for FDSP_SL_P2_1 Bits [7:0] Bit Name FDSP_SL_P2[15:8] Settings Description FastDSP Safeload Parameter 2 (B2 Coefficient) Value to Be Written Address: 0xC076, Reset: 0x00, Name: FDSP_SL_P2_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P2[7:0] (R/W) FastDSP Safeload Param eter 2 (B2 Coefficient) Value to Be Written Table 158. Bit Descriptions for FDSP_SL_P2_0 Bits [7:0] Bit Name FDSP_SL_P2[7:0] Settings Description FastDSP Safeload Parameter 2 (B2 Coefficient) Value to Be Written Rev. A | Page 171 of 280 ADAU1787 Data Sheet FastDSP SAFELOAD PARAMETER 3 VALUE REGISTERS Address: 0xC077, Reset: 0x00, Name: FDSP_SL_P3_3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P3[31:24] (R/W) FastDSP Safeload Parameter 3 (A1 Coefficient) Value to Be Written Table 159. Bit Descriptions for FDSP_SL_P3_3 Bits [7:0] Bit Name FDSP_SL_P3[31:24] Settings Description FastDSP Safeload Parameter 3 (A1 Coefficient) Value to Be Written Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0xC078, Reset: 0x00, Name: FDSP_SL_P3_2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P3[23:16] (R/W) FastDSP Safeload Parameter 3 (A1 Coefficient) Value to Be Written Table 160. Bit Descriptions for FDSP_SL_P3_2 Bits [7:0] Bit Name FDSP_SL_P3[23:16] Settings Description FastDSP Safeload Parameter 3 (A1 Coefficient) Value to Be Written Address: 0xC079, Reset: 0x00, Name: FDSP_SL_P3_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P3[15:8] (R/W) FastDSP Safeload Param eter 3 (A1 Coefficient) Value to Be Written Table 161. Bit Descriptions for FDSP_SL_P3_1 Bits [7:0] Bit Name FDSP_SL_P3[15:8] Settings Description FastDSP Safeload Parameter 3 (A1 Coefficient) Value to Be Written Address: 0xC07A, Reset: 0x00, Name: FDSP_SL_P3_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P3[7:0] (R/W) FastDSP Safeload Param eter 3 (A1 Coefficient) Value to Be Written Table 162. Bit Descriptions for FDSP_SL_P3_0 Bits [7:0] Bit Name FDSP_SL_P3[7:0] Settings Description FastDSP Safeload Parameter 3 (A1 Coefficient) Value to Be Written Rev. A | Page 172 of 280 Data Sheet ADAU1787 FastDSP SAFELOAD PARAMETER 4 VALUE REGISTERS Address: 0xC07B, Reset: 0x00, Name: FDSP_SL_P4_3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P4[31:24] (R/W) FastDSP Safeload Parameter 4 (A2 Coefficient) Value to Be Written Table 163. Bit Descriptions for FDSP_SL_P4_3 Bits [7:0] Bit Name FDSP_SL_P4[31:24] Settings Description FastDSP Safeload Parameter 4 (A2 Coefficient) Value to Be Written Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0xC07C, Reset: 0x00, Name: FDSP_SL_P4_2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P4[23:16] (R/W) FastDSP Safeload Parameter 4 (A2 Coefficient) Value to Be Written Table 164. Bit Descriptions for FDSP_SL_P4_2 Bits [7:0] Bit Name FDSP_SL_P4[23:16] Settings Description FastDSP Safeload Parameter 4 (A2 Coefficient) Value to Be Written Address: 0xC07D, Reset: 0x00, Name: FDSP_SL_P4_1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P4[15:8] (R/W) FastDSP Safeload Param eter 4 (A2 Coefficient) Value to Be Written Table 165. Bit Descriptions for FDSP_SL_P4_1 Bits [7:0] Bit Name FDSP_SL_P4[15:8] Settings Description FastDSP Safeload Parameter 4 (A2 Coefficient) Value to Be Written Address: 0xC07E, Reset: 0x00, Name: FDSP_SL_P4_0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] FDSP_SL_P4[7:0] (R/W) FastDSP Safeload Param eter 4 (A2 Coefficient) Value to Be Written Table 166. Bit Descriptions for FDSP_SL_P4_0 Bits [7:0] Bit Name FDSP_SL_P4[7:0] Settings Description FastDSP Safeload Parameter 4 (A2 Coefficient) Value to Be Written Rev. A | Page 173 of 280 ADAU1787 Data Sheet FastDSP SAFELOAD UPDATE REGISTER Address: 0xC07F, Reset: 0x00, Name: FDSP_SL_UPDATE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:1] RESERVED [0] FDSP_SL_UPDATE (W) FastDSP Safeload Update 0: No Action. 1: Writing of 1 causes update of safeload parameters at the beginning of next fram e. Table 167. Bit Descriptions for FDSP_SL_UPDATE Bits [7:1] 0 Bit Name RESERVED FDSP_SL_UPDATE Settings 0 1 Description Reserved. FastDSP Safeload Update. Writing a 1 to this register writes the parameter values in the FDSP_SL_Px_x registers to the addresses in the current bank associated with the instruction number in the FDSP_SL_ADDR register at the beginning of the next frame. No Action. Writing of 1 causes update of safeload parameters at the beginning of next frame. Reset 0x0 0x0 Access R W Reset 0x0 0x0 Access R R/W SigmaDSP FRAME RATE SOURCE SELECT REGISTER Address: 0xC080, Reset: 0x00, Name: SDSP_CTRL1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] SDSP_SPEED (R/W) Sigm aDSP Clock Speed Control. 0: Sigm aDSP low speed, low voltage operation using 24.576 MHz core clock. 1: Sigm aDSP high speed, high voltage operation using 49.152 MHz core clock. [3:0] SDSP_RATE_SOURCE (R/W) Sigm aDSP Frame Rate Source 0000: ADC Channel 0 and Channel 1. 0001: ADC Channel 2 and Channel 3. 0010: Digital Microphone Channel 0 and Channel 1. ... 1101: Decimator Channel 6 and Channel 7. 1110: Input Asynchronous Sam ple Rate Converter. 1111: Fixed rate determ ined by SDSP_RATE_DIV. Table 168. Bit Descriptions for SDSP_CTRL1 Bits [7:5] 4 Bit Name RESERVED SDSP_SPEED Settings 0 1 Description Reserved. SigmaDSP Clock Speed Control. SigmaDSP low speed, low voltage operation using 24.576 MHz core clock frequency. SigmaDSP high speed, high voltage operation using 49.152 MHz core clock frequency. Rev. A | Page 174 of 280 Data Sheet Bits [3:0] ADAU1787 Bit Name SDSP_RATE_SOURCE Settings 0000 0001 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 Description SigmaDSP Frame Rate Source. ADC Channel 0 and Channel 1. ADC Channel 2 and Channel 3. Digital Microphone Channel 0 and Channel 1. Digital Microphone Channel 2 and Channel 3. Digital Microphone Channel 4 and Channel 5. Digital Microphone Channel 6 and Channel 7. Serial Audio Interface 0. Serial Audio Interface 1. Decimator Channel 0 and Channel 1. Decimator Channel 2 and Channel 3. Decimator Channel 4 and Channel 5. Decimator Channel 6 and Channel 7. Input Asynchronous Sample Rate Converter. Fixed rate determined by SDSP_RATE_DIV. Reset 0x0 Access R/W Reset 0x0 0x0 Access R R/W SigmaDSP RUN REGISTER Address: 0xC081, Reset: 0x00, Name: SDSP_CTRL2 [7:1] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [0] SDSP_RUN (R/W) Allows Sigm aDSP to run with the go signal 0: SigmaDSP has no go signal. Not running, but RAMs can be loaded if SDSP_EN = 1. 1: SigmaDSP has go signal and is running. Table 169. Bit Descriptions for SDSP_CTRL2 Bits [7:1] 0 Bit Name RESERVED SDSP_RUN Settings 0 1 Description Reserved. Allows SigmaDSP to run with the go signal. SigmaDSP has no go signal. Not running, but RAMs can be loaded if SDSP_EN = 1. SigmaDSP has go signal and is running. Rev. A | Page 175 of 280 ADAU1787 Data Sheet SigmaDSP WATCHDOG CONTROLS REGISTER Address: 0xC082, Reset: 0x00, Name: SDSP_CTRL3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [0] SDSP_WDOG_EN (R/W) SigmaDSP Watchdog Enable 0: Sigm aDSP Watchdog Off. 1: Sigm aDSP Watchdog On. [4] SDSP_WDOG_MUTE (R/W) Sigm aDSP Watchdog Mute 0: Sigm aDSP Watchdog Unm ute. 1: Sigm aDSP Watchdog Mute. [3:1] RESERVED Table 170. Bit Descriptions for SDSP_CTRL3 Bits [7:5] 4 Bit Name RESERVED SDSP_WDOG_MUTE Settings 0 1 [3:1] 0 RESERVED SDSP_WDOG_EN 0 1 Description Reserved. SigmaDSP Watchdog Mute. SigmaDSP Watchdog Unmute. SigmaDSP Watchdog Mute. Reserved. SigmaDSP Watchdog Enable SigmaDSP Watchdog Off. SigmaDSP Watchdog On. Reset 0x0 0x0 Access R R/W 0x0 0x0 R R/W SigmaDSP WATCHDOG VALUE REGISTERS Address: 0xC083, Reset: 0x00, Name: SDSP_CTRL4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 : 0 ] S D S P _W D O G _V A L [ 2 3 : 1 6 ] ( R / W ) Sig m a D SP W a tc h d o g Va lu e Table 171. Bit Descriptions for SDSP_CTRL4 Bits [7:0] Bit Name SDSP_WDOG_VAL[23:16] Settings Description SigmaDSP Watchdog Value Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0xC084, Reset: 0x00, Name: SDSP_CTRL5 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 : 0 ] S D S P _W D O G _V A L [ 1 5 : 8 ] ( R /W ) Sig m a D SP W a tc h d o g Va lu e Table 172. Bit Descriptions for SDSP_CTRL5 Bits [7:0] Bit Name SDSP_WDOG_VAL[15:8] Settings Description SigmaDSP Watchdog Value Address: 0xC085, Reset: 0x00, Name: SDSP_CTRL6 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 : 0 ] S D S P _W D O G _V A L [ 7 : 0 ] ( R /W ) Sig m a D SP W a t c h d o g Va lu e Table 173. Bit Descriptions for SDSP_CTRL6 Bits [7:0] Bit Name SDSP_WDOG_VAL[7:0] Settings Description SigmaDSP Watchdog Value Rev. A | Page 176 of 280 Data Sheet ADAU1787 SigmaDSP MODULO DATA MEMORY START POSITION REGISTERS Address: 0xC086, Reset: 0x07, Name: SDSP_CTRL7 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 [7:4] RESERVED [3:0] SDSP_MOD_DATA_MEM[11:8] (R/W) Sigm aDSP Modulo Data Mem ory Start Position Table 174. Bit Descriptions for SDSP_CTRL7 Bits [7:4] [3:0] Bit Name RESERVED SDSP_MOD_DATA_MEM[11:8] Settings Description Reserved SigmaDSP Modulo Data Memory Start Position Reset 0x0 0x7 Access R R/W Address: 0xC087, Reset: 0xF4, Name: SDSP_CTRL8 7 6 5 4 3 2 1 0 1 1 1 1 0 1 0 0 [7:0] SDSP_MOD_DATA_MEM[7:0] (R/W) Sigm aDSP Modulo Data Mem ory Start Position Table 175. Bit Descriptions for SDSP_CTRL8 Bits [7:0] Bit Name SDSP_MOD_DATA_MEM[7:0] Settings Description SigmaDSP Modulo Data Memory Start Position Reset 0xF4 Access R/W Reset 0x7 Access R/W Reset 0xFF Access R/W SigmaDSP FIXED FRAME RATE DIVISOR REGISTERS Address: 0xC088, Reset: 0x07, Name: SDSP_CTRL9 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 [7:0] SDSP_RATE_DIV[15:8] (R/W) Sigm aDSP Go Signal Division. Number of 49.152 MHz clock cycles between go signal is SDSP_RATE_DIV plus 1 when SDSP_RATE_SOURCE set to fixed. Table 176. Bit Descriptions for SDSP_CTRL9 Bits [7:0] Bit Name SDSP_RATE_DIV[15:8] Settings Description SigmaDSP Go Signal Division. Number of 49.152 MHz clock cycles between go signal is SDSP_RATE_DIV plus 1 when SDSP_RATE_SOURCE set to fixed. Address: 0xC089, Reset: 0xFF, Name: SDSP_CTRL10 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 [7:0] SDSP_RATE_DIV[7:0] (R/W) Sigm aDSP Go Signal Division. Num ber of 49.152 MHz clock cycles between go signal is SDSP_RATE_DIV plus 1 when SDSP_RATE_SOURCE set to fixed. Table 177. Bit Descriptions for SDSP_CTRL10 Bits [7:0] Bit Name SDSP_RATE_DIV[7:0] Settings Description SigmaDSP Go Signal Division. Number of 49.152 MHz clock cycles between go signal is SDSP_RATE_DIV plus 1 when SDSP_RATE_SOURCE set to fixed. Rev. A | Page 177 of 280 ADAU1787 Data Sheet SigmaDSP SET INTERRUPTS REGISTER Address: 0xC08A, Reset: 0x00, Name: SDSP_CTRL11 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] RESERVED [3] SDSP_INT3 (W) Sigm aDSP Trigger Interrupt 3 0: Writing of 0 has no effect. 1: Writing of 1 triggers Sigm aDSP interrupt. [2] SDSP_INT2 (W) Sigm aDSP Trigger Interrupt 2 0: Writing of 0 has no effect. 1: Writing of 1 triggers Sigm aDSP interrupt. [0] SDSP_INT0 (W) Sigm aDSP Trigger Interrupt 0 0: Writing of 0 has no effect. 1: Writing of 1 triggers Sigm aDSP interrupt. [1] SDSP_INT1 (W) Sigm aDSP Trigger Interrupt 1 0: Writing of 0 has no effect. 1: Writing of 1 triggers Sigm aDSP interrupt. Table 178. Bit Descriptions for SDSP_CTRL11 Bits [7:4] 3 Bit Name RESERVED SDSP_INT3 Settings 0 1 2 SDSP_INT2 0 1 1 SDSP_INT1 0 1 0 SDSP_INT0 0 1 Description Reserved. SigmaDSP Trigger Interrupt 3. Writing of 0 has no effect. Writing of 1 triggers SigmaDSP interrupt. SigmaDSP Trigger Interrupt 2. Writing of 0 has no effect. Writing of 1 triggers SigmaDSP interrupt. SigmaDSP Trigger Interrupt 1. Writing of 0 has no effect. Writing of 1 triggers SigmaDSP interrupt. SigmaDSP Trigger Interrupt 0. Writing of 0 has no effect. Writing of 1 triggers SigmaDSP interrupt. Rev. A | Page 178 of 280 Reset 0x0 0x0 Access R W 0x0 W 0x0 W 0x0 W Data Sheet ADAU1787 MULTIPURPOSE PIN 0 AND PIN 1 MODE SELECT REGISTER Address: 0xC08B, Reset: 0x00, Name: MP_CTRL1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] MP1_MODE (R/W) Multipurpose Pin 1 Mode Selection (BCLK_0). 0x0: Normal Operation. 0x1: Digital Microphone Channel 4 and Channel 5 Input. 0x2: Digital Microphone Channel 6 and Channel 7 Input. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. [3:0] MP0_MODE (R/W) Multipurpose Pin 0 Mode Selection (FSYNC_0). 0x0: Norm al Operation. 0x1: Digital Microphone Channel 4 and Channel 5 Input. 0x2: Digital Microphone Channel 6 and Channel 7 Input. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. Table 179. Bit Descriptions for MP_CTRL1 Bits [7:4] Bit Name MP1_MODE Settings 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA [3:0] MP0_MODE 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA Description Multipurpose Pin 1 Mode Selection (BCLK_0). Normal Operation. Digital Microphone Channel 4 and Channel 5 Input. Digital Microphone Channel 6 and Channel 7 Input. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Multipurpose Pin 0 Mode Selection (FSYNC_0). Normal Operation. Digital Microphone Channel 4 and Channel 5 Input. Digital Microphone Channel 6 and Channel 7 Input. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Rev. A | Page 179 of 280 Reset 0x0 Access R/W 0x0 R/W ADAU1787 Data Sheet MULTIPURPOSE PIN 2 AND PIN 3 MODE SELECT REGISTER Address: 0xC08C, Reset: 0x00, Name: MP_CTRL2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] MP3_MODE (R/W) Multipurpose Pin 3 Mode Selection (FSYNC_1). 0x0: Normal Operation. 0x1: Digital Microphone Channel 4 and Channel 5 Input. 0x2: Digital Microphone Channel 6 and Channel 7 Input. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. [3:0] MP2_MODE (R/W) Multipurpose Pin 2 Mode Selection (SDATAI_0). 0x0: Norm al Operation. 0x1: Digital Microphone Channel 4 and Channel 5 Input. 0x2: Digital Microphone Channel 6 and Channel 7 Input. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. Table 180. Bit Descriptions for MP_CTRL2 Bits [7:4] Bit Name MP3_MODE Settings 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA [3:0] MP2_MODE 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA Description Multipurpose Pin 3 Mode Selection (FSYNC_1). Normal Operation. Digital Microphone Channel 4 and Channel 5 Input. Digital Microphone Channel 6 and Channel 7 Input. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Multipurpose Pin 2 Mode Selection (SDATAI_0). Normal Operation. Digital Microphone Channel 4 and Channel 5 Input. Digital Microphone Channel 6 and Channel 7 Input. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Rev. A | Page 180 of 280 Reset 0x0 Access R/W 0x0 R/W Data Sheet ADAU1787 MULTIPURPOSE PIN 4 AND PIN 5 MODE SELECT REGISTER Address: 0xC08D, Reset: 0x00, Name: MP_CTRL3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] MP5_MODE (R/W) Multipurpose Pin 5 Mode Selection (SDATAO_1). 0x0: Normal Operation. 0x1: Digital Microphone Channel 4 and Channel 5 Input. 0x2: Digital Microphone Channel 6 and Channel 7 Input. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. [3:0] MP4_MODE (R/W) Multipurpose Pin 4 Mode Selection (BCLK_1). 0x0: Norm al Operation. 0x1: Digital Microphone Channel 4 and Channel 5 Input. 0x2: Digital Microphone Channel 6 and Channel 7 Input. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. Table 181. Bit Descriptions for MP_CTRL3 Bits [7:4] Bit Name MP5_MODE Settings 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA [3:0] MP4_MODE 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA Description Multipurpose Pin 5 Mode Selection (SDATAO_1). Normal Operation. Digital Microphone Channel 4 and Channel 5 Input. Digital Microphone Channel 6 and Channel 7 Input. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Multipurpose Pin 4 Mode Selection (BCLK_1). Normal Operation. Digital Microphone Channel 4 and Channel 5 Input. Digital Microphone Channel 6 and Channel 7 Input. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Rev. A | Page 181 of 280 Reset 0x0 Access R/W 0x0 R/W ADAU1787 Data Sheet MULTIPURPOSE PIN 6 AND PIN 7 MODE SELECT REGISTER Address: 0xC08E, Reset: 0x00, Name: MP_CTRL4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] MP7_MODE (R/W) Multipurpose Pin 7 Mode Selection (DMIC_CLK0). 0x0: Normal Operation. 0x1: Digital Microphone Channel 4 and Channel 5 Input. 0x2: Digital Microphone Channel 6 and Channel 7 Input. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. [3:0] MP6_MODE (R/W) Multipurpose Pin 6 Mode Selection (SDATAI_1). 0x0: Norm al Operation. 0x1: Digital Microphone Channel 4 and Channel 5 Input. 0x2: Digital Microphone Channel 6 and Channel 7 Input. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. Table 182. Bit Descriptions for MP_CTRL4 Bits [7:4] Bit Name MP7_MODE Settings 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA [3:0] MP6_MODE 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA Description Multipurpose Pin 7 Mode Selection (DMIC_CLK0). Normal Operation. Digital Microphone Channel 4 and Channel 5 Input. Digital Microphone Channel 6 and Channel 7 Input. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Multipurpose Pin 6 Mode Selection (SDATAI_1). Normal Operation. Digital Microphone Channel 4 and Channel 5 Input. Digital Microphone Channel 6 and Channel 7 Input. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Rev. A | Page 182 of 280 Reset 0x0 Access R/W 0x0 R/W Data Sheet ADAU1787 MULTIPURPOSE PIN 8 AND PIN 9 MODE SELECT REGISTER Address: 0xC08F, Reset: 0x00, Name: MP_CTRL5 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] MP9_MODE (R/W) Multipurpose Pin 9 Mode Selection (DMIC01). 0x0: Normal Operation. 0x3: General-Purpose Input. 0x4: General-Purpose Output from GPIOx_OUT bits. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. [3:0] MP8_MODE (R/W) Multipurpose Pin 8 Mode Selection (DMIC_CLK1). 0x0: Norm al Operation. 0x1: Digital Microphone Channel 4 and Channel 5 Input. 0x2: Digital Microphone Channel 6 and Channel 7 Input. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. Table 183. Bit Descriptions for MP_CTRL5 Bits [7:4] Bit Name MP9_MODE Settings 0x0 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA [3:0] MP8_MODE 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA Description Multipurpose Pin 9 Mode Selection (DMIC01). Normal Operation. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Multipurpose Pin 8 Mode Selection (DMIC_CLK1). Normal Operation. Digital Microphone Channel 4 and Channel 5 Input. Digital Microphone Channel 6 and Channel 7 Input. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Rev. A | Page 183 of 280 Reset 0x0 Access R/W 0x0 R/W ADAU1787 Data Sheet MULTIPURPOSE PIN 10 AND PIN 11 MODE SELECT REGISTER Address: 0xC090, Reset: 0x00, Name: MP_CTRL6 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] MP11_MODE (R/W) Multipurpose Pin 11 Mode Selection (SELFBOOT). 0x0: Normal Operation. 0x1: Digital Microphone Channel 4 and Channel 5 Input. 0x2: Digital Microphone Channel 6 and Channel 7 Input. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. [3:0] MP10_MODE (R/W) Multipurpose Pin 10 Mode Selection (DMIC23). 0x0: Norm al Operation. 0x3: General-Purpose Input. 0x4: General-Purpose Output from GPIOx_OUT bits. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. Table 184. Bit Descriptions for MP_CTRL6 Bits [7:4] Bit Name MP11_MODE Settings 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA [3:0] MP10_MODE 0x0 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA Description Multipurpose Pin 11 Mode Selection (SELFBOOT). Normal Operation. Digital Microphone Channel 4 and Channel 5 Input. Digital Microphone Channel 6 and Channel 7 Input. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Multipurpose Pin 10 Mode Selection (DMIC23). Normal Operation. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Rev. A | Page 184 of 280 Reset 0x0 Access R/W 0x0 R/W Data Sheet ADAU1787 GENERAL-PURPOSE INPUT DEBOUNCE CONTROL AND MASTER CLOCK OUTPUT RATE SELECTION REGISTER Address: 0xC091, Reset: 0x10, Name: MP_CTRL7 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 [7] RESERVED [6:4] MCLKO_RATE (R/W) Master Clock Output Rate Selection 0: Master Clock Output at 24.576 MHz. 1: Master Clock Output at 12.288 MHz. 10: Master Clock Output at 6.144 MHz. 11: Master Clock Output at 3.072 MHz. 100: Master Clock Output at 1.536 MHz. 101: Master Clock Output at 768 kHz. 110: Master Clock Output at 384 kHz. 111: Master Clock Output at 192 kHz. [2:0] GPI_DB (R/W) General-Purpose Input Debounce 0: GPIO Input without Debounce. 1: GPIO Input with Debounce (0.3 m s). 10: GPIO Input with Debounce (0.6 m s). 11: GPIO Input with Debounce (0.9 m s). 100: GPIO Input with Debounce (5 m s). 101: GPIO Input with Debounce (10 m s). 110: GPIO Input with Debounce (20 m s). [3] RESERVED Table 185. Bit Descriptions for MP_CTRL7 Bits 7 [6:4] Bit Name RESERVED MCLKO_RATE Settings 0 1 10 11 100 101 110 111 3 [2:0] RESERVED GPI_DB 0 1 10 11 100 101 110 Description Reserved. Master Clock Output Rate Selection. Master Clock Output at 24.576 MHz. Master Clock Output at 12.288 MHz. Master Clock Output at 6.144 MHz. Master Clock Output at 3.072 MHz. Master Clock Output at 1.536 MHz. Master Clock Output at 768 kHz. Master Clock Output at 384 kHz. Master Clock Output at 192 kHz. Reserved. General-Purpose Input Debounce. GPIO Input without Debounce. GPIO Input with Debounce (0.3 ms). GPIO Input with Debounce (0.6 ms). GPIO Input with Debounce (0.9 ms). GPIO Input with Debounce (5 ms). GPIO Input with Debounce (10 ms). GPIO Input with Debounce (20 ms). Rev. A | Page 185 of 280 Reset 0x0 0x1 Access R R/W 0x0 0x0 R R/W ADAU1787 Data Sheet GENERAL-PURPOSE OUTPUTS CONTROL PIN 0 TO PIN 7 REGISTER Address: 0xC092, Reset: 0x00, Name: MP_CTRL8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] GPIO7_OUT (R/W) GPIO7 Output Setting 0: MP7 pin set low when used as general-purpose output. 1: MP7 pin set high when used as general-purpose output. [0] GPIO0_OUT (R/W) GPIO0 Output Setting 0: MP0 pin set low when used as general-purpose output. 1: MP0 pin set high when used as general-purpose output. [6] GPIO6_OUT (R/W) GPIO6 Output Setting 0: MP6 pin set low when used as general-purpose output. 1: MP6 pin set high when used as general-purpose output. [1] GPIO1_OUT (R/W) GPIO1 Output Setting 0: MP1 pin set low when used as general-purpose output. 1: MP1 pin set high when used as general-purpose output. [5] GPIO5_OUT (R/W) GPIO5 Output Setting 0: MP5 pin set low when used as general-purpose output. 1: MP5 pin set high when used as general-purpose output. [2] GPIO2_OUT (R/W) GPIO2 Output Setting 0: MP2 pin set low when used as general-purpose output. 1: MP2 pin set high when used as general-purpose output. [4] GPIO4_OUT (R/W) GPIO4 Output Setting 0: MP4 pin set low when used as general-purpose output. 1: MP4 pin set high when used as general-purpose output. [3] GPIO3_OUT (R/W) GPIO3 Output Setting 0: MP3 pin set low when used as general-purpose output. 1: MP3 pin set high when used as general-purpose output. Table 186. Bit Descriptions for MP_CTRL8 Bits 7 Bit Name GPIO7_OUT Settings 0 1 6 GPIO6_OUT 0 1 5 GPIO5_OUT 0 1 4 GPIO4_OUT 0 1 3 GPIO3_OUT 0 1 2 GPIO2_OUT 0 1 1 GPIO1_OUT 0 1 0 GPIO0_OUT 0 1 Description GPIO7 Output Setting. MP7 pin set low when used as general-purpose output. MP7 pin set high when used as general-purpose output. GPIO6 Output Setting. MP6 pin set low when used as general-purpose output. MP6 pin set high when used as general-purpose output. GPIO5 Output Setting. MP5 pin set low when used as general-purpose output. MP5 pin set high when used as general-purpose output. GPIO4 Output Setting. MP4 pin set low when used as general-purpose output. MP4 pin set high when used as general-purpose output. GPIO3 Output Setting. MP3 pin set low when used as general-purpose output. MP3 pin set high when used as general-purpose output. GPIO2 Output Setting. MP2 pin set low when used as general-purpose output. MP2 pin set high when used as general-purpose output. GPIO1 Output Setting. MP1 pin set low when used as general-purpose output. MP1 pin set high when used as general-purpose output. GPIO0 Output Setting. MP0 pin set low when used as general-purpose output. MP0 pin set high when used as general-purpose output. Rev. A | Page 186 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet ADAU1787 GENERAL-PURPOSE OUTPUTS CONTROL PIN 8 TO PIN 10 REGISTER Address: 0xC093, Reset: 0x00, Name: MP_CTRL9 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] GPIO12_OUT (R/W) GPIO12 Output Setting 0: MP12 pin set low when used as general-purpose output. 1: MP12 pin set high when used as general-purpose output. [3] GPIO11_OUT (R/W) GPIO11 Output Setting 0: MP11 pin set low when used as general-purpose output. 1: MP11 pin set high when used as general-purpose output. [0] GPIO8_OUT (R/W) GPIO8 Output Setting 0: MP8 pin set low when used as general-purpose output. 1: MP8 pin set high when used as general-purpose output. [1] GPIO9_OUT (R/W) GPIO9 Output Setting 0: MP9 pin set low when used as general-purpose output. 1: MP9 pin set high when used as general-purpose output. [2] GPIO10_OUT (R/W) GPIO10 Output Setting 0: MP10 pin set low when used as general-purpose output. 1: MP10 pin set high when used as general-purpose output. Table 187. Bit Descriptions for MP_CTRL9 Bits [7:5] 4 Bit Name RESERVED GPIO12_OUT Settings 0 1 3 GPIO11_OUT 0 1 2 GPIO10_OUT 0 1 1 GPIO9_OUT 0 1 0 GPIO8_OUT 0 1 Description Reserved. GPIO12 Output Setting. MP12 pin set low when used as general-purpose output. MP12 pin set high when used as general-purpose output. GPIO11 Output Setting. MP11 pin set low when used as general-purpose output. MP11 pin set high when used as general-purpose output. GPIO10 Output Setting. MP10 pin set low when used as general-purpose output. MP10 pin set high when used as general-purpose output. GPIO9 Output Setting. MP9 pin set low when used as general-purpose output. MP9 pin set high when used as general-purpose output. GPIO8 Output Setting. MP8 pin set low when used as general-purpose output. MP8 pin set high when used as general-purpose output. Rev. A | Page 187 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W ADAU1787 Data Sheet FSYNC_0 PIN CONTROLS REGISTER Address: 0xC094, Reset: 0x05, Name: FSYNC0_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 [7:6] RESERVED [5] FSYNC0_PULL_SEL (R/W) FSYNC_0 Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [4] FSYNC0_PULL_EN (R/W) FSYNC_0 Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by FSYNC0_PULL_SEL bit. [1:0] FSYNC0_DRIVE (R/W) FSYNC_0 Pin Drive Strength 0: 2 m A Output Drive. 1: 4 m A Output Drive. 10: 8 m A Output Drive. 11: 12 m A Output Drive. [2] FSYNC0_SLEW (R/W) FSYNC_0 Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [3] RESERVED Table 188. Bit Descriptions for FSYNC0_CTRL Bits [7:6] 5 Bit Name RESERVED FSYNC0_PULL_SEL Settings 0 1 4 FSYNC0_PULL_EN 0 1 3 2 RESERVED FSYNC0_SLEW 0 1 [1:0] FSYNC0_DRIVE 0 1 10 11 Description Reserved. FSYNC_0 Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. FSYNC_0 Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by FSYNC0_PULL_SEL bit. Reserved. FSYNC_0 Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. FSYNC_0 Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Rev. A | Page 188 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x1 R R/W 0x1 R/W Data Sheet ADAU1787 BCLK_0 PIN CONTROLS REGISTER Address: 0xC095, Reset: 0x05, Name: BCLK0_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 [7:6] RESERVED [1:0] BCLK0_DRIVE (R/W) BCLK_0 Pin Drive Strength 0: 2 m A Output Drive. 1: 4 m A Output Drive. 10: 8 m A Output Drive. 11: 12 m A Output Drive. [5] BCLK0_PULL_SEL (R/W) BCLK_0 Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [2] BCLK0_SLEW (R/W) BCLK_0 Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [4] BCLK0_PULL_EN (R/W) BCLK_0 Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by BCLK0_PULL_SEL bit. [3] RESERVED Table 189. Bit Descriptions for BCLK0_CTRL Bits [7:6] 5 Bit Name RESERVED BCLK0_PULL_SEL Settings 0 1 4 BCLK0_PULL_EN 0 1 3 2 RESERVED BCLK0_SLEW 0 1 [1:0] BCLK0_DRIVE 0 1 10 11 Description Reserved. BCLK_0 Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. BCLK_0 Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by BCLK0_PULL_SEL bit. Reserved. BCLK_0 Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. BCLK_0 Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x1 R R/W 0x1 R/W Reset 0x0 0x1 Access R R/W 0x0 0x0 R R/W SDATAO_0 PIN CONTROL REGISTER Address: 0xC096, Reset: 0x04, Name: SDATAO0_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 [ 7 : 3 ] R ES ER V ED [ 2 ] S D A T A O 0 _S L EW ( R /W ) SD ATAO _0 Pin Sle w Ra te 0 : Fa s t Sle w Ra te . 1 : Slo w Sle w Ra te . [ 0 ] S D A T A O 0 _D R IV E ( R /W ) SD ATAO _0 D r iv e Str e n g th 0 : No r m a l D r iv e Str e n g th . 1 : H ig h D r iv e Str e n g th . [ 1 ] R ES ER V ED Table 190. Bit Descriptions for SDATAO0_CTRL Bits [7:3] 2 Bit Name RESERVED SDATAO0_SLEW Settings 0 1 1 0 RESERVED SDATAO0_DRIVE 0 1 Description Reserved. SDATAO_0 Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. Reserved. SDATAO_0 Drive Strength. Normal Drive Strength. High Drive Strength. Rev. A | Page 189 of 280 ADAU1787 Data Sheet SDATAI_0 PIN CONTROLS REGISTER Address: 0xC097, Reset: 0x05, Name: SDATAI0_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 [7:6] RESERVED [5] SDATAI0_PULL_SEL (R/W) SDATAI_0 Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [4] SDATAI0_PULL_EN (R/W) SDATAI_0 Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by SDATAI0_PULL_SEL bit. [1:0] SDATAI0_DRIVE (R/W) SDATAI_0 Pin Drive Strength 0: 2 mA Output Drive. 1: 4 mA Output Drive. 10: 8 mA Output Drive. 11: 12 mA Output Drive. [2] SDATAI0_SLEW (R/W) SDATAI_0 Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [3] RESERVED Table 191. Bit Descriptions for SDATAI0_CTRL Bits [7:6] 5 Bit Name RESERVED SDATAI0_PULL_SEL Settings 0 1 4 SDATAI0_PULL_EN 0 1 3 2 RESERVED SDATAI0_SLEW 0 1 [1:0] SDATAI0_DRIVE 0 1 10 11 Description Reserved. SDATAI_0 Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. SDATAI_0 Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by SDATAI0_PULL_SEL bit. Reserved. SDATAI_0 Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. SDATAI_0 Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Rev. A | Page 190 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x1 R R/W 0x1 R/W Data Sheet ADAU1787 FSYNC_1 PIN CONTROLS REGISTER Address: 0xC098, Reset: 0x05, Name: FSYNC1_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 [7:6] RESERVED [5] FSYNC1_PULL_SEL (R/W) FSYNC_1 Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [4] FSYNC1_PULL_EN (R/W) FSYNC_1 Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by FSYNC1_PULL_SEL bit. [1:0] FSYNC1_DRIVE (R/W) FSYNC_1 Pin Drive Strength 0: 2 m A Output Drive. 1: 4 m A Output Drive. 10: 8 m A Output Drive. 11: 12 m A Output Drive. [2] FSYNC1_SLEW (R/W) FSYNC_1 Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [3] RESERVED Table 192. Bit Descriptions for FSYNC1_CTRL Bits [7:6] 5 Bit Name RESERVED FSYNC1_PULL_SEL Settings 0 1 4 FSYNC1_PULL_EN 0 1 3 2 RESERVED FSYNC1_SLEW 0 1 [1:0] FSYNC1_DRIVE 0 1 10 11 Description Reserved. FSYNC_1 Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. FSYNC_1 Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by FSYNC1_PULL_SEL bit. Reserved. FSYNC_1 Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. FSYNC_1 Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Rev. A | Page 191 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x1 R R/W 0x1 R/W ADAU1787 Data Sheet BCLK_1 PIN CONTROLS REGISTER Address: 0xC099, Reset: 0x05, Name: BCLK1_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 [7:6] RESERVED [5] BCLK1_PULL_SEL (R/W) BCLK_1 Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [4] BCLK1_PULL_EN (R/W) BCLK_1 Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by BCLK1_PULL_SEL bit. [1:0] BCLK1_DRIVE (R/W) BCLK_1 Pin Drive Strength 0: 2 m A Output Drive. 1: 4 m A Output Drive. 10: 8 m A Output Drive. 11: 12 m A Output Drive. [2] BCLK1_SLEW (R/W) BCLK_1 Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [3] RESERVED Table 193. Bit Descriptions for BCLK1_CTRL Bits [7:6] 5 Bit Name RESERVED BCLK1_PULL_SEL Settings 0 1 4 BCLK1_PULL_EN 0 1 3 2 RESERVED BCLK1_SLEW 0 1 [1:0] BCLK1_DRIVE 0 1 10 11 Description Reserved. BCLK_1 Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. BCLK_1 Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by BCLK1_PULL_SEL bit. Reserved. BCLK_1 Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. BCLK_1 Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Rev. A | Page 192 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x1 R R/W 0x1 R/W Data Sheet ADAU1787 SDATAO_1 PIN CONTROLS REGISTER Address: 0xC09A, Reset: 0x05, Name: SDATAO1_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 [7:6] RESERVED [5] SDATAO1_PULL_SEL (R/W) SDATAO_1 Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [4] SDATAO1_PULL_EN (R/W) SDATAO_1 Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by SDATAO1_PULL_SEL bit. [1:0] SDATAO1_DRIVE (R/W) SDATAO_1 Pin Drive Strength 0: 2 mA Output Drive. 1: 4 mA Output Drive. 10: 8 mA Output Drive. 11: 12 mA Output Drive. [2] SDATAO1_SLEW (R/W) SDATAO_1 Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [3] RESERVED Table 194. Bit Descriptions for SDATAO1_CTRL Bits [7:6] 5 Bit Name RESERVED SDATAO1_PULL_SEL Settings 0 1 4 SDATAO1_PULL_EN 0 1 3 2 RESERVED SDATAO1_SLEW 0 1 [1:0] SDATAO1_DRIVE 0 1 10 11 Description Reserved. SDATAO_1 Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. SDATAO_1 Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by SDATAO1_PULL_SEL bit. Reserved. SDATAO_1 Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. SDATAO_1 Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Rev. A | Page 193 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x1 R R/W 0x1 R/W ADAU1787 Data Sheet SDATAI_1 PIN CONTROLS REGISTER Address: 0xC09B, Reset: 0x05, Name: SDATAI1_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 [7:6] RESERVED [5] SDATAI1_PULL_SEL (R/W) SDATAI_1 Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [4] SDATAI1_PULL_EN (R/W) SDATAI_1 Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by SDATAI1_PULL_SEL bit. [1:0] SDATAI1_DRIVE (R/W) SDATAI_1 Pin Drive Strength 0: 2 mA Output Drive. 1: 4 mA Output Drive. 10: 8 mA Output Drive. 11: 12 mA Output Drive. [2] SDATAI1_SLEW (R/W) SDATAI_1 Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [3] RESERVED Table 195. Bit Descriptions for SDATAI1_CTRL Bits [7:6] 5 Bit Name RESERVED SDATAI1_PULL_SEL Settings 0 1 4 SDATAI1_PULL_EN 0 1 3 2 RESERVED SDATAI1_SLEW 0 1 [1:0] SDATAI1_DRIVE 0 1 10 11 Description Reserved. SDATAI_1 Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. SDATAI_1 Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by SDATAI1_PULL_SEL bit. Reserved. SDATAI_1 Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. SDATAI_1 Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Rev. A | Page 194 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x1 R R/W 0x1 R/W Data Sheet ADAU1787 DMIC_CLK0 PIN CONTROLS REGISTER Address: 0xC09C, Reset: 0x05, Name: DMIC_CLK0_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 [7:6] RESERVED [5] DMIC_CLK0_PULL_SEL (R/W) DMIC_CLK0 Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [4] DMIC_CLK0_PULL_EN (R/W) DMIC_CLK0 Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by DMIC_CLK0_PULL_SEL bit. [1:0] DMIC_CLK0_DRIVE (R/W) DMIC_CLK0 Pin Drive Strength 0: 2 mA Output Drive. 1: 4 mA Output Drive. 10: 8 mA Output Drive. 11: 12 m A Output Drive. [2] DMIC_CLK0_SLEW (R/W) DMIC_CLK0 Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [3] RESERVED Table 196. Bit Descriptions for DMIC_CLK0_CTRL Bits [7:6] 5 Bit Name RESERVED DMIC_CLK0_PULL_SEL Settings 0 1 4 DMIC_CLK0_PULL_EN 0 1 3 2 RESERVED DMIC_CLK0_SLEW 0 1 [1:0] DMIC_CLK0_DRIVE 0 1 10 11 Description Reserved. DMIC_CLK0 Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. DMIC_CLK0 Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by DMIC_CLK0_PULL_SEL bit. Reserved. DMIC_CLK0 Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. DMIC_CLK0 Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Rev. A | Page 195 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x1 R R/W 0x1 R/W ADAU1787 Data Sheet DMIC_CLK1 PIN CONTROLS REGISTER Address: 0xC09D, Reset: 0x05, Name: DMIC_CLK1_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 [7:6] RESERVED [5] DMIC_CLK1_PULL_SEL (R/W) DMIC_CLK1 Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [4] DMIC_CLK1_PULL_EN (R/W) DMIC_CLK1 Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by DMIC_CLK1_PULL_SEL bit. [1:0] DMIC_CLK1_DRIVE (R/W) DMIC_CLK1 Pin Drive Strength 0: 2 mA Output Drive. 1: 4 mA Output Drive. 10: 8 mA Output Drive. 11: 12 m A Output Drive. [2] DMIC_CLK1_SLEW (R/W) DMIC_CLK1 Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [3] RESERVED Table 197. Bit Descriptions for DMIC_CLK1_CTRL Bits [7:6] 5 Bit Name RESERVED DMIC_CLK1_PULL_SEL Settings 0 1 4 DMIC_CLK1_PULL_EN 0 1 3 2 RESERVED DMIC_CLK1_SLEW 0 1 [1:0] DMIC_CLK1_DRIVE 0 1 10 11 Description Reserved. DMIC_CLK1 Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. DMIC_CLK1 Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by DMIC_CLK1_PULL_SEL bit. Reserved. DMIC_CLK1 Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. DMIC_CLK1 Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Rev. A | Page 196 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x1 R R/W 0x1 R/W Data Sheet ADAU1787 DMIC01 PIN CONTROLS REGISTER Address: 0xC09E, Reset: 0x05, Name: DMIC01_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 [7:6] RESERVED [5] DMIC01_PULL_SEL (R/W) DMIC01 Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [4] DMIC01_PULL_EN (R/W) DMIC01 Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by DMIC01_PULL_SEL bit. [1:0] DMIC01_DRIVE (R/W) DMIC01 Pin Drive Strength 0: 2 m A Output Drive. 1: 4 m A Output Drive. 10: 8 m A Output Drive. 11: 12 m A Output Drive. [2] DMIC01_SLEW (R/W) DMIC01 Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [3] RESERVED Table 198. Bit Descriptions for DMIC01_CTRL Bits [7:6] 5 Bit Name RESERVED DMIC01_PULL_SEL Settings 0 1 4 DMIC01_PULL_EN 0 1 3 2 RESERVED DMIC01_SLEW 0 1 [1:0] DMIC01_DRIVE 0 1 10 11 Description Reserved. DMIC01 Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. DMIC01 Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by DMIC01_PULL_SEL bit. Reserved. DMIC01 Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. DMIC01 Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Rev. A | Page 197 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x1 R R/W 0x1 R/W ADAU1787 Data Sheet DMIC23 PIN CONTROLS REGISTER Address: 0xC09F, Reset: 0x05, Name: DMIC23_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 [7:6] RESERVED [1:0] DMIC23_DRIVE (R/W) DMIC23 Pin Drive Strength 0: 2 m A Output Drive. 1: 4 m A Output Drive. 10: 8 m A Output Drive. 11: 12 m A Output Drive. [5] DMIC23_PULL_SEL (R/W) DMIC23 Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [2] DMIC23_SLEW (R/W) DMIC23 Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [4] DMIC23_PULL_EN (R/W) DMIC23 Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by DMIC23_PULL_SEL bit. [3] RESERVED Table 199. Bit Descriptions for DMIC23_CTRL Bits [7:6] 5 Bit Name RESERVED DMIC23_PULL_SEL Settings 0 1 4 DMIC23_PULL_EN 0 1 3 2 RESERVED DMIC23_SLEW 0 1 [1:0] DMIC23_DRIVE 0 1 10 11 Description Reserved. DMIC23 Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. DMIC23 Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by DMIC23_PULL_SEL bit. Reserved. DMIC23 Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. DMIC23 Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x1 R R/W 0x1 R/W SDA/MISO PIN CONTROLS REGISTER Address: 0xC0A0, Reset: 0x00, Name: I2C_SPI_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:2] RESERVED [1] SCL_SCLK_DRIVE (R/W) SCL/SCLK Output Pin Drive Strength 0: 4 m A drive strength. 1: 20 mA Drive Strength. May be required for fast m ode plus I2C operation. [0] SDA_MISO_DRIVE (R/W) SDA/MISO Output Pin Drive Strength 0: 4 mA Drive Strength. 1: 20 m A Drive Strength. May be required for fast mode plus I2C operation. Table 200. Bit Descriptions for I2C_SPI_CTRL Bits [7:2] 1 Bit Name RESERVED SCL_SCLK_DRIVE Settings 0 1 0 SDA_MISO_DRIVE 0 1 Description Reserved. SCL/SCLK Output Pin Drive Strength. 4 mA Drive Strength. 20 mA Drive Strength. May be required for fast mode plus I2C operation. SDA/MISO Output Pin Drive Strength. 4 mA Drive Strength. 20 mA Drive Strength. May be required for fast mode plus I2C operation. Rev. A | Page 198 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W Data Sheet ADAU1787 IRQ SIGNALING AND CLEARING REGISTER Address: 0xC0A1, Reset: 0x00, Name: IRQ_CTRL1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5] IRQ2_FUNC (R/W) IRQ2 Output Function Control 0: Active Low Interrupt Signaling. 1: Active High Interrupt Signaling. [4] IRQ1_FUNC (R/W) IRQ1 Output Function Control 0: Active Low Interrupt Signaling on Pin. 1: Active High Interrupt Signaling on Pin. [0] IRQ1_CLEAR (R/W1T) Write once to clear IRQ1 0: Not applicable. 1: Write once to clear IRQ1. [1] IRQ2_CLEAR (R/W1T) Write once to clear IRQ2 0: Not applicable. 1: Write once to clear IRQ2. [3:2] RESERVED Table 201. Bit Descriptions for IRQ_CTRL1 Bits [7:6] 5 Bit Name RESERVED IRQ2_FUNC Settings 0 1 4 IRQ1_FUNC 0 1 [3:2] 1 RESERVED IRQ2_CLEAR 0 1 0 IRQ1_CLEAR 0 1 Description Reserved. IRQ2 Output Function Control. Active Low Interrupt Signaling. Active High Interrupt Signaling. IRQ1 Output Function Control. Active Low Interrupt Signaling on Pin. Active High Interrupt Signaling on Pin. Reserved. Write once to clear IRQ2. Not applicable. Write once to clear IRQ2. Write once to clear IRQ1. Not applicable. Write once to clear IRQ1. Rev. A | Page 199 of 280 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x0 R R/W1T 0x0 R/W1T ADAU1787 Data Sheet IRQ1 MASKING REGISTERS Address: 0xC0A2, Reset: 0xF3, Name: IRQ1_MASK1 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 1 [7] IRQ1_ADC3_CLIP_MASK (R/W) Mask ADC Channel 3 Clipping to IRQ1 0: Event causes IRQ. 1: Event masked and does not cause IRQ. [0] IRQ1_DAC0_CLIP_MASK (R/W) Mask DAC Channel 0 Clipping to IRQ1 0: Event causes IRQ. 1: Event masked and does not cause IRQ. [6] IRQ1_ADC2_CLIP_MASK (R/W) Mask ADC Channel 2 Clipping to IRQ1 0: Event causes IRQ. 1: Event masked and does not cause IRQ. [1] IRQ1_DAC1_CLIP_MASK (R/W) Mask DAC Channel 1 Clipping to IRQ1 0: Event causes IRQ. 1: Event masked and does not cause IRQ. [5] IRQ1_ADC1_CLIP_MASK (R/W) Mask ADC Channel 1 Clipping to IRQ1 0: Event causes IRQ. 1: Event masked and does not cause IRQ. [3:2] RESERVED [4] IRQ1_ADC0_CLIP_MASK (R/W) Mask ADC Channel 0 Clipping to IRQ1 0: Event causes IRQ. 1: Event masked and does not cause IRQ. Table 202. Bit Descriptions for IRQ1_MASK1 Bits 7 Bit Name IRQ1_ADC3_CLIP_MASK Settings 0 1 6 IRQ1_ADC2_CLIP_MASK 0 1 5 IRQ1_ADC1_CLIP_MASK 0 1 4 IRQ1_ADC0_CLIP_MASK 0 1 [3:2] 1 RESERVED IRQ1_DAC1_CLIP_MASK 0 1 0 IRQ1_DAC0_CLIP_MASK 0 1 Description Mask ADC Channel 3 Clipping to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask ADC Channel 2 Clipping to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask ADC Channel 1 Clipping to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask ADC Channel 0 Clipping to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Reserved. Mask DAC Channel 1 Clipping to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask DAC Channel 0 Clipping to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Rev. A | Page 200 of 280 Reset 0x1 Access R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x0 0x1 R R/W 0x1 R/W Data Sheet ADAU1787 Address: 0xC0A3, Reset: 0xFF, Name: IRQ1_MASK2 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 [7] IRQ1_ASRCO_UNLOCKED_MASK (R/W) Mask Output ASRC Locked to Unlocked Transition to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [0] IRQ1_PLL_LOCKED_MASK (R/W) Mask PLL Unlocked to Locked Transition to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [6] IRQ1_ASRCO_LOCKED_MASK (R/W) Mask Output ASRC Unlocked to Locked Transition to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [1] IRQ1_PLL_UNLOCKED_MASK (R/W) Mask PLL Locked to Unlocked Transition to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [5] IRQ1_ASRCI_UNLOCKED_MASK (R/W) Mask Input ASRC Locked to Unlocked Transition to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [2] IRQ1_AVDD_UVW_MASK (R/W) Mask AVDD Undervoltage Warning to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [4] IRQ1_ASRCI_LOCKED_MASK (R/W) Mask Input ASRC Unlocked to Locked Transition to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [3] IRQ1_PRAMP_MASK (R/W) Mask Param eter Ramp Com plete Transition to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. Table 203. Bit Descriptions for IRQ1_MASK2 Bits 7 Bit Name IRQ1_ASRCO_UNLOCKED_MASK Settings 0 1 6 IRQ1_ASRCO_LOCKED_MASK 0 1 5 IRQ1_ASRCI_UNLOCKED_MASK 0 1 4 IRQ1_ASRCI_LOCKED_MASK 0 1 3 IRQ1_PRAMP_MASK 0 1 2 IRQ1_AVDD_UVW_MASK 0 1 1 IRQ1_PLL_UNLOCKED_MASK 0 1 0 IRQ1_PLL_LOCKED_MASK 0 1 Description Mask Output ASRC Locked to Unlocked Transition to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask Output ASRC Unlocked to Locked Transition to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask Input ASRC Locked to Unlocked Transition to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask Input ASRC Unlocked to Locked Transition to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask Parameter Ramp Complete Transition to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask AVDD Undervoltage Warning to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask PLL Locked to Unlocked Transition to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask PLL Unlocked to Locked Transition to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Rev. A | Page 201 of 280 Reset 0x1 Access R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W ADAU1787 Data Sheet Address: 0xC0A4, Reset: 0x1F, Name: IRQ1_MASK3 7 6 5 4 3 2 1 0 0 0 0 1 1 1 1 1 [7:5] RESERVED [4] IRQ1_POWER_UP_COMPLETE_MASK (R/W) Mask Power Up Not Finished to Com pleted Transition to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [3] IRQ1_SDSP3_MASK (R/W) Mask SigmaDSP Interrupt 3 to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [0] IRQ1_SDSP0_MASK (R/W) Mask SigmaDSP Interrupt 0 to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [1] IRQ1_SDSP1_MASK (R/W) Mask SigmaDSP Interrupt 1 to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [2] IRQ1_SDSP2_MASK (R/W) Mask SigmaDSP Interrupt 2 to IRQ1 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. Table 204. Bit Descriptions for IRQ1_MASK3 Bits [7:5] 4 Bit Name RESERVED IRQ1_POWER_UP_COMPLETE_MASK Settings 0 1 3 IRQ1_SDSP3_MASK 0 1 2 IRQ1_SDSP2_MASK 0 1 1 IRQ1_SDSP1_MASK 0 1 0 IRQ1_SDSP0_MASK 0 1 Description Reserved. Mask Power Up Not Finished to Completed Transition to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask SigmaDSP Interrupt 3 to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask SigmaDSP Interrupt 2 to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask SigmaDSP Interrupt 1 to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Mask SigmaDSP Interrupt 0 to IRQ1. Event causes IRQ. Event masked and does not cause IRQ. Rev. A | Page 202 of 280 Reset 0x0 0x1 Access R R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W Data Sheet ADAU1787 IRQ2 MASKING REGISTERS Address: 0xC0A5, Reset: 0xF3, Name: IRQ2_MASK1 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 1 [7] IRQ2_ADC3_CLIP_MASK (R/W) Mask ADC Channel 3 Clipping to IRQ2 0: Event causes IRQ. 1: Event masked and does not cause IRQ. [0] IRQ2_DAC0_CLIP_MASK (R/W) Mask DAC Channel 0 Clipping to IRQ2 0: Event causes IRQ. 1: Event masked and does not cause IRQ. [6] IRQ2_ADC2_CLIP_MASK (R/W) Mask ADC Channel 2 Clipping to IRQ2 0: Event causes IRQ. 1: Event masked and does not cause IRQ. [1] IRQ2_DAC1_CLIP_MASK (R/W) Mask DAC Channel 1 Clipping to IRQ2 0: Event causes IRQ. 1: Event masked and does not cause IRQ. [5] IRQ2_ADC1_CLIP_MASK (R/W) Mask ADC Channel 1 Clipping to IRQ2 0: Event causes IRQ. 1: Event masked and does not cause IRQ. [3:2] RESERVED [4] IRQ2_ADC0_CLIP_MASK (R/W) Mask ADC Channel 0 Clipping to IRQ2 0: Event causes IRQ. 1: Event masked and does not cause IRQ. Table 205. Bit Descriptions for IRQ2_MASK1 Bits 7 Bit Name IRQ2_ADC3_CLIP_MASK Settings 0 1 6 IRQ2_ADC2_CLIP_MASK 0 1 5 IRQ2_ADC1_CLIP_MASK 0 1 4 IRQ2_ADC0_CLIP_MASK 0 1 [3:2] 1 RESERVED IRQ2_DAC1_CLIP_MASK 0 1 0 IRQ2_DAC0_CLIP_MASK 0 1 Description Mask ADC Channel 3 Clipping to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask ADC Channel 2 Clipping to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask ADC Channel 1 Clipping to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask ADC Channel 0 Clipping to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Reserved. Mask DAC Channel 1 Clipping to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask DAC Channel 0 Clipping to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Rev. A | Page 203 of 280 Reset 0x1 Access R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x0 0x1 R R/W 0x1 R/W ADAU1787 Data Sheet Address: 0xC0A6, Reset: 0xFF, Name: IRQ2_MASK2 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 [7] IRQ2_ASRCO_UNLOCKED_MASK (R/W) Mask Output ASRC Locked to Unlocked Transition to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [0] IRQ2_PLL_LOCKED_MASK (R/W) Mask PLL Unlocked to Locked Transition to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [6] IRQ2_ASRCO_LOCKED_MASK (R/W) Mask Output ASRC Unlocked to Locked Transition to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [1] IRQ2_PLL_UNLOCKED_MASK (R/W) Mask PLL Locked to Unlocked Transition to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [5] IRQ2_ASRCI_UNLOCKED_MASK (R/W) Mask Input ASRC Locked to Unlocked Transition to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [2] IRQ2_AVDD_UVW_MASK (R/W) Mask AVDD Undervoltage Warning to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [4] IRQ2_ASRCI_LOCKED_MASK (R/W) Mask Input ASRC Unlocked to Locked Transition to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [3] IRQ2_PRAMP_MASK (R/W) Mask Param eter Ramp Com plete Transition to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. Table 206. Bit Descriptions for IRQ2_MASK2 Bits 7 Bit Name IRQ2_ASRCO_UNLOCKED_MASK Settings 0 1 6 IRQ2_ASRCO_LOCKED_MASK 0 1 5 IRQ2_ASRCI_UNLOCKED_MASK 0 1 4 IRQ2_ASRCI_LOCKED_MASK 0 1 3 IRQ2_PRAMP_MASK 0 1 2 IRQ2_AVDD_UVW_MASK 0 1 1 IRQ2_PLL_UNLOCKED_MASK 0 1 0 IRQ2_PLL_LOCKED_MASK 0 1 Description Mask Output ASRC Locked to Unlocked Transition to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask Output ASRC Unlocked to Locked Transition to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask Input ASRC Locked to Unlocked Transition to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask Input ASRC Unlocked to Locked Transition to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask Parameter Ramp Complete Transition to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask AVDD Undervoltage Warning to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask PLL Locked to Unlocked Transition to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask PLL Unlocked to Locked Transition to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Rev. A | Page 204 of 280 Reset 0x1 Access R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W Data Sheet ADAU1787 Address: 0xC0A7, Reset: 0x1F, Name: IRQ2_MASK3 7 6 5 4 3 2 1 0 0 0 0 1 1 1 1 1 [7:5] RESERVED [0] IRQ2_SDSP0_MASK (R/W) Mask SigmaDSP Interrupt 0 to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [4] IRQ2_POWER_UP_COMPLETE_MASK (R/W) Mask Power Up Not Finished to Com pleted Transition to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [1] IRQ2_SDSP1_MASK (R/W) Mask SigmaDSP Interrupt 1 to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [3] IRQ2_SDSP3_MASK (R/W) Mask SigmaDSP Interrupt 3 to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. [2] IRQ2_SDSP2_MASK (R/W) Mask SigmaDSP Interrupt 2 to IRQ2 0: Event causes IRQ. 1: Event m asked and does not cause IRQ. Table 207. Bit Descriptions for IRQ2_MASK3 Bits [7:5] 4 Bit Name RESERVED IRQ2_POWER_UP_COMPLETE_MASK Settings Description Reserved. Mask Power Up Not Finished to Completed Transition to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask SigmaDSP Interrupt 3 to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask SigmaDSP Interrupt 2 to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask SigmaDSP Interrupt 1 to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. Mask SigmaDSP Interrupt 0 to IRQ2. Event causes IRQ. Event masked and does not cause IRQ. 0 1 3 IRQ2_SDSP3_MASK 0 1 2 IRQ2_SDSP2_MASK 0 1 1 IRQ2_SDSP1_MASK 0 1 0 IRQ2_SDSP0_MASK 0 1 Reset 0x0 0x1 Access R R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W Reset 0x0 0x0 Access R W 0x0 0x0 R W CHIP RESETS REGISTER Address: 0xC0A8, Reset: 0x00, Name: RESETS 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] SOFT_RESET (W) Software Reset Not Including Register Settings 0: Not applicable. 1: Write 1 once to soft reset. [0] SOFT_FULL_RESET (W) Software Reset of Entire IC. 0: Not applicable. 1: Write 1 once to soft full reset. [3:1] RESERVED Table 208. Bit Descriptions for RESETS Bits [7:5] 4 Bit Name RESERVED SOFT_RESET Settings 0 1 [3:1] 0 RESERVED SOFT_FULL_RESET 0 1 Description Reserved. Software Reset Not Including Register Settings. Not applicable. Write 1 once to soft reset. Reserved. Software Reset of Entire IC. Not applicable. Write 1 once to soft full reset. Rev. A | Page 205 of 280 ADAU1787 Data Sheet FastDSP CURRENT LAMBDA REGISTER Address: 0xC0A9, Reset: 0x3F, Name: READ_LAMBDA 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [ 7 : 6 ] R ES ER V ED [ 5 : 0 ] F D S P _C U R R EN T _L A M B D A ( R ) Fa s tD SP Ba n k Sw it c h Ra m p Cu r r e n t La m b d a St a tu s 0 : Ba n k s w itc h p a r a m e te r r a m p is a t 1 /6 4 o f fu ll r a m p . 1 : Ba n k s w itc h p a r a m e te r r a m p is a t 2 /6 4 o f fu ll r a m p . ... 6 2 : Ba n k s w itc h p a r a m e te r r a m p is a t 6 3 /6 4 o f fu ll r a m p . 6 3 : Ba n k s w itc h p a r a m e te r r a m p is c o m p le te . Table 209. Bit Descriptions for READ_LAMBDA Bits [7:6] [5:0] Bit Name RESERVED FDSP_CURRENT_LAMBDA Settings 0 1 … 62 63 Description Reserved. FastDSP Bank Switch Ramp Current Lambda Status. Lambda is a 6-bit value representing the point along the linear interpolation curve between two banks at which the bank ramp switch stops. 0 = ((63/64) × A + (1/64) × B), 1 = ((62/64) × A + (2/64) × B), … , 62 = ((1/64) × A + (63/64) × B), and 63 = B (default) lambda can be updated on-the-fly via the control interface. To complete a bank switch, a value of 63 (default setting) must be set. Actual current ramp point (FDSP_CURRENT_LAMBDA: 0 to 63) can be read via a status register. When this point reaches 63, the bank switch is complete, and the current parameters used matches the current bank. Actual step size of linear interpolation is ~12 bits (4096 steps). Parameters in banks that are being ramped between should not change during a bank switch. Bank switch parameter ramp is at 1/64 of full ramp. Bank switch parameter ramp is at 2/64 of full ramp. … Bank switch parameter ramp is at 63/64 of full ramp. Bank switch parameter ramp is complete. Rev. A | Page 206 of 280 Reset 0x0 0x3F Access R R Data Sheet ADAU1787 CHIP STATUS 1 REGISTER Address: 0xC0AA, Reset: 0x00, Name: STATUS1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] A D C 3 _C L IP ( R ) AD C Ch a n n e l 3 Clip D e te c to r 0 : No r m a l O p e r a tio n . 1 : Am p lif ie r Clip p in g D e te c t e d . [ 0 ] D A C 0 _C L IP ( R ) D AC Ch a n n e l 0 Clip D e te c t o r 0 : No r m a l O p e r a t io n . 1 : Clip p in g D e t e c te d . [ 6 ] A D C 2 _C L IP ( R ) AD C Ch a n n e l 2 Clip D e te c to r 0 : No r m a l O p e r a tio n . 1 : Am p lif ie r Clip p in g D e te c t e d . [ 1 ] D A C 1 _C L I P ( R ) D AC Ch a n n e l 1 Clip D e te c to r 0 : No r m a l O p e r a t io n . 1 : Clip p in g D e t e c te d . [ 5 ] A D C 1 _C L I P ( R ) AD C Ch a n n e l 1 Clip D e t e c to r 0 : No r m a l O p e r a tio n . 1 : Am p lif ie r Clip p in g D e te c t e d . [ 3 : 2 ] R ES ER V ED [ 4 ] A D C 0 _C L IP ( R ) AD C Ch a n n e l 0 Clip D e te c to r 0 : No r m a l O p e r a tio n . 1 : Am p lif ie r Clip p in g D e te c t e d . Table 210. Bit Descriptions for STATUS1 Bits 7 Bit Name ADC3_CLIP Settings 0 1 6 ADC2_CLIP 0 1 5 ADC1_CLIP 0 1 4 ADC0_CLIP 0 1 [3:2] 1 RESERVED DAC1_CLIP 0 1 0 DAC0_CLIP 0 1 Description ADC Channel 3 Clip Detector. Normal Operation. Amplifier Clipping Detected. ADC Channel 2 Clip Detector. Normal Operation. Amplifier Clipping Detected. ADC Channel 1 Clip Detector. Normal Operation. Amplifier Clipping Detected. ADC Channel 0 Clip Detector. Normal Operation. Amplifier Clipping Detected. Reserved. DAC Channel 1 Clip Detector. Normal Operation. Clipping Detected. DAC Channel 0 Clip Detector. Normal Operation. Clipping Detected. Rev. A | Page 207 of 280 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R ADAU1787 Data Sheet CHIP STATUS 2 REGISTER Address: 0xC0AB, Reset: 0x00, Name: STATUS2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] POWER_UP_COMPLETE (R) Status of the power domain power up caused by POWER_EN=1 [6] SYNC_LOCK (R) Reads the m ultichip synchronization lock status [5] SPT1_LOCK (R) Reads the Serial Port 1 lock status [4] SPT0_LOCK (R) Reads the Serial Port 0 lock status [0] PLL_LOCK (R) Reads the PLL lock status 0: PLL is not locked. 1: PLL is locked. [1] AVDD_UVW (R) AVDD Undervoltage Warning 0: Normal Operation. 1: Undervoltage on AVDD Detected. [2] ASRCI_LOCK (R) Input ASRCI Lock Status 0: ASRC currently unlocked. 1: ASRC currently locked. [3] ASRCO_LOCK (R) Output ASRCI Lock Status 0: ASRC currently unlocked. 1: ASRC currently locked. Table 211. Bit Descriptions for STATUS2 Bits 7 6 5 4 3 Bit Name POWER_UP_COMPLETE SYNC_LOCK SPT1_LOCK SPT0_LOCK ASRCO_LOCK Settings 0 1 2 ASRCI_LOCK 0 1 1 AVDD_UVW 0 1 0 PLL_LOCK 0 1 Description Status of the power domain power up caused by POWER_EN = 1. Reads the multichip synchronization lock status. Reads the Serial Port 1 lock status. Reads the Serial Port 0 lock status. Output ASRCI Lock Status. ASRC currently unlocked. ASRC currently locked. Input ASRCI Lock Status. ASRC currently unlocked. ASRC currently locked. AVDD Undervoltage Warning. Normal Operation. Undervoltage on AVDD Detected. Reads the PLL lock status. PLL is not locked. PLL is locked. Rev. A | Page 208 of 280 Reset 0x0 0x0 0x0 0x0 0x0 Access R R R R R 0x0 R 0x0 R 0x0 R Data Sheet ADAU1787 GENERAL-PURPOSE INPUT READ 0 TO INPUT READ 7 REGISTER Address: 0xC0AC, Reset: 0x00, Name: GPI1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] GPIO7_IN (R) GPIO7 Input Reading 0: MP7 (set as GPIO 7) is low. 1: MP7 (set as GPIO 7) is high. [0] GPIO0_IN (R) GPIO0 Input Reading 0: MP0 (set as GPIO 0) is low. 1: MP0 (set as GPIO 0) is high. [6] GPIO6_IN (R) GPIO6 Input Reading 0: MP6 (set as GPIO 6) is low. 1: MP6 (set as GPIO 6) is high. [1] GPIO1_IN (R) GPIO1 Input Reading 0: MP1 (set as GPIO 1) is low. 1: MP1 (set as GPIO 1) is high. [5] GPIO5_IN (R) GPIO5 Input Reading 0: MP5 (set as GPIO 5) is low. 1: MP5 (set as GPIO 5) is high. [2] GPIO2_IN (R) GPIO2 Input Reading 0: MP2 (set as GPIO 2) is low. 1: MP2 (set as GPIO 2) is high. [4] GPIO4_IN (R) GPIO4 Input Reading 0: MP4 (set as GPIO 4) is low. 1: MP4 (set as GPIO 4) is high. [3] GPIO3_IN (R) GPIO3 Input Reading 0: MP3 (set as GPIO 3) is low. 1: MP3 (set as GPIO 3) is high. Table 212. Bit Descriptions for GPI1 Bits 7 Bit Name GPIO7_IN Settings 0 1 6 GPIO6_IN 0 1 5 GPIO5_IN 0 1 4 GPIO4_IN 0 1 3 GPIO3_IN 0 1 2 GPIO2_IN 0 1 1 GPIO1_IN 0 1 0 GPIO0_IN 0 1 Description GPIO7 Input Reading. MP7 (set as GPIO 7) is low. MP7 (set as GPIO 7) is high. GPIO6 Input Reading. MP6 (set as GPIO 6) is low. MP6 (set as GPIO 6) is high. GPIO5 Input Reading. MP5 (set as GPIO 5) is low. MP5 (set as GPIO 5) is high. GPIO4 Input Reading. MP4 (set as GPIO 4) is low. MP4 (set as GPIO 4) is high. GPIO3 Input Reading. MP3 (set as GPIO 3) is low. MP3 (set as GPIO 3) is high. GPIO2 Input Reading. MP2 (set as GPIO 2) is low. MP2 (set as GPIO 2) is high. GPIO1 Input Reading. MP1 (set as GPIO 1) is low. MP1 (set as GPIO 1) is high. GPIO0 Input Reading. MP0 (set as GPIO 0) is low. MP0 (set as GPIO 0) is high. Rev. A | Page 209 of 280 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R ADAU1787 Data Sheet GENERAL-PURPOSE INPUT READ 8 TO INPUT READ 10 REGISTER Address: 0xC0AD, Reset: 0x00, Name: GPI2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [0] GPIO8_IN (R) GPIO8 Input Reading 0: MP8 (set as GPIO 8) is low. 1: MP8 (set as GPIO 8) is high. [4] GPIO12_IN (R) GPIO12 Input Reading 0: MP12 (set as GPIO 12) is low. 1: MP12 (set as GPIO 12) is high. [1] GPIO9_IN (R) GPIO9 Input Reading 0: MP9 (set as GPIO 9) is low. 1: MP9 (set as GPIO 9) is high. [3] GPIO11_IN (R) GPIO11 Input Reading 0: MP11 (set as GPIO 11) is low. 1: MP11 (set as GPIO 11) is high. [2] GPIO10_IN (R) GPIO10 Input Reading 0: MP10 (set as GPIO10) is low. 1: MP10 (set as GPIO 10) is high. Table 213. Bit Descriptions for GPI2 Bits [7:5] 4 Bit Name RESERVED GPIO12_IN Settings 0 1 3 GPIO11_IN 0 1 2 GPIO10_IN 0 1 1 GPIO9_IN 0 1 0 GPIO8_IN 0 1 Description Reserved. GPIO12 Input Reading. MP12 (set as GPIO 12) is low. MP12 (set as GPIO 12) is high. GPIO11 Input Reading. MP11 (set as GPIO 11) is low. MP11 (set as GPIO 11) is high. GPIO10 Input Reading. MP10 (set as GPIO10) is low. MP10 (set as GPIO 10) is high. GPIO9 Input Reading. MP9 (set as GPIO 9) is low. MP9 (set as GPIO 9) is high. GPIO8 Input Reading. MP8 (set as GPIO 8) is low. MP8 (set as GPIO 8) is high. Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 R DSP STATUS REGISTER Address: 0xC0AE, Reset: 0x00, Name: DSP_STATUS 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:1] RESERVED [0] SDSP_WDOG_ERROR (R) Sigm aDSP Watchdog Error 0: No Watchdog Error. 1: Watchdog Error. Table 214. Bit Descriptions for DSP_STATUS Bits [7:1] 0 Bit Name RESERVED SDSP_WDOG_ERROR Settings 0 1 Description Reserved. SigmaDSP Watchdog Error. No Watchdog Error. Watchdog Error. Rev. A | Page 210 of 280 Reset 0x0 0x0 Access R R Data Sheet ADAU1787 IRQ1 STATUS 1 REGISTER Address: 0xC0AF, Reset: 0x00, Name: IRQ1_STATUS1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] IRQ1_ADC3_CLIP (R) ADC Channel 3 Clipping Detected 0: Interrupt not triggered. 1: Clipping detected. [0] IRQ1_DAC0_CLIP (R) DAC Channel 0 Clipping Detected 0: Interrupt not triggered. 1: Clipping detected. [6] IRQ1_ADC2_CLIP (R) ADC Channel 2 Clipping Detected 0: Interrupt not triggered. 1: Clipping detected. [1] IRQ1_DAC1_CLIP (R) DAC Channel 1 Clipping Detected 0: Interrupt not triggered. 1: Clipping detected. [5] IRQ1_ADC1_CLIP (R) ADC Channel 1 Clipping Detected 0: Interrupt not triggered. 1: Clipping detected. [3:2] RESERVED [4] IRQ1_ADC0_CLIP (R) ADC Channel 0 Clipping Detected 0: Interrupt not triggered. 1: Clipping detected. Table 215. Bit Descriptions for IRQ1_STATUS1 Bits 7 Bit Name IRQ1_ADC3_CLIP Settings 0 1 6 IRQ1_ADC2_CLIP 0 1 5 IRQ1_ADC1_CLIP 0 1 4 IRQ1_ADC0_CLIP 0 1 [3:2] 1 RESERVED IRQ1_DAC1_CLIP 0 1 0 IRQ1_DAC0_CLIP 0 1 Description ADC Channel 3 Clipping Detected. Interrupt not triggered. Clipping detected. ADC Channel 2 Clipping Detected. Interrupt not triggered. Clipping detected. ADC Channel 1 Clipping Detected. Interrupt not triggered. Clipping detected. ADC Channel 0 Clipping Detected Interrupt not triggered. Clipping detected. Reserved. DAC Channel 1 Clipping Detected. Interrupt not triggered. Clipping detected. DAC Channel 0 Clipping Detected. Interrupt not triggered. Clipping detected. Rev. A | Page 211 of 280 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R ADAU1787 Data Sheet IRQ1 STATUS 2 REGISTER Address: 0xC0B0, Reset: 0x00, Name: IRQ1_STATUS2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] IRQ1_ASRCO_UNLOCKED (R) Output ASRC Locked to Unlocked Transition Detected 0: Interrupt not triggered by PLL lock event. 1: Unlocked to locked transition detected. [6] IRQ1_ASRCO_LOCKED (R) Output ASRC Unlocked to Locked Transition Detected 0: Interrupt not triggered by PLL lock event. 1: Unlocked to locked transition detected. [5] IRQ1_ASRCI_UNLOCKED (R) Input ASRC Locked to Unlocked Transition Detected 0: Interrupt not triggered by PLL lock event. 1: Unlocked to locked transition detected. [4] IRQ1_ASRCI_LOCKED (R) Input ASRC Unlocked to Locked Transition Detected 0: Interrupt not triggered by PLL lock event. 1: Unlocked to locked transition detected. [0] IRQ1_PLL_LOCKED (R) PLL Unlocked to Locked Transition Detected 0: Interrupt not triggered by PLL lock event. 1: PLL unlocked to locked transition detected. [1] IRQ1_PLL_UNLOCKED (R) PLL Locked to Unlocked Transition Detected 0: Interrupt not triggered by PLL lock event. 1: PLL unlocked to locked transition detected. [2] IRQ1_AVDD_UVW (R) AVDD Undervoltage Warning Detected 0: Interrupt not triggered. 1: AVDD undervoltage warning detected. [3] IRQ1_PRAMP (R) Parameter Ramp Complete Interrupt 0: Interrupt not triggered. 1: Interrupt triggered. Table 216. Bit Descriptions for IRQ1_STATUS2 Bits 7 Bit Name IRQ1_ASRCO_UNLOCKED Settings 0 1 6 IRQ1_ASRCO_LOCKED 0 1 5 IRQ1_ASRCI_UNLOCKED 0 1 4 IRQ1_ASRCI_LOCKED 0 1 3 IRQ1_PRAMP 0 1 2 IRQ1_AVDD_UVW 0 1 1 IRQ1_PLL_UNLOCKED 0 1 0 IRQ1_PLL_LOCKED 0 1 Description Output ASRC Locked to Unlocked Transition Detected. Interrupt not triggered by PLL lock event. Unlocked to locked transition detected. Output ASRC Unlocked to Locked Transition Detected. Interrupt not triggered by PLL lock event. Unlocked to locked transition detected. Input ASRC Locked to Unlocked Transition Detected. Interrupt not triggered by PLL lock event. Unlocked to locked transition detected. Input ASRC Unlocked to Locked Transition Detected. Interrupt not triggered by PLL lock event. Unlocked to locked transition detected. Parameter Ramp Complete Interrupt. Interrupt not triggered. Interrupt triggered. AVDD Undervoltage Warning Detected. Interrupt not triggered. AVDD undervoltage warning detected. PLL Locked to Unlocked Transition Detected. Interrupt not triggered by PLL lock event. PLL unlocked to locked transition detected. PLL Unlocked to Locked Transition Detected. Interrupt not triggered by PLL lock event. PLL unlocked to locked transition detected. Rev. A | Page 212 of 280 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet ADAU1787 IRQ1 STATUS 3 REGISTER Address: 0xC0B1, Reset: 0x00, Name: IRQ1_STATUS3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] IRQ1_POWER_UP_COMPLETE (R) Power Up Not Finished to Com pleted Transition Detected 0: Interrupt not triggered by power-up com plete event. 1: Power-up com plete transition detected. [3] IRQ1_SDSP3 (R) Sigm aDSP Interrupt 3 0: Interrupt not triggered. 1: Interrupt triggered. [0] IRQ1_SDSP0 (R) Sigm aDSP Interrupt 0 0: Interrupt not triggered. 1: Interrupt triggered. [1] IRQ1_SDSP1 (R) Sigm aDSP Interrupt 1 0: Interrupt not triggered. 1: Interrupt triggered. [2] IRQ1_SDSP2 (R) Sigm aDSP Interrupt 2 0: Interrupt not triggered. 1: Interrupt triggered. Table 217. Bit Descriptions for IRQ1_STATUS3 Bits [7:5] 4 Bit Name RESERVED IRQ1_POWER_UP_COMPLETE Settings 0 1 3 IRQ1_SDSP3 0 1 2 IRQ1_SDSP2 0 1 1 IRQ1_SDSP1 0 1 0 IRQ1_SDSP0 0 1 Description Reserved. Power Up Not Finished to Completed Transition Detected. Interrupt not triggered by power-up complete event. Power-up complete transition detected. SigmaDSP Interrupt 3. Interrupt not triggered. Interrupt triggered. SigmaDSP Interrupt 2. Interrupt not triggered. Interrupt triggered. SigmaDSP Interrupt 1. Interrupt not triggered. Interrupt triggered. SigmaDSP Interrupt 0. Interrupt not triggered. Interrupt triggered. Rev. A | Page 213 of 280 Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 R ADAU1787 Data Sheet IRQ2 STATUS 1 REGISTER Address: 0xC0B2, Reset: 0x00, Name: IRQ2_STATUS1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] IRQ2_ADC3_CLIP (R) ADC Channel 3 Clipping Detected 0: Interrupt not triggered. 1: Clipping detected. [0] IRQ2_DAC0_CLIP (R) DAC Channel 0 Clipping Detected 0: Interrupt not triggered. 1: Clipping detected. [6] IRQ2_ADC2_CLIP (R) ADC Channel 2 Clipping Detected 0: Interrupt not triggered. 1: Clipping detected. [1] IRQ2_DAC1_CLIP (R) DAC Channel 1 Clipping Detected 0: Interrupt not triggered. 1: Clipping detected. [5] IRQ2_ADC1_CLIP (R) ADC Channel 1 Clipping Detected 0: Interrupt not triggered. 1: Clipping detected. [3:2] RESERVED [4] IRQ2_ADC0_CLIP (R) ADC Channel 0 Clipping Detected 0: Interrupt not triggered. 1: Clipping detected. Table 218. Bit Descriptions for IRQ2_STATUS1 Bits 7 Bit Name IRQ2_ADC3_CLIP Settings 0 1 6 IRQ2_ADC2_CLIP 0 1 5 IRQ2_ADC1_CLIP 0 1 4 IRQ2_ADC0_CLIP 0 1 [3:2] 1 RESERVED IRQ2_DAC1_CLIP 0 1 0 IRQ2_DAC0_CLIP 0 1 Description ADC Channel 3 Clipping Detected. Interrupt not triggered. Clipping detected. ADC Channel 2 Clipping Detected. Interrupt not triggered. Clipping detected. ADC Channel 1 Clipping Detected. Interrupt not triggered. Clipping detected. ADC Channel 0 Clipping Detected. Interrupt not triggered. Clipping detected. Reserved. DAC Channel 1 Clipping Detected. Interrupt not triggered. Clipping detected. DAC Channel 0 Clipping Detected. Interrupt not triggered. Clipping detected. Rev. A | Page 214 of 280 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R Data Sheet ADAU1787 IRQ2 STATUS 2 REGISTER Address: 0xC0B3, Reset: 0x00, Name: IRQ2_STATUS2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] IRQ2_ASRCO_UNLOCKED (R) Output ASRC Locked to Unlocked Transition Detected 0: Interrupt not triggered by PLL lock event. 1: Unlocked to locked transition detected. [6] IRQ2_ASRCO_LOCKED (R) Output ASRC Unlocked to Locked Transition Detected 0: Interrupt not triggered by PLL lock event. 1: Unlocked to locked transition detected. [5] IRQ2_ASRCI_UNLOCKED (R) Input ASRC Locked to Unlocked Transition Detected 0: Interrupt not triggered by PLL lock event. 1: Unlocked to locked transition detected. [4] IRQ2_ASRCI_LOCKED (R) Input ASRC Unlocked to Locked Transition Detected 0: Interrupt not triggered by PLL lock event. 1: Unlocked to locked transition detected. [0] IRQ2_PLL_LOCKED (R) PLL Unlocked to Locked Transition Detected 0: Interrupt not triggered by PLL lock event. 1: PLL unlocked to locked transition detected. [1] IRQ2_PLL_UNLOCKED (R) PLL Locked to Unlocked Transition Detected 0: Interrupt not triggered by PLL lock event. 1: PLL unlocked to locked transition detected. [2] IRQ2_AVDD_UVW (R) AVDD Undervoltage Warning Detected 0: Interrupt not triggered. 1: AVDD undervoltage warning detected. [3] IRQ2_PRAMP (R) Parameter Ramp Complete Interrupt 0: Interrupt not triggered. 1: Interrupt triggered. Table 219. Bit Descriptions for IRQ2_STATUS2 Bits 7 Bit Name IRQ2_ASRCO_UNLOCKED Settings 0 1 6 IRQ2_ASRCO_LOCKED 0 1 5 IRQ2_ASRCI_UNLOCKED 0 1 4 IRQ2_ASRCI_LOCKED 0 1 3 IRQ2_PRAMP 0 1 2 IRQ2_AVDD_UVW 0 1 1 IRQ2_PLL_UNLOCKED 0 1 0 IRQ2_PLL_LOCKED 0 1 Description Output ASRC Locked to Unlocked Transition Detected. Interrupt not triggered by PLL lock event. Unlocked to locked transition detected. Output ASRC Unlocked to Locked Transition Detected. Interrupt not triggered by PLL lock event. Unlocked to locked transition detected. Input ASRC Locked to Unlocked Transition Detected. Interrupt not triggered by PLL lock event. Unlocked to locked transition detected. Input ASRC Unlocked to Locked Transition Detected. Interrupt not triggered by PLL lock event. Unlocked to locked transition detected. Parameter Ramp Complete Interrupt. Interrupt not triggered. Interrupt triggered. AVDD Undervoltage Warning Detected. Interrupt not triggered. AVDD undervoltage warning detected. PLL Locked to Unlocked Transition Detected. Interrupt not triggered by PLL lock event. PLL unlocked to locked transition detected. PLL Unlocked to Locked Transition Detected. Interrupt not triggered by PLL lock event. PLL unlocked to locked transition detected. Rev. A | Page 215 of 280 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R ADAU1787 Data Sheet IRQ2 STATUS 3 REGISTER Address: 0xC0B4, Reset: 0x00, Name: IRQ2_STATUS3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4] IRQ2_POWER_UP_COMPLETE (R) Power Up Not Finished to Com pleted Transition Detected 0: Interrupt not triggered by power-up com plete event. 1: Power-up com plete transition detected. [3] IRQ2_SDSP3 (R) Sigm aDSP Interrupt 3 0: Interrupt not triggered. 1: Interrupt triggered. [0] IRQ2_SDSP0 (R) Sigm aDSP Interrupt 0 0: Interrupt not triggered. 1: Interrupt triggered. [1] IRQ2_SDSP1 (R) Sigm aDSP Interrupt 1 0: Interrupt not triggered. 1: Interrupt triggered. [2] IRQ2_SDSP2 (R) Sigm aDSP Interrupt 2 0: Interrupt not triggered. 1: Interrupt triggered. Table 220. Bit Descriptions for IRQ2_STATUS3 Bits [7:5] 4 Bit Name RESERVED IRQ2_POWER_UP_COMPLETE Settings 0 1 3 IRQ2_SDSP3 0 1 2 IRQ2_SDSP2 0 1 1 IRQ2_SDSP1 0 1 0 IRQ2_SDSP0 0 1 Description Reserved. Power Up Not Finished to Completed Transition Detected. Interrupt not triggered by power-up complete event. Power-up complete transition detected. SigmaDSP Interrupt 3. Interrupt not triggered. Interrupt triggered. SigmaDSP Interrupt 2. Interrupt not triggered. Interrupt triggered. SigmaDSP Interrupt 1. Interrupt not triggered. Interrupt triggered. SigmaDSP Interrupt 0. Interrupt not triggered. Interrupt triggered. Rev. A | Page 216 of 280 Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet ADAU1787 SERIAL PORT 0 CONTROL 1 REGISTER Address: 0xC0B5, Reset: 0x00, Name: SPT0_CTRL1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [6] SPT0_TRI_STATE (R/W) Serial Port Output, Tristate Enable 1: Tristate Enable. 0: Tristate Disable. [5:4] SPT0_SLOT_WIDTH (R/W) Serial Port, Selects Slot Width 00: 32 BCLKs per Slot. 01: 16 BCLKs per Slot. 10: 24 BCLKs per Slot. [0] SPT0_SAI_MODE (R/W) Serial Port, Selects Frame Clock Mode 0: Stereo. 50% duty cycle frame clock (I2S, left justified, or right justified). 1: TDM. Fram e clock is single bit clock wide pulse. [3:1] SPT0_DATA_FORMAT (R/W) Serial Port, Selects Data Delay from Frame Clock Edge 001: Left Justified, Delay by 0. 000: Typical I2S Mode, Delay by 1. 010: Delay by 8. 011: Delay by 12. 100: Delay by 16. Table 221. Bit Descriptions for SPT0_CTRL1 Bits 7 6 Bit Name RESERVED SPT0_TRI_STATE Settings 1 0 [5:4] SPT0_SLOT_WIDTH 00 01 10 [3:1] SPT0_DATA_FORMAT 001 000 010 011 100 0 SPT0_SAI_MODE 0 1 Description Reserved. Serial Port Output, Tristate Enable. Tristate Enable. Tristate Disabled. Serial Port, Selects Slot Width. 32 BCLKs per Slot. 16 BCLKs per Slot. 24 BCLKs per Slot. Serial Port, Selects Data Format from Frame Clock Edge. Left Justified, Delay by 0. Typical I2S Mode, Delay by 1. Delay by 8. Delay by 12. Delay by 16. Serial Port, Selects Frame Clock Mode. Stereo. 50% duty-cycle frame clock (I2S, left justified, or right justified). TDM. Frame clock is single bit clock wide pulse. Rev. A | Page 217 of 280 Reset 0x0 0x0 Access R/W R/W 0x0 R/W 0x0 R/W 0x0 R/W ADAU1787 Data Sheet SERIAL PORT 0 CONTROL 2 REGISTER Address: 0xC0B6, Reset: 0x00, Name: SPT0_CTRL2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] SPT0_LRCLK_POL (R/W) Serial Port, Selects Fram e Clock Polarity 0: Normal Polarity. 1: Inverted Polarity. [6:4] SPT0_LRCLK_SRC (R/W) Serial Port, Selects Fram e Clock Source and Rate 000: Frame clock is from external source. 001: Generates frame clock with 48 kHz. 010: Generates frame clock with 96 kHz. 011: Generates frame clock with 192 kHz. 100: Generates frame clock with 12 kHz. 101: Generates frame clock with 24 kHz. 110: Generates frame clock with 384 kHz. 111: Generates frame clock with 768 kHz. [2:0] SPT0_BCLK_SRC (R/W) Serial Port, Selects BCLK Source and Rate 000: BCLK is from external source. 001: Generates BCLK at 3.072 MHz. 010: Generates BCLK at 6.144 MHz. 011: Generates BCLK at 12.288 MHz. 100: Generates BCLK at 24.576 MHz. [3] SPT0_BCLK_POL (R/W) Serial Port, Selects BCLK Polarity 0: Captured on rising edge. 1: Captured on falling edge. Table 222. Bit Descriptions for SPT0_CTRL2 Bits 7 Bit Name SPT0_LRCLK_POL Settings 0 1 [6:4] SPT0_LRCLK_SRC 000 001 010 011 100 101 110 111 3 SPT0_BCLK_POL 0 1 [2:0] SPT0_BCLK_SRC 000 001 010 011 100 Description Serial Port, Selects Frame Clock Polarity. Normal Polarity. Inverted Polarity. Serial Port, Selects Frame Clock Source and Rate. Frame clock is from external source. Generates frame clock with 48 kHz. Generates frame clock with 96 kHz. Generates frame clock with 192 kHz. Generates frame clock with 12 kHz. Generates frame clock with 24 kHz. Generates frame clock with 384 kHz. Generates frame clock with 768 kHz. Serial Port, Selects BCLK Polarity. Captured on rising edge. Captured on falling edge. Serial Port, Selects BCLK Source and Rate. BCLK is from external source. Generates BCLK at 3.072 MHz. Generates BCLK at 6.144 MHz. Generates BCLK at 12.288 MHz. Generates BCLK at 24.576 MHz. Rev. A | Page 218 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet ADAU1787 SERIAL PORT 0 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) Address: 0xC0B7, Reset: 0x10, Name: SPT0_ROUTE0 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE0 (R/W) Serial Port Output Route Slot 0 (Left). 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 223. Bit Descriptions for SPT0_ROUTE0 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE0 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 0 (Left). FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 219 of 280 Reset 0x0 0x10 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x11 Access R R/W SERIAL PORT 0 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) Address: 0xC0B8, Reset: 0x11, Name: SPT0_ROUTE1 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE1 (R/W) Serial Port Output Route Slot 1 (Right). 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 224. Bit Descriptions for SPT0_ROUTE1 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE1 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 1 (Right). FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 220 of 280 Data Sheet Bits Bit Name ADAU1787 Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 221 of 280 Reset Access ADAU1787 Data Sheet SERIAL PORT 0 OUTPUT ROUTING SLOT 2 REGISTER Address: 0xC0B9, Reset: 0x3F, Name: SPT0_ROUTE2 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE2 (R/W) Serial Port Output Route Slot 2 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 225. Bit Descriptions for SPT0_ROUTE2 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE2 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 2. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 222 of 280 Reset 0x0 0x3F Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 0 OUTPUT ROUTING SLOT 3 REGISTER Address: 0xC0BA, Reset: 0x3F, Name: SPT0_ROUTE3 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE3 (R/W) Serial Port Output Route Slot 3 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 226. Bit Descriptions for SPT0_ROUTE3 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE3 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 3. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 223 of 280 ADAU1787 Bits Bit Name Data Sheet Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 224 of 280 Reset Access Data Sheet ADAU1787 SERIAL PORT 0 OUTPUT ROUTING SLOT 4 REGISTER Address: 0xC0BB, Reset: 0x3F, Name: SPT0_ROUTE4 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE4 (R/W) Serial Port Output Route Slot 4 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 227. Bit Descriptions for SPT0_ROUTE4 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE4 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 4. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 225 of 280 Reset 0x0 0x3F Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 0 OUTPUT ROUTING SLOT 5 REGISTER Address: 0xC0BC, Reset: 0x3F, Name: SPT0_ROUTE5 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE5 (R/W) Serial Port Output Route Slot 5 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 228. Bit Descriptions for SPT0_ROUTE5 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE5 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 5. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 226 of 280 Data Sheet Bits Bit Name ADAU1787 Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 227 of 280 Reset Access ADAU1787 Data Sheet SERIAL PORT 0 OUTPUT ROUTING SLOT 6 REGISTER Address: 0xC0BD, Reset: 0x3F, Name: SPT0_ROUTE6 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE6 (R/W) Serial Port Output Route Slot 6 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 229. Bit Descriptions for SPT0_ROUTE6 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE6 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 6. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 228 of 280 Reset 0x0 0x3F Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 0 OUTPUT ROUTING SLOT 7 REGISTER Address: 0xC0BE, Reset: 0x3F, Name: SPT0_ROUTE7 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE7 (R/W) Serial Port Output Route Slot 7 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 230. Bit Descriptions for SPT0_ROUTE7 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE7 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 7. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 229 of 280 ADAU1787 Bits Bit Name Data Sheet Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 230 of 280 Reset Access Data Sheet ADAU1787 SERIAL PORT 0 OUTPUT ROUTING SLOT 8 REGISTER Address: 0xC0BF, Reset: 0x3F, Name: SPT0_ROUTE8 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE8 (R/W) Serial Port Output Route Slot 8 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 231. Bit Descriptions for SPT0_ROUTE8 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE8 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 8. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 231 of 280 Reset 0x0 0x3F Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 0 OUTPUT ROUTING SLOT 9 REGISTER Address: 0xC0C0, Reset: 0x3F, Name: SPT0_ROUTE9 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE9 (R/W) Serial Port Output Route Slot 9 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 232. Bit Descriptions for SPT0_ROUTE9 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE9 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 9. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 232 of 280 Data Sheet Bits Bit Name ADAU1787 Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 233 of 280 Reset Access ADAU1787 Data Sheet SERIAL PORT 0 OUTPUT ROUTING SLOT 10 REGISTER Address: 0xC0C1, Reset: 0x3F, Name: SPT0_ROUTE10 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE10 (R/W) Serial Port Output Route Slot 10 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 233. Bit Descriptions for SPT0_ROUTE10 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE10 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 10. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 234 of 280 Reset 0x0 0x3F Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 0 OUTPUT ROUTING SLOT 11 REGISTER Address: 0xC0C2, Reset: 0x3F, Name: SPT0_ROUTE11 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE11 (R/W) Serial Port Output Route Slot 11 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 234. Bit Descriptions for SPT0_ROUTE11 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE11 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 11. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 235 of 280 ADAU1787 Bits Bit Name Data Sheet Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 236 of 280 Reset Access Data Sheet ADAU1787 SERIAL PORT 0 OUTPUT ROUTING SLOT 12 REGISTER Address: 0xC0C3, Reset: 0x3F, Name: SPT0_ROUTE12 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE12 (R/W) Serial Port Output Route Slot 12 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 235. Bit Descriptions for SPT0_ROUTE12 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE12 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 12. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 237 of 280 Reset 0x0 0x3F Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 0 OUTPUT ROUTING SLOT 13 REGISTER Address: 0xC0C4, Reset: 0x3F, Name: SPT0_ROUTE13 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE13 (R/W) Serial Port Output Route Slot 13 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 236. Bit Descriptions for SPT0_ROUTE13 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE13 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 13. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 238 of 280 Data Sheet Bits Bit Name ADAU1787 Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 239 of 280 Reset Access ADAU1787 Data Sheet SERIAL PORT 0 OUTPUT ROUTING SLOT 14 REGISTER Address: 0xC0C5, Reset: 0x3F, Name: SPT0_ROUTE14 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE14 (R/W) Serial Port Output Route Slot 14 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 237. Bit Descriptions for SPT0_ROUTE14 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE14 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 14. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 240 of 280 Reset 0x0 0x3F Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 0 OUTPUT ROUTING SLOT 15 REGISTER Address: 0xC0C6, Reset: 0x3F, Name: SPT0_ROUTE15 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT0_OUT_ROUTE15 (R/W) Serial Port Output Route Slot 15 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 238. Bit Descriptions for SPT0_ROUTE15 Bits [7:6] [5:0] Bit Name RESERVED SPT0_OUT_ROUTE15 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 15. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 241 of 280 ADAU1787 Bits Bit Name Data Sheet Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 242 of 280 Reset Access Data Sheet ADAU1787 SERIAL PORT 1 CONTROL 1 REGISTER Address: 0xC0C7, Reset: 0x00, Name: SPT1_CTRL1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [6] SPT1_TRI_STATE (R/W) Serial Port Output, Tristate Enable 1: Tristate Enable. 0: Tristate Disable. [5:4] SPT1_SLOT_WIDTH (R/W) Serial Port, Selects Slot Width 00: 32 BCLKs per Slot. 01: 16 BCLKs per Slot. 10: 24 BCLKs per Slot. [0] SPT1_SAI_MODE (R/W) Serial Port, Selects Frame Clock Mode 0: Stereo. 50% duty cycle frame clock (I2S, left justified, or right justified). 1: TDM. Fram e clock is single bit clock wide pulse. [3:1] SPT1_DATA_FORMAT (R/W) Serial Port, Selects Data Delay from Frame Clock Edge 001: Left Justified, Delay by 0. 000: Typical I2S Mode, Delay by 1. 010: Delay by 8. 011: Delay by 12. 100: Delay by 16. Table 239. Bit Descriptions for SPT1_CTRL1 Bits 7 6 Bit Name RESERVED SPT1_TRI_STATE Settings 1 0 [5:4] SPT1_SLOT_WIDTH 00 01 10 [3:1] SPT1_DATA_FORMAT 001 000 010 011 100 0 SPT1_SAI_MODE 0 1 Description Reserved. Serial Port Output, Tristate Enable. Tristate Enable. Tristate Disabled. Serial Port, Selects Slot Width. 32 BCLKs per Slot. 16 BCLKs per Slot. 24 BCLKs per Slot. Serial Port, Selects Data Format from Frame Clock Edge. Left Justified, Delay by 0. Typical I2S Mode, Delay by 1. Delay by 8. Delay by 12. Delay by 16. Serial Port, Selects Frame Clock Mode. Stereo. 50% duty-cycle frame clock (I2S, left justified, or right justified). TDM. Frame clock is single bit clock wide pulse. Rev. A | Page 243 of 280 Reset 0x0 0x0 Access R/W R/W 0x0 R/W 0x0 R/W 0x0 R/W ADAU1787 Data Sheet SERIAL PORT 1 CONTROL 2 REGISTER Address: 0xC0C8, Reset: 0x00, Name: SPT1_CTRL2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] SPT1_LRCLK_POL (R/W) Serial Port, Selects Fram e Clock Polarity 0: Normal Polarity. 1: Inverted Polarity. [6:4] SPT1_LRCLK_SRC (R/W) Serial Port, Selects Fram e Clock Source and Rate 000: Frame clock is from external source. 001: Generates frame clock with 48 kHz. 010: Generates frame clock with 96 kHz. 011: Generates frame clock with 192 kHz. 100: Generates frame clock with 12 kHz. 101: Generates frame clock with 24 kHz. 111: Generates frame clock with 768 kHz. 110: Generates frame clock with 384 kHz. [2:0] SPT1_BCLK_SRC (R/W) Serial Port, Selects BCLK Source and Rate 000: BCLK is from external source. 001: Generates BCLK at 3.072 MHz. 010: Generates BCLK at 6.144 MHz. 011: Generates BCLK at 12.288 MHz. 100: Generates BCLK at 24.576 MHz. [3] SPT1_BCLK_POL (R/W) Serial Port, Selects BCLK Polarity 0: Captured on rising edge. 1: Captured on falling edge. Table 240. Bit Descriptions for SPT1_CTRL2 Bits 7 Bit Name SPT1_LRCLK_POL Settings 0 1 [6:4] SPT1_LRCLK_SRC 000 001 010 011 100 101 111 110 3 SPT1_BCLK_POL 0 1 [2:0] SPT1_BCLK_SRC 000 001 010 011 100 Description Serial Port, Selects Frame Clock Polarity. Normal Polarity. Inverted Polarity. Serial Port, Selects Frame Clock Source and Rate. LRCLK is from external. Generates frame clock with 48 kHz. Generates frame clock with 96 kHz. Generates frame clock with 192 kHz. Generates frame clock with 12 kHz. Generates frame clock with 24 kHz. Generates frame clock with 768 kHz. Generates frame clock with 384 kHz. Serial Port, Selects BCLK Polarity. Captured on rising edge. Captured on falling edge. Serial Port, Selects BCLK Source and Rate. BCLK is from external source. Generates BCLK at 3.072 MHz. Generates BCLK at 6.144 MHz. Generates BCLK at 12.288 MHz. Generates BCLK at 24.576 MHz. Rev. A | Page 244 of 280 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet ADAU1787 SERIAL PORT 1 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) Address: 0xC0C9, Reset: 0x10, Name: SPT1_ROUTE0 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE0 (R/W) Serial Port Output Route Slot 0 (Left). 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 241. Bit Descriptions for SPT1_ROUTE0 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE0 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 0 (Left). FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 245 of 280 Reset 0x0 0x10 Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x11 Access R R/W SERIAL PORT 1 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) Address: 0xC0CA, Reset: 0x11, Name: SPT1_ROUTE1 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE1 (R/W) Serial Port Output Route Slot 1 (Right). 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 242. Bit Descriptions for SPT1_ROUTE1 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE1 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 1 (Right). FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 246 of 280 Data Sheet Bits Bit Name ADAU1787 Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. DMIC Channel 0. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 247 of 280 Reset Access ADAU1787 Data Sheet SERIAL PORT 1 OUTPUT ROUTING SLOT 2 REGISTER Address: 0xC0CB, Reset: 0x3F, Name: SPT1_ROUTE2 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE2 (R/W) Serial Port Output Route Slot 2 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 243. Bit Descriptions for SPT1_ROUTE2 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE2 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 2. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 248 of 280 Reset 0x0 0x3F Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 1 OUTPUT ROUTING SLOT 3 REGISTER Address: 0xC0CC, Reset: 0x3F, Name: SPT1_ROUTE3 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE3 (R/W) Serial Port Output Route Slot 3 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 244. Bit Descriptions for SPT1_ROUTE3 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE3 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 3. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 249 of 280 ADAU1787 Bits Bit Name Data Sheet Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 250 of 280 Reset Access Data Sheet ADAU1787 SERIAL PORT 1 OUTPUT ROUTING SLOT 4 REGISTER Address: 0xC0CD, Reset: 0x3F, Name: SPT1_ROUTE4 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE4 (R/W) Serial Port Output Route Slot 4 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 245. Bit Descriptions for SPT1_ROUTE4 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE4 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 4. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 251 of 280 Reset 0x0 0x3F Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 1 OUTPUT ROUTING SLOT 5 REGISTER Address: 0xC0CE, Reset: 0x3F, Name: SPT1_ROUTE5 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE5 (R/W) Serial Port Output Route Slot 5 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 246. Bit Descriptions for SPT1_ROUTE5 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE5 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 5. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 252 of 280 Data Sheet Bits Bit Name ADAU1787 Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 253 of 280 Reset Access ADAU1787 Data Sheet SERIAL PORT 1 OUTPUT ROUTING SLOT 6 REGISTER Address: 0xC0CF, Reset: 0x3F, Name: SPT1_ROUTE6 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE6 (R/W) Serial Port Output Route Slot 6 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 247. Bit Descriptions for SPT1_ROUTE6 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE6 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 6. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 254 of 280 Reset 0x0 0x3F Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 1 OUTPUT ROUTING SLOT 7 REGISTER Address: 0xC0D0, Reset: 0x3F, Name: SPT1_ROUTE7 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE7 (R/W) Serial Port Output Route Slot 7 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 248. Bit Descriptions for SPT1_ROUTE7 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE7 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 7. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 255 of 280 ADAU1787 Bits Bit Name Data Sheet Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 256 of 280 Reset Access Data Sheet ADAU1787 SERIAL PORT 1 OUTPUT ROUTING SLOT 8 REGISTER Address: 0xC0D1, Reset: 0x3F, Name: SPT1_ROUTE8 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE8 (R/W) Serial Port Output Route Slot 8 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 249. Bit Descriptions for SPT1_ROUTE8 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE8 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 8. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 257 of 280 Reset 0x0 0x3F Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 1 OUTPUT ROUTING SLOT 9 REGISTER Address: 0xC0D2, Reset: 0x3F, Name: SPT1_ROUTE9 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE9 (R/W) Serial Port Output Route Slot 9 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 250. Bit Descriptions for SPT1_ROUTE9 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE9 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 9. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 258 of 280 Data Sheet Bits Bit Name ADAU1787 Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 259 of 280 Reset Access ADAU1787 Data Sheet SERIAL PORT 1 OUTPUT ROUTING SLOT 10 REGISTER Address: 0xC0D3, Reset: 0x3F, Name: SPT1_ROUTE10 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE10 (R/W) Serial Port Output Route Slot 10 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 251. Bit Descriptions for SPT1_ROUTE10 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE10 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 10. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 260 of 280 Reset 0x0 0x3F Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 1 OUTPUT ROUTING SLOT 11 REGISTER Address: 0xC0D4, Reset: 0x3F, Name: SPT1_ROUTE11 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE11 (R/W) Serial Port Output Route Slot 11 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 252. Bit Descriptions for SPT1_ROUTE11 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE11 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 11. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 261 of 280 ADAU1787 Bits Bit Name Data Sheet Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 262 of 280 Reset Access Data Sheet ADAU1787 SERIAL PORT 1 OUTPUT ROUTING SLOT 12 REGISTER Address: 0xC0D5, Reset: 0x3F, Name: SPT1_ROUTE12 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE12 (R/W) Serial Port Output Route Slot 12 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 253. Bit Descriptions for SPT1_ROUTE12 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE12 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 12. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 263 of 280 Reset 0x0 0x3F Access R R/W ADAU1787 Bits Bit Name Data Sheet Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 1 OUTPUT ROUTING SLOT 13 REGISTER Address: 0xC0D6, Reset: 0x3F, Name: SPT1_ROUTE13 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE13 (R/W) Serial Port Output Route Slot 13 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 254. Bit Descriptions for SPT1_ROUTE13 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE13 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 13. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 264 of 280 Data Sheet Bits Bit Name ADAU1787 Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 265 of 280 Reset Access ADAU1787 Data Sheet SERIAL PORT 1 OUTPUT ROUTING SLOT 14 REGISTER Address: 0xC0D7, Reset: 0x3F, Name: SPT1_ROUTE14 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE14 (R/W) Serial Port Output Route Slot 14 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 255. Bit Descriptions for SPT1_ROUTE14 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE14 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 Description Reserved. Serial Port Output Route Slot 14. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. Rev. A | Page 266 of 280 Reset 0x0 0x3F Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Reset Access Reset 0x0 0x3F Access R R/W SERIAL PORT 1 OUTPUT ROUTING SLOT 15 REGISTER Address: 0xC0D8, Reset: 0x3F, Name: SPT1_ROUTE15 7 6 5 4 3 2 1 0 0 0 1 1 1 1 1 1 [7:6] RESERVED [5:0] SPT1_OUT_ROUTE15 (R/W) Serial Port Output Route Slot 15 000000: FastDSP Channel 0. 000001: FastDSP Channel 1. 000010: FastDSP Channel 2. ... 110110: Fast to Slow Decimator Channel 6. 110111: Fast to Slow Decimator Channel 7. 111111: No Output. Slot not used. Table 256. Bit Descriptions for SPT1_ROUTE15 Bits [7:6] [5:0] Bit Name RESERVED SPT1_OUT_ROUTE15 Settings 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 Description Reserved. Serial Port Output Route Slot 15. FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. Rev. A | Page 267 of 280 ADAU1787 Bits Bit Name Data Sheet Settings 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111111 Description FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Output ASRC Channel 0. Output ASRC Channel 1. Output ASRC Channel 2. Output ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digitial Microphone Channel 0. Digitial Microphone Channel 1. Digitial Microphone Channel 2. Digitial Microphone Channel 3. Digitial Microphone Channel 4. Digitial Microphone Channel 5. Digitial Microphone Channel 6. Digitial Microphone Channel 7. Fast to Slow Decimator Channel 0. Fast to Slow Decimator Channel 1. Fast to Slow Decimator Channel 2. Fast to Slow Decimator Channel 3. Fast to Slow Decimator Channel 4. Fast to Slow Decimator Channel 5. Fast to Slow Decimator Channel 6. Fast to Slow Decimator Channel 7. No Output. Slot not used. Rev. A | Page 268 of 280 Reset Access Data Sheet ADAU1787 MP12 PIN CONTROL REGISTER Address: 0xC0D9, Reset: 0x00, Name: MP_CTRL10 [7:4] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [3:0] MP12_MODE (R/W) Multipurpose Pin 12 Mode Selection (SW_EN). 0x0: Norm al Operation. 0x1: Digital Microphone Channel 4 and Channel 5 Input. 0x2: Digital Microphone Channel 6 and Channel 7 Input. ... 0x8: IRQ2 Output. 0x9: PDM Clock Output. 0xA: PDM Data Output. Table 257. Bit Descriptions for MP_CTRL10 Bits [7:4] [3:0] Bit Name RESERVED MP12_MODE Settings 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA Description Reserved. Multipurpose Pin 12 Mode Selection (SW_EN). Normal Operation. Digital Microphone Channel 4 and Channel 5 Input. Digital Microphone Channel 6 and Channel 7 Input. General-Purpose Input. General-Purpose Output from GPIOx_OUT bits. General-Purpose Output from SigmaDSP. Master Clock Output. IRQ1 Output. IRQ2 Output. PDM Clock Output. PDM Data Output. Rev. A | Page 269 of 280 Reset 0x0 0x0 Access R R/W ADAU1787 Data Sheet SELFBOOT PIN CONTROLS REGISTER Address: 0xC0DA, Reset: 0x45, Name: SELFBOOT_CTRL 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 1 [7] RESERVED [1:0] SELFBOOT_DRIVE (R/W) SELFBOOT Pin Drive Strength 0: 2 m A Output Drive. 1: 4 m A Output Drive. 10: 8 m A Output Drive. 11: 12 mA Output Drive. [6] SELFBOOT_SLEW (R/W) SELFBOOT Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [5] SELFBOOT_PULL_SEL (R/W) SELFBOOT Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [3:2] RESERVED [4] SELFBOOT_PULL_EN (R/W) SELFBOOT Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by SELFBOOT_PULL_SEL bit. Table 258. Bit Descriptions for SELFBOOT_CTRL Bits 7 6 Bit Name RESERVED SELFBOOT_SLEW Settings 0 1 5 SELFBOOT_PULL_SEL 0 1 4 SELFBOOT_PULL_EN 0 1 [3:2] [1:0] RESERVED SELFBOOT_DRIVE 0 1 10 11 Description Reserved. SELFBOOT Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. SELFBOOT Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. SELFBOOT Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by SELFBOOT_PULL_SEL bit. Reserved. SELFBOOT Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Rev. A | Page 270 of 280 Reset 0x0 0x1 Access R R/W 0x0 R/W 0x0 R/W 0x1 0x1 R R/W Data Sheet ADAU1787 SW_EN PIN CONTROLS REGISTER Address: 0xC0DB, Reset: 0x45, Name: SW_EN_CTRL 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 1 [7] RESERVED [1:0] SWEN_DRIVE (R/W) SW_EN Pin Drive Strength 0: 2 m A Output Drive. 1: 4 m A Output Drive. 10: 8 m A Output Drive. 11: 12 mA Output Drive. [6] SWEN_SLEW (R/W) SW_EN Pin Slew Rate 0: Fast Slew Rate. 1: Slow Slew Rate. [5] SWEN_PULL_SEL (R/W) SW_EN Pin Weak Pull-Up/Down Selection 0: Weak pull-down when enabled. 1: Weak pull-up when enabled. [3:2] RESERVED [4] SWEN_PULL_EN (R/W) SW_EN Pin Weak Pull-Up/Down Enable 0: No pull-up or pull-down. 1: Weak pull-up or pull-down set by SWEN_PULL_SEL bit. Table 259. Bit Descriptions for SW_EN_CTRL Bits 7 6 Bit Name RESERVED SWEN_SLEW Settings 0 1 5 SWEN_PULL_SEL 0 1 4 SWEN_PULL_EN 0 1 [3:2] [1:0] RESERVED SWEN_DRIVE 0 1 10 11 Description Reserved. SW_EN Pin Slew Rate. Determines the slew rate of the pin when used as an output. Fast Slew Rate. Slow Slew Rate. SW_EN Pin Weak Pull-Up/Down Selection. Weak pull-down when enabled. Weak pull-up when enabled. SW_EN Pin Weak Pull-Up/Down Enable. No pull-up or pull-down. Weak pull-up or pull-down set by SWEN_PULL_SEL bit. Reserved. SW_EN Pin Drive Strength. Determines the drive strength of the pin when used as an output. 2 mA Output Drive. 4 mA Output Drive. 8 mA Output Drive. 12 mA Output Drive. Rev. A | Page 271 of 280 Reset 0x0 0x1 Access R R/W 0x0 R/W 0x0 R/W 0x0 0x1 R R/W ADAU1787 Data Sheet PDM SAMPLE RATE AND FILTERING CONTROL REGISTER Address: 0xC0DC, Reset: 0x02, Name: PDM_CTRL1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 [7] PDM_MORE_FILT (R/W) PDM Output Additional Interpolation Filtering Selection 0: Less Interpolation Filtering: Lower Delay. 1: More Interpolation Filtering: Higher Delay. [6:5] RESERVED [4] PDM_RATE (R/W) PDM Output Rate 0: 6.144 MHz PDM Output Rate. 1: 3.072 MHz PDM Output Rate. [2:0] PDM_FS (R/W) PDM Output Path Sample Rate Selection 000: 12 kHz Sam ple Rate. 001: 24 kHz Sam ple Rate. 010: 48 kHz Sam ple Rate. 011: 96 kHz Sam ple Rate. 100: 192 kHz Sam ple Rate. 101: 384 kHz Sam ple Rate. 110: 768 kHz Sam ple Rate. [3] PDM_FCOMP (R/W) PDM Output Frequency Response Com pensation 0: High frequency response is not com pensated (lower delay). 1: High frequency response is compensated for samples rates of 192 kHz or lower when PDM_MORE_FILT = 1 (higher delay). Table 260. Bit Descriptions for PDM_CTRL1 Bits 7 Bit Name PDM_MORE_FILT Settings 0 1 [6:5] 4 RESERVED PDM_RATE 0 1 3 PDM_FCOMP 0 1 [2:0] PDM_FS 000 001 010 011 100 101 110 Description PDM Output Additional Interpolation Filtering Selection. Less Interpolation Filtering: Lower Delay. More Interpolation Filtering: Higher Delay. Reserved. PDM Output Rate. 6.144 MHz PDM Output Rate. 3.072 MHz PDM Output Rate. PDM Output Frequency Response Compensation. High frequency response is not compensated (lower delay). High frequency response is compensated for samples rates of 192 kHz or lower when DAC_MORE_FILT = 1 (higher delay). PDM Output Path Sample Rate Selection. 12 kHz Sample Rate. 24 kHz Sample Rate. 48 kHz Sample Rate. 96 kHz Sample Rate. 192 kHz Sample Rate. 384 kHz Sample Rate. 768 kHz Sample Rate. Rev. A | Page 272 of 280 Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 R/W 0x2 R/W Data Sheet ADAU1787 PDM MUTING, HIGH-PASS, AND VOLUME OPTIONS REGISTER Address: 0xC0DD, Reset: 0xC4, Name: PDM_CTRL2 7 6 5 4 3 2 1 0 1 1 0 0 0 1 0 0 [7] PDM1_MUTE (R/W) PDM Output Channel 1 Mute Control 0: PDM Output Unmuted. 1: PDM Output Muted. [0] PDM_VOL_LINK (R/W) PDM Output Volume Link 0: Each ADC channel uses its respective volum e value. 1: All ADC channels use Channel 0 volum e value. [6] PDM0_MUTE (R/W) PDM Output Channel 0 Mute Control 0: PDM Output Unmuted. 1: PDM Output Muted. [5] PDM1_HPF_EN (R/W) PDM Output Channel 1 Enable High-Pass Filter 0: PDM Output High-Pass Filter Off. 1: PDM Output High-Pass Filter On. [4] PDM0_HPF_EN (R/W) PDM Output 0 Enable High-Pass Filter 0: PDM Output High-Pass Filter Off. 1: PDM Output High-Pass Filter On. [1] PDM_HARD_VOL (R/W) PDM Output Hard Volume 0: Soft Volume Ramping. 1: Hard/Imm ediate Volum e Change. [2] PDM_VOL_ZC (R/W) PDM Output Volume Zero Cross Control 0: Volume change occurs at any time. 1: Volume change only occurs at zero crossing. [3] RESERVED Table 261. Bit Descriptions for PDM_CTRL2 Bits 7 Bit Name PDM1_MUTE Settings 0 1 6 PDM0_MUTE 0 1 5 PDM1_HPF_EN 0 1 4 PDM0_HPF_EN 0 1 3 2 RESERVED PDM_VOL_ZC 0 1 1 PDM_HARD_VOL 0 1 0 PDM_VOL_LINK 0 1 Description PDM Output Channel 1 Mute Control. PDM Output Unmuted. PDM Output Muted. PDM Output Channel 0 Mute Control. PDM Output Unmuted. PDM Output Muted. PDM Output Channel 1 Enable High-Pass Filter. PDM Output High-Pass Filter Off. PDM Output High-Pass Filter On. PDM Output 0 Enable High-Pass Filter. PDM Output High-Pass Filter Off. PDM Output High-Pass Filter On. Reserved. PDM Output Volume Zero Cross Control. Volume change occurs at any time. Volume change only occurs at zero crossing. PDM Output Hard Volume. Soft Volume Ramping. Hard/Immediate Volume Change. PDM Output Volume Link. Each ADC channel uses its respective volume value. All ADC channels use Channel 0 volume value. Rev. A | Page 273 of 280 Reset 0x1 Access R/W 0x1 R/W 0x0 R/W 0x0 R/W 0x0 0x1 R R/W 0x0 R/W 0x0 R/W ADAU1787 Data Sheet PDM OUTPUT CHANNEL 0 VOLUME REGISTER Address: 0xC0DE, Reset: 0x40, Name: PDM_VOL0 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] PDM0_VOL (R/W) PDM Output Channel 0 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 262. Bit Descriptions for PDM_VOL0 Bits [7:0] Bit Name PDM0_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description PDM Output Channel 0 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 274 of 280 Reset 0x40 Access R/W Data Sheet ADAU1787 PDM OUTPUT CHANNEL 1 VOLUME REGISTER Address: 0xC0DF, Reset: 0x40, Name: PDM_VOL1 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] PDM1_VOL (R/W) PDM Output Channel 1 Volum e Control 00000000: +24 dB. 00000001: +23.625 dB. 00000010: +23.35 dB. ... 11111101: −70.875 dB. 11111110: −71.25 dB. 11111111: Mute. Table 263. Bit Descriptions for PDM_VOL1 Bits [7:0] Bit Name PDM1_VOL Settings 00000000 00000001 00000010 00000011 00000100 … 00111111 01000000 01000001 … 11111101 11111110 11111111 Description PDM Output Channel 1 Volume Control. +24 dB. +23.625 dB. +23.35 dB. +22.875 dB. +22.5 dB. … +0.375 dB. 0 dB. −0.375 dB. … −70.875 dB. −71.25 dB. Mute. Rev. A | Page 275 of 280 Reset 0x40 Access R/W ADAU1787 Data Sheet PDM OUTPUT CHANNEL 0 ROUTING REGISTER Address: 0xC0E0, Reset: 0x00, Name: PDM_ROUTE0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESERVED [6:0] PDM0_ROUTE (R/W) PDM Output Channel 0 Input Routing 0000000: Serial Port 0 Channel 0. 0000001: Serial Port 0 Channel 1. 0000010: Serial Port 0 Channel 2. ... 1001101: Digital Microphone Channel 5. 1001110: Digital Microphone Channel 6. 1001111: Digital Microphone Channel 7. Table 264. Bit Descriptions for PDM_ROUTE0 Bits 7 [6:0] Bit Name RESERVED PDM0_ROUTE Settings 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Description Reserved. PDM Output Channel 0 Input Routing. Serial Port 0 Channel 0. Serial Port 0 Channel 1. Serial Port 0 Channel 2. Serial Port 0 Channel 3. Serial Port 0 Channel 4. Serial Port 0 Channel 5. Serial Port 0 Channel 6. Serial Port 0 Channel 7. Serial Port 0 Channel 8. Serial Port 0 Channel 9. Serial Port 0 Channel 10. Serial Port 0 Channel 11. Serial Port 0 Channel 12. Serial Port 0 Channel 13. Serial Port 0 Channel 14. Serial Port 0 Channel 15. Serial Port 1 Channel 0. Serial Port 1 Channel 1. Serial Port 1 Channel 2. Serial Port 1 Channel 3. Serial Port 1 Channel 4. Serial Port 1 Channel 5. Serial Port 1 Channel 6. Serial Port 1 Channel 7. Serial Port 1 Channel 8. Serial Port 1 Channel 9. Serial Port 1 Channel 10. Serial Port 1 Channel 11. Serial Port 1 Channel 12. Serial Port 1 Channel 13. Serial Port 1 Channel 14. Serial Port 1 Channel 15. Rev. A | Page 276 of 280 Reset 0x0 0x0 Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Description FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digital Microphone Channel 0. Digital Microphone Channel 1. Digital Microphone Channel 2. Digital Microphone Channel 3. Digital Microphone Channel 4. Digital Microphone Channel 5. Digital Microphone Channel 6. Digital Microphone Channel 7. Rev. A | Page 277 of 280 Reset Access ADAU1787 Data Sheet PDM OUTPUT CHANNEL 1 ROUTING REGISTER Address: 0xC0E1, Reset: 0x01, Name: PDM_ROUTE1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7] RESERVED [6:0] PDM1_ROUTE (R/W) PDM Output Channel 1 Input Routing 0000000: Serial Port 0 Channel 0. 0000001: Serial Port 0 Channel 1. 0000010: Serial Port 0 Channel 2. ... 1001101: Digital Microphone Channel 5. 1001110: Digital Microphone Channel 6. 1001111: Digital Microphone Channel 7. Table 265. Bit Descriptions for PDM_ROUTE1 Bits 7 [6:0] Bit Name RESERVED PDM1_ROUTE Settings 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 Description Reserved. PDM Output Channel 1 Input Routing. Serial Port 0 Channel 0. Serial Port 0 Channel 1. Serial Port 0 Channel 2. Serial Port 0 Channel 3. Serial Port 0 Channel 4. Serial Port 0 Channel 5. Serial Port 0 Channel 6. Serial Port 0 Channel 7. Serial Port 0 Channel 8. Serial Port 0 Channel 9. Serial Port 0 Channel 10. Serial Port 0 Channel 11. Serial Port 0 Channel 12. Serial Port 0 Channel 13. Serial Port 0 Channel 14. Serial Port 0 Channel 15. Serial Port 1 Channel 0. Serial Port 1 Channel 1. Serial Port 1 Channel 2. Serial Port 1 Channel 3. Serial Port 1 Channel 4. Serial Port 1 Channel 5. Serial Port 1 Channel 6. Serial Port 1 Channel 7. Serial Port 1 Channel 8. Serial Port 1 Channel 9. Serial Port 1 Channel 10. Serial Port 1 Channel 11. Serial Port 1 Channel 12. Serial Port 1 Channel 13. Serial Port 1 Channel 14. Serial Port 1 Channel 15. Rev. A | Page 278 of 280 Reset 0x0 0x1 Access R R/W Data Sheet Bits Bit Name ADAU1787 Settings 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 Description FastDSP Channel 0. FastDSP Channel 1. FastDSP Channel 2. FastDSP Channel 3. FastDSP Channel 4. FastDSP Channel 5. FastDSP Channel 6. FastDSP Channel 7. FastDSP Channel 8. FastDSP Channel 9. FastDSP Channel 10. FastDSP Channel 11. FastDSP Channel 12. FastDSP Channel 13. FastDSP Channel 14. FastDSP Channel 15. SigmaDSP Channel 0. SigmaDSP Channel 1. SigmaDSP Channel 2. SigmaDSP Channel 3. SigmaDSP Channel 4. SigmaDSP Channel 5. SigmaDSP Channel 6. SigmaDSP Channel 7. SigmaDSP Channel 8. SigmaDSP Channel 9. SigmaDSP Channel 10. SigmaDSP Channel 11. SigmaDSP Channel 12. SigmaDSP Channel 13. SigmaDSP Channel 14. SigmaDSP Channel 15. Input ASRC Channel 0. Input ASRC Channel 1. Input ASRC Channel 2. Input ASRC Channel 3. ADC Channel 0. ADC Channel 1. ADC Channel 2. ADC Channel 3. Digital Microphone Channel 0. Digital Microphone Channel 1. Digital Microphone Channel 2. Digital Microphone Channel 3. Digital Microphone Channel 4. Digital Microphone Channel 5. Digital Microphone Channel 6. Digital Microphone Channel 7. Rev. A | Page 279 of 280 Reset Access ADAU1787 Data Sheet OUTLINE DIMENSIONS 2.735 2.695 2.655 0.285 7 6 5 4 3 2 1 A BALL A1 IDENTIFIER B 2.360 2.320 2.280 1.75 REF C D E 0.2975 2.10 REF 0.320 0.290 0.260 SIDE VIEW BOTTOM VIEW (BALL SIDE UP) COPLANARITY 0.05 0.280 0.240 0.200 PKG-005423 SEATING PLANE 0.210 0.180 0.150 07-28-2017-A 0.530 0.470 0.410 F 0.35 BALL PITCH TOP VIEW (BALL SIDE DOWN) Figure 72. 42-Ball Wafer Level Chip Scale Package [WLCSP] (CB-42-2) Dimensions shown in millimeters ORDERING GUIDE Model1 ADAU1787BCBZRL EVAL-ADAU1787Z 1 Temperature Range −40°C to +85°C Package Description 42-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. ©2019-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D20127-0-1/20(A) Rev. A | Page 280 of 280 Package Option CB-42-2