12-Channel, High Performance,
192 kHz, 24-Bit DAC
ADAU1962A
Data Sheet
FEATURES
GENERAL DESCRIPTION
Differential or single-ended voltage DAC output
114 dB DAC dynamic range, A-weighted, differential
−97 dB total harmonic distortion plus noise (THD + N),
differential
110 dB DAC dynamic range, A-weighted, single-ended
−95 dB THD + N, single-ended
2.5 V digital and 3.3 V analog and input/output (I/O) supplies
249 mW total quiescent power
Phase-locked loop (PLL) generated or direct master clock
Low electromagnetic interference (EMI) design
Linear regulator driver to generate digital supply
Supports 24-bit and 32 kHz to 192 kHz sample rates
Low propagation 192 kHz sample rate mode
Log volume control with autoramp function
Temperature sensor with digital readout ±3°C accuracy
SPI and I2C controllable for flexibility
Software-controllable clickless mute
Software power-down
Right justified, left justified, I2S, and TDM modes
Master and slave modes with up to 12-channel input/output
80-lead LQFP package
Qualified for automotive applications
The ADAU1962A is a high performance, single-chip digital-toanalog converter (DAC) that provides 12 DACs with differential or
single-ended outputs using the Analog Devices, Inc., patented
multibit sigma-delta (Σ-Δ) architecture. A serial peripheral interface
(SPI)/I2C port is included, allowing a microcontroller to adjust
volume and many other parameters. The ADAU1962A operates
from 2.5 V digital and 3.3 V analog supplies. A linear regulator
is included to generate the digital supply voltage from the analog
supply voltage. The ADAU1962A is available in an 80-lead LQFP.
The ADAU1962A is designed for low EMI. This consideration
is apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the internal master clock from
an external left-right frame clock (LRCLK), the ADAU1962A
can eliminate the need for a separate high frequency master clock
and can be used with or without a bit clock. The DACs are
designed using the latest Analog Devices continuous time
architectures to further minimize EMI. By using 2.5 V digital
supplies, power consumption is minimized, and the digital
waveforms are a smaller amplitude, further reducing emissions.
Note that throughout this data sheet, multifunction pins, such
as SCLK/SCL, are referred to by the entire pin name or by a
single function of the pin, for example, SCLK, when only that
function is relevant.
APPLICATIONS
Automotive audio systems
Home theater systems
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT
ADAU1962A
SERIAL DATA PORT
DAC
DAC
DAC
ANALOG
AUDIO
OUTPUTS
DAC
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
SDATA
IN
SDATA
IN
CLOCKS
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
DAC
ANALOG
AUDIO
OUTPUTS
DAC
DAC
DAC
SPI/I2C
CONTROL PORT
CONTROL DATA
INPUT/OUTPUT
INTERNAL
TEMP
SENSOR
11371-001
PRECISION
VOLTAGE
REFERENCE
Figure 1.
Rev. A
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Technical Support
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ADAU1962A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
PLL and Clock Control 0 Register ........................................... 25
Applications ....................................................................................... 1
PLL and Clock Control 1 Register ........................................... 26
General Description ......................................................................... 1
Block Power-Down and Thermal Sensor Control 1 Register27
Functional Block Diagram .............................................................. 1
Power-Down Control 2 Register .............................................. 28
Revision History ............................................................................... 2
Power-Down Control 3 Register .............................................. 29
Specifications..................................................................................... 3
Thermal Sensor Temperature Readout Register .................... 29
Analog Performance Specifications: TA = 25°C ....................... 3
DAC Control 0 Register ............................................................ 30
Analog Performance Specifications: TA = 105°C ..................... 4
DAC Control 1 Register ............................................................ 31
Crystal Oscillator Specifications................................................. 4
DAC Control 2 Register ............................................................ 32
Digital Input/Output Specifications........................................... 5
DAC Individual Channel Mutes 1 Register ............................ 33
Power Supply Specifications........................................................ 5
DAC Individual Channel Mutes 2 Register ............................ 34
Digital Filters ................................................................................. 6
Master Volume Control Register.............................................. 35
Timing Specifications .................................................................. 6
DAC 1 Volume Control Register .............................................. 35
Absolute Maximum Ratings............................................................ 8
DAC 2 Volume Control Register .............................................. 36
Thermal Resistance ...................................................................... 8
DAC 3 Volume Control Register .............................................. 36
ESD Caution .................................................................................. 8
DAC 4 Volume Control Register .............................................. 37
Pin Configuration and Function Descriptions ............................. 9
DAC 5 Volume Control Register .............................................. 37
Typical Performance Characteristics ........................................... 12
DAC 6 Volume Control Register .............................................. 38
Typical Application Circuits.......................................................... 13
DAC 7 Volume Control Register .............................................. 38
Theory of Operation ...................................................................... 14
DAC 8 Volume Control Register .............................................. 39
DACs ............................................................................................ 14
DAC 9 Volume Control Register .............................................. 39
Clock Signals ............................................................................... 14
DAC 10 Volume Control Register............................................ 40
Power-Up and Reset ................................................................... 16
DAC 11 Volume Control Register............................................ 40
Standalone Mode ........................................................................ 16
DAC 12 Volume Control Register............................................ 41
I C Control Port .......................................................................... 16
Pad Strength Register ................................................................. 41
Serial Control Port: SPI Control Mode ................................... 19
DAC Power Adjust 1 Register ................................................... 42
Power Supply and Voltage Reference ....................................... 20
DAC Power Adjust 2 Register ................................................... 43
Serial Data Ports—Data Format ............................................... 20
DAC Power Adjust 3 Register ..................................................... 44
Time-Division Multiplexed (TDM) Modes ............................ 21
Outline Dimensions ....................................................................... 48
Temperature Sensor ................................................................... 21
Ordering Guide .......................................................................... 48
Additional Modes ....................................................................... 23
Automotive Products ................................................................. 48
2
Register Summary .......................................................................... 24
Register Details ............................................................................... 25
REVISION HISTORY
3/16—Rev. 0 to Rev. A
Changes to Table 4 ............................................................................ 5
7/13—Revision 0: Initial Version
Rev. A | Page 2 of 48
Data Sheet
ADAU1962A
SPECIFICATIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width =
24 bits, load capacitance (digital output) = 20 pF, load current (digital output) = ±1 mA or 1.5 kΩ to ½ DVDD supply, input voltage high = 2.0 V,
input voltage low = 0.8 V, analog audio output resistive load = 3100 Ω per pin, unless otherwise noted.
ANALOG PERFORMANCE SPECIFICATIONS: TA = 25°C
Specifications guaranteed at supply voltages of AVDDx = 3.3 V, DVDD = 2.5 V, ambient temperature1 (TA) = 25°C, unless otherwise noted.
Table 1.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range (DNR)
No Filter (RMS)
With A-Weighted Filter (RMS)
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Differential Output
Single-Ended Output
Full-Scale Differential Output Voltage
Full-Scale Single-Ended Output Voltage
Gain Error
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-Emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
REGULATOR
Input Supply Voltage
Regulated Output Voltage
TEMPERATURE SENSOR
Temperature Accuracy
Temperature Readout Range
Temperature Readout Step Size
Temperature Sample Rate
1
Test Conditions/Comments
Min
Typ
20 Hz to 20 kHz, −60 dB input
Differential output
Differential output
Single-ended output
Single-ended output
105.5
108.5
102.5
105.5
111
114
107
110
Two channels running −1 dBFS
All channels running −1 dBFS
Two channels running −1 dBFS
All channels running −1 dBFS
−97
−97
−95
−95
2.00 (2.83)
1.00 (1.41)
−10
−25
−30
−6
Max
Unit
dB
dB
dB
dB
−85
−85
−80
−80
+10
+25
+30
100
0
0.375
95.25
±0.6
33
dB
dB
dB
dB
V rms (V p-p)
V rms (V p-p)
%
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
TS_REF pin
CM pin
CM pin
1.40
1.40
1.50
1.50
1.50
1.56
1.56
V
V
V
VSUPPLY pin
VSENSE pin
3.14
2.25
3.3
2.50
3.46
2.59
V
V
+3
+140
°C
°C
°C
Hz
−3
−60
1
0.25
Functionally guaranteed at −40°C to +125°C case temperature.
Rev. A | Page 3 of 48
6
ADAU1962A
Data Sheet
ANALOG PERFORMANCE SPECIFICATIONS: TA = 105°C
Specifications guaranteed at supply voltages of AVDDx = 3.3 V, DVDD = 2.5 V, ambient temperature1 (TA) = 105°C, unless otherwise
noted.
Table 2.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range (DNR)
No Filter (RMS)
With A-Weighted Filter (RMS)
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Differential Output
Single-Ended Output
Full-Scale Differential Output Voltage
Full-Scale Single-Ended Output Voltage
Gain Error
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-Emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
REGULATOR
Input Supply Voltage
Regulated Output Voltage
TEMPERATURE SENSOR
Temperature Accuracy
Temperature Readout Range
Temperature Readout Step Size
Temperature Sample Rate
1
Test Conditions/Comments
Min
Typ
20 Hz to 20 kHz, −60 dB input
Differential output
Differential output
Single-ended output
Single-ended output
106.5
109.5
101.5
104.5
110
113
108
110
Two channels running −1 dBFS
All channels running −1 dBFS
Two channels running −1 dBFS
All channels running −1 dBFS
−92
−92
−90
−90
2.00 (2.83)
1.00 (1.41)
−10
−25
−30
−6
Max
Unit
dB
dB
dB
dB
−83
−83
−80
−80
+10
+25
+30
100
0
0.375
95.25
±0.6
33
dB
dB
dB
dB
V rms (V p-p)
V rms (V p-p)
%
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
TS_REF pin
CM pin
CM pin
1.40
1.40
1.50
1.50
1.50
1.56
1.56
V
V
V
VSUPPLY pin
VSENSE pin
3.14
2.25
3.3
2.50
3.46
2.55
V
V
+3
+140
°C
°C
°C
Hz
−3
−60
1
0.25
6
Functionally guaranteed at −40°C to +125°C case temperature.
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 3.
Parameter
TRANSCONDUCTANCE
TA = 25°C
TA = 105°C
Min
Typ
Max
Unit
6.4
5.2
7 to 10
7.5 to 8.5
14
12
mmhos
mmhos
Rev. A | Page 4 of 48
Data Sheet
ADAU1962A
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +105°C, IOVDD = 3.3 V ± 5%, unless otherwise noted.
Table 4.
Parameter
DIGITAL INPUT
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Leakage
INPUT CAPACITANCE
DIGITAL OUTPUT
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Test Conditions/Comments
Min
Typ
Max
Unit
0.3 × IOVDD
10
10
5
V
V
μA
μA
pF
0.1 × IOVDD
V
V
0.7 × IOVDD
IIH at VIH = 3.3 V
IIL at VIL = 0 V
IOH = 1 mA
IOL = 1 mA
0.8 × IOVDD
POWER SUPPLY SPECIFICATIONS
Table 5.
Parameter
SUPPLIES
Voltage
Analog Current
Normal Operation
Power-Down
Digital Current
Normal Operation
Power-Down
PLL Current
Normal Operation
Power-Down
Input/Output Current
Normal Operation
Power-Down
QUIESCENT DISSIPATION—DITHER INPUT
Operation
All Supplies
Analog Supply
Digital Supply
PLL Supply
I/O Supply
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
Test Conditions/Comments
Min
Typ
Max
Unit
AVDDx
DVDD
PLLVDD
IOVDD
VSUPPLY
AVDDx = 3.3 V
3.14
2.25
2.25
3.14
3.14
3.3
2.5
2.5
3.3
3.3
3.46
3.46
3.46
3.46
3.46
V
V
V
V
V
DVDD = 2.5 V
fS = 48 kHz to 192 kHz
No MCLK or I2S
PLLVDD = 2.5 V
fS = 48 kHz to 192 kHz
45
1
mA
μA
30
4
mA
μA
5
1
mA
μA
4
1
mA
μA
249
148
75
13
13
0
mW
mW
mW
mW
mW
mW
88
85
85
75
dB
dB
dB
dB
IOVDD = 3.3 V
MCLK = 256 × fS, 48 kHz
AVDDx = 3.3 V, DVDD/PLLVDD = 2.5 V, IOVDD = 3.3 V
AVDDx = 3.3 V, 12.4 mW per channel
DVDD = 2.5 V
PLLVDD = 2.5 V
IOVDD = 3.3 V
1 kHz, 200 mV p-p, differential
20 kHz, 200 mV p-p, differential
1 kHz, 200 mV p-p, single-ended
20 kHz, 200 mV p-p, single-ended
Rev. A | Page 5 of 48
ADAU1962A
Data Sheet
DIGITAL FILTERS
Table 6.
Parameter
DAC INTERPOLATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Propagation Delay
Mode
Factor
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
192 kHz low propagation delay mode, typical at 192 kHz
0.4535 × fS
0.3646 × fS
0.3646 × fS
Min
Typ
Max
22
35
70
±0.01
±0.05
±0.1
0.5 × fS
0.5 × fS
0.5 × fS
0.5465 × fS
0.6354 × fS
0.6354 × fS
24
48
96
26
61
122
68
68
68
25/fS
11/fS
8/fS
2/fS
521
115
42
10
Unit
kHz
kHz
kHz
dB
dB
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
μs
μs
μs
μs
TIMING SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 2.5 V ± 10%, unless otherwise noted.
Table 7.
Parameter
INPUT MASTER CLOCK (MCLKI) AND RESET
tMH
fMCLK
fBCLK
tPDR
tPDRR
PLL
Lock Time
Output Duty Cycle, MCLKO Pin
Description
Min
Master clock duty cycle, DAC clock source = PLL clock at
256 × fS, 384 × fS, 512 × fS, and 768 × fS
DAC clock source = direct MCLKI at 512 × fS (bypass onchip PLL)
MCLKI frequency of the MCLKI/XTALI pin, PLL mode
Direct MCLKI 512 × fS mode
DBCLK pin frequency, PLL mode
Low
Recovery, reset to active output
MCLKI input of the MCLKI/XTALI pin
DLRCLK pin input
256 × fS VCO clock
Rev. A | Page 6 of 48
Typ
Max
Unit
40
60
%
40
60
%
6.9
40.5
27.1
27.0
MHz
MHz
MHz
ns
ms
10
50
60
ms
ms
%
15
300
40
Data Sheet
ADAU1962A
Parameter
SPI PORT
fSCLK
tSCH
tSCL
tMOS
tMOH
tSSS
tSSH
tSSHIGH
tMIE
tMID
tMIH
tMITS
Description
See Figure 19
SCLK frequency, not shown in Figure 19
SCLK high
SCLK low
MOSI setup, time to SCLK rising
MOSI hold, time from SCLK rising
SS setup, time to SCLK rising
SS hold, time from SCLK falling
SS high
MISO enable from SS falling
MISO delay from SCLK falling
MISO hold from SCLK falling, not shown in Figure 19
MISO tristate from SS rising
2
IC
fSCL
tSCLL
tSCLH
tSCS
See Figure 2 and Figure 15
SCL clock frequency
SCL low
SCL high
Setup time (start condition), relevant for repeated start
condition
Hold time (start condition), first clock generated after
this period
Setup time (stop condition)
Data setup time
SDA and SCL rise time
SDA and SCL fall time
Bus-free time between stop and start
See Figure 21
DBCLK high, slave mode
DBCLK low, slave mode
DLRCLK setup, time to DBCLK rising, slave mode
DLRCLK hold from DBCLK rising, slave mode
DLRCLK skew from DBCLK falling, master mode
DSDATAx setup to DBCLK rising
DSDATAx hold from DBCLK rising
tSCH
tSSH
tDS
tSR
tSF
tBFT
DAC SERIAL PORT
tDBH
tDBL
tDLS
tDLH
tDLS
tDDS
tDDH
tDS
tSCH
Min
tSF
tSCS
Figure 2. I2C Timing Diagram
Rev. A | Page 7 of 48
tSSH
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
1.3
0.6
0.6
400
kHz
μs
μs
μs
0.6
μs
0.6
100
1.3
μs
ns
ns
ns
μs
10
10
10
5
−8
10
5
ns
ns
ns
ns
ns
ns
ns
300
300
tSCLH
tSCLL
10
30
tSCH
tBFT
Unit
30
30
11371-002
SCL
Max
35
35
10
10
10
10
10
SDA
tSR
Typ
+8
ADAU1962A
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
Parameter
Analog (AVDDx)
Input/Output (IOVDD)
Digital (DVDD)
PLL (PLLVDD)
VSUPPLY
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Case)
Storage Temperature Range
Rating
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
±20 mA
–0.3 V to AVDDx + 0.3 V
−0.3 V to DVDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
θJA represents junction-to-ambient thermal resistance, and
θJC represents the junction-to-case thermal resistance. All
characteristics are for a 4-layer board with a solid ground plane.
Table 9. Thermal Resistance
Package Type
80-Lead LQFP
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 8 of 48
θJA
42.3
θJC
10.0
Unit
°C/W
Data Sheet
ADAU1962A
DAC_BIAS3 1
AGND2
69
CM
70
TS_REF
71
DAC5P
72
DAC5N
73
DAC6P
74
DAC7P
DAC7N
75
DAC6N
DAC8P
76
DAC8N
DAC11P
77
DAC9P
DAC11N
78
DAC9N
DAC12P
79
DAC10N
DAC12N
80
DAC10P
AGND3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
68
67
66
65
64
63
62
61
60 DAC_BIAS2
PIN 1
INDICATOR
DAC_BIAS4 2
59 DAC_BIAS1
AVDD3 3
58 AVDD2
NC 4
57 DAC4N
NC 5
56 DAC4P
NC 6
55 DAC3N
NC 7
54 DAC3P
NC 8
53 DAC2N
NC 9
52 DAC2P
ADAU1962A
NC 10
51 DAC1N
TOP VIEW
(Not to Scale)
NC 11
50 DAC1P
AVDD4 12
49 AVDD1
AGND4 13
48 AGND1
PLLGND 14
47 PU/RST
LF 15
46 SA_MODE
PLLVDD 16
45 SS/ADDR0/SA
MCLKI/XTALI 17
44 SCLK/SCL
XTALO 18
43 MISO/SDA/SA
MCLKO 19
42 MOSI/ADDR1/SA
DVDD 20
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DGND
VSENSE
VDRIVE
VSUPPLY
DGND
DBCLK
DLRCLK
DVDD
DGND
SA1
SA2
DSDATA6
DSDATA5
DSDATA4
DSDATA3
DSDATA2
DSDATA1
IOVDD
DGND
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. SEE THE STANDALONE MODE SECTION (TABLE 13 AND TABLE 14) FOR THE SA_MODE SETTINGS
FOR PIN 31, PIN 32, PIN 42, PIN 43, AND PIN 45.
11371-003
21
IOVDD
41 DVDD
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
1
2
3
4 to 11
12
13
14
15
16
17
18
19
20, 29, 41
21, 26, 30, 40
22, 39
23
Mnemonic1, 2
DAC_BIAS3
DAC_BIAS4
AVDD3
NC
AVDD4
AGND4
PLLGND
LF
PLLVDD
MCLKI/XTALI
XTALO
MCLKO
DVDD
DGND
IOVDD
VSENSE
Type3
I
I
PWR
NC
PWR
GND
GND
O
PWR
I
O
O
PWR
GND
PWR
I
24
VDRIVE
O
Description
DAC Bias 3. AC couple with a 470 nF to AGND3.
DAC Bias 4. AC couple with a 470 nF to AVDD3.
Analog Power.
No Connect. Do not connect to these pins.
Analog Power.
Analog Ground.
PLL Ground.
PLL Loop Filter. Reference the LF pin to PLLVDD.
PLL Power. Apply 2.5 V to power the PLL.
Master Clock Input/Input to Crystal Inverter. This is a multifunction pin.
Output from Crystal Inverter.
Master Clock Output.
Digital Power, 2.5 V.
Digital Ground.
Power for Digital Input and Output Pins, 3.3 V.
2.5 V Regulator Output, Pass Transistor Collector. Bypass VSENCE with a 10 μF capacitor in
parallel with a 100 nF capacitor.
Pass Transistor Base Driver.
Rev. A | Page 9 of 48
ADAU1962A
Data Sheet
Pin No.
25
Mnemonic1, 2
VSUPPLY
Type3
I
27
28
31
DBCLK
DLRCLK
SA1
I/O
I/O
I
32
SA2
I
33
34
35
36
37
38
42
DSDATA6
DSDATA5
DSDATA4
DSDATA3
DSDATA2
DSDATA1
MOSI/ADDR1/SA
I
I
I
I
I
I
I
43
MISO/SDA/SA
I/O
44
45
SCLK/SCL
SS/ADDR0/SA
I
I
46
SA_MODE
I
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
PU/RST
AGND1
AVDD1
DAC1P
DAC1N
DAC2P
DAC2N
DAC3P
DAC3N
DAC4P
DAC4N
AVDD2
DAC_BIAS1
DAC_BIAS2
AGND2
CM
I
GND
PWR
O
O
O
O
O
O
O
O
PWR
I
I
GND
O
63
TS_REF
O
64
65
66
67
68
69
70
71
72
73
74
75
DAC5P
DAC5N
DAC6P
DAC6N
DAC7P
DAC7N
DAC8P
DAC8N
DAC9P
DAC9N
DAC10P
DAC10N
O
O
O
O
O
O
O
O
O
O
O
O
Description
3.3 V Voltage Regulator Input, Pass Transistor Emitter. Bypass VSUPPLY with a 10 μF capacitor
in parallel with a 100 nF capacitor.
Bit Clock for DACs.
Frame Clock for DACs.
Standalone Mode, Time Domain Multiplexed (SA_MODE TDM) State. See the Standalone
Mode section, Table 13, and Table 14 for more information.
Standalone Mode, Time Domain Multiplexed (SA_MODE TDM) State. See the Standalone
Mode section, Table 13, and Table 14 for more information.
DAC11 and DAC 12 Serial Data Input.
DAC9 and DAC 10 Serial Data Input.
DAC7 and DAC 8 Serial Data Input.
DAC5 and DAC 6 Serial Data Input.
DAC3 and DAC 4 Serial Data Input.
DAC1 and DAC 2 Serial Data Input.
Master Output Slave Input (SPI)/Address 1 (I2C)/SA_MODE State (see the Standalone Mode
section and Table 13).
Master Output Slave Input (SPI)/Control Data Input (I2C)/SA_MODE State (see the Standalone
Mode section and Table 13).
Serial Clock Input (SPI)/Control Clock Input (I2C)
Slave Select (SPI) (Active Low)/Address 0 (I2C)/SA_MODE State (see the Standalone Mode
section and Table 13).
Standalone Mode. This pin allows mode control of ADAU1962A using Pin 42, Pin 43, and
Pin 45, Pin 31, and Pin 32 (high active). See Table 13 and Table 14 for more information.
Power-Up/Reset (Active Low). See the Power-Up and Reset section for more information.
Analog Ground.
Analog Power.
DAC1 Positive Output.
DAC1 Negative Output.
DAC2 Positive Output.
DAC2 Negative Output.
DAC3 Positive Output.
DAC3 Negative Output.
DAC4 Positive Output.
DAC4 Negative Output.
Analog Power.
DAC Bias 1. AC couple Pin 59 with a 470 nF capacitor to AVDD2.
DAC Bias 2. AC couple Pin 60 with a 470 nF capacitor to AGND2.
Analog Ground.
Common-Mode Reference Filter Capacitor Connection. Bypass the CM pin with a 10 μF capacitor in
parallel with a 100 nF capacitor to AGND2. This reference can be shut off in the PLL_CLK_CTRL1
register (Register 0x01) and the pin can be driven with an outside voltage source.
Voltage Reference Filter Capacitor Connection. Bypass Pin 63 with a 10 μF capacitor in parallel with
a 100 nF capacitor to AGND2.
DAC5 Positive Output.
DAC5 Negative Output.
DAC6 Positive Output.
DAC6 Negative Output.
DAC7 Positive Output.
DAC7 Negative Output.
DAC8 Positive Output.
DAC8 Negative Output.
DAC9 Positive Output.
DAC9 Negative Output.
DAC10 Positive Output.
DAC10 Negative Output.
Rev. A | Page 10 of 48
Data Sheet
Pin No.
76
77
78
79
80
1
2
3
Mnemonic1, 2
DAC11P
DAC11N
DAC12P
DAC12N
AGND3
ADAU1962A
Type3
O
O
O
O
GND
Description
DAC11 Positive Output.
DAC11 Negative Output.
DAC12 Positive Output.
DAC12 Negative Output.
Analog Ground.
AVDD1, AVDD2, AVDD3, and AVDD4 are referred to elsewhere in this document as AVDDx when AVDDx means any or all of the ADVD pins.
DAC Channel 1 to DAC Channel 12 pins are referred to elsewhere in this document as DACx, DACxP, or DACxN when it means any or all of the DAC channel pins.
I = input, O = output, I/O = input/output, PWR = power, and GND = ground, and NC = no connect.
Rev. A | Page 11 of 48
ADAU1962A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.05
0.20
0.04
0.15
0.03
0.10
MAGNITUDE (dB)
MAGNITUDE (dB)
0.02
0.01
0
–0.01
0.05
0
–0.05
–0.02
–0.10
–0.03
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
FREQUENCY (FACTORED TO fS)
–0.20
0
–20
–20
–30
–30
MAGNITUDE (dB)
0
–10
–40
–50
–60
–80
–90
–90
–100
–100
0.4
0.5
0.6
0.7
0.8
0.9
0.30
0.35
0.40
1.0
–60
–70
0.3
0.25
–50
–80
FREQUENCY (FACTORED TO fS)
0.20
–40
–70
1.0
11371-005
MAGNITUDE (dB)
0
0.2
0.15
Figure 6. DAC Pass-Band Filter Response, 96 kHz
–10
0.1
0.10
FREQUENCY (FACTORED TO fS)
Figure 4. DAC Pass-Band Filter Response, 48 kHz
0
0.05
11371-006
0
11371-004
–0.05
11371-007
–0.15
–0.04
Figure 5. DAC Stop-Band Filter Response, 48 kHz
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
FREQUENCY (FACTORED TO fS)
Figure 7. DAC Stop-Band Filter Response, 96 kHz
Rev. A | Page 12 of 48
Data Sheet
ADAU1962A
TYPICAL APPLICATION CIRCUITS
Typical application circuits are shown in Figure 8 to Figure 13.
Recommended loop filters for DLRCLK and MCLKI/XTALI
modes of the PLL reference are shown in Figure 8. Output filters
for the DAC outputs are shown in Figure 10 to Figure 13, and
an external regulator circuit is shown in Figure 9. When pins for
multiple outputs are referred to generically in this datasheet, there
is an x in place of the number. For example, DACxP refers to
DAC1P through DAC12P.
DLRCLK
LF
VSENSE
2.5V
+
10µF
11371-013
100nF
Figure 9. Recommended 2.5 V Regulator Circuit
562Ω
DACxP
PLLVDD
10µF
+
237Ω
11371-008
OUTPUTxP
2.7nF
Figure 8. Recommended Loop Filters for DLRCLK and MCLKI/XTALI PLL
Reference Modes
DACxN
10µF
+
237Ω
OUTPUTxN
49.9kΩ
11371-009
49.9kΩ
Figure 10. Typical DAC Output Passive Filter Circuit (Differential)
10µF
475Ω
2.7nF
OUTPUTxP
49.9kΩ
11371-010
DACxP
+
PLLVDD
FZT953
C
390pF
3.32kΩ
E
B
VDRIVE
5.6nF
2.2nF
3.3V
1kΩ
MCLKI/XTALI
39nF
10µF
+
Figure 11. Typical DAC Output Passive Filter Circuit (Single-Ended)
1.1nF
AD8672ARZ
DACxP
1.50kΩ
1.54kΩ
5
100Ω
7
4.7µF
+
OUTPUTxP
6
+12V DC
422Ω
2.49kΩ
100kΩ
8
0.1µF
4.7µF
0.1µF
4.7µF
+
1nF
4.7µF
1nF
4.7µF
+
V+
V–
4
+
+
100kΩ
–12V DC
DACxN
2
1.50kΩ
422Ω
2.49kΩ
100Ω
1
1.54kΩ
3
4.7µF
+
OUTPUTxN
11371-011
AD8672ARZ
1.1nF
Figure 12. Typical DAC Output Active Filter Circuit (Differential)
1.1nF
1.50kΩ
1.54kΩ
AD8672ARZ
100Ω 4.7µF
+
DACxP
1nF
422Ω
2.49kΩ
4.7µF
OUTPUTxP
100kΩ
+
Figure 13. Typical DAC Output Active Filter Circuit (Single-Ended)
Rev. A | Page 13 of 48
11371-012
LF
100nF
VSUPPLY
ADAU1962A
Data Sheet
THEORY OF OPERATION
DACs
The 12 ADAU1962A DAC channels are differential for improved
noise and distortion performance and are voltage output for
simplified connection. The DACs include on-chip digital
interpolation filters with 68 dB stop-band attenuation and linear
phase response, operating at an oversampling ratio of 256×
(48 kHz range), 128× (96 kHz range), or 64× (192 kHz range).
Each channel has its own independently programmable
attenuator, adjustable in 255 steps in increments of 0.375 dB.
Digital inputs are supplied through six serial data input pins
(two channels on each pin), a common frame clock (DLRCLK),
and a bit clock (DBCLK). Alternatively, any one of the TDM modes
can be used to access up to 12 channels on a single TDM data line.
The ADAU1962A has a low propagation delay mode; this
mode is an option for an fS of 192 kHz and is enabled in Register
DAC_CTRL0[2:1]. By setting these bits to 0b11, the propagation
delay is reduced by the amount shown in Table 6. The shorter delay
is achieved by reducing the amount of digital filtering; the negative
impact of selecting this mode is reduced audio frequency response
and increased out-of-band energy.
Because AVDD is supplied with 3.3 V, each analog output pin
has a nominal common-mode (CM) dc level of 1.5 V. With a 0 dB
full-scale digital input signal, each pin swings approximately
±1.42 V peak (2.83 V p-p and 2 V rms). Therefore, the voltage
swing differentially across the two pins is 5.66 V p-p (4 V rms). The
differential analog outputs require a single-order passive differential
resistor-capacitor (RC) filter only to provide the specified DNR
performance; see Figure 10 or Figure 11 for an example filter. The
outputs can easily drive differential inputs on a separate printed
circuit board (PCB) through cabling as well as differential inputs
on the same PCB.
If more signal level is required, or if a more robust filter is needed,
a single op amp gain stage designed as a second-order, low-pass
Bessel filter can be used to remove the high frequency out-ofband noise present on each pin of the differential outputs. The
choice of components and design of this circuit is critical to yield
the full DNR of the DACs (see the recommended passive and
active circuits in Figure 10, Figure 11, Figure 12, and Figure 13).
The differential filter can be built into an active difference amplifier
to provide a single-ended output with gain, if necessary. Note that
the use of op amps with low slew rate or low bandwidth can cause
high frequency noise and tones to fold down into the audio
band; exercise care when selecting these components.
The ADAU1962A offers control over the analog performance
of the DACs; it is possible to program the registers to reduce the
power consumption with the trade-off of lower SNR and THD + N.
Table 11. DAC Power vs. Performance
Register Setting
Total AVDDx Current
SNR
THD + N (−1 dBFS Signal)
Best Performance
45 mA
Reference
Reference
The reduced power consumption is the result of changing the
internal bias current to the analog output amplifiers.
Register DAC_POWER1 to Register DAC_POWER3 present four
basic settings for the DAC power vs. performance in each of the
12 channels: best performance, good performance, lower power,
and lowest power. Alternatively, in Register PLL_CLK_CTRL1[7:6],
the LOPWR_MODE bits offer global control over the power and
performance for all 12 channels. To select the lower power or
lowest power settings, set Bit 7 and Bit 6 of the DAC_POWERx
registers to 0b10 or 0b11, respectively. The default setting is 0b00.
This setting allows the channels to be controlled individually
using the DAC_POWERx registers. The data presented in Table 11
shows the result of setting all 12 channels to each of the four
settings. The SNR and THD + N specifications are shown in
relation to the measured performance of a device at the best
performance setting.
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
CLOCK SIGNALS
Upon powering the ADAU1962A and asserting the PU/RST pin
high, the part starts in either standalone mode (SA_MODE) or
program mode, depending on the state of SA_MODE (Pin 46).
The clock functionality of SA_MODE is described in the
Standalone Mode section.
In program mode, the default for the ADAU1962A is for the
MCLKO pin to feed a buffered output of the MCLKI signal on
the MCLKI/XTALI pin. The default for the DLRCLK and
DBCLK ports is slave mode; the DAC must be driven with a
coherent set of master clock, frame clock, and bit clock signals
to function.
The MCLKO pin can be programmed to provide different clock
signals using Register PLL_CLK_CTRL1[5:4]. The default, 0b10,
provides a buffered copy of the clock signal that is driving the
MCLKI pin. Two modes, 0b00 and 0b01, provide low jitter clock
signals.
The b00 setting yields a clock rate between 4 MHz and 6 MHz,
and the b01 setting yields a clock rate between 8 MHz and 12 MHz.
Both of these clock frequencies are scaled as ratios of master
clock automatically inside the ADAU1962A. As an example, an
input to MCLKI of 8.192 MHz and a setting of 0b00 yield an
MCLKO frequency of (8.192/2) = 4.096 MHz. Alternatively, an
MCLKI of 36.864 MHz and a setting of 0b01 yield an MCLKO
frequency of (36.864/3) = 12.288 MHz. The 0b11 setting disables
the MCLKO pin.
Good Performance
40 mA
−0.2 dB
−1.8 dB
Rev. A | Page 14 of 48
Low Power
35 mA
−1.5 dB
−3.0 dB
Lowest Power
30 mA
−14.2 dB
−5.8 dB
Data Sheet
ADAU1962A
After the PU/RST pin is asserted high, the PLL_CLK_CTRLx
registers (Register 0x00 and Register 0x01) can be programmed.
The on-chip PLL can be selected to use the clock appearing at the
MCLKI/XTALI pin at a frequency of 256, 384, 512, or 768 times
the sample rate (fS), referenced to the 48 kHz mode from the
master clock select (MCS) setting, as described in Table 12.
In 96 kHz mode, the master clock frequency stays at the same
absolute frequency; therefore, the actual multiplication rate is
divided by 2. In 192 kHz mode, the actual multiplication rate is
divided by 4.
For example, if the ADAU1962A is programmed in 256 × fS
mode, the frequency of the master clock input is 256 × 48 kHz =
12.288 MHz. If the ADAU1962A is then switched to 96 kHz
operation (by writing to DAC_CTRL0[2:1]), the frequency of the
master clock remains at 12.288 MHz, which is an MCS ratio of
128 × fS in this example. Therefore, in 192 kHz mode, MCS
becomes 64 × fS. The internal clock for the digital core varies
by mode: 512 × fS (48 kHz mode), 256 × fS (96 kHz mode), or
128 × fS (192 kHz mode). By default, the on-board PLL generates
this internal master clock from an external clock.
The PLL must be powered and stable before using the
ADAU1962A as a source for quality audio. The PLL is enabled
by reset and does not require writing to the I2C or SPI port for
normal operation.
With the PLL enabled, the performance of the ADAU1962A is
not affected by jitter as high as a 300 ps rms time interval error
(TIE). When the internal PLL is disabled, use an independent
crystal oscillator to generate the master clock.
When using the ADAU1962A in direct master clock mode, power
down the PLL in the PDN_THRMSENS_CTRL_1 register. For
direct master clock mode, a frequency of 512 × fS (referenced to
48 kHz mode) must be fed into the MCLKI pin, and the CLK_SEL
bit in the PLL_CLK_CTRL1 register must be set to 1. However,
for the device to function, 2.5 V power must be connected to
the PLLVDD pin.
The PLL of the ADAU1962A can also be programmed to run from
an external LRCLK. Setting the PLLIN bits in the PLL_CLK_CTRL0
register to 0b01, and connecting the appropriate loop filter to the
LF pin (see Figure 8), the PLL generates all of the necessary
internal clocks for operation with no external master clock. This
mode reduces the number of high frequency signals in the
design, reducing EMI emissions.
It is possible to further reduce EMI emissions of the circuit by using
the internal bit clock generation setting of the BCLK_GEN bit in
the DAC_CTRL1 register. Setting the BCLK_GEN bit to 1
(internal) and the SAI_MS bit to 0 (slave), the ADAU1962A
generates its own bit clock; this configuration works with the
PLL input register (PLL_CLK_CTRL0[7:6]) set to either
MCLKI/XTALI or DLRCLK. The clock on the DLRCLK pin is the
only required clock in DLRCLK PLL mode.
Table 12. MCS and fS Modes
Frequency Sample Select
DAC_CTRL0[2:1]
fS (kHz)
Bit Setting
32
44.1
48
64
88.2
96
128
176.4
192
0b00
0b00
0b00
0b01
0b01
0b01
0b10 or 0b11
0b10 or 0b11
0b10 or 0b11
Setting 0, 0b00
Master Clock
Ratio
(MHz)
256 × fS 8.192
256 × fS 11.2896
256 × fS 12.288
128 × fS 8.192
128 × fS 11.2896
128 × fS 12.288
64 × fS
8.192
64 × fS
11.2896
64 × fS
12.288
Master Clock Select (MCS), PLL_CLK_CTRL0[2:1]
Setting 1, 0b01
Setting 2, 0b10
Master Clock
Master Clock
Ratio
(MHz)
Ratio
(MHz)
384 × fS 12.288
512 × fS 16.384
384 × fS 16.9344
512 × fS 22.5792
384 × fS 18.432
512 × fS 24.576
192 × fS 12.288
256 × fS 16.384
192 × fS 16.9344
256 × fS 22.5792
192 × fS 18.432
256 × fS 24.576
96 × fS
12.288
128 × fS 16.384
96 × fS
16.9344
128 × fS 22.5792
96 × fS
18.432
128 × fS 24.576
Rev. A | Page 15 of 48
Setting 3, 0b11
Master Clock
Ratio
(MHz)
768 × fS 24.576
768 × fS 33.8688
768 × fS 36.864
384 × fS 24.576
384 × fS 33.8688
384 × fS 36.864
192 × fS 24.576
192 × fS 33.8688
192 × fS 36.864
ADAU1962A
Data Sheet
POWER-UP AND RESET
Power sequencing for the ADAU1962A must start with AVDDx
and IOVDD, followed by DVDD. It is very important that AVDDx
be settled at a regulated voltage and that IOVDD be within 10% of
regulated voltage before applying DVDD. When using the internal
regulator of the ADAU1962A, this timing occurs by default.
To guarantee proper startup, pull the PU/RST pin low by an
external resistor and then drive it high after the power supplies
have stabilized. The PU/RST can also be pulled high using a
simple RC network.
When both SA_MODE (Pin 46) and SS/ADDR0/SA (Pin 45) are
set high, TDM mode is selected. Table 14 shows the available
TDM modes; these modes are set by connecting Pin 31 (SA1) and
Pin 32 (SA2) to GND or IOVDD.
Table 14. TDM Modes
Pin No.
31 to 32
Setting
00
01
10
11
Function
TDM4, DLRCLK pulse
TDM8, DLRCLK pulse
TDM16, DLRCLK pulse
TDM8, DLRCLK 50% duty cycle
Driving the PU/RST pin low puts the part into a very low power
state (
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