Blackfin
Embedded Processor
ADSP-BF531/ADSP-BF532/ADSP-BF533
FEATURES
PERIPHERALS
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages (see Operating Conditions
on Page 20)
Qualified for Automotive Applications (see Automotive Products on Page 62)
Programmable on-chip voltage regulator
160-ball CSP_BGA, 169-ball PBGA, and 176-lead LQFP
packages
Parallel peripheral interface PPI, supporting
ITU-R 656 video data formats
2 dual-channel, full duplex synchronous serial ports, supporting eight stereo I2S channels
2 memory-to-memory DMAs
8 peripheral DMAs
SPI-compatible port
Three 32-bit timer/counters with PWM support
Real-time clock and watchdog timer
32-bit core timer
Up to 16 general-purpose I/O pins (GPIO)
UART with support for IrDA
Event handler
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
MEMORY
Up to 148K bytes of on-chip memory (see Table 1 on Page 3)
Memory management unit providing memory protection
External memory controller with glueless support for
SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI and
external memory
B
INTERRUPT
CONTROLLER
L1
DATA
MEMORY
DMA
CONTROLLER
DMA CORE BUS
EXTERNAL ACCESS BUS
DMA
EXTERNAL
BUS
EXTERNAL PORT
FLASH, SDRAM CONTROL
WATCHDOG
TIMER
RTC
PPI
DMA ACCESS BUS
L1
INSTRUCTION
MEMORY
PERIPHERAL ACCESS BUS
JTAG TEST AND EMULATION
VOLTAGE REGULATOR
TIMER0-2
GPIO
PORT
F
SPI
UART
SPORT0-1
16
BOOT ROM
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. I
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ADSP-BF531/ADSP-BF532/ADSP-BF533
TABLE OF CONTENTS
Features ................................................................. 1
Development Tools .............................................. 15
Memory ................................................................ 1
Additional Information ........................................ 16
Peripherals ............................................................. 1
Related Signal Chains ........................................... 16
General Description ................................................. 3
Pin Descriptions .................................................... 17
Portable Low Power Architecture ............................. 3
Specifications ........................................................ 20
System Integration ................................................ 3
Operating Conditions ........................................... 20
Processor Peripherals ............................................. 3
Electrical Characteristics ....................................... 22
Blackfin Processor Core .......................................... 4
Absolute Maximum Ratings ................................... 25
Memory Architecture ............................................ 4
ESD Sensitivity ................................................... 25
DMA Controllers .................................................. 8
Package Information ............................................ 26
Real-Time Clock ................................................... 8
Timing Specifications ........................................... 27
Watchdog Timer .................................................. 9
Output Drive Currents ......................................... 43
Timers ............................................................... 9
Test Conditions .................................................. 45
Serial Ports (SPORTs) ............................................ 9
Thermal Characteristics ........................................ 49
Serial Peripheral Interface (SPI) Port ....................... 10
160-Ball CSP_BGA Ball Assignment ........................... 50
UART Port ........................................................ 10
169-Ball PBGA Ball Assignment ................................. 53
General-Purpose I/O Port F ................................... 10
176-Lead LQFP Pinout ............................................ 56
Parallel Peripheral Interface ................................... 11
Outline Dimensions ................................................ 58
Dynamic Power Management ................................ 11
Surface-Mount Design .......................................... 61
Voltage Regulation .............................................. 13
Automotive Products .............................................. 62
Clock Signals ..................................................... 13
Ordering Guide ..................................................... 63
Booting Modes ................................................... 14
Instruction Set Description ................................... 15
REVISION HISTORY
8/13— Rev. H to Rev. I
Updated Development Tools .................................... 15
Corrected Conditions value of the VIL specification in
Operating Conditions ............................................. 20
Added notes to Table 30 in
Serial Ports—Enable and Three-State .......................... 36
Added Timer Clock Timing ...................................... 41
Revised Timer Cycle Timing ..................................... 41
Updated Ordering Guide ......................................... 63
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ADSP-BF531/ADSP-BF532/ADSP-BF533
GENERAL DESCRIPTION
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are
members of the Blackfin® family of products, incorporating the
Analog Devices, Inc./Intel Micro Signal Architecture (MSA).
Blackfin processors combine a dual-MAC state-of-the-art signal
processing engine, the advantages of a clean, orthogonal RISClike microprocessor instruction set, and single instruction, multiple data (SIMD) multimedia capabilities into a single
instruction set architecture.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are
completely code and pin-compatible, differing only with respect
to their performance and on-chip memory. Specific performance and memory configurations are shown in Table 1.
ADSP-BF532
SPORTs
UART
SPI
GP Timers
Watchdog Timers
RTC
Parallel Peripheral Interface
GPIOs
L1 Instruction SRAM/Cache
L1 Instruction SRAM
L1 Data SRAM/Cache
L1 Data SRAM
L1 Scratchpad
L3 Boot ROM
2
1
1
3
1
1
1
16
16K bytes
16K bytes
16K bytes
2
1
1
3
1
1
1
16
16K bytes
32K bytes
32K bytes
Maximum Speed Grade
Package Options:
CSP_BGA
Plastic BGA
LQFP
400 MHz 400 MHz 600 MHz
Memory Configuration
Features
4K bytes
1K bytes
ADSP-BF533
ADSP-BF531
Table 1. Processor Comparison
2
1
1
3
1
1
1
16
16K bytes
64K bytes
32K bytes
32K bytes
4K bytes 4K bytes
1K bytes 1K bytes
160-Ball 160-Ball 160-Ball
169-Ball 169-Ball 169-Ball
176-Lead 176-Lead 176-Lead
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like programmability, multimedia support, and leading-edge signal
processing in one integrated package.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature
dynamic power management—the ability to vary both the voltage and frequency of operation to significantly lower overall
power consumption. Varying the voltage and frequency can
result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This
translates into longer battery life for portable appliances.
SYSTEM INTEGRATION
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are
highly integrated system-on-a-chip solutions for the next generation of digital communication and consumer multimedia
applications. By combining industry-standard interfaces with a
high performance signal processing core, users can develop
cost-effective solutions quickly without the need for costly
external components. The system peripherals include a UART
port, an SPI port, two serial ports (SPORTs), four general-purpose timers (three with PWM capability), a real-time clock, a
watchdog timer, and a parallel peripheral interface.
PROCESSOR PERIPHERALS
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors contain a rich set of peripherals connected to the core via several
high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the
functional block diagram in Figure 1 on Page 1). The generalpurpose peripherals include functions such as UART, timers
with PWM (pulse-width modulation) and pulse measurement
capability, general-purpose I/O pins, a real-time clock, and a
watchdog timer. This set of functions satisfies a wide variety of
typical system support needs and is augmented by the system
expansion capabilities of the part. In addition to these generalpurpose peripherals, the processors contain high speed serial
and parallel ports for interfacing to a variety of audio, video, and
modem codec functions; an interrupt controller for flexible
management of interrupts from the on-chip peripherals or
external sources; and power management control functions to
tailor the performance and power characteristics of the processor and system to many application scenarios.
All of the peripherals, except for general-purpose I/O, real-time
clock, and timers, are supported by a flexible DMA structure.
There is also a separate memory DMA channel dedicated to
data transfers between the processor’s various memory spaces,
including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough
bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals.
The processors include an on-chip voltage regulator in support
of the processor’s dynamic power management capability. The
voltage regulator provides a range of core voltage levels from
VDDEXT. The voltage regulator can be bypassed at the user’s
discretion.
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ADSP-BF531/ADSP-BF532/ADSP-BF533
BLACKFIN PROCESSOR CORE
As shown in Figure 2 on Page 5, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the
register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and
population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of
video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average
operations, and 8-bit subtract/absolute value/accumulate (SAA)
operations. Also provided are the compare/select and vector
search instructions.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). Quad 16-bit operations
are possible using the second ALU.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
Rev. I
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In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors view
memory as a single unified 4G byte address space, using 32-bit
addresses. All resources, including internal memory, external
memory, and I/O control registers, occupy separate sections of
this common address space. The memory portions of this
address space are arranged in a hierarchical structure to provide
a good cost/performance balance of some very fast, low latency
on-chip memory as cache or SRAM, and larger, lower cost and
performance off-chip memory systems. See Figure 3, Figure 4,
and Figure 5 on Page 6.
The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of
physical memory.
The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code or
data between the internal memory and the external
memory spaces.
Internal (On-Chip) Memory
The processors have three blocks of on-chip memory that provide high bandwidth access to the core.
The first block is the L1 instruction memory, consisting of up to
80K bytes SRAM, of which 16K bytes can be configured as a
four way set-associative cache. This memory is accessed at full
processor speed.
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
ADDRESS ARITHMETIC UNIT
I3
L3
B3
M3
I2
L2
B2
M2
I1
L1
B1
M1
I0
L0
B0
M0
SP
FP
P5
DAG1
P4
P3
DAG0
P2
DA1 32
P1
DA0 32
TO MEMORY
P0
32
PREG
32
RAB
SD 32
LD1 32
LD0 32
ASTAT
32
32
R7.H
R6.H
R7.L
R6.L
R5.H
R5.L
R4.H
R4.L
R3.H
R3.L
R2.H
R2.L
R1.H
R1.L
R0.H
R0.L
SEQUENCER
ALIGN
16
16
8
8
8
8
DECODE
BARREL
SHIFTER
40
40
40
A0
32
40
A1
LOOP BUFFER
CONTROL
UNIT
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
The second on-chip memory block is the L1 data memory, consisting of one or two banks of up to 32K bytes. The memory
banks are configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM, which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the external bus interface unit
(EBIU). This 16-bit interface provides a glueless connection to a
bank of synchronous DRAM (SDRAM) as well as up to four
banks of asynchronous memory devices including flash,
EPROM, ROM, SRAM, and memory mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128M bytes of SDRAM. The SDRAM controller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
Rev. I
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1M byte segment regardless of the size of the devices used, so
that these banks are only contiguous if each is fully populated
with 1M byte of memory.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one containing the control MMRs for all core functions,
and the other containing the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs
are accessible only in supervisor mode and appear as reserved
space to on-chip peripherals.
Booting
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors contain a small boot kernel, which configures the appropriate
peripheral for booting. If the processors are configured to boot
from boot ROM memory space, the processor starts executing
from the on-chip boot ROM. For more information, see Booting Modes on Page 14.
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
0xFFFF FFFF
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
0xFFC0 0000
RESERVED
RESERVED
0xFFB0 1000
0xFFB0 1000
0xFFB0 0000
0xFFB0 0000
RESERVED
RESERVED
0xFFA1 4000
INTERNAL MEMORY MAP
0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 0000
RESERVED
0xFFA0 C000
INSTRUCTION SRAM (16K BYTE)
0xFFA0 8000
RESERVED
0xFFA0 0000
RESERVED
0xFF90 8000
RESERVED
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 0000
INSTRUCTION SRAM (64K BYTE)
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM/CACHE (16K BYTE)
0xFF90 4000
DATA BANK B SRAM (16K BYTE)
INTERNAL MEMORY MAP
SCRATCHPAD SRAM (4K BYTE)
SCRATCHPAD SRAM (4K BYTE)
0xFF90 0000
RESERVED
0xFF90 4000
0xFF80 8000
DATA BANK A SRAM/CACHE (16K BYTE)
RESERVED
0xFF80 8000
0xFF80 4000
DATA BANK A SRAM (16K BYTE)
DATA BANK A SRAM/CACHE (16K BYTE)
0xFF80 4000
0xFF80 0000
RESERVED
RESERVED
RESERVED
EXTERNAL MEMORY MAP
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
EXTERNAL MEMORY MAP
0xEF00 0000
0xEF00 0000
SDRAM MEMORY (16M BYTE TO 128M BYTE)
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
0x0000 0000
Figure 3. ADSP-BF531 Internal/External Memory Map
Figure 5. ADSP-BF533 Internal/External Memory Map
Event Handling
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTE)
The event controller on the processors handle all asynchronous
and synchronous events to the processor. The ADSP-BF531/
ADSP-BF532/ADSP-BF533 processors provide event handling
that supports both nesting and prioritization. Nesting allows
multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes
precedence over servicing of a lower priority event. The controller provides support for five different types of events:
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
INTERNAL MEMORY MAP
0xFFB0 0000
RESERVED
0xFFA1 4000
INSTRUCTION SRAM/CACHE (16K BYTE)
0xFFA1 0000
INSTRUCTION SRAM (32K BYTE)
0xFFA0 8000
RESERVED
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM/CACHE (16K BYTE)
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
0xFF90 4000
• Reset – This event resets the processor.
RESERVED
0xFF80 8000
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shutdown of the system.
DATA BANK A SRAM/CACHE (16K BYTE)
0xFF80 4000
RESERVED
0xEF00 0000
EXTERNAL MEMORY MAP
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTE)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTE)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTE)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTE)
0x2000 0000
RESERVED
0x0800 0000
• Exceptions – Events that occur synchronously to program
flow (i.e., the exception is taken before the instruction is
allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
SDRAM MEMORY (16M BYTE TO 128M BYTE)
0x0000 0000
Figure 4. ADSP-BF532 Internal/External Memory Map
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors’ event
controller consists of two stages, the core event controller (CEC)
and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize
and control all system events. Conceptually, interrupts from the
peripherals enter into the SIC, and are then routed directly into
the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority interrupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the processor. Table 2 describes the
inputs to the CEC, identifies their names in the event vector
table (EVT), and lists their priorities.
Table 2. Core Event Controller (CEC)
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
Emulation/Test Control
Reset
Nonmaskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
EVT Entry
EMU
RST
NMI
EVX
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Peripheral Interrupt Event
PLL Wakeup
DMA Error
PPI Error
SPORT 0 Error
SPORT 1 Error
SPI Error
UART Error
Real-Time Clock
DMA Channel 0 (PPI)
DMA Channel 1 (SPORT 0 Receive)
DMA Channel 2 (SPORT 0 Transmit)
DMA Channel 3 (SPORT 1 Receive)
DMA Channel 4 (SPORT 1 Transmit)
DMA Channel 5 (SPI)
DMA Channel 6 (UART Receive)
DMA Channel 7 (UART Transmit)
Timer 0
Timer 1
Timer 2
Port F GPIO Interrupt A
Port F GPIO Interrupt B
Memory DMA Stream 0
Memory DMA Stream 1
Software Watchdog Timer
Default Mapping
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG12
IVG12
IVG13
IVG13
IVG13
Event Control
The processors provide a very flexible mechanism to control the
processing of events. In the CEC, three registers are used to
coordinate and control events. Each register is 32 bits wide:
• CEC interrupt latch register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it can also be written to clear (cancel) latched events. This
register can be read while in supervisor mode and can only
be written while in supervisor mode when the corresponding IMASK bit is cleared.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processors provide a default mapping, the user
can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment
registers (SIC_IARx). Table 3 describes the inputs into the SIC
and the default mappings into the CEC.
Rev. I
Table 3. System Interrupt Controller (SIC)
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• CEC interrupt mask register (IMASK) – The IMASK register controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and is processed by the CEC when asserted. A
cleared bit in the IMASK register masks the event,
preventing the processor from servicing the event even
though the event may be latched in the ILAT register. This
register can be read or written while in supervisor mode.
Note that general-purpose interrupts can be globally
enabled and disabled with the STI and CLI instructions,
respectively.
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ADSP-BF531/ADSP-BF532/ADSP-BF533
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but can be read while in supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3.
• SIC interrupt mask register (SIC_IMASK) – This register
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in this register, that
peripheral event is unmasked and is processed by the system when asserted. A cleared bit in this register masks the
peripheral event, preventing the processor from servicing
the event.
• SIC interrupt status register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event.
• SIC interrupt wakeup enable register (SIC_IWR) – By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. See Dynamic
Power Management on Page 11.
Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the
general-purpose interrupt to the IPEND output asserted is three
core clock cycles; however, the latency can be much higher,
depending on the activity within and the state of the processor.
DMA CONTROLLERS
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have
multiple, independent DMA channels that support automated
data transfers with minimal overhead for the processor core.
DMA transfers can occur between the processor’s internal
memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the
DMA-capable peripherals and external devices connected to the
external memory interfaces, including the SDRAM controller
and the asynchronous memory controller. DMA-capable
Rev. I
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peripherals include the SPORTs, SPI port, UART, and PPI. Each
individual DMA-capable peripheral has at least one dedicated
DMA channel.
The DMA controller supports both 1-dimensional (1-D) and 2dimensional (2-D) DMA transfers. DMA transfer initialization
can be implemented from registers or from sets of parameters
called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
de-interleaved on the fly.
Examples of DMA types supported by the DMA controller
include:
• A single, linear buffer that stops upon completion
• A circular, autorefreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
two pairs of memory DMA channels provided for transfers
between the various memories of the processor system. This
enables transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash
memory—with minimal processor intervention. Memory DMA
transfers can be controlled by a very flexible descriptor-based
methodology or by a standard register-based autobuffer
mechanism.
REAL-TIME CLOCK
The processor real-time clock (RTC) provides a robust set of
digital watch features, including current time, stopwatch, and
alarm. The RTC is clocked by a 32.768 kHz crystal external to
the ADSP-BF531/ADSP-BF532/ADSP-BF533 processors. The
RTC peripheral has dedicated power supply pins so that it can
remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several
programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on
programmable stopwatch countdown, or interrupt at a programmed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60 second counter, a 60 minute counter, a
24 hour counter, and a 32,768 day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. The two alarms are time of day and a day
and time of that day.
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ADSP-BF531/ADSP-BF532/ADSP-BF533
The stopwatch function counts down from a programmed
value, with one second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like other peripherals, the RTC can wake up the processor from
sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from deep sleep mode, and wake up the on-chip internal voltage
regulator from a powered-down state.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 6.
R1
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system
clock or to a count of external signals.
X1
C1
There are four general-purpose programmable timer units in
the ADSP-BF531/ADSP-BF532/ADSP-BF533 processors. Three
timers have an external pin that can be configured either as a
pulse-width modulator (PWM) or timer output, as an input to
clock the timer, or as a mechanism for measuring pulse widths
and periods of external events. These timers can be synchronized to an external clock input to the PF1 pin (TACLK), an
external clock input to the PPI_CLK pin (TMRCLK), or to the
internal SCLK.
The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide an
autobaud detect function for a serial channel.
RTXO
RTXI
TIMERS
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
C2
SUGGESTED COMPONENTS:
X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22 pF
C2 = 22 pF
R1 = 10 M:
SERIAL PORTS (SPORTs)
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors
incorporate two dual-channel synchronous serial ports
(SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features:
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
• I2S capable operation.
Figure 6. External Components for RTC
WATCHDOG TIMER
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors
include a 32-bit timer that can be used to implement a software
watchdog function. A software watchdog can improve system
availability by forcing the processor to a known state through
generation of a hardware reset, nonmaskable interrupt (NMI),
or general-purpose interrupt, if the timer expires before being
reset by software. The programmer initializes the count value of
the timer, enables the appropriate interrupt, then enables the
timer. Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
• Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels
of I2S stereo audio.
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 bits to 32 bits in length, transferred most-significant-bit first or least-significant-bit first.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or μ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
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ADSP-BF531/ADSP-BF532/ADSP-BF533
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data-word or
after transferring an entire data buffer or buffers
through DMA.
• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
• Multichannel capability – Each SPORT supports 128 channels out of a 1,024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
An additional 250 mV of SPORT input hysteresis can be
enabled by setting Bit 15 of the PLL_CTL register. When this bit
is set, all SPORT input pins have the increased hysteresis.
The baud rate, serial data format, error code generation and status, and interrupts for the UART port are programmable.
The UART programmable features include:
• Supporting bit rates ranging from (fSCLK/1,048,576) bits per
second to (fSCLK/16) bits per second.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have
an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices.
The SPI interface uses three pins for transferring data: two data
pins (master output-slave input, MOSI, and master input-slave
output, MISO) and a clock pin (serial clock, SCK). An SPI chip
select input pin (SPISS) lets other SPI devices select the processor, and seven SPI chip select output pins (SPISEL7–1) let the
processor select other SPI devices. The SPI select pins are reconfigured general-purpose I/O pins. Using these pins, the SPI port
provides a full-duplex, synchronous serial interface which supports both master/slave modes and multimaster environments.
• Supporting data formats from seven bits to 12 bits per
frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
f SCLK
UART Clock Rate = ---------------------------------------------16 UART_Divisor
where the 16-bit UART_Divisor comes from the UART_DLH
register (most significant 8 bits) and UART_DLL register (least
significant 8 bits).
In conjunction with the general-purpose timer functions,
autobaud detection is supported.
The baud rate and clock phase/polarities for the SPI port are
programmable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. The SPI
DMA controller can only service unidirectional accesses at any
given time.
The capabilities of the UART are further extended with support
for the Infrared Data Association (IrDA®) serial infrared physical layer link specification (SIR) protocol.
The SPI port clock rate is calculated as:
GENERAL-PURPOSE I/O PORT F
f SCLK
SPI Clock Rate = ----------------------------------2 SPI_BAUD
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have
16 bidirectional, general-purpose I/O pins on Port F (PF15–0).
Each general-purpose I/O pin can be individually controlled by
manipulation of the GPIO control, status and interrupt
registers:
where the 16-bit SPI_BAUD register contains a value of 2 to
65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
UART PORT
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors provide a full-duplex universal asynchronous receiver/transmitter
(UART) port, which is fully compatible with PC-standard
UARTs. The UART port provides a simplified UART interface
to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART port
includes support for 5 data bits to 8 data bits, 1 stop bit or 2 stop
bits, and none, even, or odd parity. The UART port supports
two modes of operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
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• GPIO direction control register – Specifies the direction of
each individual PFx pin as input or output.
• GPIO control and status registers – The processor employs
a “write one to modify” mechanism that allows any combination of individual GPIO pins to be modified in a single
instruction, without affecting the level of any other GPIO
pins. Four control registers are provided. One register is
written in order to set GPIO pin values, one register is written in order to clear GPIO pin values, one register is written
in order to toggle GPIO pin values, and one register is written in order to specify GPIO pin values. Reading the GPIO
status register allows software to interrogate the sense of
the GPIO pin.
• GPIO interrupt mask registers – The two GPIO interrupt
mask registers allow each individual PFx pin to function as
an interrupt to the processor. Similar to the two GPIO
control registers that are used to set and clear individual
GPIO pin values, one GPIO interrupt mask register sets
bits to enable interrupt function, and the other GPIO interrupt mask register clears bits to disable interrupt function.
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
PFx pins defined as inputs can be configured to generate
hardware interrupts, while output PFx pins can be triggered by software interrupts.
• GPIO interrupt sensitivity registers – The two GPIO interrupt sensitivity registers specify whether individual PFx
pins are level- or edge-sensitive and specify—if edge-sensitive—whether just the rising edge or both the rising and
falling edges of the signal are significant. One register
selects the type of sensitivity, and one register selects which
edges are significant for edge-sensitivity.
PARALLEL PERIPHERAL INTERFACE
The processors provide a parallel peripheral interface (PPI) that
can connect directly to parallel ADCs and DACs, video encoders and decoders, and other general-purpose peripherals. The
PPI consists of a dedicated input clock pin, up to three frame
synchronization pins, and up to 16 data pins. The input clock
supports parallel data rates up to half the system clock rate and
the synchronization signals can be configured as either inputs or
outputs.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bi-directional data transfer with up to 16 bits of
data. Up to three frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex bidirectional transfer of 8- or 10-bit video data. Additionally, onchip decode of embedded start-of-line (SOL) and start-of-field
(SOF) preamble packets is supported.
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct sub modes are supported:
• Input mode – Frame syncs and data are inputs into the PPI.
• Frame capture mode – Frame syncs are outputs from the
PPI, but data are inputs.
• Output mode – Frame syncs and data are outputs from the
PPI.
Output Mode
Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hardware signaling.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applications. Three distinct sub modes are supported:
• Active video only mode
• Vertical blanking only mode
• Entire field mode
Active Video Only Mode
Active video only mode is used when only the active video portion of a field is of interest and not any of the blanking intervals.
The PPI does not read in any data between the end of active
video (EAV) and start of active video (SAV) preamble symbols,
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory;
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV
code. The user specifies the number of active video lines per
frame (in PPI_COUNT register).
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
Entire Field Mode
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that can be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after
synchronization to Field 1. Data is transferred to or from the
synchronous channels through eight DMA engines that work
autonomously from the processor core.
Input Mode
DYNAMIC POWER MANAGEMENT
Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_COUNT register. The PPI supports 8-bit and 10-bit
through 16-bit data, programmable in the PPI_CONTROL
register.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors provides four operating modes, each with a different performance/
power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor
core supply voltage, further reducing power dissipation. Control
of clocking to each of the processor peripherals also reduces
power consumption. See Table 4 for a summary of the power
settings for each mode.
Frame Capture Mode
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled
peripherals run at full speed.
Frame capture mode allows the video source(s) to act as a slave
(e.g., for frame capture). The processors control when to read
from the video source(s). PPI_FS1 is an HSYNC output and
PPI_FS2 is a VSYNC output.
Rev. I
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Full-On Operating Mode—Maximum Performance
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before it can transition to the full-on or sleep modes.
Table 4. Power Settings
0 V to provide the lowest static power dissipation. Any critical
information stored internally (memory contents, register contents, etc.) must be written to a nonvolatile storage device prior
to removing power if the processor state is to be preserved.
Since VDDEXT is still supplied in this mode, all of the external
pins three-state, unless otherwise specified. This allows other
devices that may be connected to the processor to still have
power applied without drawing unwanted current. The internal
supply regulator can be woken up either by a real-time clock
wakeup or by asserting the RESET pin.
Power Savings
Mode
Full On
Active
Core
PLL
Clock
PLL
Bypassed (CCLK)
Enabled No
Enabled
Enabled/ Yes
Enabled
Disabled
Enabled —
Disabled
Disabled —
Disabled
Sleep
Deep
Sleep
Hibernate Disabled
—
System
Clock
(SCLK)
Enabled
Enabled
Internal
Power
(VDDINT)
On
On
Enabled On
Disabled On
Disabled Disabled Off
As shown in Table 5, the processors support three different
power domains. The use of multiple power domains maximizes
flexibility, while maintaining compliance with industry standards and conventions. By isolating the internal logic of the
processor into its own power domain, separate from the RTC
and other I/O, the processor can take advantage of dynamic
power management without affecting the RTC or other I/O
devices. There are no sequencing requirements for the various
power domains.
Table 5. Power Domains
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the
processor. When in the sleep mode, assertion of wakeup causes
the processor to sense the value of the BYPASS bit in the PLL
control register (PLL_CTL). If BYPASS is disabled, the processor will transition to the full-on mode. If BYPASS is enabled, the
processor will transition to the active mode.
When in the sleep mode, system DMA access to L1 memory is
not supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode can
only be exited by assertion of the reset interrupt (RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the processor to transition to the active mode. Assertion of RESET while
in deep sleep mode causes the processor to transition to the fullon mode.
Power Domain
All internal logic, except RTC
RTC internal logic and crystal I/O
All other I/O
VDD Range
VDDINT
VDDRTC
VDDEXT
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as:
power savings factor
f CCLKRED V DDINTRED 2 t RED
- -------------------------- ----------= -------------------f CCLKNOM V DDINTNOM t NOM
where the variables in the equation are:
Hibernate State—Maximum Static Power Savings
fCCLKNOM is the nominal core clock frequency
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to
the FREQ bits of the VR_CTL register. In addition to disabling
the clocks, this sets the internal power supply voltage (VDDINT) to
fCCLKRED is the reduced core clock frequency
Rev. I
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VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
For further details on the on-chip voltage regulator and related
board design guidelines, see the Switching Regulator Design
Considerations for ADSP-BF533 Blackfin Processors (EE-228)
applications note on the Analog Devices web site (www.analog.com)—use site search on “EE-228”.
tNOM is the duration running at fCCLKNOM
tRED is the duration running at fCCLKRED
The percent power savings is calculated as:
% power savings = 1 – power savings factor 100%
VOLTAGE REGULATION
CLOCK SIGNALS
The Blackfin processor provides an on-chip voltage regulator
that can generate appropriate VDDINT voltage levels from the
VDDEXT supply. See Operating Conditions on Page 20 for regulator tolerances and acceptable VDDEXT ranges for specific models.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors can
be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator.
Figure 7 shows the typical external components required to
complete the power management system. The regulator controls the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while keeping I/O power (VDDEXT) supplied.
While in the hibernate state, I/O power is still being applied,
eliminating the need for external buffers. The voltage regulator
can be activated from this power-down state either through an
RTC wakeup or by asserting RESET, both of which initiate a
boot sequence. The regulator can also be disabled and bypassed
at the user’s discretion.
If an external clock is used, it should be a TTL-compatible signal
and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the processors include an on-chip oscillator circuit, an external crystal can be used. For fundamental
frequency operation, use the circuit shown in Figure 8.
Blackfin
CLKOUT
TO PLL CIRCUITRY
EN
SET OF DECOUPLING
CAPACITORS
VDDEXT
(LOW-INDUCTANCE)
700:
VDDEXT
VDDEXT
+
XTAL
CLKIN
100μF
1M:
0: *
10μH
100nF
+
VDDINT
+
18pF*
100μF
FDS9431A
10μF
LOW ESR
18pF*
FOR OVERTONE
OPERATION ONLY
100μF
ZHCS1000
VROUT
SHORT AND LOWINDUCTANCE WIRE
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
VROUT
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
GND
Figure 7. Voltage Regulator Circuit
Voltage Regulator Layout Guidelines
Regulator external component placement, board routing, and
bypass capacitors all have a significant effect on noise injected
into the other analog circuits on-chip. The VROUT1–0 traces
and voltage regulator external components should be considered as noise sources when doing board layout and should not
be routed or placed near sensitive circuits or components on the
board. All internal and I/O power supplies should be well
bypassed with bypass capacitors placed as close to the processors as possible.
Rev. I
|
Figure 8. External Crystal Connections
A parallel-resonant, fundamental frequency, microprocessorgrade crystal is connected across the CLKIN and XTAL pins.
The on-chip resistance between CLKIN and the XTAL pin is in
the 500 k range. Further parallel resistors are typically not recommended. The two capacitors and the series resistor shown in
Figure 8 fine tune the phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 8 are
typical values only. The capacitor values are dependent upon
the crystal manufacturer's load capacitance recommendations
and the physical PCB layout. The resistor value depends on the
drive level specified by the crystal manufacturer. System designs
should verify the customized values based on careful investigation on multiple devices over the allowed temperature range.
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 8.
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ADSP-BF531/ADSP-BF532/ADSP-BF533
As shown in Figure 9, the core clock (CCLK) and system
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user programmable 0.5 to 64 multiplication factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10, but it can be
modified by a software instruction sequence. On-the-fly
frequency changes can be effected by simply writing to the
PLL_DIV register.
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
CLKIN
PLL
0.5u to 64u
“COARSE” ADJUSTMENT
ON-THE-FLY
÷ 1, 2, 4, 8
CCLK
÷ 1 to 15
SCLK
Table 7. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
Example Frequency Ratios
(MHz)
Divider Ratio
VCO/CCLK
VCO
CCLK
1:1
300
300
2:1
300
150
4:1
400
100
8:1
200
25
BOOTING MODES
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have
two mechanisms (listed in Table 8) for automatically loading
internal L1 instruction memory after a reset. A third mode is
provided to execute from external memory, bypassing the boot
sequence.
VCO
Table 8. Booting Modes
BMODE1–0 Description
00
Execute from 16-bit external memory (bypass
boot ROM)
01
Boot from 8-bit or 16-bit FLASH
10
Boot from serial master connected to SPI
11
Boot from serial slave EEPROM/flash (8-,16-, or 24bit address range, or Atmel AT45DB041,
AT45DB081, or AT45DB161serial flash)
SCLK d CCLK
SCLK d 133 MHz
Figure 9. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
Table 6. Example System Clock Ratios
Signal Name
SSEL3–0
0001
0101
1010
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, implement the following modes:
Example Frequency Ratios
(MHz)
Divider Ratio
VCO/SCLK
VCO
SCLK
1:1
100
100
5:1
400
80
10:1
500
50
The maximum frequency of the system clock is fSCLK. The divisor ratio must be chosen to limit the system clock frequency to
its maximum of fSCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing the appropriate
values to the PLL divisor register (PLL_DIV). When the SSEL
value is changed, it affects all of the peripherals that derive their
clock signals from the SCLK signal.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
Rev. I
|
Page 14 of 64 |
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit or 16-bit external flash memory – The flash
boot routine located in boot ROM memory space is set up
using asynchronous Memory Bank 0. All configuration settings are set for the slowest device possible (3-cycle hold
time; 15-cycle R/W access times; 4-cycle setup).
• Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit
addressable, or Atmel AT45DB041, AT45DB081, or
AT45DB161) – The SPI uses the PF2 output pin to select a
single SPI EEPROM/flash device, submits a read command
and successive address bytes (0x00) until a valid 8-, 16-, or
24-bit addressable EEPROM/flash device is detected, and
begins clocking data into the processor at the beginning of
L1 instruction memory.
• Boot from SPI serial master – The Blackfin processor operates in SPI slave mode and is configured to receive the bytes
of the LDR file from an SPI host (master) agent. To hold off
the host device from transmitting while the boot ROM is
busy, the Blackfin processor asserts a GPIO pin, called host
wait (HWAIT), to signal the host device not to send any
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
more bytes until the flag is deasserted. The GPIO pin is
chosen by the user and this information is transferred to
the Blackfin processor via bits[10:5] of the FLAG header in
the LDR image.
For each of the boot modes, a 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks can be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified programming model.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.
Rev. I
|
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit www.analog.com/
cces.
The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders®, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices
processors.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
Page 15 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Board Support Packages for Evaluation Hardware
ADDITIONAL INFORMATION
Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download
area of the product web page.
The following publications that describe the ADSP-BF531/
ADSP-BF532/ADSP-BF533 processors (and related processors)
can be ordered from any Analog Devices sales office or accessed
electronically on our website:
• Getting Started With Blackfin Processors
• ADSP-BF533 Blackfin Processor Hardware Reference
• Blackfin Processor Programming Reference
• ADSP-BF531/ADSP-BF532/ADSP-BF533 Blackfin
Processor Anomaly List
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and TCP/
IP stacks. For more information see the following web pages:
• www.analog.com/ucos3
• www.analog.com/ucfs
• www.analog.com/ucusbd
• www.analog.com/lwip
Algorithmic Modules
To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules” or “SHARC software
modules”.
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the "signal chain" entry in
Wikipedia or the Glossary of EE Terms on the Analog Devices
website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The Application Signal Chains page in the Circuits from the
LabTM site (http://www.analog.com/circuits) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the Engineer-to-Engineer
Note “Analog Devices JTAG Emulation Technical Reference”
(EE-68) on the Analog Devices website (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.
Rev. I
|
Page 16 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
PIN DESCRIPTIONS
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors pin
definitions are listed in Table 9.
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins. These pins are all
driven high, with the exception of CLKOUT, which toggles at
the system clock rate. During hibernate, all outputs are threestated unless otherwise noted in Table 9.
If BR is active (whether or not RESET is asserted), the memory
pins are also three-stated. All unused I/O pins have their input
buffers disabled with the exception of the pins that need pullups or pull-downs as noted in the table.
In order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate functionality is shown in italics.
Table 9. Pin Descriptions
Type Function
Driver
Type1
ADDR19–1
O
Address Bus for Async/Sync Access
A
DATA15–0
I/O
Data Bus for Async/Sync Access
A
ABE1–0/SDQM1–0
O
Byte Enables/Data Masks for Async/Sync Access
A
Pin Name
Memory Interface
BR
I
Bus Request (This pin should be pulled high if not used.)
BG
O
Bus Grant
A
BGH
O
Bus Grant Hang
A
O
Bank Select (Require pull-ups if hibernate is used.)
A
Asynchronous Memory Control
AMS3–0
ARDY
I
Hardware Ready Control (This pin should be pulled high if not used.)
AOE
O
Output Enable
A
ARE
O
Read Enable
A
AWE
O
Write Enable
A
SRAS
O
Row Address Strobe
A
SCAS
O
Column Address Strobe
A
SWE
O
Write Enable
A
SCKE
O
Clock Enable (Requires pull-down if hibernate is used.)
A
CLKOUT
O
Clock Output
B
SA10
O
A10 Pin
A
SMS
O
Bank Select
A
TMR0
I/O
Timer 0
C
TMR1/PPI_FS1
I/O
Timer 1/PPI Frame Sync1
C
TMR2/PPI_FS2
I/O
Timer 2/PPI Frame Sync2
C
PPI3–0
I/O
PPI3–0
C
PPI_CLK/TMRCLK
I
PPI Clock/External Timer Reference
Synchronous Memory Control
Timers
PPI Port
Rev. I
|
Page 17 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 9. Pin Descriptions (Continued)
Type Function
Driver
Type1
PF0/SPISS
I/O
GPIO/SPI Slave Select Input
C
PF1/SPISEL1/TACLK
I/O
GPIO/SPI Slave Select Enable 1/Timer Alternate Clock Input
C
PF2/SPISEL2
I/O
GPIO/SPI Slave Select Enable 2
C
PF3/SPISEL3/PPI_FS3
I/O
GPIO/SPI Slave Select Enable 3/PPI Frame Sync 3
C
PF4/SPISEL4/PPI15
I/O
GPIO/SPI Slave Select Enable 4/PPI 15
C
PF5/SPISEL5/PPI14
I/O
GPIO/SPI Slave Select Enable 5/PPI 14
C
PF6/SPISEL6/PPI13
I/O
GPIO/SPI Slave Select Enable 6/PPI 13
C
PF7/SPISEL7/PPI12
I/O
GPIO/SPI Slave Select Enable 7/PPI 12
C
PF8/PPI11
I/O
GPIO/PPI 11
C
PF9/PPI10
I/O
GPIO/PPI 10
C
PF10/PPI9
I/O
GPIO/PPI 9
C
PF11/PPI8
I/O
GPIO/PPI 8
C
PF12/PPI7
I/O
GPIO/PPI 7
C
PF13/PPI6
I/O
GPIO/PPI 6
C
PF14/PPI5
I/O
GPIO/PPI 5
C
PF15/PPI4
I/O
GPIO/PPI 4
C
TCK
I
JTAG Clock
TDO
O
JTAG Serial Data Out
TDI
I
JTAG Serial Data In
Pin Name
Port F: GPIO/Parallel Peripheral
Interface Port/SPI/Timers
JTAG Port
C
TMS
I
JTAG Mode Select
TRST
I
JTAG Reset (This pin should be pulled low if JTAG is not used.)
EMU
O
Emulation Output
C
MOSI
I/O
Master Out Slave In
C
MISO
I/O
Master In Slave Out (This pin should be pulled high through a 4.7 k resistor if booting via the C
SPI port.)
SCK
I/O
SPI Clock
D
RSCLK0
I/O
SPORT0 Receive Serial Clock
D
RFS0
I/O
SPORT0 Receive Frame Sync
C
DR0PRI
I
SPORT0 Receive Data Primary
DR0SEC
I
SPORT0 Receive Data Secondary
TSCLK0
I/O
SPORT0 Transmit Serial Clock
D
TFS0
I/O
SPORT0 Transmit Frame Sync
C
DT0PRI
O
SPORT0 Transmit Data Primary
C
SPI Port
Serial Ports
DT0SEC
O
SPORT0 Transmit Data Secondary
C
RSCLK1
I/O
SPORT1 Receive Serial Clock
D
Rev. I
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Page 18 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 9. Pin Descriptions (Continued)
Pin Name
RFS1
Type Function
Driver
Type1
I/O
C
SPORT1 Receive Frame Sync
DR1PRI
I
SPORT1 Receive Data Primary
DR1SEC
I
SPORT1 Receive Data Secondary
TSCLK1
I/O
SPORT1 Transmit Serial Clock
D
TFS1
I/O
SPORT1 Transmit Frame Sync
C
DT1PRI
O
SPORT1 Transmit Data Primary
C
DT1SEC
O
SPORT1 Transmit Data Secondary
C
RX
I
UART Receive
TX
O
UART Transmit
RTXI
I
RTC Crystal Input (This pin should be pulled low when not used.)
RTXO
O
RTC Crystal Output (Does not three-state in hibernate.)
CLKIN
I
Clock/Crystal Input (This pin needs to be at a level or clocking.)
XTAL
O
Crystal Output
RESET
I
Reset (This pin is always active during core power-on.)
NMI
I
Nonmaskable Interrupt (This pin should be pulled low when not used.)
BMODE1–0
I
Boot Mode Strap (These pins must be pulled to the state required for the desired boot mode.)
O
External FET Drive (These pins should be left unconnected when unused and are driven high
during hibernate.)
VDDEXT
P
I/O Power Supply
VDDINT
P
Core Power Supply
VDDRTC
P
Real-Time Clock Power Supply (This pin should be connected to VDDEXT when not used and should
remain powered at all times.)
GND
G
External Ground
UART Port
C
Real-Time Clock
Clock
Mode Controls
Voltage Regulator
VROUT1–0
Supplies
1
Refer to Figure 33 on Page 43 to Figure 44 on Page 44.
Rev. I
|
Page 19 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
SPECIFICATIONS
Component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter
Conditions
VDDINT Internal Supply Voltage
1
VDDINT Internal Supply Voltage
1
VDDINT Internal Supply Voltage
1
Nonautomotive 400 MHz and 500 MHz speed grade models
Nonautomotive 533 MHz speed grade models
600 MHz speed grade models
Automotive 400 MHz speed grade models2
1
2
VDDEXT External Supply Voltage
2
2
VDDINT Internal Supply Voltage1
VDDINT Internal Supply Voltage
2
Automotive 533 MHz speed grade models
3
Nonautomotive grade models
2
2
Min Nominal
Max Unit
0.8 1.2
1.45
V
0.8 1.25
1.45
V
0.8 1.30
1.45
V
0.95 1.2
1.45
V
0.95 1.25
1.45
V
1.75 1.8/3.3
3.6
V
VDDEXT External Supply Voltage
Automotive grade models
2.7 3.3
3.6
V
VDDRTC Real-Time Clock
Power Supply Voltage
Nonautomotive grade models2
1.75 1.8/3.3
3.6
V
VDDRTC Real-Time Clock
Power Supply Voltage
Automotive grade models2
2.7 3.3
3.6
V
VIH
High Level Input Voltage4, 5
VDDEXT =1.85 V
1.3
V
VIH
4, 5
VDDEXT =Maximum
2.0
V
6
VDDEXT =Maximum
2.2
V
High Level Input Voltage
VIHCLKIN High Level Input Voltage
7
VIL
Low Level Input Voltage
VDDEXT =1.75 V
+0.3 V
VIL
Low Level Input Voltage7
VDDEXT =2.7 V
+0.6 V
TJ
Junction Temperature
160-Ball Chip Scale Ball Grid Array (CSP_BGA) @ TAMBIENT = 0°C to +70°C
TJ
Junction Temperature
160-Ball Chip Scale Ball Grid Array (CSP_BGA) @ TAMBIENT = –40°C to +85°C –40
+105 °C
0
+95
°C
TJ
Junction Temperature
160-Ball Chip Scale Ball Grid Array (CSP_BGA) @ TAMBIENT = –40°C to +105°C –40
+125 °C
TJ
Junction Temperature
169-Ball Plastic Ball Grid Array (PBGA) @ TAMBIENT = –40°C to +105°C
–40
+125 °C
TJ
Junction Temperature
169-Ball Plastic Ball Grid Array (PBGA) @ TAMBIENT = –40°C to +85°C
–40
+105 °C
TJ
Junction Temperature
176-Lead Quad Flatpack (LQFP) @ TAMBIENT = –40°C to +85°C
–40
+100 °C
1
The regulator can generate VDDINT at levels of 0.85 V to 1.2 V with –5% to +10% tolerance, 1.25 V with –4% to +10% tolerance, and 1.3 V with –0% to +10% tolerance.
See Ordering Guide on Page 63.
3
When VDDEXT < 2.25 V, on-chip voltage regulation is not supported.
4
Applies to all input and bidirectional pins except CLKIN.
5
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on
the input VDDEXT, because VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bidirectional pins (DATA15–0, TMR2–0, PF15–0, PPI3–0,
RSCLK1–0, TSCLK1–0, RFS1–0, TFS1–0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS,
TRST, CLKIN, RESET, NMI, and BMODE1–0).
6
Applies to CLKIN pin only.
7
Applies to all input and bidirectional pins.
2
Rev. I
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Page 20 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
The following three tables describe the voltage/frequency
requirements for the processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock (Table 10 and Table 11) and system clock (Table 13)
specifications. Table 12 describes phase-locked loop operating
conditions.
Table 10. Core Clock (CCLK) Requirements—500 MHz, 533 MHz, and 600 MHz Models
Parameter
fCCLK CCLK Frequency (VDDINT = 1.3 V Minimum)1
fCCLK CCLK Frequency (VDDINT = 1.2 V Minimum)2
fCCLK CCLK Frequency (VDDINT = 1.14 V Minimum)3
fCCLK CCLK Frequency (VDDINT = 1.045 V Minimum)
fCCLK CCLK Frequency (VDDINT = 0.95 V Minimum)
fCCLK CCLK Frequency (VDDINT = 0.85 V Minimum)
fCCLK CCLK Frequency (VDDINT = 0.8 V Minimum)
Internal Regulator Setting
1.30 V
1.25 V
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
Max
600
533
500
444
400
333
250
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1
Applies to 600 MHz models only. See Ordering Guide on Page 63.
Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 63. 533 MHz models cannot support internal regulator levels above 1.25 V.
3
Applies to 500 MHz, 533 MHz, and 600 MHz models. See Ordering Guide on Page 63. 500 MHz models cannot support internal regulator levels above 1.20 V.
2
Table 11. Core Clock (CCLK) Requirements—400 MHz Models1
Parameter
fCCLK CCLK Frequency (VDDINT = 1.14 V Minimum)
fCCLK CCLK Frequency (VDDINT = 1.045 V Minimum)
fCCLK CCLK Frequency (VDDINT = 0.95 V Minimum)
fCCLK CCLK Frequency (VDDINT = 0.85 V Minimum)
fCCLK CCLK Frequency (VDDINT = 0.8 V Minimum)
1
2
Internal Regulator Setting
1.20 V
1.10 V
1.00 V
0.90 V
0.85 V
All2 Other TJ
Max
400
364
333
280
250
TJ = 125°C
Max
400
333
295
Unit
MHz
MHz
MHz
MHz
MHz
See Ordering Guide on Page 63.
See Operating Conditions on Page 20.
Table 12. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO
50
Max fCCLK
MHz
Voltage Controlled Oscillator (VCO) Frequency
Table 13. System Clock (SCLK) Requirements
Parameter1
CSP_BGA/PBGA
fSCLK
fSCLK
LQFP
fSCLK
fSCLK
1
VDDEXT = 1.8 V
Max
VDDEXT = 2.5 V/3.3 V
Max
Unit
CLKOUT/SCLK Frequency (VDDINT 1.14 V)
CLKOUT/SCLK Frequency (VDDINT 1.14 V)
100
100
133
100
MHz
MHz
CLKOUT/SCLK Frequency (VDDINT 1.14 V)
CLKOUT/SCLK Frequency (VDDINT 1.14 V)
100
83
133
83
MHz
MHz
tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK.
Rev. I
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Page 21 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
ELECTRICAL CHARACTERISTICS
400 MHz1
Parameter
Test Conditions
Min
Typical
500 MHz/533 MHz/600 MHz2
Max
Min
Typical
Max
Unit
VOH
High Level
VDDEXT = 1.75 V, IOH = –0.5 mA
Output Voltage3 VDDEXT = 2.25 V, IOH = –0.5 mA
VDDEXT = 3.0 V, IOH = –0.5 mA
VOL
Low Level
VDDEXT = 1.75 V, IOL = 2.0 mA
Output Voltage3 VDDEXT = 2.25 V/3.0 V,
IOL = 2.0 mA
0.2
0.4
0.2
0.4
V
V
IIH
High Level Input VDDEXT = Max, VIN = VDD Max
Current4
10.0
10.0
μA
IIHP
High Level Input VDDEXT = Max, VIN = VDD Max
Current JTAG5
50.0
50.0
μA
IIL6
Low Level Input VDDEXT = Max, VIN = 0 V
Current4
10.0
10.0
μA
IOZH
Three-State
Leakage
Current7
VDDEXT = Max, VIN = VDD Max
10.0
10.0
μA
IOZL6
Three-State
Leakage
Current7
VDDEXT = Max, VIN = 0 V
10.0
10.0
μA
CIN
Input
Capacitance8
fIN = 1 MHz, TAMBIENT = 25°C,
VIN = 2.5 V
89
pF
VDDINT Current in VDDINT = 0.8 V, TJ = 25°C,
Sleep Mode
SCLK = 25 MHz
IDD-TYP11
VDDINT Current
VDDINT = 1.14 V, fCCLK = 400 MHz,
TJ = 25°C
IDD-TYP11
VDDINT Current
IDD-TYP11
IDD-TYP11
IDD-INT
V
V
V
4
32.5
10
37.5
mA
mA
VDDINT = 1.2 V, fCCLK = 500 MHz,
TJ = 25°C
190
mA
VDDINT Current
VDDINT = 1.2 V, fCCLK = 533 MHz,
TJ = 25°C
200
mA
VDDINT Current
VDDINT = 1.3 V, fCCLK = 600 MHz,
TJ = 25°C
245
mA
VDDRTC Current
VDDRTC = 3.3 V, TJ = 25°C
50
100
20
VDDINT Current in fCCLK = 0 MHz
Deep Sleep
Mode
VDDINT Current
125
mA
152
IDDHIBERNATE10 VDDEXT Current in VDDEXT = 3.6 V, CLKIN = 0 MHz,
Hibernate State TJ = Max, voltage regulator off
(VDDINT = 0 V)
IDDDEEPSLEEP
89
7.5
IDDSLEEP
10
1.5
1.9
2.4
4
IDDDEEPSLEEP10 VDDINT Current in VDDINT = 1.0 V, fCCLK = 0 MHz,
Deep Sleep
TJ = 25°C, ASF = 0.00
Mode
IDDRTC
1.5
1.9
2.4
Table 15
fCCLK > 0 MHz
IDDDEEPSLEEP
+ (Table 17
ASF)
1
Applies to all 400 MHz speed grade models. See Ordering Guide on Page 63.
Applies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. See Ordering Guide on Page 63.
3
Applies to output and bidirectional pins.
4
Applies to input pins except JTAG inputs.
2
|
Page 22 of 64 |
100
August 2013
16
A
A
20
6
Rev. I
50
Table 14
mA
IDDDEEPSLEEP mA
+ (Table 17
ASF)
ADSP-BF531/ADSP-BF532/ADSP-BF533
5
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
Absolute value.
7
Applies to three-statable pins.
8
Applies to all signal pins.
9
Guaranteed, but not tested.
10
See the ADSP-BF533 Blackfin Processor Hardware Reference Manual for definitions of sleep, deep sleep, and hibernate operating modes.
11
See Table 16 for the list of IDDINT power vectors covered by various Activity Scaling Factors (ASF).
6
System designers should refer to Estimating Power for the
ADSP-BF531/BF532/BF533 Blackfin Processors (EE-229), which
provides detailed information for optimizing designs for lowest
power. All topics discussed in this section are described in detail
in EE-229. Total power dissipation has two components:
current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP
specifies static power dissipation as a function of voltage
(VDDINT) and temperature (see Table 14 or Table 15), and IDDINT
specifies the total power specification for the listed test conditions, including the dynamic component as a function of voltage
(VDDINT) and frequency (Table 17).
1. Static, including leakage current
The dynamic component is also subject to an Activity Scaling
Factor (ASF) which represents application code running on the
processor (Table 16).
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and processor activity. Electrical Characteristics on Page 22 shows the
Table 14. Static Current–500 MHz, 533 MHz, and 600 MHz Speed Grade Devices (mA)1
2
TJ (°C)
–45
0
25
40
55
70
85
100
115
125
1
2
Voltage (VDDINT)2
0.80 V 0.85 V 0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V
4.3
5.3
5.9
7.0
8.2
9.8
11.2
13.0
15.2
18.8
21.3
24.1
27.8
31.6
35.6
40.1
45.3
51.4
35.3
39.9
45.0
50.9
57.3
64.4
72.9
80.9
90.3
52.3
58.5
65.1
73.3
81.3
90.9
101.2 112.5 125.5
73.6
82.5
92.0
102.7 114.4 126.3 141.2 155.7 172.7
100.8 112.5 124.5 137.4 152.6 168.4 186.5 205.4 227.0
133.3 148.5 164.2 180.5 198.8 219.0 241.0 264.5 290.6
178.3 196.3 216.0 237.6 259.9 284.6 311.9 342.0 373.1
223.3 245.9 270.2 295.7 323.5 353.3 386.1 421.1 460.1
278.5 305.8 334.1 364.3 397.4 432.4 470.6 509.3 553.4
1.25 V
17.7
58.1
101.4
138.7
191.1
250.3
319.7
408.0
500.9
600.6
1.30 V
20.2
65.0
112.1
154.4
212.1
276.2
350.2
446.1
545.0
652.1
1.32 V
21.6
68.5
118.0
160.6
220.8
287.1
364.6
462.6
566.5
676.5
1.375 V
25.5
78.4
133.7
180.6
247.6
320.4
404.9
511.1
624.3
742.1
1.43 V
30.1
89.8
151.6
203.1
277.7
357.4
449.7
564.7
688.1
814.1
1.45 V
32.0
94.3
158.7
212.0
289.5
371.9
467.2
585.6
712.8
841.9
Values are guaranteed maximum IDDDEEPSLEEP specifications.
Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 20.
Table 15. Static Current–400 MHz Speed Grade Devices (mA)1
2
TJ (°C)
–45
0
25
40
55
70
85
100
115
125
1
2
0.80 V
0.9
3.3
7.5
12.0
18.3
27.7
38.2
54.1
73.9
98.7
0.85 V
1.1
3.7
8.4
13.1
20.0
30.3
41.7
58.1
80.0
106.3
0.90 V
1.3
4.2
9.4
14.3
21.9
32.6
44.9
63.2
86.3
113.8
0.95 V
1.5
4.8
10.0
15.9
23.6
35.3
48.6
67.8
91.9
122.1
1.00 V
1.8
5.5
11.2
17.4
26.0
38.2
52.7
73.2
99.1
130.8
Voltage (VDDINT)2
1.05 V
1.10 V
2.2
2.6
6.3
7.2
12.6
14.1
19.4
21.5
28.2
30.8
41.7
45.2
57.3
61.7
78.8
84.9
106.6
114.1
140.2
149.7
1.15 V
3.1
8.1
15.5
23.5
33.7
49.0
66.7
91.5
122.4
160.4
Values are guaranteed maximum IDDDEEPSLEEP specifications.
Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 20.
Rev. I
|
Page 23 of 64 |
August 2013
1.20 V
3.8
8.9
17.2
25.8
36.8
52.8
72.0
98.4
131.1
171.9
1.25 V
4.4
10.1
19.0
28.1
39.8
57.6
77.5
106.0
140.9
183.8
1.30 V
5.0
11.2
21.2
30.8
43.4
62.4
83.9
113.8
151.1
197.0
1.32 V
5.4
11.9
21.9
32.0
45.0
64.2
86.5
117.2
155.5
202.4
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 16. Activity Scaling Factors
IDDINT Power Vector1
IDD-PEAK
IDD-HIGH
IDD-TYP
IDD-APP
IDD-NOP
IDD-IDLE
1
2
Activity Scaling Factor (ASF)2
1.27
1.25
1.00
0.86
0.72
0.41
See EE-229 for power vector definitions.
All ASF values determined using a 10:1 CCLK:SCLK ratio.
Table 17. Dynamic Current (mA, with ASF = 1.0)1
Voltage (VDDINT)2
Frequency
(MHz)2
50
100
200
250
300
375
400
425
475
500
533
600
1
2
0.80 V
12.7
22.6
40.8
50.1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.85 V
13.9
24.2
44.1
53.8
63.5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.90 V
15.3
26.2
46.9
57.2
67.4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.95 V
16.8
28.1
50.3
61.4
72.4
88.6
93.9
N/A
N/A
N/A
N/A
N/A
1.00 V
18.1
30.1
53.3
64.7
76.2
93.5
99.3
N/A
N/A
N/A
N/A
N/A
1.05 V
19.4
31.8
56.9
68.9
81.0
99.0
105.0
111.0
N/A
N/A
N/A
N/A
1.10 V
21.0
34.7
59.9
72.9
85.9
104.6
110.8
117.3
130.3
N/A
N/A
N/A
1.15 V
22.3
36.2
63.1
76.8
90.6
110.3
116.8
123.5
136.8
143.5
N/A
N/A
1.20 V
24.0
38.4
66.7
81.0
95.2
116.0
123.0
129.9
143.8
150.7
160.4
N/A
1.25 V
25.4
40.5
70.2
85.1
100.0
122.1
129.4
136.8
151.4
158.7
168.8
N/A
1.30 V
26.4
43.0
73.8
89.3
104.8
128.0
135.7
143.2
158.1
165.6
176.5
196.2
1.32 V
27.2
43.4
75.0
90.8
106.6
130.0
137.9
145.6
161.1
168.8
179.6
199.6
1.375 V
28.7
45.7
78.7
95.2
111.8
136.2
144.6
152.6
168.9
177.0
188.2
209.3
1.43 V
30.3
47.9
82.4
99.6
116.9
142.4
151.2
159.7
176.6
185.2
196.8
219.0
1.45 V
30.7
48.9
84.6
102.0
119.4
145.5
154.3
162.8
179.7
188.2
200.5
222.6
The values are not guaranteed as stand-alone maximum specifications, they must be combined with static current per the equations of Electrical Characteristics on Page 22.
Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 20.
Rev. I
|
Page 24 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 18 may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect device
reliability.
Table 18. Absolute Maximum Ratings
Parameter
Rating
Internal (Core) Supply Voltage (VDDINT)
–0.3 V to +1.45 V
External (I/O) Supply Voltage (VDDEXT)
–0.5 V to +3.8 V
Input Voltage
1, 2
–0.5 V to +3.8 V
Output Voltage Swing
–0.5 V to VDDEXT + 0.5 V
Storage Temperature Range
–65°C to +150°C
Junction Temperature While Biased
125°C
1
2
Applies to 100% transient duty cycle. For other duty cycles see Table 19.
Applies only when VDDEXT is within specifications. When VDDEXT is outside specifications, the range is VDDEXT 0.2 V.
Table 19. Maximum Duty Cycle for Input Transient Voltage1
VIN Min (V)2
VIN Max (V)2
Maximum Duty Cycle3
–0.50
+3.80
100%
–0.70
+4.00
40%
–0.80
+4.10
25%
–0.90
+4.20
15%
–1.00
+4.30
10%
1
Applies to all signal pins with the exception of CLKIN, XTAL, VROUT1–0.
The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding
duty cycle.
3
Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. This is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence.
2
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Rev. I
|
Page 25 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
PACKAGE INFORMATION
The information presented in Figure 10 and Table 20 provides
details about the package branding for the Blackfin processors.
For a complete listing of product availability, see the Ordering
Guide on Page 63.
a
ADSP-BF53x
tppZccc
vvvvvv.x n.n
#yyww country_of_origin
B
Figure 10. Product Information on Package
Table 20. Package Brand Information1
Brand Key
Field Description
ADSP-BF53x Either ADSP-BF531, ADSP-BF532, or ADSP-BF533
t
Temperature Range
pp
Package Type
Z
RoHS Compliant Part
ccc
See Ordering Guide
vvvvvv.x
Assembly Lot Code
n.n
Silicon Revision
#
RoHS Compliant Designation
yyww
Date Code
1
Non Automotive only. For branding information specific to Automotive
products, contact Analog Devices Inc.
Rev. I
|
Page 26 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 21 and Figure 11 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 25, combinations of
CLKIN and clock multipliers/divisors must not result in core/
system clocks exceeding the maximum limits allowed for the
processor, including system clock restrictions related to supply
voltage.
Table 21. Clock and Reset Timing
Parameter
Timing Requirements
tCKIN
CLKIN Period1, 2, 3, 4
tCKINL
CLKIN Low Pulse
CLKIN High Pulse
tCKINH
tWRST
RESET Asserted Pulse Width Low5
tNOBOOT
RESET Deassertion to First External Access Delay6
Min
Max
Unit
25.0
10.0
10.0
11 tCKIN
3 tCKIN
100.0
ns
ns
ns
ns
ns
5 tCKIN
1
Applies to PLL bypass mode and PLL non bypass mode.
2
CLKIN frequency must not change on the fly.
3
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 11 on Page 21 through
Table 13 on Page 21. Since the default behavior of the PLL is to multiply the CLKIN frequency by 10, the 400 MHz speed grade parts cannot use the full CLKIN period range.
4
If the DF bit in the PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
5
Applies after power-up sequence is complete. See Table 22 and Figure 12 for power-up reset timing.
6
Applies when processor is configured in No Boot Mode (BMODE1-0 = b#00).
tCKIN
CLKIN
tCKINL
tCKINH
tNOBOOT
tWRST
RESET
Figure 11. Clock and Reset Timing
Table 22. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirement
RESET Deasserted After the VDDINT, VDDEXT, VDDRTC, and CLKIN Pins Are Stable and 3500 tCKIN
Within Specification
tRST_IN_PWR
tRST_IN_PWR
RESET
CLKIN
V
DD_SUPPLIES
In Figure 12, VDD_SUPPLIES is VDDINT, VDDEXT, VDDRTC
Figure 12. Power-Up Reset Timing
Rev. I
|
Page 27 of 64 |
August 2013
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Read Cycle Timing
Table 23. Asynchronous Memory Read Cycle Timing
Parameter
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
tHDAT
DATA15–0 Hold After CLKOUT
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
Output Delay After CLKOUT1
tDO
tHO
Output Hold After CLKOUT 1
1
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
2.1
1.0
4.0
1.0
2.1
0.8
4.0
0.0
6.0
6.0
1.0
0.8
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
CLKOUT
tDO
tHO
AMSx
ABE1–0
ADDR19–1
AOE
tDO
tHO
ARE
tSARDY
tHARDY
tHARDY
ARDY
tSARDY
DATA 15–0
Figure 13. Asynchronous Memory Read Cycle Timing
Rev. I
|
Page 28 of 64 |
August 2013
tSDAT
ns
ns
ns
ns
tHDAT
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
Asynchronous Memory Write Cycle Timing
Table 24. Asynchronous Memory Write Cycle Timing
Parameter
Timing Requirements
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT1
tDO
tHO
Output Hold After CLKOUT 1
1
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
4.0
1.0
4.0
0.0
6.0
1.0
6.0
1.0
6.0
1.0
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
PROGRAMMED ACCESS
WRITE ACCESS EXTEND HOLD
2 CYCLES
1 CYCLE 1 CYCLE
SETUP
2 CYCLES
CLKOUT
tDO
tHO
AMSx
ABE1–0
ADDR19–1
tDO
tHO
AWE
tSARDY tHARDY
ARDY
tHARDY
tSARDY
tENDAT
DATA 15–0
Figure 14. Asynchronous Memory Write Cycle Timing
Rev. I
|
Page 29 of 64 |
August 2013
tDDAT
ns
ns
6.0
0.8
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
SDRAM Interface Timing
Table 25. SDRAM Interface Timing1
Parameter
Timing Requirements
tSSDAT
DATA Setup Before CLKOUT
tHSDAT
DATA Hold After CLKOUT
Switching Characteristics
tDCAD
Command, ADDR, Data Delay After CLKOUT2
tHCAD
Command, ADDR, Data Hold After CLKOUT2
Data Disable After CLKOUT
tDSDAT
tENSDAT
Data Enable After CLKOUT
tSCLK
CLKOUT Period3
tSCLKH
CLKOUT Width High
tSCLKL
CLKOUT Width Low
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
2.1
0.8
1.5
0.8
6.0
4.0
1.0
1.0
6.0
4.0
1.0
10.0
2.5
2.5
1.0
7.5
2.5
2.5
1
SDRAM timing for TJ > 105°C is limited to 100 MHz.
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
3
Refer to Table 13 on Page 21 for maximum fSCLK at various VDDINT.
2
tSCLK
CLKOUT
tSSDAT
tHSDAT
tSCLKL
tSCLKH
DATA (IN)
tENSDAT
tDCAD
tHCAD
DATA (OUT)
tDCAD
tHCAD
COMMAND,
ADDRESS
(OUT)
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 15. SDRAM Interface Timing
Rev. I
|
Page 30 of 64 |
August 2013
ns
ns
tDSDAT
ns
ns
ns
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
External Port Bus Request and Grant Cycle Timing
Table 26 and Figure 16 describe external port bus request and
bus grant operations.
Table 26. External Port Bus Request and Grant Cycle Timing
Parameter
Timing Requirements
tBS BR Asserted to CLKOUT High Setup
tBH CLKOUT High to BR Deasserted Hold Time
Switching Characteristics
tSD CLKOUT Low to AMSx, Address, and ARE/AWE Disable
tSE CLKOUT Low to AMSx, Address, and ARE/AWE Enable
tDBG CLKOUT High to BG High Setup
tEBG CLKOUT High to BG Deasserted Hold Time
tDBH CLKOUT High to BGH High Setup
tEBH CLKOUT High to BGH Deasserted Hold Time
VDDEXT = 1.8 V
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
LQFP/PBGA Packages CSP_BGA Package
All Packages
Min
Max
Min
Max
Min
Max
Unit
4.6
1.0
4.6
1.0
4.5
4.5
6.0
6.0
6.0
6.0
4.6
0.0
4.5
4.5
5.5
4.6
5.5
4.6
4.5
4.5
3.6
3.6
3.6
3.6
CLKOUT
tBS
tBH
BR
tSD
tSE
tSD
tSE
tSD
tSE
AMSx
ADDR 19-1
ABE1-0
AWE
ARE
t DBG
tEBG
tDBH
tEBH
BG
BGH
Figure 16. External Port Bus Request and Grant Cycle Timing
Rev. I
|
Page 31 of 64 |
August 2013
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
Parallel Peripheral Interface Timing
Table 27 and Figure 17 through Figure 22 describe parallel
peripheral interface operations.
Table 27. Parallel Peripheral Interface Timing
Parameter
Timing Requirements
tPCLKW PPI_CLK Width
tPCLK PPI_CLK Period1
tSFSPE External Frame Sync Setup Before PPI_CLK Edge
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE External Frame Sync Hold After PPI_CLK
tSDRPE Receive Data Setup Before PPI_CLK
tHDRPE Receive Data Hold After PPI_CLK
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE Internal Frame Sync Delay After PPI_CLK
tHOFSPE Internal Frame Sync Hold After PPI_CLK
tDDTPE Transmit Data Delay After PPI_CLK
tHDTPE Transmit Data Hold After PPI_CLK
1
2
VDDEXT = 1.8 V
LQFP/PBGA Packages
Min
Max
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
CSP_BGA Package
All Packages
Min
Max
Min
Max
Unit
8.0
20.0
6.0
8.0
20.0
6.0
6.0
15.0
4.02
1.02
3.5
1.5
1.02
3.5
1.5
1.02
3.5
1.5
11.0
8.0
1.7
1.7
11.0
1.8
PPI_CLK frequency cannot exceed fSCLK/2.
Applies when PPI_CONTROL Bit 8 is cleared. See Figure 19 and Figure 22.
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_CLK
tDFSPE
tHOFSPE
tPCLKW
tPCLK
PPI_FS1/2
tSDRPE
tHDRPE
PPI_DATA
Figure 17. PPI GP Rx Mode with Internal Frame Sync Timing
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
PPI_CLK
tSFSPE
tPCLKW
tHFSPE
tPCLK
PPI_FS1/2
tSDRPE
tHDRPE
PPI_DATA
Figure 18. PPI GP Rx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 1)
Rev. I
|
Page 32 of 64 |
8.0
1.7
9.0
1.8
August 2013
ns
ns
ns
ns
ns
ns
ns
9.0
1.8
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
DATA
SAMPLED
FRAME SYNC
SAMPLED
PPI_CLK
tSFSPE
tPCLKW
tHFSPE
tPCLK
PPI_FS1/2
tSDRPE
tHDRPE
PPI_DATA
Figure 19. PPI GP Rx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 0)
FRAME SYNC
DRIVEN
DATA
DRIVEN
DATA
DRIVEN
tPCLK
PPI_CLK
tHOFSPE
tDFSPE
tPCLKW
PPI_FS1/2
tDDTPE
tHDTPE
PPI_DATA
Figure 20. PPI GP Tx Mode with Internal Frame Sync Timing
DATA DRIVEN /
FRAME SYNC SAMPLED
PPI_CLK
tSFSPE
tHFSPE
tPCLKW
tPCLK
PPI_FS1/2
tDDTPE
tHDTPE
PPI_DATA
Figure 21. PPI GP Tx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 1)
FRAME SYNC
SAMPLED
DATA
DRIVEN
PPI_CLK
tSFSPE
tHFSPE
tPCLKW
tPCLK
PPI_FS1/2
tDDTPE
tHDTPE
PPI_DATA
Figure 22. PPI GP Tx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 0)
Rev. I
|
Page 33 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Port Timing
Table 28 through Table 31 on Page 37 and Figure 23 on Page 35
through Figure 26 on Page 37 describe Serial Port operations.
Table 28. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRE Receive Data Setup Before RSCLKx1
tHDRE Receive Data Hold After RSCLKx1
tSCLKEW TSCLKx/RSCLKx Width
tSCLKE TSCLKx/RSCLKx Period
tSUDTE Start-Up Delay From SPORT Enable To First External TFSx3
tSUDRE Start-Up Delay From SPORT Enable To First External RFSx3
Switching Characteristics
tDFSE TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)4
tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1
tDDTE Transmit Data Delay After TSCLKx1
tHDTE Transmit Data Hold After TSCLKx1
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
3.0
3.0
3.0
3.0
8.0
20.0
4.0 × tSCLKE
4.0 × tSCLKE
3.0
3.0
3.0
3.0
4.5
15.02
4.0 × tSCLKE
4.0 × tSCLKE
10.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
10.0
0.0
10.0
0.0
10.0
0.0
ns
ns
ns
ns
1
Referenced to sample edge.
For receive mode with external RSCLKx and external RFSx only, the maximum specification is 11.11 ns (90 MHz).
3
Verified in design but untested. After being enabled, the serial port requires external clock pulses—before the first external frame sync edge—to initialize the serial port.
4
Referenced to drive edge.
2
Table 29. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRI Receive Data Setup Before RSCLKx1
tHDRI Receive Data Hold After RSCLKx1
Switching Characteristics
tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1
tDDTI Transmit Data Delay After TSCLKx1
tHDTI Transmit Data Hold After TSCLKx1
tSCLKIW TSCLKx/RSCLKx Width
1
2
Referenced to sample edge.
Referenced to drive edge.
Rev. I
|
Page 34 of 64 |
August 2013
Min
VDDEXT = 1.8 V
Max
11.0
2.0
9.5
0.0
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
9.0
2.0
9.0
0.0
3.0
1.0
3.0
1.0
3.0
2.5
6.0
ns
ns
ns
ns
3.0
2.0
4.5
ns
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
DRIVE EDGE
SAMPLE EDGE
SAMPLE EDGE
tSCLKE
tSCLKEW
tSCLKIW
RSCLKx
RSCLKx
tDFSE
tDFSI
tHOFSI
tHOFSE
RFSx
(OUTPUT)
RFSx
(OUTPUT)
tSFSI
tHFSI
RFSx
(INPUT)
tSFSE
tHFSE
tSDRE
tHDRE
RFSx
(INPUT)
tSDRI
tHDRI
DRx
DRx
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
tSCLKIW
SAMPLE EDGE
t SCLKEW
TSCLKx
tSCLKE
TSCLKx
tD FSI
tDFSE
tHOFSI
tHOFSE
TFSx
(OUTPUT)
TFSx
(OUTPUT)
tSFSI
tHFSI
tSFSE
TFSx
(INPUT)
TFSx
(INPUT)
tDDTI
tDDTE
tHDTI
tHDTE
DTx
DTx
Figure 23. Serial Ports
TSCLKx
(INPUT)
tSUDTE
TFSx
(INPUT)
RSCLKx
(INPUT)
tSUDRE
RFSx
(INPUT)
FIRST
TSCLKx/RSCLKx
EDGE AFTER
SPORT ENABLED
Figure 24. Serial Port Start Up with External Clock and Frame Sync
Rev. I
|
Page 35 of 64 |
August 2013
tHFSE
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 30. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLKx1
tDDTTE
Data Disable Delay from External TSCLKx1, 2, 3
tDTENI
Data Enable Delay from Internal TSCLKx1
tDDTTI
Data Disable Delay from Internal TSCLKx1, 2, 3
Min
VDDEXT = 1.8 V
Max
0
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
0
10.0
2.0
2.0
3.0
1
Referenced to drive edge.
Applicable to multichannel mode only.
3
TSCLKx is tied to RSCLKx.
2
DRIVE EDGE
DRIVE EDGE
TSCLKx
tDTENE/I
tDDTTE/I
DTx
Figure 25. Enable and Three-State
Rev. I
|
Page 36 of 64 |
August 2013
10.0
3.0
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 31. External Late Frame Sync
VDDEXT = 1.8 V
VDDEXT = 1.8 V
LQFP/PBGA Packages
CSP_BGA Package
Min
Max
Min
Max
Parameter
Switching Characteristics
tDDTLFSE Data Delay from Late External TFSx or External RFSx
in multichannel mode with MCMEN = 01, 2
tDTENLFS Data Enable from Late FS or in multichannel mode 0
with MCMEN = 01, 2
1
2
10.5
10.0
0
In multichannel mode, TFSx enable and TFSx valid follow tDTENLFS and tDDTLFSE.
If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
EXTERNAL RFSx IN MULTI-CHANNEL MODE
SAMPLE
DRIVE
EDGE
EDGE
DRIVE
EDGE
RSCLKx
RFSx
tDDTLFSE
tDTENLFSE
1ST BIT
DTx
LATE EXTERNAL TFSx
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
TSCLKx
TFSx
tDDTLFSE
1ST BIT
DTx
Figure 26. External Late Frame Sync
Rev. I
|
Page 37 of 64 |
VDDEXT = 2.5 V/3.3 V
All Packages
Min
Max
August 2013
10.0
0
Unit
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port—Master Timing
Table 32. Serial Peripheral Interface (SPI) Port—Master Timing
VDDEXT = 1.8 V
VDDEXT = 1.8 V
LQFP/PBGA Packages
CSP_BGA Package
Min
Max
Min
Max
Parameter
Timing Requirements
tSSPIDM Data Input Valid to SCK Edge (Data Input Setup) 10.5
–1.5
tHSPIDM SCK Sampling Edge to Data Input Invalid
Switching Characteristics
tSDSCIM SPISELx Low to First SCK Edge
2 × tSCLK – 1.5
tSPICHM Serial Clock High Period
2 × tSCLK – 1.5
tSPICLM Serial Clock Low Period
2 × tSCLK – 1.5
tSPICLK Serial Clock Period
4 × tSCLK – 1.5
2 × tSCLK – 1.5
tHDSM Last SCK Edge to SPISELx High
tSPITDM Sequential Transfer Delay
2 × tSCLK – 1.5
tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay)
tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold) –1.0
VDDEXT = 2.5 V/3.3 V
All Packages
Min
Max
Unit
9
–1.5
7.5
–1.5
ns
ns
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
4 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
4 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
ns
ns
ns
ns
ns
ns
ns
6
6
6
–1.0
–1.0
SPIxSELy
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SPIxSCK
(OUTPUT)
tDDSPIDM
tHDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
CPHA = 1
tHSPIDM
SPIxMISO
(INPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
CPHA = 0
tSSPIDM
tHSPIDM
SPIxMISO
(INPUT)
Figure 27. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. I
|
Page 38 of 64 |
August 2013
tSPITDM
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 33. Serial Peripheral Interface (SPI) Port—Slave Timing
VDDEXT = 1.8 V
VDDEXT = 1.8 V
LQFP/PBGA Packages
CSP_BGA Package
Min
Max
Min
Max
Parameter
Timing Requirements
tSPICHS Serial Clock High Period
2 × tSCLK –1.5
2 × tSCLK –1.5
tSPICLS Serial Clock Low Period
tSPICLK Serial Clock Period
4 × tSCLK
tHDS
Last SCK Edge to SPISS Not Asserted
2 × tSCLK –1.5
tSPITDS Sequential Transfer Delay
2 × tSCLK –1.5
tSDSCI SPISS Assertion to First SCK Edge
2 × tSCLK –1.5
tSSPID Data Input Valid to SCK Edge (Data Input Setup) 1.6
1.6
tHSPID SCK Sampling Edge to Data Input Invalid
Switching Characteristics
tDSOE SPISS Assertion to Data Out Active
0
tDSDHI SPISS Deassertion to Data High Impedance
0
tDDSPID SCK Edge to Data Out Valid (Data Out Delay)
tHDSPID SCK Edge to Data Out Invalid (Data Out Hold) 0
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
1.6
1.6
10
10
10
0
0
9
9
10
VDDEXT = 2.5 V/3.3 V
All Packages
Min
Max
Unit
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
1.6
1.6
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
8
8
10
0
SPIxSS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tHDS
tSPICLK
SPIxSCK
(INPUT)
tDSOE
tDDSPID
tDDSPID
tHDSPID
tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 1
tSSPID
tHSPID
SPIxMOSI
(INPUT)
tDSOE
tHDSPID
tDDSPID
tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 0
tSSPID
tHSPID
SPIxMOSI
(INPUT)
Figure 28. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. I
|
Page 39 of 64 |
August 2013
tSPITDS
ns
ns
ns
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
General-Purpose I/O Port F Pin Cycle Timing
Table 34. General-Purpose I/O Port F Pin Cycle Timing
Parameter
Timing Requirement
tWFI
GPIO Input Pulse Width
Switching Characteristic
tGPOD GPIO Output Delay from CLKOUT Low
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
tSCLK + 1
tSCLK + 1
6
CLKOUT
tGPOD
GPIO OUTPUT
tWFI
GPIO INPUT
Figure 29. GPIO Cycle Timing
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
For information on the UART port receive and transmit operations, see the ADSP-BF533 Blackfin Processor Hardware
Reference.
Rev. I
|
Page 40 of 64 |
August 2013
ns
6
ns
ADSP-BF531/ADSP-BF532/ADSP-BF533
Timer Clock Timing
Table 35 and Figure 30 describe timer clock timing.
Table 35. Timer Clock Timing
Parameter
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
Min
Max
Unit
12
ns
PPI_CLK
tTODP
TMRx OUTPUT
Figure 30. Timer Clock Timing
Timer Cycle Timing
Table 36 and Figure 31 describe timer expired operations. The
input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input frequency
of fSCLK/2 MHz.
Table 36. Timer Cycle Timing
Parameter
Timing Characteristics
tWL Timer Pulse Width Low1
tWH Timer Pulse Width High1
tTIS Timer Input Setup Time Before CLKOUT Low2
tTIH Timer Input Hold Time After CLKOUT Low2
Switching Characteristics
tHTO Timer Pulse Width Output
tTOD Timer Output Update Delay After CLKOUT High
1
2
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
1 × tSCLK
1 × tSCLK
8.0
1.5
1 × tSCLK
1 × tSCLK
6.5
1.5
ns
ns
ns
ns
1 × tSCLK
(232–1) × tSCLK
7.5
1 × tSCLK
(232–1) × tSCLK
6.5
ns
ns
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
tTOD
TMRx OUTPUT
tTIS
tTIH
tHTO
TMRx INPUT
tWH,tWL
Figure 31. Timer PWM_OUT Cycle Timing
Rev. I
|
Page 41 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
JTAG Test and Emulation Port Timing
Table 37. JTAG Port Timing
Parameter
Timing Requirements
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
tHTAP
TDI, TMS Hold After TCK High
tSSYS
System Inputs Setup Before TCK High1
tHSYS
System Inputs Hold After TCK High1
tTRSTW TRST Pulse Width2 (Measured in TCK Cycles)
Switching Characteristics
tDTDO
TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
Min
VDDEXT = 1.8 V
Max
20
4
4
4
5
4
0
1
10
12
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
20
4
4
4
5
4
ns
ns
ns
ns
ns
TCK
0
10
12
ns
ns
System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
RESET, NMI, BMODE1–0, BR, PPI3–0.
50 MHz maximum.
3
System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
2
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 32. JTAG Port Timing
Rev. I
|
Page 42 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
OUTPUT DRIVE CURRENTS
150
150
VDDEXT = 2.75V
VDDEXT = 2.50V
VDDEXT = 2.25V
SOURCE CURRENT (mA)
100
VDDEXT = 2.75V
VDDEXT = 2.50V
VDDEXT = 2.25V
100
SOURCE CURRENT (mA)
Figure 33 through Figure 44 show typical current-voltage characteristics for the output drivers of the processors. The curves
represent the current drive capability of the output drivers as a
function of output voltage.
50
50
0
VOH
–50
–100
0
–150
VOH
VOL
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
–50
Figure 36. Drive Current B (VDDEXT = 2.5 V)
VOL
–100
80
–150
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
Figure 33. Drive Current A (VDDEXT = 2.5 V)
80
VDDEXT = 1.9V
SOURCE CURRENT (mA)
60
VDDEXT = 1.8V
VDDEXT = 1.7V
40
60
VDDEXT = 1.9V
VDDEXT = 1.8V
40
VDDEXT = 1.7V
20
0
–20
–40
20
–60
0
–80
0
–20
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
–40
Figure 37. Drive Current B (VDDEXT = 1.8 V)
–60
–80
0
0.5
1.0
1.5
150
2.0
VDDEXT = 3.65V
VDDEXT = 3.30V
VDDEXT = 2.95V
SOURCE VOLTAGE (V)
Figure 34. Drive Current A (VDDEXT = 1.8 V)
150
VDDEXT = 3.65V
VDDEXT = 3.30V
VDDEXT = 2.95V
SOURCE CURRENT (mA)
100
50
SOURCE CURRENT (mA)
100
50
0
VOH
–50
–100
0
VOL
VOH
–150
–50
0
–100
–150
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SOURCE VOLTAGE (V)
Figure 35. Drive Current A (VDDEXT = 3.3 V)
Rev. I
|
1.0
1.5
2.0
SOURCE VOLTAGE (V)
2.5
Figure 38. Drive Current B (VDDEXT = 3.3 V)
VOL
0
0.5
Page 43 of 64 |
August 2013
3.0
3.5
ADSP-BF531/ADSP-BF532/ADSP-BF533
60
100
40
SOURCE CURRENT (mA)
VDDEXT = 2.75V
VDDEXT = 2.50V
VDDEXT = 2.25V
SOURCE CURRENT (mA)
20
0
VOH
–20
–40
80
VDDEXT = 2.75V
VDDEXT = 2.50V
60
VDDEXT = 2.25V
40
20
0
VOH
–20
–40
–60
VOL
VOL
–80
–60
0
0.5
1.0
1.5
2.0
2.5
3.0
–100
SOURCE VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
Figure 39. Drive Current C (VDDEXT = 2.5 V)
Figure 42. Drive Current D (VDDEXT = 2.5 V)
30
VDDEXT = 1.9V
VDDEXT = 1.8V
60
VDDEXT = 1.7V
0
–10
–20
–30
–40
VDDEXT = 1.9V
VDDEXT = 1.8V
40
10
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
20
VDDEXT = 1.7V
20
0
–20
–40
0
0.5
1.0
1.5
2.0
–60
0
SOURCE VOLTAGE (V)
Figure 40. Drive Current C (VDDEXT = 1.8 V)
1.5
2.0
150
VDDEXT = 3.65V
VDDEXT = 3.30V
VDDEXT = 2.95V
60
40
20
0
VOH
–20
–40
VOL
–60
VDDEXT = 3.65V
VDDEXT = 3.30V
VDDEXT = 2.95V
100
SOURCE CURRENT (mA)
80
SOURCE CURRENT (mA)
1.0
SOURCE VOLTAGE (V)
Figure 43. Drive Current D (VDDEXT = 1.8 V)
100
50
0
VOH
–50
VOL
–100
–80
–100
0
0.5
–150
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
SOURCE VOLTAGE (V)
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
2.5
Figure 44. Drive Current D (VDDEXT = 3.3 V)
Figure 41. Drive Current C (VDDEXT = 3.3 V)
Rev. I
|
Page 44 of 64 |
August 2013
3.0
3.5
ADSP-BF531/ADSP-BF532/ADSP-BF533
TEST CONDITIONS
All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 45
shows the measurement point for ac measurements (except output enable/disable). The measurement point VMEAS is 0.95 V for
VDDEXT (nominal) = 1.8 V or 1.5 V for VDDEXT (nominal) = 2.5 V/
3.3 V.
The time tDECAY is calculated with test loads CL and IL, and with
V equal to 0.1 V for VDDEXT (nominal) = 1.8 V or 0.5 V for
VDDEXT (nominal) = 2.5 V/3.3 V.
The time tDIS_MEASURED is the interval from when the reference
signal switches, to when the output voltage decays V from the
measured output high or output low voltage.
REFERENCE
SIGNAL
INPUT
OR
OUTPUT
VMEAS
VMEAS
tDIS_MEASURED
tDIS
VOH
(MEASURED)
Figure 45. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
VOL
(MEASURED)
Output Enable Time Measurement
tENA_MEASURED
tENA
VOH (MEASURED) ⴚ ⌬V
VOH(MEASURED)
VTRIP(HIGH)
VOL (MEASURED) + ⌬V
VTRIP(LOW)
VOL (MEASURED)
tDECAY
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
The output enable time tENA is the interval from the point when
a reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 46.
The time tENA_MEASURED is the interval, from when the reference
signal switches, to when the output voltage reaches VTRIP(high)
or VTRIP (low).
For VDDEXT (nominal) = 1.8 V—VTRIP (high) is 1.3 V and VTRIP
(low) is 0.7 V.
For VDDEXT (nominal) = 2.5 V/3.3 V—VTRIP (high) is 2.0 V and
VTRIP (low) is 1.0 V.
Time tTRIP is the interval from when the output starts driving to
when the output reaches the VTRIP (high) or VTRIP (low) trip
voltage.
OUTPUT STOPS DRIVING
Figure 46. Output Enable/Disable
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose V
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. CL is
the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time is tDECAY
plus the various output disable times as specified in the Timing
Specifications on Page 27 (for example tDSDAT for an SDRAM
write cycle as shown in SDRAM Interface Timing on Page 30).
t ENA = t ENA_MEASURED – t TRIP
If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left
side of Figure 45.
t DIS = t DIS_MEASURED – t DECAY
The time for the voltage on the bus to decay by V is dependent
on the capacitive load CL and the load current II. This decay time
can be approximated by the equation:
t DECAY = C L V I L
|
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
Time tENA is calculated as shown in the equation:
Rev. I
tTRIP
Page 45 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Capacitive Loading
16
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 47). VLOAD is 0.95 V for VDDEXT
(nominal) = 1.8 V or 1.5 V for VDDEXT (nominal) =
2.5 V/3.3 V. Figure 48 through Figure 59 on Page 48 show how
output rise time varies with capacitance. The delay and hold
specifications given should be derated by a factor derived from
these figures. The graphs in these figures may not be linear outside the ranges shown.
RISE AND FALL TIME ns (10% to 90%)
14
TESTER PIN ELECTRONICS
50Ω
VLOAD
T1
70Ω
FALL TIME
8
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 48. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 1.75 V
ZO = 50Ω (impedance)
TD = 4.04 ± 1.18 ns
0.5pF
2pF
14
RISE AND FALL TIME ns (10% to 90%)
4pF
10
DUT
OUTPUT
45Ω
50Ω
RISE TIME
12
400Ω
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
12
RISE TIME
10
FALL TIME
8
6
4
2
Figure 47. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 49. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 2.25 V
RISE AND FALL TIME ns (10% to 90%)
12
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 50. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 3.65 V
Rev. I
|
Page 46 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
30
12
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
14
RISE TIME
10
8
FALL TIME
6
4
25
RISE TIME
20
FALL TIME
15
10
5
2
0
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
0
250
Figure 51. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver B at VDDEXT = 1.75 V
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 54. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver C at VDDEXT = 1.75 V
30
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
12
10
RISE TIME
8
FALL TIME
6
4
25
RISE TIME
20
15
FALL TIME
10
5
2
0
0
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
50
250
Figure 52. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver B at VDDEXT = 2.25 V
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 55. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver C at VDDEXT = 2.25 V
RISE AND FALL TIME ns (10% to 90%)
20
RISE AND FALL TIME ns (10% to 90%)
10
9
8
RISE TIME
7
6
FALL TIME
5
4
3
2
16
RISE TIME
14
12
FALL TIME
10
8
6
4
2
1
0
18
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
0
250
Figure 53. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver B at VDDEXT = 3.65 V
Rev. I
|
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 56. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver C at VDDEXT = 3.65 V
Page 47 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
SCK (66MHz DRIVER), VDDEXT = 1.7V
RISE AND FALL TIME ns (10% to 90%)
18
16
RISE TIME
14
12
FALL TIME
10
8
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 57. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver D at VDDEXT = 1.75 V
RISE AND FALL TIME ns (10% to 90%)
18
16
14
RISE TIME
12
10
FALL TIME
8
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 58. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver D at VDDEXT = 2.25 V
RISE AND FALL TIME ns (10% to 90%)
14
12
RISE TIME
10
8
FALL TIME
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 59. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver D at VDDEXT = 3.65 V
Rev. I
|
Page 48 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
THERMAL CHARACTERISTICS
Table 38. Thermal Characteristics for BC-160 Package
To determine the junction temperature on the application
printed circuit board, use:
T J = T CASE + JT P D
Parameter
Condition
Typical
Unit
JA
0 Linear m/s Airflow
27.1
JMA
1 Linear m/s Airflow
23.85
JMA
2 Linear m/s Airflow
22.7
JC
Not Applicable
7.26
JT
0 Linear m/s Airflow
0.14
JT
1 Linear m/s Airflow
0.26
JT
2 Linear m/s Airflow
0.35
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
where:
TJ = Junction temperature (°C).
TCASE = Case temperature (°C) measured by customer at top
center of package.
JT = From Table 38 through Table 40.
PD = Power dissipation (see the power dissipation discussion
and the tables on 23 for the method to calculate PD).
Values of JA are provided for package comparison and printed
circuit board design considerations. JA can be used for a first
order approximation of TJ by the equation:
Table 39. Thermal Characteristics for ST-176-1 Package
T J = T A + JA P D
where:
TA = ambient temperature (°C).
In Table 38 through Table 40, airflow measurements comply
with JEDEC standards JESD51–2 and JESD51–6, and the junction-to-board measurement complies with JESD51–8. The
junction-to-case measurement complies with MIL-STD-883
(Method 1012.1). All measurements use a 2S2P JEDEC test
board.
|
Condition
Typical
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
JA
0 Linear m/s Airflow
34.9
JMA
1 Linear m/s Airflow
33.0
JMA
2 Linear m/s Airflow
32.0
JT
0 Linear m/s Airflow
0.50
JT
1 Linear m/s Airflow
0.75
JT
2 Linear m/s Airflow
1.00
Table 40. Thermal Characteristics for B-169 Package
Thermal resistance JA in Table 38 through Table 40 is the figure
of merit relating to performance of the package and board in a
convective environment. JMA represents the thermal resistance
under two conditions of airflow. JT represents the correlation
between TJ and TCASE.
Rev. I
Parameter
Page 49 of 64 |
Parameter
Condition
Typical
Unit
JA
0 Linear m/s Airflow
22.8
JMA
1 Linear m/s Airflow
20.3
JMA
2 Linear m/s Airflow
19.3
JC
Not Applicable
10.39
JT
0 Linear m/s Airflow
0.59
JT
1 Linear m/s Airflow
0.88
JT
2 Linear m/s Airflow
1.37
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
160-BALL CSP_BGA BALL ASSIGNMENT
Table 41 lists the CSP_BGA ball assignment by signal. Table 42
on Page 51 lists the CSP_BGA ball assignment by ball number.
Table 41. 160-Ball CSP_BGA Ball Assignment (Alphabetical by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CLKIN
CLKOUT
DATA0
DATA1
DATA2
DATA3
Ball No.
H13
H12
J14
K14
L14
J13
K13
L13
K12
L12
M12
M13
M14
N14
N13
N12
M11
N11
P13
P12
P11
E14
F14
F13
G12
G13
E13
G14
H14
P10
N10
N4
P3
D14
A12
B14
M9
N9
P9
M8
Signal
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
N8
P8
M7
N7
P7
M6
N6
P6
M5
N5
P5
P4
K1
J2
G3
F3
H1
H2
F2
E3
M2
A10
A14
B11
C4
C5
C11
D4
D7
D8
D10
D11
F4
F11
G11
H4
H11
K4
K11
L5
Rev. I
|
Signal
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PPI_CLK
PPI0
PPI1
PPI2
PPI3
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTXI
RTXO
RX
SA10
SCAS
Page 50 of 64 |
August 2013
Ball No.
L6
L8
L10
M4
M10
P14
E2
D3
B10
D2
C1
C2
C3
B1
B2
B3
B4
A2
A3
A4
A5
B5
B6
A6
C6
C9
C8
B8
A7
B7
C10
J3
G2
L1
G1
A9
A8
L3
E12
C14
Signal
SCK
SCKE
SMS
SRAS
SWE
TCK
TDI
TDO
TFS0
TFS1
TMR0
TMR1
TMR2
TMS
TRST
TSCLK0
TSCLK1
TX
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
Ball No.
D1
B13
C13
D13
D12
P2
M3
N3
H3
E1
L2
M1
K2
N2
N1
J1
F1
K3
A1
C7
C12
D5
D9
F12
G4
J4
J12
L7
L11
P1
D6
E4
E11
J11
L4
L9
B9
A13
B12
A11
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 42. 160-Ball CSP_BGA Ball Assignment (Numerical by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
Signal
VDDEXT
PF8
PF9
PF10
PF11
PF14
PPI2
RTXO
RTXI
GND
XTAL
CLKIN
VROUT0
GND
PF4
PF5
PF6
PF7
PF12
PF13
PPI3
PPI1
VDDRTC
NMI
GND
VROUT1
SCKE
CLKOUT
PF1
PF2
PF3
GND
GND
PF15
VDDEXT
PPI0
PPI_CLK
RESET
GND
VDDEXT
Ball No.
C13
C14
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
E1
E2
E3
E4
E11
E12
E13
E14
F1
F2
F3
F4
F11
F12
F13
F14
G1
G2
G3
G4
G11
G12
G13
G14
Signal
SMS
SCAS
SCK
PF0
MOSI
GND
VDDEXT
VDDINT
GND
GND
VDDEXT
GND
GND
SWE
SRAS
BR
TFS1
MISO
DT1SEC
VDDINT
VDDINT
SA10
ARDY
AMS0
TSCLK1
DT1PRI
DR1SEC
GND
GND
VDDEXT
AMS2
AMS1
RSCLK1
RFS1
DR1PRI
VDDEXT
GND
AMS3
AOE
ARE
Rev. I
|
Ball No.
H1
H2
H3
H4
H11
H12
H13
H14
J1
J2
J3
J4
J11
J12
J13
J14
K1
K2
K3
K4
K11
K12
K13
K14
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
M1
M2
Page 51 of 64 |
Signal
DT0PRI
DT0SEC
TFS0
GND
GND
ABE1
ABE0
AWE
TSCLK0
DR0SEC
RFS0
VDDEXT
VDDINT
VDDEXT
ADDR4
ADDR1
DR0PRI
TMR2
TX
GND
GND
ADDR7
ADDR5
ADDR2
RSCLK0
TMR0
RX
VDDINT
GND
GND
VDDEXT
GND
VDDINT
GND
VDDEXT
ADDR8
ADDR6
ADDR3
TMR1
EMU
August 2013
Ball No.
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Signal
TDI
GND
DATA12
DATA9
DATA6
DATA3
DATA0
GND
ADDR15
ADDR9
ADDR10
ADDR11
TRST
TMS
TDO
BMODE0
DATA13
DATA10
DATA7
DATA4
DATA1
BGH
ADDR16
ADDR14
ADDR13
ADDR12
VDDEXT
TCK
BMODE1
DATA15
DATA14
DATA11
DATA8
DATA5
DATA2
BG
ADDR19
ADDR18
ADDR17
GND
ADSP-BF531/ADSP-BF532/ADSP-BF533
Figure 60 shows the top view of the CSP_BGA ball configuration. Figure 61 shows the bottom view of the CSP_BGA ball
configuration.
1
2
3
4
5
6
7
8
9
14 13 12 11 10 9
10 11 12 13 14
8
7
6
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
KEY:
KEY:
VDDINT
VDDEXT
GND
VDDRTC
VDDINT
GND
VDDRTC
I/O
VROUT
VDDEXT
I/O
VROUT
Figure 61. 160-Ball CSP_BGA Ground Configuration (Bottom View)
Figure 60. 160-Ball CSP_BGA Ground Configuration (Top View)
Rev. I
|
Page 52 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
169-BALL PBGA BALL ASSIGNMENT
Table 43 lists the PBGA ball assignment by signal. Table 44 on
Page 54 lists the PBGA ball assignment by ball number.
Table 43. 169-Ball PBGA Ball Assignment (Alphabetical by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CLKIN
CLKOUT
DATA0
DATA1
DATA2
DATA3
Ball No.
H16
H17
J16
J17
K16
K17
L16
L17
M16
M17
N17
N16
P17
P16
R17
R16
T17
U15
T15
U16
T14
D17
E16
E17
F16
F17
C16
G16
G17
T13
U17
U5
T5
C17
A14
D16
U14
T12
U13
T11
Signal
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
U12
U11
T10
U10
T9
U9
T8
U8
U7
T7
U6
T6
M2
M1
H1
H2
K2
K1
F1
F2
U1
B16
F11
G7
G8
G9
G10
G11
H7
H8
H9
H10
H11
J7
J8
J9
J10
J11
K7
K8
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PPI_CLK
PPI0
PPI1
PPI2
PPI3
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTCVDD
Rev. I
|
Ball No.
K9
K10
K11
L7
L8
L9
L10
L11
M9
T16
E2
E1
B11
D2
C1
B1
C2
A1
A2
B3
A3
B4
A4
B5
A5
A6
B6
A7
B7
B10
B9
A9
B8
A8
A12
N1
J1
N2
J2
F10
Page 53 of 64 |
Signal
RTXI
RTXO
RX
SA10
SCAS
SCK
SCKE
SMS
SRAS
SWE
TCK
TDI
TDO
TFS0
TFS1
TMR0
TMR1
TMR2
TMS
TRST
TSCLK0
TSCLK1
TX
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
August 2013
Ball No.
A10
A11
T1
B15
A16
D1
B14
A17
A15
B17
U4
U3
T4
L1
G2
R1
P2
P1
T3
U2
L2
G1
R2
F12
G12
H12
J12
K12
L12
M10
M11
M12
B2
F6
F7
F8
F9
G6
H6
J6
Signal
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VROUT0
VROUT1
XTAL
Ball No.
K6
L6
M6
M7
M8
T2
B12
B13
A13
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 44. 169-Ball PBGA Ball Assignment (Numerical by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
C1
C2
C16
C17
D1
D2
Signal
PF4
PF5
PF7
PF9
PF11
PF12
PF14
PPI3
PPI1
RTXI
RTXO
RESET
XTAL
CLKIN
SRAS
SCAS
SMS
PF2
VDDEXT
PF6
PF8
PF10
PF13
PF15
PPI2
PPI0
PPI_CLK
NMI
VROUT0
VROUT1
SCKE
SA10
GND
SWE
PF1
PF3
ARDY
BR
SCK
PF0
Ball No.
D16
D17
E1
E2
E16
E17
F1
F2
F6
F7
F8
F9
F10
F11
F12
F16
F17
G1
G2
G6
G7
G8
G9
G10
G11
G12
G16
G17
H1
H2
H6
H7
H8
H9
H10
H11
H12
H16
H17
J1
Signal
CLKOUT
AMS0
MOSI
MISO
AMS1
AMS2
DT1PRI
DT1SEC
VDDEXT
VDDEXT
VDDEXT
VDDEXT
RTCVDD
GND
VDD
AMS3
AOE
TSCLK1
TFS1
VDDEXT
GND
GND
GND
GND
GND
VDD
ARE
AWE
DR1PRI
DR1SEC
VDDEXT
GND
GND
GND
GND
GND
VDD
ABE0
ABE1
RFS1
Ball No.
J2
J6
J7
J8
J9
J10
J11
J12
J16
J17
K1
K2
K6
K7
K8
K9
K10
K11
K12
K16
K17
L1
L2
L6
L7
L8
L9
L10
L11
L12
L16
L17
M1
M2
M6
M7
M8
M9
M10
M11
Rev. I
|
Signal
RSCLK1
VDDEXT
GND
GND
GND
GND
GND
VDD
ADDR1
ADDR2
DT0SEC
DT0PRI
VDDEXT
GND
GND
GND
GND
GND
VDD
ADDR3
ADDR4
TFS0
TSCLK0
VDDEXT
GND
GND
GND
GND
GND
VDD
ADDR5
ADDR6
DR0SEC
DR0PRI
VDDEXT
VDDEXT
VDDEXT
GND
VDD
VDD
Page 54 of 64 |
Ball No.
M12
M16
M17
N1
N2
N16
N17
P1
P2
P16
P17
R1
R2
R16
R17
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
U1
U2
U3
U4
U5
U6
U7
U8
August 2013
Signal
VDD
ADDR7
ADDR8
RFS0
RSCLK0
ADDR10
ADDR9
TMR2
TMR1
ADDR12
ADDR11
TMR0
TX
ADDR14
ADDR13
RX
VDDEXT
TMS
TDO
BMODE1
DATA15
DATA13
DATA10
DATA8
DATA6
DATA3
DATA1
BG
ADDR19
ADDR17
GND
ADDR15
EMU
TRST
TDI
TCK
BMODE0
DATA14
DATA12
DATA11
Ball No.
U9
U10
U11
U12
U13
U14
U15
U16
U17
Signal
DATA9
DATA7
DATA5
DATA4
DATA2
DATA0
ADDR16
ADDR18
BGH
ADSP-BF531/ADSP-BF532/ADSP-BF533
A1 BALL PAD CORNER
A
B
C
D
E
F
KEY
G
H
V
GND
NC
V
I/O
V
ROUT
DDINT
J
K
DDEXT
L
M
N
P
R
T
U
2
1
4
6
8
5
3
10
7
12
11
9
14
16
15
13
17
TOP VIEW
Figure 62. 169-Ball PBGA Ground Configuration (Top View)
A1 BALL PAD CORNER
A
B
KEY:
C
D
E
V
DDINT
GND
NC
V
DDEXT
I/O
V
F
G
H
J
K
L
M
N
P
R
T
U
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BOTTOM VIEW
Figure 63. 169-Ball PBGA Ground Configuration (Bottom View)
Rev. I
|
Page 55 of 64 |
August 2013
ROUT
ADSP-BF531/ADSP-BF532/ADSP-BF533
176-LEAD LQFP PINOUT
Table 45 lists the LQFP pinout by signal. Table 46 on Page 57
lists the LQFP pinout by lead number.
Table 45. 176-Lead LQFP Pin Assignment (Alphabetical by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CLKIN
CLKOUT
DATA0
DATA1
DATA2
Lead No.
151
150
149
148
147
146
142
141
140
139
138
137
136
135
127
126
125
124
123
122
121
161
160
159
158
154
162
153
152
119
120
96
95
163
10
169
116
115
114
Signal
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Lead No.
113
112
110
109
108
105
104
103
102
101
100
99
98
74
73
63
62
68
67
59
58
83
1
2
3
7
8
9
15
19
30
39
40
41
42
43
44
56
70
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
Rev. I
|
Lead No.
88
89
90
91
92
97
106
117
128
129
130
131
132
133
144
155
170
174
175
176
54
55
14
51
50
49
48
47
46
38
37
36
35
34
33
32
29
28
27
Page 56 of 64 |
Signal
PPI_CLK
PPI0
PPI1
PPI2
PPI3
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTXI
RTXO
RX
SA10
SCAS
SCK
SCKE
SMS
SRAS
SWE
TCK
TDI
TDO
TFS0
TFS1
TMR0
TMR1
TMR2
TMS
TRST
TSCLK0
TSCLK1
TX
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
August 2013
Lead No.
21
22
23
24
26
13
75
64
76
65
17
16
82
164
166
53
173
172
167
165
94
86
87
69
60
79
78
77
85
84
72
61
81
6
12
20
31
45
57
Signal
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
Lead No.
71
93
107
118
134
145
156
171
25
52
66
80
111
143
157
168
18
5
4
11
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 46. 176-Lead LQFP Pin Assignment (Numerical by Lead Number)
Lead No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Signal
GND
GND
GND
VROUT1
VROUT0
VDDEXT
GND
GND
GND
CLKIN
XTAL
VDDEXT
RESET
NMI
GND
RTXO
RTXI
VDDRTC
GND
VDDEXT
PPI_CLK
PPI0
PPI1
PPI2
VDDINT
PPI3
PF15
PF14
PF13
GND
VDDEXT
PF12
PF11
PF10
PF9
PF8
PF7
PF6
GND
GND
Lead No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Signal
GND
GND
GND
GND
VDDEXT
PF5
PF4
PF3
PF2
PF1
PF0
VDDINT
SCK
MISO
MOSI
GND
VDDEXT
DT1SEC
DT1PRI
TFS1
TSCLK1
DR1SEC
DR1PRI
RFS1
RSCLK1
VDDINT
DT0SEC
DT0PRI
TFS0
GND
VDDEXT
TSCLK0
DR0SEC
DR0PRI
RFS0
RSCLK0
TMR2
TMR1
TMR0
VDDINT
Lead No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Rev. I
|
Signal
TX
RX
EMU
TRST
TMS
TDI
TDO
GND
GND
GND
GND
GND
VDDEXT
TCK
BMODE1
BMODE0
GND
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
GND
VDDEXT
DATA7
DATA6
DATA5
VDDINT
DATA4
DATA3
DATA2
DATA1
DATA0
GND
VDDEXT
BG
BGH
Page 57 of 64 |
Lead No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
August 2013
Signal
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
ADDR14
ADDR13
GND
GND
GND
GND
GND
GND
VDDEXT
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
VDDINT
GND
VDDEXT
ADDR4
ADDR3
ADDR2
ADDR1
ABE1
ABE0
AWE
ARE
AOE
GND
VDDEXT
VDDINT
AMS3
AMS2
AMS1
Lead No.
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Signal
AMS0
ARDY
BR
SA10
SWE
SCAS
SRAS
VDDINT
CLKOUT
GND
VDDEXT
SMS
SCKE
GND
GND
GND
ADSP-BF531/ADSP-BF532/ADSP-BF533
OUTLINE DIMENSIONS
Dimensions in the outline dimension figures are shown in
millimeters.
0.75
0.60
0.45
26.20
26.00 SQ
25.80
1.60
MAX
133
132
176
1
PIN 1
24.20
24.00 SQ
23.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
89
44
45
VIEW A
VIEW A
ROTATED 90° CCW
88
0.50
BSC
LEAD PITCH
COMPLIANT TO JEDEC STANDARDS MS-026-BGA
Figure 64. 176-Lead Low Profile Quad Flat Package [LQFP]
(ST-176-1)
Dimensions shown in millimeters
Rev. I
|
Page 58 of 64 |
August 2013
0.27
0.22
0.17
ADSP-BF531/ADSP-BF532/ADSP-BF533
A1 BALL
CORNER
12.10
12.00 SQ
11.90
A
B
C
D
E
F
G
H
J
K
L
M
N
P
10.40
BSC SQ
0.80
BSC
TOP VIEW
1.70
1.60
1.35
A1 BALL
CORNER
14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
DETAIL A
DETAIL A
1.31
1.21
1.11
0.40 NOM
0.25 MIN
SEATING
PLANE
*0.55
COPLANARITY
0.45
0.12
0.40
BALL DIAMETER
*COMPLIANT TO JEDEC STANDARDS MO-205-AE WITH THE EXCEPTION
TO BALL DIAMETER.
Figure 65. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-160-2)
Dimensions shown in millimeters
Rev. I
|
Page 59 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
A1 CORNER
INDEX AREA
19.20
19.00 SQ
18.80
17
A1 BALL PAD
INDICATOR
17.05
16.95 SQ
16.85
TOP VIEW
16
15
14
12 10 8
6
4
2
13 11 9
7
5
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
16.00
BSC SQ
1.00
BSC
BOTTOM VIEW
2.50
2.23
1.97
DETAIL A
0.65
0.56
0.45
0.50 NOM
0.40 MIN
SEATING
PLANE
DETAIL A
0.70
0.60
0.50
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MS-034-AAG-2
Figure 66. 169-Ball Plastic Ball Grid Array [PBGA]
(B-169)
Dimensions shown in millimeters
Rev. I
|
Page 60 of 64 |
August 2013
1.22
1.17
1.12
0.20 MAX
COPLANARITY
ADSP-BF531/ADSP-BF532/ADSP-BF533
SURFACE-MOUNT DESIGN
Table 47 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351,
Generic Requirements for Surface-Mount Design and Land Pattern Standard.
Table 47. BGA Data for Use with Surface-Mount Design
Package
Chip Scale Package Ball Grid Array (CSP_BGA) BC-160-2
Plastic Ball Grid Array (PBGA) B-169
Rev. I
Ball Attach Type
Solder Mask Defined
Solder Mask Defined
|
Page 61 of 64 |
August 2013
Solder Mask Opening
0.40 mm diameter
0.43 mm diameter
Ball Pad Size
0.55 mm diameter
0.56 mm diameter
ADSP-BF531/ADSP-BF532/ADSP-BF533
AUTOMOTIVE PRODUCTS
The ADBF531W, ADBF532W, and ADBF533W models are
available with controlled manufacturing to support the quality
and reliability requirements of automotive applications. Note
that these automotive models may have specifications that differ
from the commercial models and designers should review the
Specifications section of this data sheet carefully. Only the auto-
motive grade products shown in Table 48 are available for use in
automotive applications. Contact your local ADI account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these
models.
Table 48. Automotive Products
Product Family1,2
ADBF531WBSTZ4xx
ADBF531WBBCZ4xx
ADBF531WYBCZ4xx
ADBF532WBSTZ4xx
ADBF532WBBCZ4xx
ADBF532WYBCZ4xx
ADBF533WBBCZ5xx
ADBF533WBBZ5xx
ADBF533WYBCZ4xx
ADBF533WYBBZ4xx
Temperature Range3
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +105°C
Speed Grade
(Max)
400 MHz
400 MHz
400 MHz
400 MHz
400 MHz
400 MHz
533 MHz
533 MHz
400 MHz
400 MHz
Package Description
176-Lead LQFP
160-Ball CSP_BGA
160-Ball CSP_BGA
176-Lead LQFP
160-Ball CSP_BGA
160-Ball CSP_BGA
160-Ball CSP_BGA
169-Ball PBGA
160-Ball CSP_BGA
169-Ball PBGA
1
Package Option
ST-176-1
BC-160-2
BC-160-2
ST-176-1
BC-160-2
BC-160-2
BC-160-2
B-169
BC-160-2
B-169
Z = RoHS compliant part.
xx denotes silicon revision.
3
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 20 for junction temperature (TJ)
specification which is the only temperature specification.
2
Rev. I
|
Page 62 of 64 |
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
ORDERING GUIDE
Model 1
Temperature
Range2
Speed Grade
(Max)
Package Description
Package
Option
ADSP-BF531SBB400
–40°C to +85°C
400 MHz
169-Ball PBGA
B-169
ADSP-BF531SBBZ400
–40°C to +85°C
400 MHz
169-Ball PBGA
B-169
ADSP-BF531SBBC400
–40°C to +85°C
400 MHz
160-Ball CSP_BGA
BC-160-2
ADSP-BF531SBBCZ400
–40°C to +85°C
400 MHz
160-Ball CSP_BGA
BC-160-2
ADSP-BF531SBBCZ4RL
–40°C to +85°C
400 MHz
160-Ball CSP_BGA, 13" Tape and Reel
BC-160-2
ADSP-BF531SBSTZ400
–40°C to +85°C
400 MHz
176-Lead LQFP
ST-176-1
ADSP-BF532SBBZ400
–40°C to +85°C
400 MHz
169-Ball PBGA
B-169
ADSP-BF532SBBC400
–40°C to +85°C
400 MHz
160-Ball CSP_BGA
BC-160-2
ADSP-BF532SBBCZ400
–40°C to +85°C
400 MHz
160-Ball CSP_BGA
BC-160-2
ADSP-BF532SBSTZ400
–40°C to +85°C
400 MHz
176-Lead LQFP
ST-176-1
ADSP-BF533SBBZ400
–40°C to +85°C
400 MHz
169-Ball PBGA
B-169
ADSP-BF533SBBC400
–40°C to +85°C
400 MHz
160-Ball CSP_BGA
BC-160-2
ADSP-BF533SBBCZ400
–40°C to +85°C
400 MHz
160-Ball CSP_BGA
BC-160-2
ADSP-BF533SBSTZ400
–40°C to +85°C
400 MHz
176-Lead LQFP
ST-176-1
ADSP-BF533SBB500
–40°C to +85°C
500 MHz
169-Ball PBGA
B-169
ADSP-BF533SBBZ500
–40°C to +85°C
500 MHz
169-Ball PBGA
B-169
ADSP-BF533SBBC500
–40°C to +85°C
500 MHz
160-Ball CSP_BGA
BC-160-2
ADSP-BF533SBBCZ500
–40°C to +85°C
500 MHz
160-Ball CSP_BGA
BC-160-2
ADSP-BF533SBBC-5V
–40°C to +85°C
533 MHz
160-Ball CSP_BGA
BC-160-2
ADSP-BF533SBBCZ-5V
–40°C to +85°C
533 MHz
160-Ball CSP_BGA
BC-160-2
ADSP-BF533SKBC-6V
0°C to +70°C
600 MHz
160-Ball CSP_BGA
BC-160-2
ADSP-BF533SKBCZ-6V
0°C to +70°C
600 MHz
160-Ball CSP_BGA
BC-160-2
ADSP-BF533SKSTZ-5V
0°C to +70°C
533 MHz
176-Lead LQFP
ST-176-1
1
Z = RoHS compliant part.
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 20 for junction temperature (TJ)
specification which is the only temperature specification.
2
Rev. I
|
Page 63 of 64 |
August 2013
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