Blackfin
Embedded Processor
ADSP-BF539/ADSP-BF539F
FEATURES
Up to 533 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages; see Operating Conditions
on Page 26
Qualified for automotive applications
Programmable on-chip voltage regulator
316-ball Pb-free CSP_BGA package
MEMORY
148K bytes of on-chip memory
16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM
Optional 8M bit parallel flash with boot option
Memory management unit providing memory protection
VOLTAGE REGULATOR
External memory controller with glueless support
for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI and external
memory
PERIPHERALS
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
4 dual-channel, full-duplex synchronous serial ports,
supporting 16 stereo I2S channels
2 DMA controllers supporting 26 peripheral DMAs
4 memory-to-memory DMAs
Controller area network (CAN) 2.0B controller
Media transceiver (MXVR) for connection
to a MOST network
3 SPI-compatible ports
Three 32-bit timer/counters with PWM support
3 UARTs with support for IrDA
2 TWI controllers compatible with I2C industry standard
Up to 38 general-purpose I/O pins (GPIO)
Up to 16 general-purpose flag pins (GPF)
Real-time clock, watchdog timer, and 32-bit core timer
On-chip PLL capable of frequency multiplication
Debug/JTAG interface
JTAG TEST AND EMULATION
B
TWI0-1
GPIO
PORT
E
UART1-2
SPORT2-3
L1 INSTRUCTION
MEMORY
DMA
CONTROLLER1
SPI1-2
DMA CORE
BUS 1
DMA
EXTERNAL
BUS 1
L1 DATA
MEMORY
DMA
CONTROLLER 0
DMA CORE BUS 0
DMA
EXTERNAL
BUS 0
EXTERNAL PORT
FLASH, SDRAM CONTROL
WATCHDOG
TIMER
RTC
PPI
DMA ACCESS BUS 0
GPIO
PORT
D
INTERRUPT
CONTROLLER
DMA CORE
BUS 2
MXVR
DMA ACCESS BUS 1
GPIO
PORT
C
CAN 2.0B
PERIPHERAL ACCESS BUS
PERIPHERAL ACCESS BUS
TIMER0-2
GPIO
PORT
F
SPI0
UART0
SPORT0-1
16
8M BIT PARALLEL FLASH
(See Table 1)
BOOT ROM
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. F
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©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADSP-BF539/ADSP-BF539F
TABLE OF CONTENTS
Features ................................................................. 1
Booting Modes ................................................... 16
Memory ................................................................ 1
Instruction Set Description .................................... 17
Peripherals ............................................................. 1
Development Tools .............................................. 17
General Description ................................................. 3
Example Connections and Layout Considerations ....... 18
Low Power Architecture ......................................... 3
MXVR Board Layout Guidelines ............................. 18
System Integration ................................................ 3
Voltage Regulator Layout Guidelines ....................... 19
ADSP-BF539/ADSP-BF539F Processor Peripherals ....... 3
Additional Information ........................................ 20
Blackfin Processor Core .......................................... 4
Related Signal Chains ........................................... 20
Memory Architecture ............................................ 5
Pin Descriptions .................................................... 21
DMA Controllers .................................................. 8
Specifications ........................................................ 26
Real-Time Clock ................................................... 9
Operating Conditions ........................................... 26
Watchdog Timer .................................................. 9
Electrical Characteristics ....................................... 27
Timers ............................................................... 9
Absolute Maximum Ratings ................................... 30
Serial Ports (SPORTs) .......................................... 10
ESD Sensitivity ................................................... 30
Serial Peripheral Interface (SPI) Ports ...................... 10
Package Information ............................................ 30
2-Wire Interface ................................................. 10
Timing Specifications ........................................... 31
UART Ports ...................................................... 10
Output Drive Currents ......................................... 50
Programmable I/O Pins ........................................ 11
Test Conditions .................................................. 52
Parallel Peripheral Interface ................................... 12
Thermal Characteristics ........................................ 55
Controller Area Network (CAN) Interface ................ 12
316-Ball CSP_BGA Ball Assignment ........................... 56
Media Transceiver MAC layer (MXVR) ................... 13
Outline Dimensions ................................................ 59
Dynamic Power Management ................................ 13
Surface-Mount Design .......................................... 59
Voltage Regulation .............................................. 15
Ordering Guide ..................................................... 60
Clock Signals ..................................................... 15
REVISION HISTORY
10/13—Rev. E to Rev. F
Updated Development Tools .................................... 17
Added notes to Table 32 in
Serial Ports—Enable and Three-State .......................... 43
Added Timer Clock Timing ...................................... 48
Revised Timer Cycle Timing ..................................... 48
To view product/process change notifications (PCNs) related to
this data sheet revision, please visit the processor’s product page
on the www.analog.com website and use the View PCN link.
Rev. F
|
Page 2 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
GENERAL DESCRIPTION
The ADSP-BF539/ADSP-BF539F processors are members of
the Blackfin® family of products, incorporating the Analog
Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin
processors combine a dual-MAC, state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like
microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction set architecture.
The ADSP-BF539/ADSP-BF539F processors are completely
code compatible with other Blackfin processors, differing only
with respect to performance, peripherals, and on-chip memory.
These features are shown in Table 1.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like programmability, multimedia support, and leading edge signal
processing in one integrated package.
Table 1. Processor Features
Feature
ADSP-BF539
ADSP-BF539F8
SPORTs
4
4
UARTs
3
3
SPI
3
3
TWI
2
2
CAN
1
1
MXVR
1
1
PPI
1
1
Internal 8M bit
Parallel Flash
—
1
Instruction
SRAM/Cache
16K bytes
16K bytes
Instruction SRAM
64K bytes
64K bytes
Data SRAM/Cache
32K bytes
32K bytes
Data SRAM
32K bytes
32K bytes
Scratchpad
4K bytes
4K bytes
Maximum
Frequency
533 MHz
1066 MMACS
533 MHz
1066 MMACS
Package Option
BC-316
BC-316
The ADSP-BF539/ADSP-BF539F processors are highly integrated system-on-a-chip solutions for the next generation of
industrial and automotive applications including audio and
video signal processing. By combining advanced memory configurations, such as on-chip flash memory, with industrystandard interfaces with a high performance signal processing
core, users can develop cost-effective solutions quickly without
the need for costly external components. The system peripherals
include a MOST Network Media Transceiver (MXVR), three
UART ports, three SPI ports, four serial ports (SPORT), one
CAN interface, two 2-wire interfaces (TWI), four general-purpose timers (three with PWM capability), a real-time clock, a
watchdog timer, a parallel peripheral interface, general-purpose
I/O, and general-purpose flag pins.
ADSP-BF539/ADSP-BF539F PROCESSOR
PERIPHERALS
The ADSP-BF539/ADSP-BF539F processors contain a rich set
of peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance (see Figure 1 on Page 1).
The general-purpose peripherals include functions such as
UART, timers with PWM (pulse-width modulation) and pulse
measurement capability, general-purpose flag I/O pins, a realtime clock, and a watchdog timer. This set of functions satisfies
a wide variety of typical system support needs and is augmented
by the system expansion capabilities of the device. In addition to
these general-purpose peripherals, the processors contain high
speed serial and parallel ports for interfacing to a variety of
audio, video, and modem codec functions. An MXVR transceiver transmits and receives audio and video data and control
information on a MOST automotive multimedia network. A
CAN 2.0B controller is provided for automotive control networks. An interrupt controller manages interrupts from the onchip peripherals or external sources. And power management
control functions tailor the performance and power characteristics of the processor and system to many application scenarios.
LOW POWER ARCHITECTURE
Blackfin processors provide world class power management and
performance. Blackfin processors are designed in a low power
and low voltage design methodology and feature dynamic
power management, the ability to vary both the voltage and frequency of operation to significantly lower overall power
consumption. Varying the voltage and frequency can result in a
substantial reduction in power consumption, compared with
simply varying the frequency of operation. This translates into
longer battery life and lower heat dissipation.
Rev. F |
SYSTEM INTEGRATION
Page 3 of 60 |
All of the peripherals, GPIO, CAN, TWI, real-time clock, and
timers, are supported by a flexible DMA structure. There are
also four separate memory DMA channels dedicated to data
transfers between the processor’s various memory spaces,
including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough
bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals.
The ADSP-BF539/ADSP-BF539F processors include an on-chip
voltage regulator in support of the processor’s dynamic power
management capability. The voltage regulator provides a range
of core voltage levels from VDDEXT. The voltage regulator can be
bypassed at the user's discretion.
October 2013
ADSP-BF539/ADSP-BF539F
BLACKFIN PROCESSOR CORE
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
As shown in Figure 2, the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-bit, 16-bit, or 32-bit data from the register file.
ADDRESS ARITHMETIC UNIT
L3
B3
M3
I2
L2
B2
M2
I1
L1
B1
M1
I0
L0
B0
M0
SP
FP
P5
DAG1
P4
P3
DAG0
P2
32
32
P1
P0
TO MEMORY
DA1
DA0
I3
32
PREG
32
RAB
SD
LD1
LD0
32
32
32
ASTAT
32
32
SEQUENCER
R7.H
R6.H
R7.L
R6.L
R5.H
R5.L
R4.H
R4.L
R3.H
R3.L
R2.H
R2.L
R1.H
R1.L
R0.H
R0.L
16
ALIGN
16
8
8
8
8
DECODE
BARREL
SHIFTER
40
40
A0
32
40
40
A1
LOOP BUFFER
CONTROL
UNIT
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search
instructions.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
Rev. F
|
Page 4 of 60 |
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero overhead looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
October 2013
ADSP-BF539/ADSP-BF539F
CORE MMR REGISTERS (2M BYTES)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTES)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTES)
0xFFB0 0000
RESERVED
0xFFA1 4000
INSTRUCTION SRAM / CACHE (16K BYTES)
0xFFA1 0000
INSTRUCTION SRAM (64K BYTES)
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM / CACHE (16K BYTES)
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory management Unit (MMU) provides memory protection for individual
tasks that can be operating on the core and can protect system
registers from unintended access.
0xFF90 4000
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
0xFF80 0000
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF539/ADSP-BF539F processors view memory as a
single unified 4G byte address space, using 32-bit addresses. All
resources, including internal memory, external memory, and
I/O control registers, occupy separate sections of this common
address space. The memory portions of this address space are
arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip
memory as cache or SRAM, and larger, lower cost and performance off-chip memory systems. See Figure 3.
The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of physical
memory.
The memory DMA controller provides high bandwidth data
movement capability. It performs block transfers of code or data
between the internal memory and the external memory spaces.
Rev. F |
Page 5 of 60 |
DATA BANK B SRAM (16K BYTES)
INTERNAL MEMORY MAP
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
0xFFFF FFFF
0xFF90 0000
RESERVED
0xFF80 8000
DATA BANK A SRAM / CACHE (16K BYTES)
0xFF80 4000
DATA BANK A SRAM (16K BYTES)
RESERVED
0xEF00 0000
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTES) OR
ON-CHIP FLASH (ADSP-BF539F ONLY)
0x2030 0000
0x2020 0000
ASYNC MEMORY BANK 2 (1M BYTES) OR
ON-CHIP FLASH (ADSP-BF539F ONLY)
ASYNC MEMORY BANK 1 (1M BYTES) OR
ON-CHIP FLASH (ADSP-BF539F ONLY)
0x2010 0000
0x2000 0000
ASYNC MEMORY BANK 0 (1M BYTES) OR
ON-CHIP FLASH (ADSP-BF539F ONLY)
EXTERNAL MEMORY MAP
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
RESERVED
0x0800 0000
0x0000 0000
SDRAM MEMORY
(16M BYTES TO 128M BYTES)
Figure 3. ADSP-BF539/ADSP-BF539F Internal/External Memory Map
Internal (On-Chip) Memory
The ADSP-BF539/ADSP-BF539F processor has three blocks of
on-chip memory, providing high bandwidth access to the core.
The first is the L1 instruction memory, consisting of 80K bytes
SRAM, of which 16K bytes can be configured as a four-way setassociative cache. This memory is accessed at full processor
speed.
The second on-chip memory block is the L1 data memory, consisting of two banks of up to 32K bytes each. Each memory bank
is configurable, offering both cache and SRAM functionality.
This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratch pad SRAM, which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
October 2013
ADSP-BF539/ADSP-BF539F
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128M bytes of SDRAM. The SDRAM controller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully populated with 1M byte of memory.
Flash Memory (ADSP-BF539F Only)
The ADSP-BF539F8 processor contains a separate flash die,
connected to the EBIU bus, within the package of the processor.
Figure 4 shows how the flash memory die and Blackfin processor die are connected.
The ADSP-BF539F8 contains an 8M bit (512K × 16-bit) bottom
boot sector Spansion S29AL008J known good die flash memory.
Additional information for this product can be found in the
Spansion data sheet at www.spansion.com. Features include the
following:
• Access times as fast as 70 ns (EBIU registers must be set
appropriately)
The flash chip enable pin FCE must be connected to AMS0 or
AMS3–1 through a printed circuit board trace. When connected
to AMS0, the Blackfin processor can boot from the flash die.
When connected to AMS3–1, the flash memory appears as nonvolatile memory in the processor memory map, shown in
Figure 3.
Flash Memory Programming
The ADSP-BF539F8 flash memory can be programmed before
or after mounting on the printed circuit board.
To program the flash prior to mounting on the printed circuit
board, use a hardware programming tool that can provide the
data, address, and control stimuli to the flash die through the
external pins on the package. During this programming, VDDEXT
and GND must be provided to the package and the Blackfin
must be held in reset with bus request (BR) asserted and a
CLKIN provided.
The VisualDSP++ tools can be used to program the flash memory after the device is mounted on a printed circuit board.
Flash Memory Sector Protection
To use the sector protection feature, a high voltage (+8.5 V to
+12.5 V) must be applied to the flash FRESET pin. Refer to the
flash data sheet for details.
• Sector protection
I/O Memory Space
• One million write cycles per sector
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. Onchip I/O devices have their control registers mapped into memory mapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller
blocks, one of which contains the control MMRs for all core
functions, and the other of which contains the registers needed
for setup and control of the on-chip peripherals outside of the
core. The MMRs are accessible only in supervisor mode and
appear as reserved space to on-chip peripherals.
ADDR19-1
ARE
AWE
ARDY
DATA15-0
A18-0
OE
WE
RY/BY
DQ15-0
VSS
VCC
BYTE
CE
RESET
WP
GND
VDDEXT
AMS3-0
RESET
B
S29AL008J
FLASH DIE
ADDR19ARE
AWE
ARDY
DATA15-0
GND
VDDEXT
• 20 year data retention
Booting
The ADSP-BF539/ADSP-BF539F processors contain a small
boot kernel, which configures the appropriate peripheral for
booting. If the processors are configured to boot from boot
ROM memory space, they start executing from the on-chip boot
ROM. For more information, see Booting Modes on Page 16.
ADSP-BF539F
PACKAGE
FCE
FRESET
NC
RESET
AMS3-0
Event Handling
Figure 4. Internal Connection of Flash Memory (ADSP-BF539F8)
The Blackfin processor connects to the flash memory die with
address, data, chip enable, write enable, and output enable controls as if it were an external memory device. Note that the
write-protect input pin to the flash is not connected and inaccessible, disabling this feature.
The event controller handles all asynchronous and synchronous
events to the processor. The processors provide event handling
that supports both nesting and prioritization. Nesting allows
multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes
precedence over servicing of a lower priority event. The controller provides support for five different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
Rev. F
|
Page 6 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shutdown of the system.
• Exceptions – Events that occur synchronously to program
flow (i.e., the exception will be taken before the instruction
is allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF539/ADSP-BF539F processor’s event controller
consists of two stages, the core event controller (CEC) and the
system interrupt controller (SIC). The core event controller
works with the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from the
peripherals enter into the SIC and are then routed directly into
the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority interrupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the processor’s peripherals. Table 2 describes the inputs
to the CEC, identifies their names in the event vector table
(EVT), and lists their priorities.
System Interrupt Controller (SIC)
The system interrupt controller (SIC) provides the mapping and
routing of events from the many peripheral interrupt sources to
the prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF539/ADSP-BF539F processors provide a
default mapping, the user can alter the mappings and priorities
of interrupt events by writing the appropriate values into the
interrupt assignment registers (SIC_IARx). Table 3 describes
the inputs into the SIC and the default mappings into the CEC.
Event Control
The ADSP-BF539/ADSP-BF539F processors provide the user
with a very flexible mechanism to control the processing of
events. In the CEC, three registers are used to coordinate and
control events. Each register is 32 bits wide:
• CEC interrupt latch register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and is
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it can also be written to clear (cancel) latched events. This
Rev. F |
Page 7 of 60 |
register may be read while in supervisor mode and may
only be written while in supervisor mode when the corresponding IMASK bit is cleared.
• CEC interrupt mask register (IMASK) – The IMASK register controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event,
preventing the processor from servicing the event even
though the event can be latched in the ILAT register. This
register can be read or written while in supervisor mode.
General-purpose interrupts can be globally enabled and
disabled with the STI and CLI instructions, respectively.
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates whether the event is currently
active or nested at some level. This register is updated automatically by the controller but can be read while in
supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3 on Page 8.
• SIC interrupt mask registers (SIC_IMASKx) – These registers control the masking and unmasking of each peripheral
interrupt event. When a bit is set in these registers, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in these registers masks
the peripheral event, preventing the processor from servicing the event.
• SIC interrupt status registers (SIC_ISRx) – As multiple
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates that the
peripheral is asserting the interrupt, and a cleared bit indicates that the peripheral is not asserting the event.
• SIC interrupt wake-up enable registers (SIC_IWRx) – By
enabling the corresponding bit in these registers, a peripheral can be configured to wake up the processor, should the
core be idled or in sleep mode when the event is generated.
(For more information, see Dynamic Power Management
on Page 13.)
Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the
October 2013
ADSP-BF539/ADSP-BF539F
general-purpose interrupt to the IPEND output asserted is three
core clock cycles; however, the latency can be much higher,
depending on the activity within and the state of the processor.
Table 3. System and Core Event Mapping (Continued)
Event Source
Core
Event Name
Table 2. Core Event Controller (CEC)
DMA3 Interrupt (SPORT1 Rx)
IVG9
Priority
(0 is Highest)
DMA4 Interrupt (SPORT1 Tx)
IVG9
Event Class
EVT Entry
DMA8 Interrupt (SPORT2 Rx)
IVG9
0
Emulation/Test Control
EMU
DMA9 Interrupt (SPORT2 Tx)
IVG9
IVG9
1
Reset
RST
DMA10 Interrupt (SPORT3 Rx)
2
Nonmaskable Interrupt
NMI
DMA11 Interrupt (SPORT3 Tx)
IVG9
IVG10
3
Exception
EVX
DMA5 Interrupt (SPI0)
4
Reserved
—
DMA14 Interrupt (SPI1)
IVG10
IVG10
5
Hardware Error
IVHW
DMA15 Interrupt (SPI2)
6
Core Timer
IVTMR
DMA6 Interrupt (UART0 Rx)
IVG10
IVG10
7
General Interrupt 7
IVG7
DMA7 Interrupt (UART0 Tx)
8
General Interrupt 8
IVG8
DMA16 Interrupt (UART1 Rx)
IVG10
IVG10
9
General Interrupt 9
IVG9
DMA17 Interrupt (UART1 Tx)
10
General Interrupt 10
IVG10
DMA18 Interrupt (UART2 Rx)
IVG10
IVG10
11
General Interrupt 11
IVG11
DMA19 Interrupt (UART2 Tx)
12
General Interrupt 12
IVG12
Timer0, Timer1, Timer2 Interrupts
IVG11
IVG11
13
General Interrupt 13
IVG13
TWI0 Interrupt
14
General Interrupt 14
IVG14
TWI1 Interrupt
IVG11
IVG15
CAN Receive Interrupt
IVG11
15
General Interrupt 15
Table 3. System and Core Event Mapping
CAN Transmit Interrupt
IVG11
MXVR Status Interrupt
IVG11
Core
Event Name
MXVR Control Message Interrupt
IVG11
Event Source
MXVR Asynchronous Packet Interrupt
IVG11
PLL Wake-Up Interrupt
IVG7
Programmable Flags Interrupts
IVG12
DMA Controller 0 Error
IVG7
MDMA0 Stream 0 Interrupt
IVG13
DMA Controller 1 Error
IVG7
MDMA0 Stream 1 Interrupt
IVG13
PPI Error Interrupt
IVG7
MDMA1 Stream 0 Interrupt
IVG13
SPORT0 Error Interrupt
IVG7
MDMA1 Stream 1 Interrupt
IVG13
SPORT1 Error Interrupt
IVG7
Software Watchdog Timer
IVG13
SPORT2 Error Interrupt
IVG7
SPORT3 Error Interrupt
IVG7
MXVR Synchronous Data Interrupt
IVG7
SPI0 Error Interrupt
IVG7
SPI1 Error Interrupt
IVG7
SPI2 Error Interrupt
IVG7
UART0 Error Interrupt
IVG7
UART1 Error Interrupt
IVG7
UART2 Error Interrupt
IVG7
CAN Error Interrupt
IVG7
Real-Time Clock Interrupt
IVG8
DMA0 Interrupt (PPI)
IVG8
DMA1 Interrupt (SPORT0 Rx)
IVG9
DMA2 Interrupt (SPORT0 Tx)
IVG9
Rev. F
DMA CONTROLLERS
The processors have multiple, independent DMA controllers
that support automated data transfers with minimal overhead
for the processor core. DMA transfers can occur between the
ADSP-BF539/ADSP-BF539F processor internal memories and
any of its DMA capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable
peripherals and external devices connected to the external
memory interfaces, including the SDRAM controller and the
asynchronous memory controller. DMA capable peripherals
include the SPORTs, SPI ports, UARTs, and PPI. Each individual DMA capable peripheral has at least one dedicated DMA
channel. In addition, the MXVR peripheral has its own dedicated DMA controller, which supports its own unique set of
operating modes.
|
Page 8 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
The DMA controllers support both 1-dimensional (1-D) and
2-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of
parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements and arbitrary row and
column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
deinterleaved on the fly.
Like the other peripherals, the RTC can wake up the processor
from sleep mode upon generation of any RTC wake-up event.
Additionally, an RTC wake-up event can wake up the processor
from deep sleep mode, and wake up the on-chip internal voltage
regulator from a powered down state.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 5.
RTXI
RTXO
R1
Examples of DMA types supported by the processor’s DMA
controller include:
X1
• A single, linear buffer that stops upon completion
C1
C2
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
four memory DMA channels provided for transfers between the
various memories of the ADSP-BF539/ADSP-BF539F processor
system. This enables transfers of blocks of data between any of
the memories—including external SDRAM, ROM, SRAM, and
flash memory—with minimal processor intervention. Memory
DMA transfers can be controlled by a very flexible descriptorbased methodology or by a standard register-based autobuffer
mechanism.
REAL-TIME CLOCK
The ADSP-BF539/ADSP-BF539F processor real-time clock
(RTC) provides a robust set of digital watch features, including
current time, stopwatch, and alarm. The RTC is clocked by a
32.768 kHz crystal external to the Blackfin processors. The RTC
peripheral has dedicated power supply pins so that it can remain
powered up and clocked even when the rest of the processor is
in a low power state. The RTC provides several programmable
interrupt options, including interrupt per second, minute, hour,
or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60-second counter, a 60-minute counter, a
24-hour counter, and an 32,768-day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: the first alarm is
for a time of day. The second alarm is for a day and time of
that day.
The stopwatch function counts down from a programmed
value, with one second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Rev. F |
Page 9 of 60 |
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22pF
C2 = 22pF
R1 = 10M:
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3pF.
Figure 5. External Components for RTC
WATCHDOG TIMER
The processors include a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state through generation of a hardware reset, nonmaskable
interrupt (NMI), or general-purpose interrupt, if the timer
expires before being reset by software. Programs initialize the
count value of the timer, enable the appropriate interrupt, and
then enable the timer. Thereafter, the software must reload the
counter before it counts to zero from the programmed value.
This protects the system from remaining in an unknown state
where software, which would normally reset the timer, has
stopped running due to an external noise condition or software
error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
TIMERS
There are four general-purpose programmable timer units in
the ADSP-BF539/ADSP-BF539F processors. Three timers have
an external pin that can be configured either as a pulse-width
modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths and
periods of external events. These timers can be synchronized to
October 2013
ADSP-BF539/ADSP-BF539F
an external clock input to the PF1 pin (TACLK), an external
clock input to the PPI_CLK pin (TMRCLK), or to the internal
SCLK.
The timer units can be used in conjunction with UART0 to
measure the width of the pulses in the data stream to provide an
auto-baud detect function for a serial channel.
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
SERIAL PORTS (SPORTS)
The ADSP-BF539/ADSP-BF539F processors incorporate four
dual-channel synchronous serial ports for serial and multiprocessor communications. The SPORTs support the following
features:
• I2S capable operation.
• Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling 16 channels of
I2S stereo audio.
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 bits to 32 bits in length, transferred most significant
bit first or least significant bit first.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or μ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The processors incorporate three SPI-compatible ports that
enable the processor to communicate with multiple SPI compatible devices.
The SPI interface uses three pins for transferring data: two data
pins (master output-slave input, MOSIx, and master input-slave
output, MISOx) and a clock pin (serial clock, SCKx). An SPI
chip select input pin (SPIxSS) lets other SPI devices select the
processor. For SPI0, seven SPI chip select output pins (SPI0SEL7–1) let the processor select other SPI devices. SPI1 and
SPI2 each have a single SPI chip select output pin (SPI1SEL1
and SPI2SEL1) for SPI point-to-point communication. Each of
the SPI select pins is a reconfigured GPIO pin. Using these pins,
the SPI ports provide a full-duplex, synchronous serial interface,
which supports both master/slave modes and multimaster
environments.
The SPI ports’ baud rate and clock phase/polarities are programmable, and they each have an integrated DMA controller,
configurable to support transmit or receive data streams. Each
SPI DMA controller can only service unidirectional accesses at
any given time.
The SPI port clock rate is calculated as:
f SCLK
SPI Clock Rate = ----------------------------------2 SPIx_BAUD
where the 16-bit SPIx_BAUD register contains a value of 2 to
65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
2-WIRE INTERFACE
The processors incorporate two 2-wire interface (TWI) modules
that are compatible with the Philips Inter-IC bus standard. The
TWI modules offer the capabilities of simultaneous master and
slave operation, support for 7-bit addressing, and multimedia
data arbitration. The TWI also includes master clock synchronization and support for clock low extension.
The TWI interface uses two pins for transferring clock (SCLx)
and data (SDAx) and supports the protocol at speeds up to
400 kbps.
The TWI interface pins are compatible with 5 V logic levels.
UART PORTS
The processors incorporate three full-duplex universal asynchronous receiver/transmitter (UART) ports, which are fully
compatible with PC standard UARTs. The UART ports provide
a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA supported, asynchronous transfers of
serial data. The UART ports include support for 5 data bits to
8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd parity. The UART ports support two modes of operation:
• Multichannel capability – Each SPORT supports 128 channels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
Rev. F
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ADSP-BF539/ADSP-BF539F
• Flag interrupt mask registers – The two flag interrupt mask
registers allow each individual PFx pin to function as an
interrupt to the processor. Similar to the two flag control
registers that are used to set and clear individual flag values,
one flag interrupt mask register sets bits to enable interrupt
function, and the other flag interrupt mask register clears
bits to disable interrupt function. PFx pins defined as
inputs can be configured to generate hardware interrupts,
while output PFx pins can be triggered by software
interrupts.
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
• Flag interrupt sensitivity registers – The two flag interrupt
sensitivity registers specify whether individual PFx pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
Each UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/1,048,576) to
(fSCLK/16) bits per second.
• Supporting data formats from 7 bits to 12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
Each UART port’s clock rate is calculated as:
f SCLK
UART Clock Rate = ------------------------------------------16 UART_Divisor
The PFx pins can also be used by the SPI0 and PPI ports as
shown in Table 4, depending on how the peripherals are configured. Care must be taken so that these pins are not used for
multiple purposes simultaneously.
General-Purpose I/O Ports C, D, and E
where the 16-bit UART_Divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant 8 bits).
In conjunction with the general-purpose timer functions, autobaud detection is supported on UART0.
There are 38 general-purpose I/O pins that are multiplexed with
other peripherals. They are arranged into Ports C, D, and E as
shown in Table 4. The GPIO differ from the programmable
flags on Port F in that the GPIO pins cannot generate interrupts
to the processor.
The capabilities of the UARTs are further extended with support for the Infrared Data Association (IrDA®) Serial Infrared
Physical Layer Link Specification (SIR) protocol.
Table 4. Programmable Flag/GPIO Ports
PROGRAMMABLE I/O PINS
Peripheral
Alternate Programmable Flag/
GPIO Port Function
The ADSP-BF539/ADSP-BF539F processor has numerous
peripherals that may not all be required for every application.
Therefore, many of the pins have a secondary function as programmable I/O pins. There are two types of programmable I/O
pins with slightly different functionality: programmable flags
and general-purpose I/O.
PPI
PF15–3
Programmable Flags (GPIO Port F)
There are 16 bidirectional, general-purpose programmable flag
(PF15–0) pins on GPIO Port F. Each programmable flag can be
individually controlled by manipulation of the flag control, status, and interrupt registers:
SPORT2
PE7–0
SPORT3
PE15–8
SPI0
PF7–0
SPI1
PD4–0
SPI2
PD9–5
UART1
PD11–10
UART2
PD13–12
CAN
PC1–01
MXVR
PC9–41
• Flag direction control register – Specifies the direction of
each individual PFx pin as input or output.
1
• Flag control and status registers – The processors employ a
“write one to modify” mechanism that allows any combination of individual flags to be modified in a single
instruction, without affecting the level of any other flags.
Four control registers are provided. One register is written
in order to set flag values, one register is written in order to
clear flag values, one register is written in order to toggle
flag values, and one register is written in order to specify a
flag value. Reading the flag status register allows software to
interrogate the sense of the flags.
The general-purpose I/O pins can be individually controlled by
manipulation of the control and status registers. These pins will
not cause interrupts to be generated to the processor but can be
polled to determine their status.
Rev. F
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PC1 and PC4 are open-drain when configured as GPIO outputs.
• GPIO direction control register – Specifies the direction of
each individual GPIOx pin as input or output.
• GPIO control and status registers – The processors employ
a “write one to modify” mechanism that allows any combination of individual GPIO pins to be modified in a single
October 2013
ADSP-BF539/ADSP-BF539F
instruction, without affecting the level of any other GPIO
pin. Four control registers and a data register are provided
for each GPIO port. One register is written in order to set
GPIO pin values, one register is written in order to clear
GPIO pin values, one register is written in order to toggle
GPIO pin values, and one register is written in order to
specify a GPIO input or output. Reading the GPIO data
register allows software to determine the state of the input
GPIO pins.
Note that the GP pin is used to specify the status of the GPIO
pins PC9–PC4 at power up. If GP is tied high, then pins
PC9–PC4 are configured as GPIO after reset. The pins cannot
be reconfigured through software, and special care must be
taken with the MLF pin. If the GP pin is tied low, then the pins
are configured as MXVR pins after reset but can be reconfigured as GPIO pins through software.
PARALLEL PERIPHERAL INTERFACE
The ADSP-BF539/ADSP-BF539F processors provide a parallel
peripheral interface (PPI) that can connect directly to parallel
ADC and DAC converters, video encoders and decoders, and
other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to 3 frame synchronization pins, and
up to 16 data pins. The input clock supports parallel data rates
up to fSCLK/2 MHz, and the synchronization signals can be configured as either inputs or outputs.
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bidirectional data transfer with up to 16 bits of
data. Up to 3 frame synchronization signals are also provided.
In ITU-R 656 mode, the PPI provides half-duplex, bidirectional
transfer of 8- or 10-bit video data. Additionally, on-chip decode
of embedded start-of-line (SOL) and start-of-field (SOF) preamble packets are supported.
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
• Input Mode – Frame syncs and data are inputs into the PPI.
• Frame Capture Mode – Frame syncs are outputs from the
PPI, but data are inputs.
• Output Mode – Frame syncs and data are outputs from
the PPI.
Input Mode
This mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_COUNT register. The PPI supports 8-bit, and 10-bit
through 16-bit data and are programmable in the PPI_CONTROL register.
Rev. F
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Frame Capture Mode
This mode allows the video source(s) to act as a slave (e.g., for
frame capture). The processors control when to read from the
video source(s). PPI_FS1 is an HSYNC output, and PPI_FS2 is a
VSYNC output.
Output Mode
This mode is used for transmitting video or other data with up
to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hardware signaling.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applications. Three distinct submodes are supported:
• Active Video Only Mode
• Vertical Blanking Only Mode
• Entire Field Mode
Active Video Only Mode
This mode is used when only the active video portion of a field
is of interest and not any of the blanking intervals. The PPI will
not read in any data between the end of active video (EAV) and
start of active video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the
control byte sequences are not stored to memory; they are
filtered by the PPI. After synchronizing to the start of Field 1,
the PPI ignores incoming samples until it sees an SAV code. The
user specifies the number of active video lines per frame (in the
PPI_COUNT register).
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
Entire Field Mode
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that can be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after
synchronization to Field 1.
CONTROLLER AREA NETWORK (CAN) INTERFACE
The ADSP-BF539/ADSP-BF539F processors provide a CAN
controller that is a communication controller implementing the
controller area network (CAN) V2.0B protocol. This protocol is
an asynchronous communications protocol used in both industrial and automotive control systems. CAN is well suited for
control applications due to its ability to communicate reliably
over a network since the protocol incorporates CRC checking,
message error tracking, and fault node confinement.
October 2013
ADSP-BF539/ADSP-BF539F
The CAN controller is based on a 32-entry mailbox RAM and
supports both the standard and extended identifier (ID) message formats specified in the CAN protocol specification,
Revision 2.0, Part B.
Each mailbox consists of eight 16-bit data words. The data is
divided into fields, which includes a message identifier, a time
stamp, a byte count, up to 8 bytes of data, and several control
bits. Each node monitors the messages being passed on the network. If the identifier in the transmitted message matches an
identifier in one of its mailboxes, then the module knows that
the message was meant for it, passes the data into its appropriate
mailbox, and signals the processor of message arrival with an
interrupt.
The CAN controller can wake up the processor from sleep mode
upon generation of a wake-up event, such that the processor can
be maintained in a low power mode during idle conditions.
Additionally, a CAN wake-up event can wake up the on-chip
internal voltage regulator from the hibernate state.
The electrical characteristics of each network connection are
very stringent; therefore, the CAN interface is typically divided
into two parts: a controller and a transceiver. This allows a single controller to support different drivers and CAN networks.
The ADSP-BF539/ADSP-BF539F CAN module represents the
controller part of the interface. This module’s network I/O is a
single transmit output and a single receive input, which connect
to a line transceiver.
The CAN clock is derived from the processor system clock
(SCLK) through a programmable divider and therefore does not
require an additional crystal.
MEDIA TRANSCEIVER MAC LAYER (MXVR)
The ADSP-BF539/ADSP-BF539F processors provide a media
transceiver (MXVR) MAC layer, allowing the processor to be
connected directly to a MOST network through just an FOT or
electrical PHY.
The MXVR is fully compatible with industry standard
standalone MOST controller devices, supporting 22.579 Mbps
or 24.576 Mbps data transfer. It offers faster lock times, greater
jitter immunity, and a sophisticated DMA scheme for data
transfers. The high speed internal interface to the core and L1
memory allows the full bandwidth of the network to be utilized.
The MXVR can operate as either the network master or as a network slave.
Synchronous data is transferred to or from the synchronous
data channels through eight programmable DMA engines. The
synchronous data DMA engines can operate in various modes,
including modes that trigger DMA operation when data patterns are detected in the receive data stream. Furthermore, two
DMA engines support asynchronous traffic and control message traffic.
Interrupts are generated when a user-defined amount of synchronous data has been sent or received by the processor or
when asynchronous packets or control messages have been sent
or received.
Rev. F
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The MXVR peripheral can wake up the processor from sleep
mode when a wake-up preamble is received over the network or
based on any other MXVR interrupt event. Additionally, detection of network activity by the MXVR can be used to wake up
the processor from sleep mode and wake up the on-chip internal voltage regulator from the powered-down hibernate state.
These features allow the processor to operate in a low-power
state when there is no network activity or when data is not currently being received or transmitted by the MXVR.
The MXVR clock is provided through a dedicated external crystal or crystal oscillator. For 44.1 kHz frame syncs, use a
45.1584 MHz crystal or oscillator; for 48 kHz frame syncs, use a
49.152 MHz crystal or oscillator. If using a crystal to provide the
MXVR clock, use a parallel-resonant, fundamental mode,
microprocessor-grade crystal.
DYNAMIC POWER MANAGEMENT
The ADSP-BF539/ADSP-BF539F processors provide four operating modes, each with a different performance/power profile.
In addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
further reducing power dissipation. Control of clocking to each
of the ADSP-BF539/ADSP-BF539F processor peripherals also
reduces power consumption. See Table 5 for a summary of the
power settings for each mode.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Dynamic Power
Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.
In the active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Table 5. Power Settings
Mode/State PLL
Core
PLL
Clock
Bypassed (CCLK)
System
Clock
Core
(SCLK) Power
Full-On
Enabled
No
Enabled Enabled On
Active
Enabled/
disabled
Yes
Enabled Enabled On
Sleep
Enabled
Disabled Enabled On
Deep Sleep
Disabled
Disabled Disabled On
Hibernate
Disabled
Disabled Disabled Off
October 2013
ADSP-BF539/ADSP-BF539F
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typically, an external event or RTC activity wakes up the processor.
When in the sleep mode, assertion of a wake-up event enabled
in the SIC_IWRx register causes the processor to sense the value
of the BYPASS bit in the PLL control register (PLL_CTL). If
BYPASS is disabled, the processor transitions to the full on
mode. If BYPASS is enabled, the processor will transition to the
active mode. When in the sleep mode, system DMA access to L1
memory is not supported.
• The 1.25 V VDDINT power domain supplies all internal logic
except for the RTC logic and the MXVR PLL.
• The 3.3 V VDDEXT power domain supplies all I/O except for
the RTC and MXVR crystals.
There are no sequencing requirements for the various power
domains.
Table 6. Power Domains
Power Domain
VDD Range
RTC Crystal I/O and Logic
VDDRTC
MXVR Crystal I/O
MXEVDD
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
MXVR PLL Analog and Logic
MPIVDD
All Internal Logic Except RTC and MXVR PLL
VDDINT
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
such as the RTC may still be running but will not be able to
access internal resources or external memory. This powereddown mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous
interrupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the processor to transition to the full-on mode.
All I/O Except RTC and MXVR Crystals
VDDEXT
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This sets the internal power
supply voltage (VDDINT) to 0 V to provide the lowest static power
dissipation. Any critical information stored internally (memory
contents, register contents, etc.) must be written to a nonvolatile
storage device prior to removing power if the processor state is
to be preserved. Since VDDEXT can still be supplied in this mode,
all of the external pins three-state, unless otherwise specified.
This allows other devices that may be connected to the processor to still have power applied without drawing unwanted
current. The internal supply regulator can be woken up either
by a real-time clock wake-up, by CAN bus traffic, by asserting
the RESET pin, or by an external source via the GPW pin.
Power Savings
As shown in Table 6, the ADSP-BF539/ADSP-BF539F processors support five different power domains. The use of multiple
power domains maximizes flexibility, while maintaining compliance with industry standards and conventions:
• The 3.3 V VDDRTC power domain supplies the RTC I/O and
logic so that the RTC can remain functional when the rest
of the chip is powered off.
The VDDRTC should either be connected to an isolated supply
such as a battery (if the RTC is to operate while the rest of the
chip is powered down) or should be connected to the VDDEXT
plane on the board. The VDDRTC should remain powered when
the processor is in hibernate state and should also remain powered even if the RTC functionality is not being used in an
application. The MXEVDD should be connected to the VDDEXT
plane on the board at a single location with local bypass capacitors. The MXEVDD should remain powered when the
processor is in hibernate state and should also remain powered
even when the MXVR functionality is not being used in an
application. The MPIVDD should be connected to the VDDINT
plane on the board at a single location through a ferrite bead
with local bypass capacitors.
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive in
that, if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The dynamic power management feature of the
ADSP-BF539/ADSP-BF539F processors allow both the processor input voltage (VDDINT) and clock frequency (fCCLK) to be
dynamically controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as
Power Savings Factor
f CCLKRED V DDINTRED 2 t RED
= ------------------- ------------------------ ---------f CCLKNOM V DDINTNOM t NOM
where:
• The 3.3 V MXEVDD power domain supplies the MXVR
crystal and is separate to provide noise isolation.
fCCLKNOM is the nominal core clock frequency.
• The 1.25 V MPIVDD power domain supplies the MXVR
PLL and is separate to provide noise isolation.
VDDINTNOM is the nominal internal supply voltage.
Rev. F
|
Page 14 of 60 |
fCCLKRED is the reduced core clock frequency.
October 2013
ADSP-BF539/ADSP-BF539F
If an external clock is used, it should be a TTL-compatible signal
and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
VDDINTRED is the reduced internal supply voltage.
tNOM is the duration running at fCCLKNOM.
tRED is the duration running at fCCLKRED.
The Power Savings Factor is calculated as
% Power Savings = 1 – Power Savings Factor 100%
Alternatively, because the processors include an on-chip oscillator circuit, an external crystal can be used. For fundamental
frequency operation, use the circuit shown in Figure 7. A parallel-resonant, fundamental frequency, microprocessor-grade
crystal is connected across the CLKIN and XTAL pins. The onchip resistance between CLKIN and the XTAL pin is in the
500 kW range. Further parallel resistors are typically not recommended. The two capacitors and the series resistor, shown in
Figure 7, fine tune the phase and amplitude of the sine frequency. The capacitor and resistor values, shown in Figure 7,
are typical values only. The capacitor values are dependent upon
the crystal manufacturer’s load capacitance recommendations
and the physical PCB layout. The resistor value depends on the
drive level specified by the crystal manufacturer. System designs
should verify the customized values based on careful investigation on multiple devices over the allowed temperature range.
VOLTAGE REGULATION
The Blackfin processors provide an on-chip voltage regulator
that can generate appropriate VDDINT voltage levels from the
VDDEXT supply. See Operating Conditions on Page 26 for regulator tolerances and acceptable VDDEXT ranges for specific models.†
The regulator controls the internal logic voltage levels and is
programmable with the voltage regulator control register
(VR_CTL) in increments of 50 mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while I/O power (VDDRTC,
MXEVDD, VDDEXT) is still supplied. While in the hibernate
state, I/O power is still being applied, eliminating the need for
external buffers. The voltage regulator can be activated from
this power-down state through an RTC wake-up, a CAN wakeup, an MXVR wake-up, a general-purpose wake-up, or by
asserting RESET, all of which will then initiate a boot sequence.
The regulator can also be disabled and bypassed at the user’s
discretion.
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 7.
SET OF DECOUPLING
CAPACITORS
VDDEXT
(LOW-INDUCTANCE)
VDDEXT
+
100μF
10μH
100nF
+
VDDINT
+
As shown in Figure 8 on Page 16, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 0.5× to 64× multiplication factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10×, but it can be
modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the
PLL_DIV register.
100μF
FDS9431A
10μF
LOW ESR
100μF
Blackfin
ZHCS1000
VROUT
CLKOUT
TO PLL CIRCUITRY
EN
SHORT AND LOWINDUCTANCE WIRE
VROUT
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
700:
GND
VDDEXT
XTAL
CLKIN
Figure 6. Voltage Regulator Circuit
1M:
0: *
CLOCK SIGNALS
The ADSP-BF539/ADSP-BF539F processors can be clocked by
an external crystal, a sine wave input, or a buffered, shaped
clock derived from an external clock oscillator.
18pF*
18pF*
FOR OVERTONE
OPERATION ONLY
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
Figure 7. External Crystal Connections
†
See Switching Regulator Design Considerations for ADSP-BF533 Blackfin
Processors (EE-228).
Rev. F
|
Page 15 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
BOOTING MODES
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
CLKIN
PLL
0.5uTO 64u
“COARSE” ADJUSTMENT
ON-THE-FLY
÷ 1, 2, 4, 8
CCLK
÷ 1:15
SCLK
The ADSP-BF539/ADSP-BF539F processors have three mechanisms (listed in Table 9) for automatically loading internal L1
instruction memory after a reset. A fourth mode is provided to
execute from external memory, bypassing the boot sequence.
Table 9. Booting Modes
VCO
BMODE1–0 Description
00
Execute from 16-bit external memory
(bypass boot ROM)
01
Boot from 8-bit or 16-bit flash or boot from on-chip
flash (ADSP-BF539F only)
10
Boot from SPI serial master connected to SPI0
11
Boot from SPI serial slave EEPROM/flash
(8-,16-, or 24-bit address range, or Atmel
AT45DB041, AT45DB081, or AT45DB161serial flash)
connected to SPI0
SCLK d CCLK
SCLK d 133MHz
Figure 8. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 7 illustrates typical system clock ratios.
Table 7. Example System Clock Ratios
Signal Name Divider Ratio Example Frequency Ratios (MHz)
SSEL3–0
VCO/SCLK
VCO
SCLK
0001
1:1
100
100
0110
6:1
300
50
1010
10:1
500
50
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock frequency to its maximum of fSCLK. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
Note that when the SSEL value is changed, it will affect all the
peripherals that derive their clock signals from the SCLK signal.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 8. This programmable core clock capability is useful for
fast core frequency modifications.
Table 8. Core Clock Ratios
Signal Name
CSEL1–0
Divider Ratio
VCO/CCLK
Example Frequency Ratios
VCO
CCLK
00
1:1
300
300
01
2:1
300
150
10
4:1
500
125
11
8:1
200
25
The BMODE pins of the reset configuration register, sampled
during power-on resets and software initiated resets, implement
the following modes:
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit or 16-bit external flash memory – The 8-bit
flash boot routine located in boot ROM memory space is
set up using asynchronous memory bank 0. For
ADSP-BF539F processors, if FCE is connected to AMS0,
then the on-chip flash is booted. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit
addressable, or Atmel AT45DB041, AT45DB081, or
AT45DB161) connected to SPI0 – The SPI0 port uses the
PF2 output pin to select a single SPI EEPROM/flash device,
submits a read command and successive address bytes
(0x00) until a valid 8-, 16-, or 24-bit, or Atmel addressable
device is detected, and begins clocking data into the beginning of the L1 instruction memory.
• Boot from SPI host device connected to SPI0 – The Blackfin processor operates in SPI slave mode and is configured
to receive the bytes of the .LDR file from an SPI host (master) agent. To hold off the host device from transmitting
while the boot ROM is busy, the Blackfin processor asserts
a GPIO pin, called host wait (HWAIT), to signal the host
device not to send any more bytes until the flag is deasserted. The flag is chosen by the user and this information
is transferred to the Blackfin processor via bits 10:5 of the
FLAG header in the .LDR image.
For each of the boot modes, a 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Rev. F
|
Page 16 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
Multiple memory blocks can be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
To augment the boot modes, a secondary software loader is provided that adds additional booting mechanisms. This secondary
loader provides the ability to boot from 16-bit flash memory,
fast flash, variable baud rate, and other sources. In all boot
modes except bypass, program execution starts from on-chip L1
memory address 0xFFA0 0000.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU plus
two load/store plus two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified programming model.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.
Rev. F
|
Page 17 of 60 |
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders®, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices
processors.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
October 2013
ADSP-BF539/ADSP-BF539F
Board Support Packages for Evaluation Hardware
MXVR BOARD LAYOUT GUIDELINES
Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download
area of the product web page.
MLF pin
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
• www.analog.com/ucos3
• Capacitors:
C1: 0.1 F (PPS type, 2% tolerance recommended)
C2: 0.01 F (PPS type, 2% tolerance recommended)
• Resistor:
R1: 220 (1% tolerance)
• The RC network connected to the MLF pin should be
located physically close to the MLF pin on the board.
• The RC network should be wired up and connected to the
MLF pin using wide traces.
• The capacitors in the RC network should be grounded to
MXEGND.
• The RC network should be shielded using MXEGND
traces.
• www.analog.com/ucfs
• www.analog.com/ucusbd
• Avoid routing other switching signals near the RC network
to avoid crosstalk.
• www.analog.com/lwip
MXI driven with external clock oscillator IC (recommended)
Algorithmic Modules
To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules” or “SHARC software
modules”.
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the Engineer-to-Engineer
Note “Analog Devices JTAG Emulation Technical Reference”
(EE-68) on the Analog Devices website (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.
• MXI should be driven with the clock output of a
49.152 MHz or 45.1584 MHz clock oscillator IC.
• MXO should be left unconnected.
• Avoid routing other switching signals near the oscillator
and clock output trace to avoid crosstalk. When not possible, shield traces with ground.
MXI/MXO with external crystal
• The crystal must be a 49.152 MHz or 45.1584 MHz fundamental mode crystal.
• The crystal and load capacitors should be placed physically
close to the MXI and MXO pins on the board.
• The load capacitors should be grounded to MXEGND.
• The crystal and load capacitors should be wired up using
wide traces.
• Board trace capacitance on each lead should not be more
than 3 pF.
• Trace capacitance plus load capacitance should equal the
load capacitance specification for the crystal.
• Avoid routing other switching signals near the crystal and
components to avoid crosstalk. When not possible, shield
traces and components with ground.
MXEGND–MXVR crystal oscillator and MXVR PLL ground
• Should be routed with wide traces or as ground plane.
• Should be tied together to other board grounds at only one
point on the board.
EXAMPLE CONNECTIONS AND LAYOUT
CONSIDERATIONS
Figure 9 shows an example circuit connection of the
ADSP-BF539/ADSP-BF539F to a MOST network. This diagram
is intended as an example, and exact connections and recommended circuit values should be obtained from Analog Devices.
Rev. F
|
Page 18 of 60 |
• Avoid routing other switching signals near to MXEGND to
avoid crosstalk.
October 2013
ADSP-BF539/ADSP-BF539F
5V
5V
VDDINT (1.25V)
FB
MTXON
MPIVDD
MOST FOT
Rx_Vdd
ADSP-BF539F
Tx_Vdd
POWER GATING CIRCUIT
MOST
NETWORK
27:
0.1PF
0.01PF
MTX
TX_Data
MRX
RX_Data
MXEGND
MRXON
49.152MHz OSCILLATOR
MXI
CLKO
Status
B
MXO
RFS0
33:
MLF
L/RCLK
MFS
AUDIO DAC
33:
33:
C2
0.01PF
C1
0.1PF
MCLK
MMCLK
R1
220:
MBCLK
BCLK
AUDIO
CHANNELS
TSCLK0
F
RSCLK0
MXEGND
SDATA
DT0PRI
Figure 9. Example Connections of ADSP-BF539/ADSP-BF539F to MOST Network
MXEVDD–MXVR crystal oscillator 3.3 V power
• Should be routed with wide traces or as power plane.
• Locally bypass MXEVDD with 0.1F and 0.01 F decoupling capacitors to MXEGND.
• Avoid routing other switching signals near to MXEVDD to
avoid crosstalk.
MPIVDD–MXVR PLL 1.25 V power
• A ferrite bead should be placed between the 1.25 V VDDINT
power plane and the MPIVDD pin for noise isolation.
• Locally bypass MPIVDD with 0.1 F and 0.01 F decoupling capacitors to MXEGND.
• Avoid routing other switching signals near to MPIVDD to
avoid crosstalk.
Fiber optic transceiver (FOT) connections
• The traces between the ADSP-BF539/ADSP-BF539F processor and the FOT should be kept as short as possible.
• The receive data trace connecting the FOT receive data
output pin to the ADSP-BF539/ADSP-BF539F MRX input
pin should not have a series termination resistor. The edge
rate of the FOT receive data signal driven by the FOT is
typically very slow, and further degradation of the edge rate
is not desirable.
|
• The receive data trace and the transmit data trace between
the processor and the FOT should not be routed close to
each other in parallel over long distances to avoid crosstalk.
VOLTAGE REGULATOR LAYOUT GUIDELINES
• Should be routed with wide traces or as power plane.
Rev. F
• The transmit data trace connecting the processor’s MTX
output pin to the FOT Transmit Data input pin should
have a 27 W series termination resistor placed close to the
ADSP-BF539/ADSP-BF539F MTX pin.
Page 19 of 60 |
Regulator external component placement, board routing, and
bypass capacitors all have a significant effect on noise injected
into the other analog circuits on-chip. The VROUT1-0 traces
and voltage regulator external components should be considered as noise sources when doing board layout and should not
be routed or placed near sensitive circuits or components on the
board. All internal and I/O power supplies should be well
bypassed with bypass capacitors placed as close to the
ADSP-BF539/ADSP-BF539F as possible.
For further details on the on-chip voltage regulator and related
board design guidelines, see the Switching Regulator Design
Considerations for ADSP-BF533 Blackfin Processors (EE-228)
applications note on the Analog Devices website
(www.analog.com)—use site search on “EE-228”.
October 2013
ADSP-BF539/ADSP-BF539F
ADDITIONAL INFORMATION
The following publications that describe the ADSP-BF539/
ADSP-BF539F processors (and related processors) can be
ordered from any Analog Devices sales office or accessed electronically on our website:
• Getting Started with Blackfin Processors
• ADSP-BF539 Blackfin Processor Hardware Reference
• ADSP-BF53x/ADSP-BF56x Blackfin Processor Programming Reference
• ADSP-BF539 Blackfin Processor Anomaly List
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the "signal chain" entry in
Wikipedia or the Glossary of EE Terms on the Analog Devices
website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The Application Signal Chains page in the Circuits from the
LabTM site (http://www.analog.com/signalchains) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
Rev. F
|
Page 20 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
PIN DESCRIPTIONS
ADSP-BF539/ADSP-BF539F processor pin definitions are listed
in Table 10.
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins. These pins are all
driven high, with the exception of CLKOUT, which toggles at
the system clock rate. If BR is active (whether or not RESET is
asserted), the memory pins are also three-stated. All unused I/O
pins have their input buffers disabled with the exception of the
pins that need pull-ups or pull-downs, as noted in the table.
During hibernate, all outputs are three-stated unless otherwise
noted in Table 10.
In order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate functionality is shown in italics.
Table 10. Pin Descriptions
Type
Description
Driver
Type1
ADDR19–1
O
Address Bus for Async/Sync Access
A
DATA15–0
I/O
Data Bus for Async/Sync Access
A
ABE1–0/SDQM1–0
O
Byte Enables/Data Masks for Async/Sync Access
A
Pin Name
Memory Interface
BR
I
Bus Request (This pin should be pulled high when not used.)
BG
O
Bus Grant
A
BGH
O
Bus Grant Hang
A
AMS3–0
O
Bank Select
A
ARDY
I
Hardware Ready Control (This pin should always be pulled low when not used.)
AOE
O
Output Enable
A
ARE
O
Read Enable
A
AWE
O
Write Enable
A
FCE
I
Flash Enable (This pin is internally connected to GND on the ADSP-BF539.)
FRESET
I
Flash Reset (This pin is internally connected to GND on the ADSP-BF539.)
SRAS
O
Row Address Strobe
A
SCAS
O
Column Address Strobe
A
SWE
O
Write Enable
A
SCKE
O
Clock Enable (This pin must be pulled low through a 10 k resistor if hibernate state A
is used and SDRAM contents need to be preserved during hibernate.)
CLKOUT
O
Clock Output
B
SA10
O
A10 Pin
A
SMS
O
Bank Select
A
TMR0
I/O
Timer 0
C
TMR1/PPI_FS1
I/O
Timer 1/PPI Frame Sync1
C
TMR2/PPI_FS2
I/O
Timer 2/PPI Frame Sync2
C
Asynchronous Memory Control
Flash Control
Synchronous Memory Control
Timers
Rev. F
|
Page 21 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
Table 10. Pin Descriptions (Continued)
Pin Name
Type
Description
Driver
Type1
Parallel Peripheral Interface Port/GPIO
PF0/SPI0SS
I/O
Programmable Flag 0/SPI0 Slave Select Input
C
PF1/SPI0SEL1/TACLK
I/O
Programmable Flag 1/SPI0 Slave Select Enable 1/Timer Alternate Clock
C
PF2/SPI0SEL2
I/O
Programmable Flag 2/SPI0 Slave Select Enable 2
C
PF3/SPI0SEL3/PPI_FS3
I/O
Programmable Flag 3/SPI0 Slave Select Enable 3/PPI Frame Sync 3
C
PF4/SPI0SEL4/PPI15
I/O
Programmable Flag 4/SPI0 Slave Select Enable 4/PPI 15
C
PF5/SPI0SEL5/PPI14
I/O
Programmable Flag 5/SPI0 Slave Select Enable 5/PPI 14
C
PF6/SPI0SEL6/PPI13
I/O
Programmable Flag 6/SPI0 Slave Select Enable 6/PPI 13
C
PF7/SPI0SEL7/PPI12
I/O
Programmable Flag 7/SPI0 Slave Select Enable 7/PPI 12
C
PF8/PPI11
I/O
Programmable Flag 8/PPI 11
C
PF9/PPI10
I/O
Programmable Flag 9/PPI 10
C
PF10/PPI9
I/O
Programmable Flag 10/PPI 9
C
PF11/PPI8
I/O
Programmable Flag 11/PPI 8
C
PF12/PPI7
I/O
Programmable Flag 12/PPI 7
C
PF13/PPI6
I/O
Programmable Flag 13/PPI 6
C
PF14/PPI5
I/O
Programmable Flag 14/PPI 5
C
PF15/PPI4
I/O
Programmable Flag 15/PPI 4
C
C
PPI3–0
I/O
PPI3–0
PPI_CLK/TMRCLK
I
PPI Clock/External Timer Reference
CANTX/PC0
I/O 5 V
CAN Transmit/GPIO
C
CANRX/PC1
I/OD 5 V
CAN Receive/GPIO
C2
Controller Area Network
Media Transceiver (MXVR)/General-Purpose I/O
MTX/PC5
I/O
MXVR Transmit Data/GPIO
C
MTXON/PC9
I/O
MXVR Transmit FOT On/GPIO
C
MRX/PC4
I/OD 5 V
MXVR Receive Data/GPIO (This pin should be pulled low when not used.)
C2
MRXON
I5V
MXVR FOT Receive On (This pin should be pulled high when not used.)
C
MXI
I
MXVR Crystal Input (This pin should be pulled low when not used.)
MXO
O
MXVR Crystal Output (This pin should be left unconnected when not used.)
MLF
A I/O
MXVR Loop Filter (This pin should be pulled low when not used.)
MMCLK/PC6
I/O
MXVR Master Clock/GPIO
C
MBCLK/PC7
I/O
MXVR Bit Clock/GPIO
C
MFS/PC8
I/O
MXVR Frame Sync/GPIO
C
GP
I
GPIO PC4–9 Enable (This pin should be pulled low when MXVR is used.)
2-Wire Interface Ports
These pins are open-drain and require a pull-up resistor. See version 2.1 of the I2C specification for proper resistor values.
SDA0
I/O 5 V
TWI0 Serial Data
E
SCL0
I/O 5 V
TWI0 Serial Clock
E
SDA1
I/O 5 V
TWI1 Serial Data
E
SCL1
I/O 5 V
TWI1 Serial Clock
E
Rev. F
|
Page 22 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
Table 10. Pin Descriptions (Continued)
Pin Name
Type
Description
Driver
Type1
Serial Port0
RSCLK0
I/O
SPORT0 Receive Serial Clock
D
RFS0
I/O
SPORT0 Receive Frame Sync
C
DR0PRI
I
SPORT0 Receive Data Primary
DR0SEC
I
SPORT0 Receive Data Secondary
TSCLK0
I/O
SPORT0 Transmit Serial Clock
D
TFS0
I/O
SPORT0 Transmit Frame Sync
C
DT0PRI
O
SPORT0 Transmit Data Primary
C
DT0SEC
O
SPORT0 Transmit Data Secondary
C
RSCLK1
I/O
SPORT1 Receive Serial Clock
D
RFS1
I/O
SPORT1 Receive Frame Sync
C
Serial Port1
DR1PRI
I
SPORT1 Receive Data Primary
DR1SEC
I
SPORT1 Receive Data Secondary
TSCLK1
I/O
SPORT1 Transmit Serial Clock
D
TFS1
I/O
SPORT1 Transmit Frame Sync
C
DT1PRI
O
SPORT1 Transmit Data Primary
C
DT1SEC
O
SPORT1 Transmit Data Secondary
C
RSCLK2/PE0
I/O
SPORT2 Receive Serial Clock/GPIO
D
RFS2/PE1
I/O
SPORT2 Receive Frame Sync/GPIO
C
DR2PRI/PE2
I/O
SPORT2 Receive Data Primary/GPIO
C
Serial Port2
DR2SEC/PE3
I/O
SPORT2 Receive Data Secondary/GPIO
C
TSCLK2/PE4
I/O
SPORT2 Transmit Serial Clock/GPIO
D
TFS2/PE5
I/O
SPORT2 Transmit Frame Sync/GPIO
C
DT2PRI /PE6
I/O
SPORT2 Transmit Data Primary/GPIO
C
DT2SEC/PE7
I/O
SPORT2 Transmit Data Secondary/GPIO
C
RSCLK3/PE8
I/O
SPORT3 Receive Serial Clock/GPIO
D
RFS3/PE9
I/O
SPORT3 Receive Frame Sync/GPIO
C
DR3PRI/PE10
I/O
SPORT3 Receive Data Primary/GPIO
C
DR3SEC/PE11
I/O
SPORT3 Receive Data Secondary/GPIO
C
TSCLK3/PE12
I/O
SPORT3 Transmit Serial Clock/GPIO
D
Serial Port3
TFS3/PE13
I/O
SPORT3 Transmit Frame Sync/GPIO
C
DT3PRI /PE14
I/O
SPORT3 Transmit Data Primary/GPIO
C
DT3SEC/PE15
I/O
SPORT3 Transmit Data Secondary/GPIO
C
Rev. F
|
Page 23 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
Table 10. Pin Descriptions (Continued)
Type
Description
Driver
Type1
MOSI0
I/O
SPI0 Master Out Slave In
C
MISO0
I/O
SPI0 Master In Slave Out (This pin should always be pulled high through a 4.7 k
resistor if booting via the SPI port.)
C
SCK0
I/O
SPI0 Clock
D
Pin Name
SPI0 Port
SPI1 Port
MOSI1/PD0
I/O
SPI1 Master Out Slave In/GPIO
C
MISO1/PD1
I/O
SPI1 Master In Slave Out/GPIO
C
SCK1/PD2
I/O
SPI1 Clock/GPIO
D
SPI1SS/PD3
I/O
SPI1 Slave Select Input/GPIO
D
SPI1SEL1/PD4
I/O
SPI1 Slave Select Enable/GPIO
D
MOSI2 /PD5
I/O
SPI2 Master Out Slave In/GPIO
C
MISO2/PD6
I/O
SPI2 Master In Slave Out/GPIO
C
SCK2/PD7
I/O
SPI2 Clock/GPIO
D
SPI2SS/PD8
I/O
SPI2 Slave Select Input/GPIO
D
SPI2SEL1/PD9
I/O
SPI2 Slave Select Enable/GPIO
D
RX0
I
UART Receive
TX0
O
UART Transmit
C
RX1/PD10
I/O
UART1 Receive/GPIO
D
TX1/PD11
I/O
UART1 Transmit/GPIO
D
RX2 /PD12
I/O
UART2 Receive/GPIO
D
TX2/PD13
I/O
UART2 Transmit/GPIO
D
RTXI
I
RTC Crystal Input (This pin should be pulled low when not used.)
RTXO
O
RTC Crystal Output (Does not three-state in hibernate.)
TCK
I
JTAG Clock
TDO
O
JTAG Serial Data Out
TDI
I
JTAG Serial Data In
TMS
I
JTAG Mode Select
TRST
I
JTAG Reset (This pin should be pulled low if the JTAG port will not be used.)
EMU
O
Emulation Output
CLKIN
I
Clock/Crystal Input
XTAL
O
Crystal Output
SPI2 Port
UART0 Port
UART1 Port
UART2 Port
Real-Time Clock
JTAG Port
C
C
Clock
Rev. F
|
Page 24 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
Table 10. Pin Descriptions (Continued)
Pin Name
Type
Driver
Type1
Description
Mode Controls
RESET
I
Reset
NMI
I
Nonmaskable Interrupt (This pin should be pulled high when not used.)
BMODE1–0
I
Boot Mode Strap (These pins must be pulled to the state required for the desired boot
mode.)
O
External FET Drive 0 (These pins should be left unconnected when not used.)
VDDEXT
P
I/O Power Supply
VDDINT
P
Internal Power Supply
VDDRTC
P
Real-Time Clock Power Supply (This pin should be connected to VDDEXT when not used
and should remain powered at all times.)
MPIVDD
P
MXVR Internal Power Supply
MXEVDD
P
MXVR External Power Supply
MXEGND
G
MXVR Ground
GND
G
Ground
Voltage Regulator
VROUT1–0
Supplies
1
2
Refer to Figure 34 on Page 50 to Figure 43 on Page 51.
This pin is 5 V-tolerant when configured as an input and an open-drain when configured as an output; therefore, only the VOL curves in Figure 38 on Page 50 and Figure 39
on Page 51 and the fall time curves in Figure 51 on Page 53 and Figure 52 on Page 53 apply when configured as an output.
Rev. F
|
Page 25 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
SPECIFICATIONS
Component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter
VDDINT Internal Supply Voltage1, 2
VDDEXT External Supply Voltage3
VDDRTC Real-Time Clock Power Supply
Voltage
High Level Input Voltage4
VIH
VIH5V
High Level Input Voltage5
VIHCLKIN High Level Input Voltage6
Low Level Input Voltage4, 7
VIL
VIL5V
Low Level Input Voltage5
Junction Temperature
TJ
Conditions
Min
0.95
2.7
2.7
VDDEXT = Maximum
VDDEXT = Maximum
VDDEXT = Maximum
VDDEXT = Minimum
VDDEXT = Minimum
316-Ball Chip Scale Ball Grid Array Package (CSP_BGA)
533 MHz @ TAMBIENT = –40°C to +85°C
2.0
2.0
2.2
Nom
1.25
3.3
3.3
–40
Max
1.375
3.6
3.6
Unit
V
V
V
+0.6
+0.8
+110
V
V
V
V
V
°C
1
Parameter value applies also to MPIVDD.
The regulator can generate VDDINT at levels of 1.0 V to 1.2 V with –5% to +10% tolerance and 1.25 V with –4% to +10% tolerance.
3
Parameter value applies also to MXEVDD.
4
The 3.3 V tolerant pins are capable of accepting up to 3.6 V maximum VIH The following bidirectional pins are 3.3 V tolerant: DATA15–0, SCK2–0, MISO2–0, MOSI2–0,
PF15–0, PPI3–0, MTXON, MMCLK, MBCLK, MFS, MTX, SPI1SS, SPI1SEL1, SPI2SS, SPI2SEL1, RX2–1, TX2–1, DT2PRI, DT2SEC, TSCLK3–0, DR2PRI, DR2SEC, DT3PRI,
DT3SEC, RSCLK3–0, TFS3–0, RFS3–0, DR3PRI, DR3SEC, and TMR2–0. The following input-only pins are 3.3 V tolerant: RESET, RX0, TCK, TDI, TMS, TRST, ARDY,
BMODE1–0, BR, DR0PRI, DR0SEC, DR1PRI, DR1SEC, NMI, PPI_CLK, RTXI, and GP.
5
The 5 V tolerant pins are capable of accepting up to 5.5 V maximum VIH. The following bidirectional pins are 5 V tolerant: SCL0, SCL1, SDA0, SDA1, and CANTX. The
following input-only pins are 5 V tolerant: CANRX, MRX, MRXON.
6
Parameter value applies to the CLKIN and MXI input pins.
7
Parameter value applies to all input and bidirectional pins.
2
The following tables describe the voltage/frequency requirements for the ADSP-BF538/ADSP-BF538F processor clocks.
Take care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock (Table 11) and system clock
(Table 13) specifications. Table 12 describes phase-locked loop
operating conditions.
Table 11. Core Clock (CCLK) Requirements
Parameter
fCCLK
fCCLK
fCCLK
fCCLK
Internal Regulator
Setting
CLK Frequency (VDDINT =
CLK Frequency (VDDINT =
CLK Frequency (VDDINT =
CLK Frequency (VDDINT =
1.2 V Minimum)
1.14 V Minimum)
1.045 V Minimum)
0.95 V Minimum)
Max
533
500
444
400
Unit
MHz
MHz
MHz
MHz
Min
Max
Unit
50
Max fCCLK
MHz
1.25 V
1.20 V
1.10 V
1.00 V
Table 12. Phase-Locked Loop Operating Conditions
Parameter
fVCO
Voltage Controlled Oscillator (VCO) Frequency
Table 13. System Clock (SCLK) Requirements
Parameter1
fSCLK
CLKOUT/SCLK Frequency (VDDINT 1.14 V)
fSCLK
CLKOUT/SCLK Frequency (VDDINT 1.14 V)
1
2
Max
1332
100
tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK
Guaranteed to tSCLK = 7.5 ns. See Table 26 on Page 36.
Rev. F
|
Page 26 of 60 |
October 2013
Unit
MHz
MHz
ADSP-BF539/ADSP-BF539F
ELECTRICAL CHARACTERISTICS
Parameter1
2
VOH
High Level Output Voltage
VOL
Low Level Output Voltage2
IIH
High Level Input Current3
High Level Input Current JTAG
IIHP
4
3
Low Level Input Current
IIL
5
Test Conditions
Min
VDDEXT = +3.0 V, IOH = –0.5 mA
2.4
Typ
Max
Unit
VDDEXT = 3.0 V, IOL = 2.0 mA
0.4
V
VDDEXT= Maximum, VIN = VDD Maximum
10.0
μA
VDDEXT = Maximum, VIN = VDD Maximum
50.0
μA
VDDEXT = Maximum, VIN = 0 V
10.0
μA
V
IOZH
Three-State Leakage Current
VDDEXT = Maximum, VIN = VDD Maximum
10.0
μA
IOZL
Three-State Leakage Current5
VDDEXT = Maximum, VIN = 0 V
10.0
μA
CIN
Input Capacitance6, 7
fCCLK = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V
4
8
pF
VDDINT Current in Deep Sleep Mode
VDDINT = 1.0 V, fCCLK = 0 MHz, TJ = 25°C, ASF = 0.00
7.5
IDDDEEPSLEEP
8
mA
IDDSLEEP
VDDINT Current in Sleep Mode
VDDINT = 0.8 V, TJ = 25°C, SCLK = 25 MHz
IDD-TYP
VDDINT Current
VDDINT = 1.14 V, fCCLK = 400 MHz, TJ = 25°C
130
mA
IDD-TYP
VDDINT Current
VDDINT = 1.2 V, fCCLK = 500 MHz, TJ = 25°C
168
mA
VDDINT Current
VDDINT = 1.2 V, fCCLK = 533 MHz, TJ = 25°C
180
mA
VDDEXT Current in Hibernate State
VDDEXT = 3.6 V, CLKIN = 0 MHz, TJ = Maximum,
voltage regulator off (VDDINT = 0 V)
50
VDDRTC Current
VDDRTC = 3.3 V, TJ = 25°C
20
VDDINT Current in Deep Sleep Mode
fCCLK = 0 MHz
6
VDDINT Current
fCCLK > 0 MHz
IDD-TYP
IDDHIBERNATE
8
IDDRTC
IDDDEEPSLEEP
IDDINT9
8
1
10
Specifications subject to change without notice.
Applies to output and bidirectional pins.
3
Applies to input pins except JTAG inputs.
4
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
5
Applies to three-statable pins.
6
Applies to all signal pins.
7
Guaranteed, but not tested.
8
See the ADSP-BF539 Blackfin Processor Hardware Reference Manual for definitions of sleep, deep sleep, and hibernate operating modes.
9
See Table 15 for the list of IDDINT power vectors covered by various activity scaling factors (ASF).
2
Rev. F
|
Page 27 of 60 |
October 2013
100
mA
A
A
Table 14
mA
IDDDEEPSLEEP +
(Table 16 × ASF)
mA
ADSP-BF539/ADSP-BF539F
System designers should refer to Estimating Power for the
ADSP-BF538/BF539 Blackfin Processors (EE-298), which provides detailed information for optimizing designs for lowest
power. All topics discussed in this section are described in detail
in EE-298. Total power dissipation has two components:
current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP specifies static power dissipation as a function of voltage (VDDINT) and
temperature (see Table 14), and IDDINT specifies the total power
specification for the listed test conditions, including the
dynamic component as a function of voltage (VDDINT) and frequency (Table 16).
1. Static, including leakage current
The dynamic component is also subject to an Activity Scaling
Factor (ASF) which represents application code running on the
processor (Table 15).
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and processor activity. Electrical Characteristics on Page 27 shows the
Table 14. Static Current (mA)1
VDDINT (V)
TJ (°C)
0.80 V
0.85 V
0.90 V
0.95 V
1.00 V
1.05 V
1.10 V
1.15 V
1.20 V
1.25 V
1.30 V
1.32 V
1.375 V
–40
6.4
7.7
8.8
10.4
12.0
14.0
16.1
18.9
21.9
25.2
28.7
30.6
35.9
–25
9.2
10.9
12.5
14.5
16.7
19.3
22.1
25.6
29.5
33.7
38.1
40.5
47.2
0
16.8
18.9
21.5
24.4
27.7
31.7
35.8
40.5
45.8
51.6
58.2
61.0
69.8
25
32.9
37.2
41.4
46.2
51.8
57.4
64.2
72.3
80.0
89.3
98.9
103.3
116.4
40
48.4
54.8
60.5
67.1
74.7
82.9
91.6
101.5
112.4
123.2
136.2
142.0
158.7
55
71.2
78.6
86.5
95.8
104.9
115.7
127.1
139.8
153.6
168.0
183.7
191.0
211.8
70
102.3
112.2
122.1
133.5
146.1
159.2
173.9
189.8
206.7
225.5
245.6
254.1
279.6
85
140.7
153.0
167.0
182.5
198.0
216.0
234.3
254.0
276.0
299.1
324.3
334.8
366.6
100
190.6
207.1
224.6
244.0
265.6
285.7
309.0
333.7
360.0
387.8
417.3
431.1
469.3
105
210.2
228.1
245.1
265.6
285.8
309.2
334.0
360.1
385.6
417.2
448.0
461.5
501.1
1
Values are guaranteed maximum IDDDEEPSLEEP specifications.
Table 15. Activity Scaling Factors
IDDINT Power Vector1
IDD-PEAK-MXVR
IDD-HIGH-MXVR
IDD-PEAK
IDD-HIGH
IDD-TYP-MXVR
IDD-TYP
IDD-APP-MXVR
IDD-APP
IDD-NOP-MXVR
IDD-NOP
IDD-IDLE-MXVR
IDD-IDLE
1
2
Activity Scaling Factor (ASF)2
1.36
1.32
1.30
1.28
1.07
1.00
0.92
0.88
0.76
0.74
0.50
0.48
See EE-298 for power vector definitions.
All ASF values determined using a 10:1 CCLK:SCLK ratio.
Rev. F
|
Page 28 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
Table 16. Dynamic Current (mA, with ASF = 1.0)1
Frequency
(MHz)
50
100
200
250
300
375
400
425
475
500
533
1
0.95 V
17.5
30.1
54.8
66.8
79.3
97.9
103.8
N/A
N/A
N/A
N/A
1.00 V
19.1
32.3
58.4
71.2
84.5
103.9
110.3
116.6
N/A
N/A
N/A
1.05 V
20.5
34.4
61.8
75.7
89.0
109.9
116.9
123.7
N/A
N/A
N/A
1.10 V
22.0
37.0
65.6
79.9
94.7
116.5
123.7
130.9
145.0
N/A
N/A
1.15 V
23.5
39.2
69.7
84.5
100.0
122.2
130.0
137.2
151.8
159.9
N/A
VDDINT
1.20 V
25.4
41.7
74.3
89.8
105.5
129.7
137.5
144.7
161.4
168.9
179.8
1.25 V
27.1
44.3
76.2
94.2
111.6
136.0
144.2
152.7
169.4
177.8
188.9
1.30 V
29.1
46.4
82.2
99.4
116.8
142.9
151.2
159.9
177.8
186.3
198.8
1.32 V
29.7
47.6
83.4
101.2
119.3
145.9
154.5
163.3
181.1
190.0
202.2
1.375 V
31.6
50.3
87.8
106.5
125.5
153.6
162.4
171.8
190.4
199.6
212.5
The values are not guaranteed as standalone maximum specifications, they must be combined with static current per the equations of Electrical Characteristics on Page 27.
Rev. F
|
Page 29 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITY
Stresses greater than those listed in Table 17 may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Table 17. Absolute Maximum Ratings
Parameter
Internal (Core) Supply Voltage (VDDINT)
1
Rating
PACKAGE INFORMATION
–0.3 V to +1.4 V
The information presented in Figure 10 and Table 19 provides
information about how to read the package brand and relate it
to specific product features. For a complete listing of product
offerings, see the Ordering Guide on Page 60.
External (I/O) Supply Voltage (VDDEXT)2
–0.3 V to +3.8 V
Input Voltage3, 4
–0.5 V to +3.8 V
Input Voltage4, 5
–0.5 V to +5.5 V
Output Voltage Swing
–0.5 V to VDDEXT + 0.5 V
Junction Temperature While Biased
+125°C
Storage Temperature Range
–65°C to +150°C
a
ADSP-BF539
1
tppZccc
2
vvvvvv.x n.n
Parameter value applies also to MPIVDD.
Parameter value applies also to MXEVDD and VDDRTC.
3
Applies to 100% transient duty cycle. For other duty cycles, see Table 18.
4
Applies only when VDDEXT is within specifications. When VDDEXT is outside specifications, the range is VDDEXT ± 0.2 V.
5
Applies to pins designated as 5 V tolerant only.
#yyww country_of_origin
B
Figure 10. Product Information on Package
Table 18. Maximum Duty Cycle for Input Transient Voltage1
VIN Min (V)
2
VIN Max (V)
2
Maximum Duty Cycle
–0.50
+3.80
100%
–0.70
+4.00
40%
–0.80
+4.10
25%
–0.90
+4.20
15%
–1.00
+4.30
3
10%
1
Applies to all signal pins with the exception of CLKIN, MXI, MXO, MLF,
VROUT1–0, XTAL, RTXI, and RTXO.
2
The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
3
Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. The is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence.
Rev. F
|
Page 30 of 60 |
Table 19. Package Brand Information1
Brand Key
Field Description
t
Temperature Range
pp
Package Type
Z
RoHS Compliant Part
ccc
See Ordering Guide
vvvvvv.xw
Assembly Lot Code
n.n
Silicon Revision
#
RoHS Compliant Designation
yyww
Date Code
1
Non Automotive only. For branding information specific to Automotive
products, contact Analog Devices Inc.
October 2013
ADSP-BF539/ADSP-BF539F
TIMING SPECIFICATIONS
Component specifications are subject to change
with PCN notice.
Clock and Reset Timing
Table 20 and Figure 11 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 30, combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks that exceed maximum operating conditions.
Table 20. Clock and Reset Timing
Parameter
Timing Requirements
CLKIN Frequency (Commercial/ Industrial Models) 1, 2, 3, 4
fCKIN
CLKIN Frequency (Automotive Models) 1, 2, 3, 4
tCKINL
CLKIN Low Pulse1
tCKINH
CLKIN High Pulse1
tWRST
RESET Asserted Pulse Width Low5
tNOBOOT
RESET Deassertion to First External Access Delay6
Min
Max
Unit
10
10
8
8
11 × tCKIN
3 × tCKIN
50
50
MHz
MHz
ns
ns
ns
ns
5 × tCKIN
1
Applies to PLL bypass mode and PLL nonbypass mode.
2
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 12 on Page 26 through
Table 16 on Page 29.
3
The tCKIN period (see Figure 11) equals 1/fCKIN.
4
If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.
5
Applies after power-up sequence is complete. See Table 21 and Figure 12 for power-up reset timing.
6
Applies when processor is configured in No Boot Mode (BMODE2-0 = b#000).
tCKIN
CLKIN
tCKINL
tCKINH
tNOBOOT
tWRST
RESET
Figure 11. Clock and Reset Timing
Table 21. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirement
tRST_IN_PWR
RESET Deasserted after the VDDINT, VDDEXT, VDDRTC, MPIVDD, MXEVDD, and CLKIN
Pins are Stable and Within Specification
3500 × tCKIN
tRST_IN_PWR
RESET
CLKIN
V
DD_SUPPLIES
In Figure 12, VDD_SUPPLIES is VDDINT, VDDEXT, VDDRTC, MPIVDD, MXEVDD
Figure 12. Power-Up Reset Timing
Rev. F
|
Page 31 of 60 |
October 2013
ns
ADSP-BF539/ADSP-BF539F
Asynchronous Memory Read Cycle Timing
Table 22 and Table 23 on Page 33 and Figure 13 and Figure 14
on Page 33 describe asynchronous memory read cycle operations for synchronous and for asynchronous ARDY.
Table 22. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
2.1
ns
tHDAT
DATA15–0 Hold After CLKOUT
0.8
ns
tSARDY
ARDY Setup Before the Falling Edge of CLKOUT
4.0
ns
tHARDY
ARDY Hold After the Falling Edge of CLKOUT
0.0
ns
Switching Characteristics
tDO
Output Delay After CLKOUT1
tHO
Output Hold After CLKOUT1
1
6.0
0.8
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
CLKOUT
tDO
tHO
AMSx
ABE1–0
ADDR19–1
AOE
tDO
tHO
ARE
tSARDY
tHARDY
tHARDY
ARDY
tSARDY
tSDAT
tHDAT
DATA 15–0
Figure 13. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Rev. F
|
Page 32 of 60 |
October 2013
ns
ns
ADSP-BF539/ADSP-BF539F
Table 23. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
2.1
tHDAT
DATA15–0 Hold After CLKOUT
0.8
tDANR
ARDY Negated Delay from AMSx Asserted1
tHAA
ARDY Asserted Hold After ARE Negated
ns
ns
(S + RA – 2) × tSCLK ns
0.0
ns
Switching Characteristics
tDO
Output Delay After CLKOUT2
tHO
Output Hold After CLKOUT2
1
2
6.0
0.8
ns
S = number of programmed setup cycles, RA = number of programmed read access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
CLKOUT
tDO
tHO
AMSx
ABE1–0
ADDR19–1
AOE
tDO
tHO
ARE
tDANR
tHAA
ARDY
tSDAT
tHDAT
DATA 15–0
Figure 14. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Rev. F
|
Page 33 of 60 |
October 2013
ns
ADSP-BF539/ADSP-BF539F
Asynchronous Memory Write Cycle Timing
Table 24 and Table 25 and Figure 15 and Figure 16 describe
asynchronous memory write cycle operations for synchronous
and for asynchronous ARDY.
Table 24. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSARDY
ARDY Setup Before the Falling Edge of CLKOUT
4.0
ns
tHARDY
ARDY Hold After the Falling Edge of CLKOUT
0.0
ns
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
tDO
Output Delay After CLKOUT
tHO
Output Hold After CLKOUT1
1
6.0
1.0
1
ns
6.0
0.8
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
PROGRAMMED ACCESS
WRITE ACCESS EXTEND HOLD
2 CYCLES
1 CYCLE 1 CYCLE
SETUP
2 CYCLES
CLKOUT
tDO
tHO
AMSx
ABE1–0
ADDR19–1
tDO
tHO
AWE
tSARDY tHARDY
ARDY
tENDAT
tSARDY
tHARDY
tDDAT
DATA 15–0
Figure 15. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Rev. F
|
Page 34 of 60 |
October 2013
ns
ns
ns
ADSP-BF539/ADSP-BF539F
Table 25. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tDANR
ARDY Negated Delay from AMSx Asserted1
tHAA
ARDY Asserted Hold After ARE Negated
(S + WA – 2) × tSCLK ns
0.0
ns
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
tDO
Output Delay After CLKOUT
tHO
Output Hold After CLKOUT2
1
2
6.0
1.0
2
ns
6.0
0.8
S = Number of programmed setup cycles, WA = Number of programmed write access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
PROGRAMMED
WRITE ACCESS
2 CYCLES
ACCESS
EXTENDED
2 CYCLES
HOLD
1 CYCLE
CLKOUT
tDO
tHO
AMSx
ABE1–0
ADDR19–1
tDO
tHO
AWE
tDANW
tHAA
ARDY
tENDAT
tDDAT
DATA 15–0
Figure 16. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Rev. F
|
Page 35 of 60 |
October 2013
ns
ns
ns
ADSP-BF539/ADSP-BF539F
SDRAM Interface Timing
Table 26. SDRAM Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSDAT
DATA Setup Before CLKOUT
2.1
ns
tHSDAT
DATA Hold After CLKOUT
0.8
ns
ns
Switching Characteristics
tSCLK
CLKOUT Period1
7.5
tSCLKH
CLKOUT Width High
2.5
ns
tSCLKL
CLKOUT Width Low
2.5
ns
tDCAD
Command, ADDR, Data Delay After CLKOUT2
tHCAD
Command, ADDR, Data Hold After CLKOUT2
tDSDAT
Data Disable After CLKOUT
tENSDAT
Data Enable After CLKOUT
1
2
6.0
0.8
ns
6.0
1.0
tSCLK
CLKOUT
tHSDAT
tSCLKL
tSCLKH
DATA (IN)
tENSDAT
tDCAD
tHCAD
DATA (OUT)
tDCAD
tHCAD
COMMAND,
ADDRESS
(OUT)
NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure 17. SDRAM Interface Timing
Rev. F
|
Page 36 of 60 |
October 2013
ns
ns
SDRAM timing for TJUNCTION = 125°C is limited to 100 MHz.
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
tSSDAT
ns
tDSDAT
ADSP-BF539/ADSP-BF539F
External Port Bus Request and Grant Cycle Timing
Table 27 and Table 28 and Figure 18 and Figure 19 describe
external port bus request and grant cycle operations for synchronous and for asynchronous BR.
Table 27. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter
Min
Max
Unit
Timing Requirements
tBS
BR Setup to Falling Edge of CLKOUT
4.6
ns
tBH
Falling Edge of CLKOUT to BR Deasserted Hold Time
1.0
ns
Switching Characteristics
tSD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
4.5
ns
tSE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
4.5
ns
tDBG
CLKOUT High to BG High Setup
4.0
ns
tEBG
CLKOUT High to BG Deasserted Hold Time
4.0
ns
tDBH
CLKOUT High to BGH High Setup
4.0
ns
tEBH
CLKOUT High to BGH Deasserted Hold Time
4.0
ns
CLKOUT
tBH
tBS
BR
tSD
tSE
tSD
tSE
tSD
tSE
AMSx
ADDR 19-1
ABE1-0
AWE
ARE
t DBG
tEBG
tDBH
tEBH
BG
BGH
Figure 18. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Rev. F
|
Page 37 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
Table 28. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Parameter
Min
Max
Unit
Timing Requirement
tWBR
BR Pulse Width
2 × tSCLK
ns
Switching Characteristics
tSD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
4.5
tSE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
4.5
ns
tDBG
CLKOUT High to BG High Setup
3.6
ns
tEBG
CLKOUT High to BG Deasserted Hold Time
3.6
ns
tDBH
CLKOUT High to BGH High Setup
3.6
ns
tEBH
CLKOUT High to BGH Deasserted Hold Time
3.6
ns
CLKOUT
tWBR
BR
tSD
tSE
tSD
tSE
tSD
tSE
AMSx
ADDR 19-1
ABE1-0
AWE
ARE
t DBG
tEBG
tDBH
tEBH
BG
BGH
Figure 19. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Rev. F
|
Page 38 of 60 |
October 2013
ns
ADSP-BF539/ADSP-BF539F
Parallel Peripheral Interface Timing
Table 29 and Figure 20, Figure 21, Figure 22, and Figure 23
describe Parallel Peripheral Interface operations.
Table 29. Parallel Peripheral Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tPCLKW
PPI_CLK Width
6.0
1
ns
tPCLK
PPI_CLK Period
tSFSPE
External Frame Sync Setup Before PPI_CLK
tHFSPE
External Frame Sync Hold After PPI_CLK
1.0
ns
tSDRPE
Receive Data Setup Before PPI_CLK
2.0
ns
tHDRPE
Receive Data Hold After PPI_CLK
4.0
ns
15.0
ns
5.0
ns
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After PPI_CLK
tHOFSPE
Internal Frame Sync Hold After PPI_CLK
tDDTPE
Transmit Data Delay After PPI_CLK
tHDTPE
Transmit Data Hold After PPI_CLK
1
10.0
0.0
PPI_CLK frequency cannot exceed fSCLK/2.
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_CLK
tDFSPE
tHOFSPE
ns
10.0
0.0
tPCLKW
tPCLK
PPI_FS1/2
tSDRPE
tHDRPE
PPI_DATA
Figure 20. PPI GP Rx Mode with Internal Frame Sync Timing
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
PPI_CLK
tSFSPE
tPCLKW
tHFSPE
tPCLK
PPI_FS1/2
tSDRPE
tHDRPE
PPI_DATA
Figure 21. PPI GP Rx Mode with External Frame Sync Timing
Rev. F
|
Page 39 of 60 |
October 2013
ns
ns
ns
ADSP-BF539/ADSP-BF539F
DATA DRIVEN /
FRAME SYNC SAMPLED
PPI_CLK
tSFSPE
tHFSPE
tPCLKW
tPCLK
PPI_FS1/2
tDDTPE
tHDTPE
PPI_DATA
Figure 22. PPI GP Tx Mode with External Frame Sync Timing
FRAME SYNC
DRIVEN
DATA
DRIVEN
tPCLK
PPI_CLK
tHOFSPE
tDFSPE
tPCLKW
PPI_FS1/2
tDDTPE
tHDTPE
PPI_DATA
Figure 23. PPI GP Tx Mode with Internal Frame Sync Timing
Rev. F
|
Page 40 of 60 |
October 2013
DATA
DRIVEN
ADSP-BF539/ADSP-BF539F
Serial Ports Timing
Table 30 through Table 33 and Figure 24 through Figure 27
describe Serial Port operations.
Table 30. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)
tSDRE
Receive Data Setup Before RSCLKx1
1
1
3.0
ns
3.0
ns
3.0
ns
3.0
ns
4.5
ns
tHDRE
Receive Data Hold After RSCLKx
tSCLKEW
TSCLKx/RSCLKx Width
tSCLKE
TSCLKx/RSCLKx Period
15.0
ns
tSUDTE
Start-Up Delay From SPORT Enable To First External TFSx2
4.0 × tSCLKE
ns
tSUDRE
2
4.0 × tSCLKE
ns
Start-Up Delay From SPORT Enable To First External RFSx
Switching Characteristics
tDFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)3
tHOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)3
tDDTE
Transmit Data Delay After TSCLKx
tHDTE
Transmit Data Hold After TSCLKx3
10.0
0.0
3
ns
ns
10.0
0.0
ns
ns
1
Referenced to sample edge.
Verified in design but untested. After being enabled, the serial port requires external clock pulses—before the first external frame sync edge—to initialize the serial port.
3
Referenced to drive edge.
2
Table 31. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)
tSDRI
Receive Data Setup Before RSCLKx1
tHDRI
Receive Data Hold After RSCLKx
1
1
9.0
ns
–1.5
ns
9.0
ns
–1.5
ns
Switching Characteristics
tDFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
tHOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
tDDTI
Transmit Data Delay After TSCLKx2
tHDTI
Transmit Data Hold After TSCLKx2
–2.0
ns
tSCLKIW
TSCLKx/RSCLKx Width
4.5
ns
Referenced to sample edge.
2
Referenced to drive edge.
|
Page 41 of 60 |
October 2013
ns
ns
3.0
1
Rev. F
3.5
–1.0
ns
ADSP-BF539/ADSP-BF539F
DATA RECEIVE—INTERNAL CLOCK
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
DRIVE EDGE
SAMPLE EDGE
SAMPLE EDGE
tSCLKE
tSCLKEW
tSCLKIW
RSCLKx
RSCLKx
tDFSE
tDFSI
tHOFSI
tHOFSE
RFSx
(OUTPUT)
RFSx
(OUTPUT)
tSFSI
tHFSI
RFSx
(INPUT)
tSFSE
tHFSE
tSDRE
tHDRE
RFSx
(INPUT)
tSDRI
tHDRI
DRx
DRx
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
tSCLKIW
SAMPLE EDGE
t SCLKEW
TSCLKx
tSCLKE
TSCLKx
tD FSI
tDFSE
tHOFSI
tHOFSE
TFSx
(OUTPUT)
TFSx
(OUTPUT)
tSFSI
tHFSI
tSFSE
TFSx
(INPUT)
TFSx
(INPUT)
tDDTI
tDDTE
tHDTI
tHDTE
DTx
DTx
Figure 24. Serial Ports
TSCLKx
(INPUT)
tSUDTE
TFSx
(INPUT)
RSCLKx
(INPUT)
tSUDRE
RFSx
(INPUT)
FIRST
TSCLKx/RSCLKx
EDGE AFTER
SPORT ENABLED
Figure 25. Serial Port Start Up with External Clock and Frame Sync
Rev. F
|
Page 42 of 60 |
October 2013
tHFSE
ADSP-BF539/ADSP-BF539F
Table 32. Serial Ports—Enable and Three-State
Parameter
Min
Max
Unit
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLKx1
0
1, 2, 3
tDDTTE
Data Disable Delay from External TSCLKx
tDTENI
Data Enable Delay from Internal TSCLKx1
tDDTTI
Data Disable Delay from Internal TSCLKx1, 2, 3
ns
10.0
–2.0
ns
ns
3.0
ns
Max
Unit
10.0
ns
1
Referenced to drive edge.
2
Applicable to multichannel mode only.
3
TSCLKx is tied to RSCLKx.
DRIVE EDGE
DRIVE EDGE
TSCLKx
tDTENE/I
tDDTTE/I
DTx
Figure 26. Enable and Three-State
Table 33. External Late Frame Sync
Parameter
Min
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFSx or External RFSx in multichannel mode, MFD = 01, 2
tDTENLFS
Data Enable from Late FS or multichannel mode, MFD = 01, 2
1
2
In multichannel mode, TFSx enable and TFSx valid follow tDTENLFS and tDDTLFSE.
If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
Rev. F
|
Page 43 of 60 |
October 2013
0
ns
ADSP-BF539/ADSP-BF539F
EXTERNAL RFSx IN MULTI-CHANNEL MODE
SAMPLE
DRIVE
EDGE
EDGE
DRIVE
EDGE
RSCLKx
RFSx
tDDTLFSE
tDTENLFSE
1ST BIT
DTx
LATE EXTERNAL TFSx
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
TSCLKx
TFSx
tDDTLFSE
1ST BIT
DTx
Figure 27. External Late Frame Sync
Rev. F
|
Page 44 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
Serial Peripheral Interface Ports—Master Timing
Table 34 and Figure 28 describe SPI ports master operations.
Table 34. Serial Peripheral Interface (SPI) Ports—Master Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSPIDM
Data Input Valid to SCKx Edge (Data Input Setup)
9.0
ns
tHSPIDM
SCKx Sampling Edge to Data Input Invalid
–1.5
ns
Switching Characteristics
tSDSCIM
SPIxSELy Low to First SCKx edge
2tSCLK –1.5
ns
tSPICHM
Serial Clock High Period
2tSCLK –1.5
ns
tSPICLM
Serial Clock Low Period
2tSCLK –1.5
ns
tSPICLK
Serial Clock Period
4tSCLK –1.5
ns
tHDSM
Last SCKx Edge to SPIxSELy High
2tSCLK –1.5
ns
tSPITDM
Sequential Transfer Delay
2tSCLK –1.5
ns
tDDSPIDM
SCKx Edge to Data Out Valid (Data Out Delay)
tHDSPIDM
SCKx Edge to Data Out Invalid (Data Out Hold)
5
–1.0
ns
SPIxSELy
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SPIxSCK
(OUTPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
CPHA = 1
tHSPIDM
SPIxMISO
(INPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
CPHA = 0
tSSPIDM
tHSPIDM
SPIxMISO
(INPUT)
Figure 28. Serial Peripheral Interface (SPI) Ports—Master Timing
Rev. F
|
Page 45 of 60 |
October 2013
ns
tSPITDM
ADSP-BF539/ADSP-BF539F
Serial Peripheral Interface Ports—Slave Timing
Table 35 and Figure 29 describe SPI ports slave operations.
Table 35. Serial Peripheral Interface (SPI) Ports—Slave Timing
Parameter
Min
Max
Unit
Timing Requirements
tSPICHS
Serial Clock High Period
2tSCLK –1.5
ns
tSPICLS
Serial Clock Low Period
2tSCLK –1.5
ns
tSPICLK
Serial Clock Period
4tSCLK
ns
tHDS
Last SCKx Edge to SPIxSS Not Asserted
2tSCLK –1.5
ns
tSPITDS
Sequential Transfer Delay
2tSCLK –1.5
ns
tSDSCI
SPIxSS Assertion to First SCKx Edge
2tSCLK –1.5
ns
tSSPID
Data Input Valid to SCKx Edge (Data Input Setup)
2.0
ns
tHSPID
SCKx Sampling Edge to Data Input Invalid
2.0
ns
Switching Characteristics
tDSOE
SPIxSS Assertion to Data Out Active
0
8
ns
tDSDHI
SPIxSS Deassertion to Data High impedance
0
8
ns
tDDSPID
SCKx Edge to Data Out Valid (Data Out Delay)
10
ns
tHDSPID
SCKx Edge to Data Out Invalid (Data Out Hold)
0
ns
SPIxSS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tHDS
tSPICLK
SPIxSCK
(INPUT)
tDSOE
tDDSPID
tDDSPID
tHDSPID
tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 1
tSSPID
tHSPID
SPIxMOSI
(INPUT)
tDSOE
tHDSPID
tDDSPID
tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 0
tSSPID
tHSPID
SPIxMOSI
(INPUT)
Figure 29. Serial Peripheral Interface (SPI) Ports—Slave Timing
Rev. F
|
Page 46 of 60 |
October 2013
tSPITDS
ADSP-BF539/ADSP-BF539F
General-Purpose Port Timing
Table 36 and Figure 30 describe general-purpose operations.
Table 36. General-Purpose Port Timing
Parameter
Min
Max
Unit
Timing Requirement
tWFI
GP Port Pin Input Pulse Width
tSCLK + 1
ns
Switching Characteristic
tGPOD
GP Port Pin Output Delay from CLKOUT Low
6
ns
CLKOUT
tGPOD
GPIO OUTPUT
tWFI
GPIO INPUT
Figure 30. General-Purpose Port Cycle Timing
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
For information on the UART port receive and transmit operations, see the ADSP-BF539 Hardware Reference Manual.
MXVR Timing
Table 37 and Table 38 describe the MXVR timing requirements.
Table 37. MXVR Timing—MXI Center Frequency Requirements
Parameter
fMXI
fS = 38 kHz
38.912
MXI Center Frequency
fS = 44.1 kHz fS = 48 kHz
45.1584
49.152
Unit
MHz
Table 38. MXVR Timing— MXI Clock Requirements
Parameter
Timing Requirements
FSMXI
MXI Clock Frequency Stability
FTMXI
MXI Frequency Tolerance Over Temperature
DCMXI
MXI Clock Duty Cycle
Rev. F
|
Page 47 of 60 |
October 2013
Min
Max
Unit
–50
–300
40
+50
+300
60
ppm
ppm
%
ADSP-BF539/ADSP-BF539F
Timer Clock Timing
Table 39 and Figure 31 describe timer clock timing.
Table 39. Timer Clock Timing
Parameter
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
Min
Max
Unit
12
ns
PPI_CLK
tTODP
TMRx OUTPUT
Figure 31. Timer Clock Timing
Timer Cycle Timing
Table 40 and Figure 32 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input frequency of fSCLK/2 MHz.
Table 40. Timer Cycle Timing
Parameter
Timing Characteristics
tWL Timer Pulse Width Low1
tWH Timer Pulse Width High1
tTIS Timer Input Setup Time Before CLKOUT Low2
tTIH Timer Input Hold Time After CLKOUT Low2
Switching Characteristics
tHTO Timer Pulse Width Output
tTOD Timer Output Update Delay After CLKOUT High
1
2
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5 V/3.3 V
Min
Max
Unit
1 × tSCLK
1 × tSCLK
8.0
1.5
1 × tSCLK
1 × tSCLK
6.5
1.5
ns
ns
ns
ns
1 × tSCLK
(232–1) × tSCLK
7.5
1 × tSCLK
(232–1) × tSCLK
6.5
ns
ns
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
tTOD
TMRx OUTPUT
tTIS
tTIH
tHTO
TMRx INPUT
tWH,tWL
Figure 32. Timer PWM_OUT Cycle Timing
Rev. F
|
Page 48 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
JTAG Test and Emulation Port Timing
Table 41 and Figure 33 describe JTAG port operations.
Table 41. JTAG Port Timing
Parameter
Min
Max
Unit
Timing Requirements
tTCK
TCK Period
20
tSTAP
TDI, TMS Setup Before TCK High
4
ns
tHTAP
TDI, TMS Hold After TCK High
4
ns
tSSYS
System Inputs Setup Before TCK High1
4
ns
6
ns
4
TCK
1
tHSYS
System Inputs Hold After TCK High
tTRSTW
TRST Pulse Width2 (Measured in TCK Cycles)
ns
Switching Characteristics
tDTDO
TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low3
0
1
10
ns
12
ns
System Inputs = ARDY, BMODE1–0, BR, DATA15–0, NMI, PF15–0, PPI_CLK, PPI3–0, SCL1–0, SDA1–0, MTXON, MRXON, MMCLK, MBCLK, MFS, MTX, MRX, SPI1SS,
SPI1SEL1, SCK2–0, MISO2–0, MOSI2–0, SPI2SS, SPI2SEL1, RX2–0, TX2–1, DR0PRI, DR0SEC, DR1PRI, DR1SEC, DT2PRI, DT2SEC, DR2PRI, DR2SEC, TSCLK3–0,
RSCLK3–0, TFS3–0, RFS3–0, DT3PRI, DT3SEC, DR3PRI, DR3SEC, CANTX, CANRX, RESET, and TMR2–0.
2
50 MHz maximum
3
System Outputs = AMS, AOE, ARE, AWE, ABE, BG, DATA15–0, PF15–0, PPI3–0, MTXON, MMCLK, MBCLK, MFS, MTX, SPI1SS, SPI1SEL1, SCK2–0,
MISO2–0, MOSI2–0, SPI2SS, SPI2SEL1, RX2–1, TX2–0, DT2PRI, DT2SEC, DR2PRI, DR2SEC, DT3PRI, DT3SEC, DR3PRI, DR3SEC, TSCLK3–0, TFS3–0, RSCLK3–0,
RFS3–0, CLKOUT, CANTX, SA10, SCAS, SCKE, SMS, SRAS, SWE, and TMR2–0.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 33. JTAG Port Timing
Rev. F
|
Page 49 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
OUTPUT DRIVE CURRENTS
150
The following figures show typical current-voltage characteristics for the output drivers of the ADSP-BF539/ADSP-BF539F
processor. The curves represent the current drive capability of
the output drivers as a function of output voltage.
100
SOURCE CURRENT (mA)
VDDEXT = 2.75V
120
100
SOURCE CURRENT (mA)
80
VDDEXT = 2.75V
60
VOH
0
-50
VOL
-100
VOH
40
50
20
-150
0
0
0.5
1.0
-20
1.5
2.0
2.5
3.0
SOURCE VOLTAGE (V)
-40
Figure 36. Drive Current B (Low VDDEXT)
VOL
-60
-80
200
-100
0.5
0
1.0
1.5
2.0
3.0
2.5
VDDEXT = 3.0V
VDDEXT = 3.3V
150
SOURCE VOLTAGE (V)
VDDEXT = 3.6V
SOURCE CURRENT (mA)
100
Figure 34. Drive Current A (Low VDDEXT)
150
VDDEXT = 3.0V
VDDEXT = 3.3V
100
50
0
-50
-100
VOL
-150
VOH
-200
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SOURCE VOLTAGE (V)
-50
Figure 37. Drive Current B (High VDDEXT)
VOL
-100
80
-150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
60
SOURCE VOLTAGE (V)
VDDEXT = 2.75V
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
VDDEXT = 3.6V
VOH
50
Figure 35. Drive Current A (High VDDEXT)
40
VOH
20
0
-20
VOL
-40
-60
0
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
Figure 38. Drive Current C (Low VDDEXT)
Rev. F
|
Page 50 of 60 |
October 2013
2.5
3.0
ADSP-BF539/ADSP-BF539F
0
80
VDDEXT = 3.0 V
VDDEXT = 3.3 V
60
VDDEXT = 3.6 V
-10
VDDEXT = 2.75V
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
100
40
VOH
20
0
-20
-40
VOL
-20
-30
VOL
-40
-50
-60
-60
-80
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
4.0
0.5
1.0
Figure 39. Drive Current C (High VDDEXT)
0
80
-10
VDDEXT = 2.75V
2.5
3.0
40
VOH
20
VDDEXT = 3.0 V
VDDEXT = 3.3 V
VDDEXT = 3.6 V
-20
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
2.0
Figure 42. Drive Current E (Low VDDEXT)
100
60
1.5
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
0
-20
-40
-30
-40
VOL
-50
-60
VOL
-70
-60
-80
-80
0
0.5
1.0
1.5
2.0
2.5
3.0
0
SOURCE VOLTAGE (V)
VDDEXT = 3.0 V
VDDEXT = 3.3 V
VDDEXT = 3.6 V
SOURCE CURRENT (mA)
50
VOH
0
-50
VOL
-100
-150
0.5
1.0
1.5
2.0
2.5
1.5
2.0
2.5
Figure 43. Drive Current E (High VDDEXT)
150
0
1.0
SOURCE VOLTAGE (V)
Figure 40. Drive Current D (Low VDDEXT)
100
0.5
3.0
3.5
4.0
SOURCE VOLTAGE (V)
Figure 41. Drive Current D (High VDDEXT)
Rev. F
|
Page 51 of 60 |
October 2013
3.0
3.5
4.0
ADSP-BF539/ADSP-BF539F
TEST CONDITIONS
All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 44
shows the measurement point for ac measurements (except output enable/disable). The measurement point VMEAS is 1.5 V for
VDDEXT (nominal) = 3.3 V.
INPUT
OR
OUTPUT
tDIS_MEASURED
tDIS
tENA_MEASURED
tENA
VOH
(MEASURED)
VOH (MEASURED) ⴚ ⌬V
VOH(MEASURED)
VTRIP(HIGH)
VOL (MEASURED) + ⌬V
VTRIP(LOW)
VOL (MEASURED)
VOL
(MEASURED)
VMEAS
VMEAS
REFERENCE
SIGNAL
tDECAY
tTRIP
OUTPUT STOPS DRIVING
Figure 44. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
Figure 45. Output Enable/Disable
Output Enable Time Measurement
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
The output enable time tENA is the interval from the point when
a reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 45 on Page 52.
The time tENA_MEASURED is the interval, from when the reference
signal switches, to when the output voltage reaches VTRIP(high)
or VTRIP(low). VTRIP(high) is 2.0 V and VTRIP(low) is 1.0 V for
VDDEXT (nominal) = 3.3 V. Time tTRIP is the interval from when
the output starts driving to when the output reaches the
VTRIP(high) or VTRIP(low) trip voltage.
Time tENA is calculated as shown in the equation:
t ENA = t ENA_MEASURED – t TRIP
If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left
side of Figure 45.
t DIS = t DIS_MEASURED – t DECAY
The time for the voltage on the bus to decay by V is dependent
on the capacitive load CL and the load current IL. This decay
time can be approximated by the equation:
t DECAY = C L V I L
The time tDECAY is calculated with test loads CL and IL, and with
V equal to 0.5 V for VDDEXT (nominal) = 3.3 V.
The time tDIS+_MEASURED is the interval from when the reference
signal switches, to when the output voltage decays V from the
measured output high or output low voltage.
Rev. F
|
Page 52 of 60 |
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose V
to be the difference between the ADSP-BF539/ADSP-BF539F
processor output voltage and the input threshold for the device
requiring the hold time. CL is the total bus capacitance (per data
line), and IL is the total leakage or three-state current (per data
line). The hold time is tDECAY plus the various output disable
times as specified in the Timing Specifications on Page 31 (for
example, tDSDAT for an SDRAM write cycle as shown in Table 26
on Page 36).
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 46). VLOAD is 1.5 V for VDDEXT
(nominal) = 3.3 V. Figure 47 on Page 53 through Figure 56 on
Page 54 show how output rise and fall times vary with capacitance. The delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these
figures may not be linear outside the ranges shown.
TESTER PIN ELECTRONICS
50:
VLOAD
T1
45:
DUT
OUTPUT
70:
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
50:
0.5pF
4pF
2pF
400:
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 46. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
October 2013
ADSP-BF539/ADSP-BF539F
10
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
14
12
RISE TIME
10
FALL TIME
8
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
6
FALL TIME
5
4
3
2
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 50. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver B at VDDEXT = 3.65 V (Max)
30
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
RISE TIME
7
0
250
12
10
RISE TIME
8
FALL TIME
6
4
2
25
RISE TIME
20
15
FALL TIME
10
5
0
50
100
150
LOAD CAPACITANCE (pF)
200
0
0
250
Figure 48. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 3.65 V (Max)
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 51. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver C at VDDEXT = 2.7 V (Min)
12
20
RISE AND FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
8
1
Figure 47. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 2.7 V (Min)
0
9
10
RISE TIME
8
FALL TIME
6
4
2
18
16
RISE TIME
14
12
FALL TIME
10
8
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 49. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver B at VDDEXT = 2.7 V (Min)
Rev. F
|
Page 53 of 60 |
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 52. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver C at VDDEXT = 3.65 V (Max)
October 2013
ADSP-BF539/ADSP-BF539F
124
16
120
14
RISE TIME
FALL TIME ns (10% to 90%)
RISE AND FALL TIME ns (10% to 90%)
18
12
10
FALL TIME
8
6
4
FALL TIME
112
108
104
2
0
116
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 53. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver D at VDDEXT = 2.7 V (Min)
100
0
RISE AND FALL TIME ns (10% to 90%)
12
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 54. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver D at VDDEXT = 3.65 V (Max)
132
FALL TIME ns (10% to 90%)
128
124
FALL TIME
120
116
112
108
0
50
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 55. Typical Fall Time (10% to 90%) vs. Load Capacitance for Driver E
at VDDEXT = 2.7 V (Min)
Rev. F
|
Page 54 of 60 |
100
150
LOAD CAPACITANCE (pF)
200
250
Figure 56. Typical Fall Time (10% to 90%) vs. Load Capacitance for Driver E
at VDDEXT = 3.65 V (Max)
14
10
50
October 2013
ADSP-BF539/ADSP-BF539F
THERMAL CHARACTERISTICS
To determine the junction temperature on the application
printed circuit board use
T J = T CASE + JT P D
where:
TJ = junction temperature (°C)
TCASE = case temperature (°C) measured by customer at top center of package.
JT = from Table 42 or Table 43
PD = power dissipation (see Electrical Characteristics on Page 27
for the method to calculate PD)
Values of JA are provided for package comparison and printed
circuit board design considerations. JA can be used for a first
order approximation of TJ by the equation:
T J = T A + JA P D
where:
TA = ambient temperature (°C)
Values of JC are provided for package comparison and printed
circuit board design considerations when an external heatsink is
required.
Values of JB are provided for package comparison and printed
circuit board design considerations.
In Table 42 and Table 43, airflow measurements comply with
JEDEC standards JESD51-2 and JESD51-6, and the junction-toboard measurement complies with JESD51-8. The junction-tocase measurement complies with MIL-STD-883 (Method
1012.1). All measurements use a 2S2P JEDEC test board.
Table 42. Thermal Characteristics BC-316 Without Flash
Parameter
Condition
Typical
Unit
JA
0 linear m/s air flow
25.4
°C/W
JMA
1 linear m/s air flow
22.8
°C/W
JMA
2 linear m/s air flow
JC
22.0
°C/W
6.7
°C/W
JT
0 linear m/s air flow
0.18
°C/W
JT
1 linear m/s air flow
0.38
°C/W
JT
2 linear m/s air flow
0.40
°C/W
Table 43. Thermal Characteristics BC-316 With Flash
Parameter
Condition
Typical
Unit
JA
0 linear m/s air flow
24.3
°C/W
JMA
1 linear m/s air flow
21.8
°C/W
JMA
2 linear m/s air flow
JC
21.0
°C/W
6.3
°C/W
JT
0 linear m/s air flow
0.17
°C/W
JT
1 linear m/s air flow
0.36
°C/W
JT
2 linear m/s air flow
0.38
°C/W
Rev. F
|
Page 55 of 60 |
October 2013
ADSP-BF539/ADSP-BF539F
316-BALL CSP_BGA BALL ASSIGNMENT
Figure 57 lists the top view of the CSP_BGA ball assignment.
Figure 58 lists the bottom view of the CSP_BGA ball
assignment.
Table 44 on Page 57 lists the CSP_BGA ball assignment by ball
number. Table 45 on Page 58 lists the CSP_BGA ball assignment by signal.
A1 BALL
1
2
3
4
5
6
VDDINT
7
8
A1 BALL
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
R
R
T
T
U
U
V
V
W
W
Y
Y
9 10 11 12 13 14 15 16 17 18 19 20
GND
VDDRTC
20 19 18 17 16 15 14 13 12 11 10 9
NC
I/O
VROUTx
VDDEXT
Note: H18 and Y14 are NC for ADSP-BF539
and I/O (FCE and FRESET) for ADSP-BF539F
8
7
VDDINT
GND
VDDRTC
VDDEXT
I/O
VROUTx
6
5
4
3
2
NC
Note: H18 and Y14 are NC for ADSP-BF539
and I/O (FCE and FRESET) for ADSP-BF539F
Figure 57. 316-Ball CSP_BGA Ball Assignment (Top View)
Figure 58. 316-Ball CSP_BGA Ball Assignment (Bottom View)
Rev. F
|
Page 56 of 60 |
October 2013
1
ADSP-BF539/ADSP-BF539F
Table 44. 316-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
C2
C3
C4
C5
C6
Signal
GND
PF10
PF11
PPI_CLK
PPI0
PPI2
PF15
PF13
VDDRTC
RTXO
RTXI
GND
CLKIN
XTAL
MLF
MXO
MXI
MRXON
VROUT1
GND
PF8
GND
PF9
PF3
PPI1
PPI3
PF14
PF12
SCL0
SDA0
CANRX
CANTX
NMI
RESET
MXEVDD
MXEGND
MTXON
GND
GND
VROUT0
PF6
PF7
GND
GND
RX1
TX1
Ball No.
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
D2
D3
D7
D8
D9
D10
D11
D12
D13
D14
D18
D19
D20
E1
E2
E3
E7
E8
E9
E10
E11
E12
E13
E14
E18
E19
E20
F1
F2
F3
F7
Signal
SPI2SEL1
SPI2SS
MOSI2
MISO2
SCK2
MPIVDD
SPI1SEL1
MISO1
SPI1SS
MOSI1
SCK1
GND
MMCLK
SCKE
PF4
PF5
DT1SEC
GND
GND
GND
GND
GND
GND
GND
GND
GND
MBCLK
SMS
PF1
PF2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MTX
ARDY
PF0
MISO0
GND
GND
Ball No.
F8
F9
F10
F11
F12
F13
F14
F18
F19
F20
G1
G2
G3
G7
G8
G9
G10
G11
G12
G13
G14
G18
G19
G20
H1
H2
H3
H7
H8
H9
H10
H11
H12
H13
H14
H18
H19
H20
J1
J2
J3
J7
J8
J9
J10
J11
Signal
GND
GND
GND
GND
GND
GND
GND
DT3PRI
MRX
MFS
SCK0
MOSI0
DT0SEC
GND
GND
GND
GND
GND
GND
GND
GND
BR
CLKOUT
SRAS
DT1PRI
TSCLK1
DR1SEC
GND
GND
GND
GND
GND
GND
GND
GND
FCE
SCAS
SWE
TFS1
DR1PRI
DR0SEC
GND
GND
GND
GND
GND
Rev. F
|
Ball No.
J12
J13
J14
J18
J19
J20
K1
K2
K3
K7
K8
K9
K10
K11
K12
K13
K14
K18
K19
K20
L1
L2
L3
L7
L8
L9
L10
L11
L12
L13
L14
L18
L19
L20
M1
M2
M3
M7
M8
M9
M10
M11
M12
M13
M14
M18
Signal
GND
GND
GND
AMS0
AMS2
SA10
RFS1
TMR2
GP
GND
GND
GND
GND
GND
GND
GND
GND
AMS3
AMS1
AOE
RSCLK1
TMR1
GND
GND
GND
GND
GND
GND
GND
GND
GND
TSCLK3
ARE
AWE
DT0PRI
TMR0
GND
VDDEXT
GND
GND
GND
GND
GND
GND
VDDINT
TFS3
Page 57 of 60 |
Ball No.
M19
M20
N1
N2
N3
N7
N8
N9
N10
N11
N12
N13
N14
N18
N19
N20
P1
P2
P3
P7
P8
P9
P10
P11
P12
P13
P14
P18
P19
P20
R1
R2
R3
R7
R8
R9
R10
R11
R12
R13
R14
R18
R19
R20
T1
T2
October 2013
Signal
ABE0
ABE1
TFS0
DR0PRI
GND
VDDEXT
GND
GND
GND
GND
GND
GND
VDDINT
DT3SEC
ADDR1
ADDR2
TSCLK0
RFS0
GND
VDDEXT
GND
GND
GND
GND
GND
GND
VDDINT
DR3SEC
ADDR3
ADDR4
TX0
RSCLK0
GND
VDDEXT
GND
GND
GND
GND
GND
GND
VDDINT
DR3PRI
ADDR5
ADDR6
RX0
EMU
Ball No.
T3
T7
T8
T9
T10
T11
T12
T13
T14
T18
T19
T20
U1
U2
U3
U7
U8
U9
U10
U11
U12
U13
U14
U18
U19
U20
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
Signal
GND
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
RFS3
ADDR7
ADDR8
TRST
TMS
GND
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
RSCLK3
ADDR9
ADDR10
TDI
GND
GND
BMODE1
BMODE0
GND
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
DR2SEC
BG
BGH
DT2SEC
GND
GND
ADDR11
ADDR12
Ball No.
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Signal
TCK
GND
DATA15
DATA13
DATA11
DATA9
DATA7
DATA5
DATA3
DATA1
RSCLK2
DR2PRI
DT2PRI
RX2
TX2
ADDR18
ADDR15
ADDR13
GND
ADDR14
GND
TDO
DATA14
DATA12
DATA10
DATA8
DATA6
DATA4
DATA2
DATA0
RFS2
TSCLK2
TFS2
FRESET
SCL1
SDA1
ADDR19
ADDR17
ADDR16
GND
ADSP-BF539/ADSP-BF539F
Table 45. 316-Ball CSP_BGA Ball Assignment (Alphabetically by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CANRX
CANTX
CLKIN
CLKOUT
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
Ball No.
M19
M20
N19
N20
P19
P20
R19
R20
T19
T20
U19
U20
V19
V20
W18
W20
W17
Y19
Y18
W16
Y17
J18
K19
J19
K18
K20
E20
L19
L20
V14
V15
V5
V4
G18
B11
B12
A13
G19
Y10
W10
Y9
W9
Y8
W8
Y7
W7
Signal
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DR2PRI
DR2SEC
DR3PRI
DR3SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
DT2PRI
DT2SEC
DT3PRI
DT3SEC
EMU
FCE
FRESET
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
Y6
W6
Y5
W5
Y4
W4
Y3
W3
N2
J3
J2
H3
W12
V13
R18
P18
M1
G3
H1
D3
W13
V16
F18
N18
T2
H18
Y14
A1
A12
A20
B2
B18
B19
C3
C4
C18
D7
D8
D9
D10
D11
D12
D13
D14
D18
E3
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
E7
E8
E9
F8
F9
F10
F11
F12
F13
F14
G7
G8
G9
E10
E11
E12
E13
E14
E18
F3
F7
G10
G11
G12
G13
G14
H7
H8
H9
H10
H11
H12
H13
H14
J7
J8
J9
J10
J11
J12
J13
J14
K7
K8
K9
K10
Rev. F
|
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
K11
K12
K13
L13
L14
M3
M8
M9
M10
M11
M12
M13
N3
K14
L3
L7
L8
L9
L10
L11
L12
N8
N9
N10
N11
N12
N13
P3
P8
P9
P10
P11
P12
P13
R3
R8
R9
R10
R11
R12
R13
T3
U3
V2
V3
V6
Page 58 of 60 |
Signal
GND
GND
GND
GND
GND
GND
GP
MBCLK
MFS
MISO0
MISO1
MISO2
MLF
MMCLK
MOSI0
MOSI1
MOSI2
MPIVDD
MRXON
MRX
MTX
MTXON
MXEGND
MXEVDD
MXI
MXO
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PPI_CLK
PPI0
PPI1
October 2013
Ball No.
V17
V18
W2
W19
Y1
Y20
K3
D19
F20
F2
C14
C10
A15
C19
G2
C16
C9
C12
A18
F19
E19
B17
B16
B15
A17
A16
B13
F1
E1
E2
B4
D1
D2
C1
C2
B1
B3
A2
A3
B8
A8
B7
A7
A4
A5
B5
Signal Ball No.
PPI2
A6
PPI3
B6
B14
RESET
RFS0
P2
RFS1
K1
RFS2
Y11
RFS3
T18
RSCLK0 R2
RSCLK1 L1
RSCLK2 W11
RSCLK3 U18
RTXI
A11
RTXO
A10
RX0
T1
RX1
C5
RX2
W14
SA10
J20
H19
SCAS
SCK0
G1
SCK1
C17
SCK2
C11
SCKE
C20
SCL0
B9
SCL1
Y15
SDA0
B10
SDA1
Y16
SMS
D20
SPI1SEL1 C13
SPI1SS C15
SPI2SEL1 C7
SPI2SS C8
G20
SRAS
H20
SWE
TCK
W1
TDI
V1
TDO
Y2
TFS0
N1
TFS1
J1
TFS2
Y13
TFS3
M18
TMR0
M2
TMR1
L2
TMR2
K2
TMS
U2
U1
TRST
TSCLK0 P1
Signal
TSCLK1
TSCLK2
TSCLK3
TX0
TX1
TX2
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDRTC
VROUT0
VROUT1
XTAL
Ball No.
H2
Y12
L18
R1
C6
W15
T8
T9
T10
T11
U7
U8
U9
U10
U11
V7
M7
N7
P7
R7
T7
V8
V9
V10
V11
M14
N14
P14
R14
T12
T13
T14
U12
U13
U14
V12
A9
B20
A19
A14
ADSP-BF539/ADSP-BF539F
OUTLINE DIMENSIONS
Dimensions in the outline dimensions figures are shown in
millimeters.
A1 BALL
CORNER
17.10
17.00 SQ
16.90
A1 BALL
CORNER
20 18 16 14 12 10 8 6 4 2
19 17 15 13 11 9 7 5 3 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
15.20
BSC SQ
0.80
BSC
TOP VIEW
BOTTOM VIEW
DETAIL A
1.70 MAX
DETAIL A
1.08
1.01
0.94
0.35 NOM
0.30 MIN
SEATING
PLANE
0.50
COPLANARITY
0.20
0.45
0.40
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-MMAB-1.
WITH EXCEPTION TO BALL DIAMETER.
Figure 59. 316-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-316-2)
Dimensions shown in millimeters
SURFACE-MOUNT DESIGN
Table 46 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351,
Generic Requirements for Surface Mount Design and Land Pattern Standard.
Table 46. BGA Data for Use with Surface-Mount Design
Package Ball Attach
Type
Solder Mask Defined
Package
316-Ball CSP_BGA (BC-316-2)
Rev. F
|
Page 59 of 60 |
October 2013
Package Solder Mask
Opening
0.40 mm diameter
Package Ball Pad
Size
0.50 mm diameter
ADSP-BF539/ADSP-BF539F
ORDERING GUIDE
The models shown in the following table are available with controlled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these automotive models may have specifications that differ from the
commercial models and designers should review the product
specifications section of this data sheet carefully. Contact your
local ADI account representative for specific product ordering
information and to obtain the specific Automotive Reliability
reports for these models.
Model1
Temperature
Range2
Instruction
Rate (Max)
Flash
Memory
Package Description
Package
Option
ADBF539WBBCZ4xx
–40°C to +85°C
400 MHz
N/A
316-Ball CSP_BGA
BC-316-2
ADBF539WBBCZ5xx
–40°C to +85°C
533 MHz
N/A
316-Ball CSP_BGA
BC-316-2
ADBF539WBBCZ4F8xx
–40°C to +85°C
400 MHz
8M bit
316-Ball CSP_BGA
BC-316-2
ADBF539WBBCZ5F8xx
–40°C to +85°C
533 MHz
8M bit
316-Ball CSP_BGA
BC-316-2
1
Z = RoHS compliant part.
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 26 for junction temperature (TJ)
specification which is the only temperature specification.
2
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06699-0-10/13(F)
Rev. F
|
Page 60 of 60 |
October 2013
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