ADCLK854BCPZ-REEL7

1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer ADCLK854 FEATURES FUNCTIONAL BLOCK DIAGRAM 2 selectable differential inputs Selectable LVDS/CMOS outputs Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs 1 V/ns, unless otherwise noted. Table 1. Clock Inputs and Outputs Parameter CLOCK INPUTS Input Frequency Input Sensitivity, Differential Symbol Min Typ 0 Unit 1200 MHz mV p-p 150 Input Level Input Common-Mode Voltage Input Common-Mode Range Input Voltage Offset Input Sensitivity, Single-Ended Input Resistance (Differential) Input Capacitance Input Bias Current (Each Pin) LVDS CLOCK OUTPUTS Output Frequency Output Voltage Differential Delta VOD Offset Voltage Delta VOS Short-Circuit Current Max VCM VCMR VS/2 − 0.1 0.4 1.8 V p-p VS/2 + 0.5 VS − 0.4 V V mV mV p-p kΩ pF μA 30 150 7 2 CIN −350 +350 Conditions Differential input Jitter performance improves with higher slew rates (greater voltage swing) Larger voltage swings can turn on the protection diodes and degrade jitter performance Inputs are self-biased; enables ac coupling Inputs dc-coupled with 200 mV p-p signal applied CLKx ac-coupled; CLKx ac bypassed to ground E Full input swing Termination = 100 Ω; differential (OUTx, OUTx) See Figure 9 for swing vs. frequency E VOD ΔVOD VOS ΔVOS ISA, ISB 247 344 1.125 1.25 3 1200 454 50 1.375 50 6 MHz mV mV V mV mA CMOS CLOCK OUTPUTS Each pin (output shorted to GND) Single-ended; termination = open; OUTx and OUTx in phase With 10 pF load per output; see Figure 16 for swing vs. frequency @ 1 mA load @ 1 mA load @ 10 mA load @ 10 mA load E Output Frequency Output Voltage High Output Voltage Low Output Voltage High Output Voltage Low Reference Voltage Output Voltage Output Resistance Output Current 250 VOH VOL VOH VOL VREF VS − 0.1 0.1 VS − 0.35 0.35 VS/2 − 0.1 VS/2 60 VS/2 + 0.1 500 Rev. A | Page 3 of 16 MHz V V V V V Ω μA ±500 μA ADCLK854 TIMING CHARACTERISTICS Table 2. Timing Characteristics Parameter LVDS OUTPUTS Output Rise/Fall Time Propagation Delay, Clock-to-LVDS Output Temperature Coefficient Output Skew1 LVDS Outputs in the Same Bank All LVDS Outputs On the Same Part Across Multiple Parts Additive Time Jitter Integrated Random Jitter Symbol Min Typ Max Unit tR , tF tPD 1.5 135 2.0 2.0 235 2.7 ps ns ps/°C 50 ps 65 390 ps ps 54 74 86 150 260 Broadband Random Jitter2 Crosstalk Induced Jitter CMOS OUTPUTS Output Rise/Fall Time Propagation Delay, Clock-to-CMOS Output Temperature Coefficient Output Skew1 CMOS Outputs in the Same Bank All CMOS Outputs On the Same Part Across Multiple Parts Additive Time Jitter Integrated Random Jitter Broadband Random Jitter2 Crosstalk Induced Jitter LVDS-TO-CMOS OUTPUT SKEW3 LVDS Output(s) and CMOS Output(s) on the Same Part 1 2 3 tR, tF tPD 2.5 525 3.2 2.2 fs rms fs rms fs rms fs rms fs rms BW = 12 kHz to 20 MHz; clock = 1000 MHz BW = 50 kHz to 80 MHz; clock = 1000 MHz BW = 10Hz to 100 MHz; clock = 1000 MHz Input slew = 1 V/ns, see Figure 11 Calculated from spur energy with an interferer 10 MHz offset from the carrier 950 4.2 ps ns ps/°C 20% to 80%; CLOAD = 10 pF 10 pF load 155 ps 175 640 ps ps 56 100 260 0.8 1.6 fs rms fs rms fs rms BW = 12 kHz to 20 MHz; clock = 200 MHz Input slew = 2 V/ns, see Figure 11 Calculated from spur energy with an interferer 10 MHz offset from the carrier ns CMOS load = 10 pF and LVDS load = 100 Ω This is the difference between any two similar delay paths while operating at the same voltage and temperature. Calculated from the SNR of the ADC method. Measured at the rising edge of the clock signal. Rev. A | Page 4 of 16 Conditions Termination = 100 Ω differential; 3.5 mA 20% to 80% measured differentially VICM = VREF, VID = 0.5 V ADCLK854 CLOCK CHARACTERISTICS Table 3. Clock Output Phase Noise Parameter CLOCK-TO-LVDS ABSOLUTE PHASE NOISE 1000 MHz Min CLOCK-TO-CMOS ABSOLUTE PHASE NOISE 200 MHz Typ Max Unit −90 −108 −117 −126 −135 −141 −146 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −101 −119 −127 −138 −147 −153 −156 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Conditions Input slew rate > 1 V/ns @ 10 Hz offset @ 100 Hz offset @ 1 kHz offset @ 10 kHz offset @ 100 kHz offset @ 1 MHz offset @ 10 MHz offset Input slew rate > 1 V/ns @ 10 Hz offset @ 100 Hz offset @ 1 kHz offset @ 10 kHz offset @ 100 kHz offset @ 1 MHz offset @ 10 MHz offset LOGIC AND POWER CHARACTERISTICS Table 4. Control Pin Characteristics Parameter CONTROL PINS (IN_SEL, CTRL_x, SLEEP)1 Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance POWER Supply Voltage Requirement LVDS Outputs LVDS @ 100 MHz LVDS @ 1200 MHz Symbol Min VIH VIL IIH IIL VS − 0.4 5 −5 Typ Max Unit 8 0.4 20 +5 V V μA μA pF 1.8 1.89 V 84 175 100 215 mA mA 115 265 140 325 3 mA mA mA 2 VS 1.71 CMOS Outputs CMOS @ 100 MHz CMOS @ 250 MHz SLEEP Power Supply Rejection2 LVDS CMOS PSR t PD 0.9 ps/mV PSR t PD 1.2 ps/mV 1 These pins each have a 200 kΩ internal pull-down resistor. 2 Change in tPD per change in VS. Rev. A | Page 5 of 16 Conditions VS = 1.8 V ± 5% Full operation All outputs enabled as LVDS and loaded, RL = 100 Ω All outputs enabled as LVDS and loaded, RL = 100 Ω Full operation All outputs enabled as CMOS and loaded, CL = 10 pF All outputs enabled as CMOS and loaded, CL = 10 pF SLEEP pin pulled high; does not include power dissipated in the external resistors ADCLK854 ABSOLUTE MAXIMUM RATINGS DETERMINING JUNCTION TEMPERATURE Table 5. Parameter Supply Voltage VS to GND Inputs CLKx and CLKx CMOS Inputs Outputs Maximum Voltage Voltage Reference Voltage (VREF) Operating Temperature Ambient Range Junction Storage Temperature Range E To determine the junction temperature on the application printed circuit board (PCB), use the following equation: Rating 2V TJ = TCASE + (JT × PD) where: TJ is the junction temperature (°C). TCASE is the case temperature (°C) measured by the user at the top center of the package. JT is from Table 6. PD is the power dissipation. −0.3 V to +2 V −0.3 V to +2 V −0.3 V to +2 V −0.3 to +2 V Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first-order approximation of TJ by the equation −40°C to +85°C 150°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TJ = TA + (JA × PD) where TA is the ambient temperature (°C). Values of JB are provided in Table 6 for package comparison and PCB design considerations. ESD CAUTION THERMAL PERFORMANCE Table 6. Parameter Junction-to-Ambient Thermal Resistance Still Air 0.0 m/sec Air Flow Moving Air 1.0 m/sec Air Flow 2.5 m/sec Air Flow Junction-to-Board Thermal Resistance Moving Air 1.0 m/sec Air Flow Junction-to-Case Thermal Resistance Moving Air Die-to-Heat Sink Junction-to-Top-of-Package Characterization Parameter Still Air 0 m/sec Air Flow 1 Symbol Description (Using a 2S2P Test Board) Value1 Unit 42 °C/W 37 33 °C/W °C/W 26 °C/W 2 °C/W 0.5 °C/W JA Per JEDEC JESD51-2 JMA Per JEDEC JESD51-6 JB Per JEDEC JESD51-8 JC Per MIL-STD 883, Method 1012.1 JT Per JEDEC JESD51-2 Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. Rev. A | Page 6 of 16 ADCLK854 1 2 CLK0 3 GND 4 CLK1 5 CLK1 6 VS 7 OUT11 (OUT11B) 8 37 VS 38 GND 40 OUT3 (OUT3A) 39 OUT3 (OUT3B) 43 VS 42 OUT2 (OUT2A) 41 OUT2 (OUT2B) 44 GND 45 OUT1 (OUT1B) 36 NC 35 NC 34 OUT4 (OUT4A) 33 OUT4 (OUT4B) 32 OUT5 (OUT5A) ADCLK854 31 OUT5 (OUT5B) TOP VIEW (Not to Scale) 30 VS 29 GND OUT11 (OUT11A) 9 IN_SEL 10 28 OUT6 (OUT6A) CTRL_A 11 26 OUT7 (OUT7A) CTRL_B 12 25 OUT7 (OUT7B) GND 23 VS 24 19 20 21 22 17 18 GND VS OUT9 (OUT9B) OUT9 (OUT9A) OUT8 (OUT8B) OUT8 (OUT8A) OUT10 (OUT10B) 15 OUT10 (OUT10A) 16 CTRL_C 13 SLEEP 14 27 OUT6 (OUT6B) NOTES: 1. NC = NO CONNECT. 2. EXPOSED PADDLE MUST BE CONNECTED TO GND. 07218-002 VREF CLK0 47 OUT0 (OUT0B) 46 OUT1 (OUT1A) 48 OUT0 (OUT0A) PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 7, 18, 24, 30, 37, 43 5 6 8 9 10 11 Mnemonic VREF CLK0 CLK0 VS Description Reference Voltage. Input (Negative) 0. Input (Positive) 0. Supply Voltage. CLK1 CLK1 OUT11 (OUT11B) OUT11 (OUT11A) IN_SEL CTRL_A 12 CTRL_B 13 14 15 16 4, 17, 23, 29, 38, 44 19 20 21 22 25 CTRL_C SLEEP OUT10 (OUT10B) OUT10 (OUT10A) GND Input (Negative) 1. Input (Positive) 1. Complementary Side of Differential LVDS Output 11, or CMOS Output 11 on Channel B. True Side of Differential LVDS Output 11, or CMOS Output 11 on Channel A. Input Select. (0 = CLK0, CLK0; 1 = CLK1, CLK1). CMOS logic input with 200 kΩ pull-down resistor. Control for Output 3 to Output 0 (0 = LVDS, 1 = CMOS). CMOS logic input with 200 kΩ pull-down resistor. Control for Output 7 to Output 4 (0 = LVDS, 1 = CMOS). CMOS logic input with 200 kΩ pull-down resistor. Control for Output 11 to Output 8 (0 = LVDS, 1 = CMOS). CMOS logic input with 200 kΩ pull-down resistor. Sleep Mode Control (0 = normal operation, 1 = sleep). CMOS logic input with 200 kΩ pull down resistor. Complementary Side of Differential LVDS Output 10, or CMOS Output 10 on Channel B. True Side of Differential LVDS Output 10, or CMOS Output 10 on Channel A. Ground Pin. OUT9 (OUT9B) OUT9 (OUT9A) OUT8 (OUT8B) OUT8 (OUT8A) OUT7 (OUT7B) Complementary Side of Differential LVDS Output 9, or CMOS Output 9 on Channel B. True Side of Differential LVDS Output 9, or CMOS Output 9 on Channel A. Complementary Side of Differential LVDS Output 8, or CMOS Output 8 on Channel B. True Side of Differential LVDS Output 8, or CMOS Output 8 on Channel A. Complementary Side of Differential LVDS Output 7, or CMOS Output 7 on Channel B. E E E E E E E E Rev. A | Page 7 of 16 E ADCLK854 Pin No. 26 27 28 31 32 33 34 35 36 39 40 41 42 45 46 47 48 (49) Mnemonic OUT7 (OUT7A) OUT6 (OUT6B) OUT6 (OUT6A) OUT5 (OUT5B) OUT5 (OUT5A) OUT4 (OUT4B) OUT4 (OUT4A) NC NC OUT3 (OUT3B) OUT3 (OUT3A) OUT2 (OUT2B) OUT2 (OUT2A) OUT1 (OUT1B) OUT1 (OUT1A) OUT0 (OUT0B) OUT0 (OUT0A) EPAD E E E E E E E Description True Side of Differential LVDS Output 7, or CMOS Output 7 on Channel A. Complementary Side of Differential LVDS Output 6, or CMOS Output 6 on Channel B. True Side of Differential LVDS Output 6, or CMOS Output 6 on Channel A. Complementary Side of Differential LVDS Output 5, or CMOS Output 5 on Channel B. True Side of Differential LVDS Output 5, or CMOS Output 5 on Channel A. Complementary Side of Differential LVDS Output 4, or CMOS Output 4 on Channel B. True Side of Differential LVDS Output 4, or CMOS Output 4 on Channel A. No Connect. No Connect. Complementary Side of Differential LVDS Output 3, or CMOS Output 3 on Channel B. True Side of Differential LVDS Output 3, or CMOS Output 3 on Channel A. Complementary Side of Differential LVDS Output 2, or CMOS Output 2 on Channel B. True Side of Differential LVDS Output 2, or CMOS Output 2 on Channel A. Complementary Side of Differential LVDS Output 1, or CMOS Output 1 on Channel B. True Side of Differential LVDS Output 1, or CMOS Output 1 on Channel A. Complementary Side of Differential LVDS Output 0, or CMOS Output 0 on Channel B. True Side of Differential LVDS Output 0, or CMOS Output 0 on Channel A. Exposed Paddle. The exposed paddle must be connected to GND. Rev. A | Page 8 of 16 ADCLK854 TYPICAL PERFORMANCE CHARACTERISTICS VS = +1.8 V, TA = 25°C, unless otherwise noted. 2 M 200ps 10.0GS/s CH1 –36.0mV CH2 100mV Figure 3. LVDS Output Waveform @ 1200 MHz M 1.0ns 10.0GS/s CH1 –36.0mV 07218-006 CH2 100mV 07218-003 2 Figure 6. LVDS Output Waveform @ 200 MHz 2.3 2.4 2.3 2.2 PROPAGATION DELAY (ns) PROPATATION DELAY (ns) 2.2 2.1 2.0 1.9 2.1 2.0 1.9 1.8 1.7 1.6 1.8 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 INPUT DIFFERENTIAL (V p-p) 1.4 200 07218-004 1.7 0.1 800 1000 1200 1400 1600 Figure 7. LVDS Propagation Delay vs. VICM 715 DIFFERENTIAL OUTPUT SWING (mV p-p) 54 53 52 51 50 49 48 47 0 200 400 600 800 1000 FREQUENCY (MHz) 1200 07218-005 46 Figure 5. LVDS Output Duty Cycle vs. Frequency 705 695 685 675 1.62 1.72 1.82 POWER SUPPLY (V) 1.92 07218-008 55 DUTY CYCLE (%) 600 INPUT COMMON-MODE (mV) Figure 4. LVDS Propagation Delay vs. Input Differential Voltage (VID) 45 400 07218-007 1.5 Figure 8. LVDS Differential Output Swing vs. Power Supply Voltage Rev. A | Page 9 of 16 ADCLK854 –80 ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672), WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D). –90 –100 PHASE NOISE (dBc/Hz) 800 700 600 –110 ADCLK854 –120 –130 –140 –150 CLOCK SOURCE –160 500 100 1k 10k 100k 1M Figure 9. LVDS Differential Output Swing vs. Input Frequency 300 325 ALL BANKS CMOS 300 250 275 2 BANKS CMOS 1 BANK LVDS 250 225 CURRENT (mA) 200 175 150 125 200 150 100 100 1 BANK CMOS 2 BANKS LVDS 75 50 50 0 200 400 600 800 1000 1200 1400 1600 1800 FREQUENCY (MHz) 0 25 07218-110 0 54 400 53 350 52 DUTY CYCLE (%) 55 450 300 250 200 50 46 INPUT SLEW RATE (V/ns) 2.5 07218-011 47 2.0 175 200 225 250 49 48 1.5 150 50 100 1.0 125 51 150 0.5 100 Figure 13. LVDS/CMOS Current vs. Frequency with Various Logic Combinations 500 0 75 FREQUENCY (MHz) Figure 10. LVDS Current vs. Frequency; All Banks Set to LVDS 0 50 07218-113 ALL BANKS LVDS 25 45 0 50 100 150 200 250 FREQUENCY (MHz) Figure 14. CMOS Output Duty Cycle vs. Frequency (10 pF Load) Figure 11. Additive Broadband Jitter vs. Input Slew Rate Rev. A | Page 10 of 16 07218-014 CURRENT (mA) 100M Figure 12. Absolute Phase Noise LVDS @ 1000 MHz 350 JITTER (fs rms) 10M FREQUENCY OFFSET (Hz) 07218-012 1700 INPUT FREQUENCY (MHz) –180 10 07218-009 1600 1500 1400 1300 1200 1100 900 1000 800 700 600 500 400 100 300 –170 400 200 DIFFERENTIAL OUTPUT SWING (mV p-p) 900 ADCLK854 CH1 300mV 1.25ns/DIV CH1 954mV CH1 300mV Figure 15. CMOS Output Waveform @ 200 MHz (10 pF Load) 5.0ns/DIV 954mV Figure 18. CMOS Output Waveform @ 50 MHz (10 pF Load) 1.9 1.8 1.8 RLOAD = 750Ω 25°C RLOAD = 1kΩ 1.7 OUTPUT SWING (V) 1.7 OUTPUT SWING (V) CH1 07218-018 1 07218-015 1 1.6 85°C 1.5 1.4 1.3 1.6 RLOAD = 500Ω RLOAD = 300Ω 1.5 100 150 200 250 FREQUENCY (MHz) Figure 16. CMOS Output Swing vs. Frequency by Temperature (10 pF Load) 2.0 1.9 CL = 5pF 1.7 CL = 10pF 1.6 1.5 CL = 20pF 1.4 1.3 1.2 1.1 1.0 0 50 100 150 200 250 FREQUENCY (MHz) 07218-017 OUTPUT SWING (V) 1.8 Figure 17. CMOS Output Swing vs. Frequency by Capacitive Load Rev. A | Page 11 of 16 1.4 0 50 100 150 200 250 FREQUENCY (MHz) Figure 19. CMOS Output Swing vs. Frequency by Resistive Load 07218-019 1.1 50 07218-016 1.2 ADCLK854 FUNCTIONAL DESCRIPTION The ADCLK854 accepts a clock input from one of two inputs and distributes the selected clock to all output channels. The outputs are grouped into three banks of four and can be set to either LVDS or CMOS levels. This allows the selection of multiple logic configurations ranging from 12 LVDS to 24 CMOS outputs, along with other combinations using both types of logic. CLOCK INPUTS The ADCLK854 differential inputs are internally self-biased. The clock inputs have a resistor divider that sets the commonmode level for the inputs. The complementary inputs are biased about 30 mV lower than the true input to avoid oscillations if the input signal stops. See Figure 20 for the equivalent input circuit. The inputs can be ac-coupled or dc-coupled. Table 8 displays a guide for input logic compatibility. A single-ended input can be accommodated by ac or dc coupling to one side of the differential input; bypass the other input to ground with a capacitor. The second option allows the use of the VREF pin to set the dc bias level for the ADCLK854. The VREF pin can be connected to CLKx and CLKx through resistors. This method allows lower impedance termination of signals at the ADCLK854 (for more information, see Figure 32). The internal bias resistors remain in parallel with the external biasing. However, the relatively high impedance of the internal resistors allows the external termination to VREF to dominate. This method is also useful when offsetting the inputs; using only the internal biasing, as previously mentioned, is not desirable. E CLOCK OUTPUTS Each driver consists of a differential LVDS output or two single-ended CMOS outputs (always in phase). When the LVDS driver is enabled, the corresponding CMOS driver is in tristate; when the CMOS driver is enabled, the corresponding LVDS driver is powered down and tristated. Figure 21 and Figure 22 display the equivalent output stage. VS Note that jitter performance degrades with low input slew rate, as shown in Figure 11. See Figure 27 through Figure 32 for different termination schemes. 3.5mA VS 9kΩ OUTx OUTx 9.5kΩ CLKx 8.5kΩ GND 07218-021 10kΩ 10kΩ 07218-020 CLKx 9kΩ 3.5mA Figure 21. LVDS Output Simplified Equivalent Circuit Figure 20. ADCLK854 Input Stage VS AC-COUPLED INPUT APPLICATIONS The ADCLK854 offers two options for ac coupling. The first option requires no external components (excluding the dc blocking capacitor), it allows the user to simply couple the reference signal onto the clock input pins. For more information, see Figure 29. VS OUTB 07218-022 OUTA Figure 22. CMOS Output Equivalent Circuit Table 8. Input Logic Compatibility Supply (V) 3.3 2.5 1.8 3.3 2.5 1.8 1.5 3.3 2.5 1.8 Logic CML CML CML CMOS CMOS CMOS HSTL LVDS LVPECL LVPECL LVPECL Common Mode (V) 2.9 2.1 1.4 1.65 1.25 0.9 0.75 1.25 2.0 1.2 0.5 Output Swing (V) 0.8 0.8 0.8 3.3 2.5 1.8 0.75 0.4 0.8 0.8 0.8 Rev. A | Page 12 of 16 AC-Coupled Yes Yes Yes Not allowed Not allowed Yes Yes Yes Yes Yes Yes DC-Coupled Not allowed Not allowed Yes Not allowed Not allowed Yes Yes Yes Not allowed Yes Yes ADCLK854 CONTROL AND FUNCTION PINS CTRL_A—Logic Select This pin selects either CMOS (high) or LVDS (low) logic for Output 3, Output 2, Output 1, and Output 0. This pin has an internal 200 kΩ pull-down resistor. CTRL_B—Logic Select This pin selects either CMOS (high) or LVDS (low) logic for Output 7, Output 6, Output 5, and Output 4. This pin has an internal 200 kΩ pull-down resistor. CTRL_C—Logic Select This pin selects either CMOS (high) or LVDS (low) logic for Output 11, Output 10, Output 9, and Output 8. This pin has an internal 200 kΩ pull-down resistor. PCB with adequate capacitance (>10 μF), and bypassing all power pins with adequate capacitance (0.1 μF) as close to the part as possible. The layout of the ADCLK854 evaluation board (ADCLK854/PCBZ) provides a good layout example. Exposed Metal Paddle The exposed metal paddle on the ADCLK854 package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The ADCLK854 dissipates heat through its exposed paddle. The PCB acts as a heat sink for the ADCLK854. The PCB attachment must provide a good thermal path to a larger heat dissipation area, such as the ground plane on the PCB. This requires a grid of vias from the top layer down to the ground plane. See Figure 23 for an example. IN_SEL—Clock Input Select A logic low selects CLK0 and CLK0 whereas a logic high selects CLK1 and CLK1. This pin has an internal 200 kΩ pull-down resistor. E E VIAS TO GND PLANE Sleep mode powers down the chip except for the internal band gap. The input is active high, which puts the outputs into a high-Z state. This pin has a 200 kΩ pull-down resistor. POWER SUPPLY 07218-023 Sleep Mode Figure 23. PCB Land for Attaching Exposed Paddle The ADCLK854 requires a 1.8 V ± 5% power supply for VS. Best practice recommends bypassing the power supply on the Rev. A | Page 13 of 16 ADCLK854 APPLICATIONS INFORMATION USING THE ADCLK854 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed, analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought of as a sampling mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-to-digital output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at ≥14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR can be expressed approximately by The ADCLK854 provides clock outputs that are selectable as either CMOS or LVDS level outputs. LVDS is a differential output option that uses a current-mode output stage. The nominal current is 3.5 mA, which yields 350 mV output swing across a 100 Ω resistor. The LVDS output meets or exceeds all ANSI/TIA/EIA-644 specifications. A recommended termination circuit for the LVDS outputs is shown in Figure 25. If ac coupling is necessary, place decoupling capacitors either before or after the 100 Ω termination resistor. See Application Note AN-586 at www.analog.com for more information on LVDS. VS VS LVDS    100Ω 100Ω DIFFERENTIAL (COUPLED) LVDS 07218-025  1 SNR  20  log   2πf ATJ LVDS CLOCK DISTRIBUTION Figure 25. LVDS Output Termination where fA is the highest analog frequency being digitized and TJ is the rms jitter on the sampling clock. CMOS CLOCK DISTRIBUTION Figure 24 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB). For more information, see Application Note AN-756 and Application Note AN-501 at www.analog.com. The output drivers of the ADCLK854 can be configured as CMOS drivers. When selected as a CMOS driver, each output becomes a pair of CMOS outputs. These outputs are 1.8 V CMOS compatible. 1 SNR = 20log 2πf T A J 100 When single-ended CMOS clocking is used, some of the following guidelines apply. 18 16 Design point-to-point connections such that each driver has only one receiver, if possible. Connecting outputs in this manner allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the output trace. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. 90 TJ = 100 fS 200 f 14 S 400 f 70 S 12 1ps 60 2ps 10 10p s 8 50 40 ENOB SNR (dB) 80 100 fA FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz) 1k 07218-024 6 30 10 Figure 24. SNR and ENOB vs. Analog Input Frequency Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sample clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment. Consider the input requirements of the ADC (differential or single-ended, logic level, and termination) when selecting the best clocking/converter solution. The value of the resistor (typically 10 Ω to 100 Ω) is dependent on the board design and timing requirements. CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and signal integrity. CMOS 10Ω 60.4Ω 1.0 INCH CMOS MICROSTRIP 07218-026 110 Figure 26. Series Termination of CMOS Output Termination at the far end of the PCB trace is a second option. The CMOS outputs of the ADCLK854 do not supply enough current to provide a full voltage swing with a low impedance resistive, far end termination, as shown in Figure 27. The far end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may Rev. A | Page 14 of 16 ADCLK854 still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical networks. CLK CLK 50Ω VS 50Ω 10Ω 100Ω VCC – 2V CMOS 07218-027 100Ω CLK Figure 27. CMOS Output with Far End Termination CLK 50Ω Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The ADCLK854 offers LVDS outputs that are better suited for driving long traces wherein the inherent noise immunity of differential signaling provides superior performance for clocking converters. 50Ω 07218-030 CMOS 50Ω VCC – 2V Figure 30. Typical AC-Coupled or DC-Coupled PECL Configuration (See Table 8 for LVPECL DC-Coupling Limitations) INPUT TERMINATION OPTIONS CLK CLK CLK CLK For single-ended operation always bypass unused input to GND, as shown in Figure 31. Figure 32 illustrates the use of VREF to provide low impedance termination into VS/2. In addition, a way to negate the 30 mV input offset is with external resistor values; for example, using a 1.8 V CMOS with long traces to provide far end termination. CLK 07218-031 CLK Figure 31. Typical 1.8 V CMOS Configurations for Short Trace Lengths (See Table 8 for CMOS Compatibility) CLK 100Ω CLK VREF CLK CLK 07218-028 100Ω Figure 28. Typical AC-Coupled or DC-Coupled LVDS or HSTL Configuration (See Table 8 for More Information) Figure 32. Use of VREF to Provide Low Impedance Termination into VS/2 VCC CLK CLK VCC 07218-029 CLK CLK 07218-032 CLK CLK Figure 29. Typical AC-Coupled or DC-Coupled CML Configuration (See Table 8 for CML Coupling Limitations) Rev. A | Page 15 of 16 ADCLK854 OUTLINE DIMENSIONS 0.30 0.23 0.18 1 0.50 BSC 2.90 2.80 SQ 2.70 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 END VIEW PKG-000000 SEATING PLANE 0.50 0.40 0.30 P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 48 37 36 13 24 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.20 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-2 10-10-2018-A PIN 1 INDICATOR AREA DETAIL A (JEDEC 95) 7.10 7.00 SQ 6.90 Figure 33. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.75 mm Package Height CP-48-21 Dimensions shown in millimeters ORDERING GUIDE Model ADCLK854BCPZ1 ADCLK854BCPZ-REEL71 ADCLK854/PCBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 48-Lead LFCSP 48-Lead LFCSP Evaluation Board Z = RoHS Compliant Part. ©2009–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07218-11/20(A) Rev. A | Page 16 of 16 Package Option CP-48-21 CP-48-21