Ultrafast SiGe
ECL Clock/Data Buffers
ADCLK905/ADCLK907/ADCLK925
Data Sheet
TYPICAL APPLICATION CIRCUITS
95 ps propagation delay
7.5 GHz toggle rate
60 ps typical output rise/fall
60 fs random jitter (RJ)
On-chip terminations at both input pins
Extended industrial temperature range: −40°C to +125°C
2.5 V to 3.3 V power supply (VCC − VEE)
APPLICATIONS
VREF
VCC
VT
D
Q
D
Q
06318-001
FEATURES
VEE
Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer
Clock and data signal restoration and level shifting
Automated test equipment (ATE)
High speed instrumentation
High speed line receivers
Threshold detection
Converter clocking
VREF 1
VT1
VCC
Q1
D1
Q1
D1
GENERAL DESCRIPTION
VEE
Q2
D2
VCC
VT2
VREF 2
Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer
VREF
The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate,
10 Gbps data rate, and 60 fs random jitter (RJ).
VT
The inputs have center tapped, 100 Ω, on-chip termination
resistors. A VREF pin is available for biasing ac-coupled inputs.
D
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to VCC − 2 V for a total
differential output swing of 1.6 V.
Q2
06318-002
The ADCLK905/ADCLK907/ADCLK925 feature full-swing
emitter coupled logic (ECL) output drivers. For PECL (positive
ECL) operation, bias VCC to the positive supply and VEE to ground.
For NECL (negative ECL) operation, bias VCC to ground and
VEE to the negative supply.
VEE
D2
VCC
Q1
Q1
D
Q2
Q2
VEE
06318-003
The ADCLK905 (one input, one output), ADCLK907 (dual one
input, one output), and ADCLK925 (one input, two outputs) are
ultrafast clock/data buffers fabricated on the Analog Devices, Inc.,
proprietary XFCB3 silicon germanium (SiGe) bipolar process.
Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer
The ADCLK905/ADCLK907/ADCLK925 are available in
16-lead LFCSP packages.
Rev. B
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Technical Support
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ADCLK905/ADCLK907/ADCLK925
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................9
Applications ....................................................................................... 1
Applications Information .............................................................. 12
General Description ......................................................................... 1
Power/Ground Layout and Bypassing ..................................... 12
Typical Application Circuits............................................................ 1
Output Stages ............................................................................... 12
Revision History ............................................................................... 2
Optimizing High Speed Performance ..................................... 12
Specifications..................................................................................... 3
Buffer Random Jitter .................................................................. 12
Electrical Characteristics ............................................................. 3
Typical Application Circuits ......................................................... 13
Absolute Maximum Ratings ............................................................ 5
Evaluation Board Schematic ......................................................... 14
Thermal Resistance ...................................................................... 5
Outline Dimensions ....................................................................... 15
ESD Caution .................................................................................. 5
Ordering Guide .......................................................................... 15
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
2/2017—Rev. A to Rev. B
Changes to Figure 4 and Table 4 ..................................................... 6
Changes to Figure 5 and Table 5 ..................................................... 7
Changes to Figure 6 and Table 6 ..................................................... 8
8/2016—Rev. 0 to Rev. A
Changed CP-16-3 to CP-16-27 .................................... Throughout
Changes to Figure 4 and Table 4 ..................................................... 6
Changes to Figure 5 and Table 5 ..................................................... 7
Changes to Figure 6 and Table 6 ..................................................... 8
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 15
8/2007—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet
ADCLK905/ADCLK907/ADCLK925
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (Min) and maximum (Max) values are
given over the full VCC − VEE = 3.3 V ± 10% and TA = −40°C to +125°C variation, unless otherwise noted.
Table 1.
Parameter
DC INPUT CHARACTERISTICS
Input Voltage High Level
Input Voltage Low Level
Input Differential Range
Input Capacitance
Input Resistance, Single-Ended Mode
Input Resistance, Differential Mode
Input Resistance, Common Mode
Input Bias Current
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
Output Voltage Low Level
Output Voltage Differential
Reference Voltage
Output Voltage
Output Resistance
AC PERFORMANCE
Propagation Delay
Symbol
Min
VIH
VIL
VID
VID
122.88 MHz
Max
Unit
VEE + 1.6
VEE
0.2
VCC
VCC − 0.7
3.4
V
V
V p-p
0.2
2.8
V p-p
CIN
VOH
VOL
VOD
VREF
0.4
pF
50
100
50
20
Ω
Ω
kΩ
µA
VCC − 1.26
VCC − 1.99
610
VCC − 0.76
VCC − 1.54
1040
(VCC + 1)/2
250
tPD
Propagation Delay Temperature Coefficient
Propagation Delay Skew (Output to Output)
ADCLK907
Propagation Delay Skew (Output to Output)
ADCLK925
Propagation Delay Skew (Device to Device)
Toggle Rate
Random Jitter
Rise/Fall Time
Additive Phase Noise
622.08 MHz
Typ
−40°C to +85°C
(±1.7 V between input pins)
85°C to 125°C
(±1.4 V between input pins)
Open VT
V
V
mV
50 Ω to (VCC − 2.0 V)
50 Ω to (VCC − 2.0 V)
50 Ω to (VCC − 2.0 V)
V
Ω
−500 µA to +500 µA
VCC = 3.3 V ± 10%,
VICM = VREF, VID = 0.5 V p-p
VCC = 2.5 V ± 5%,
VICM = V REF, VID = 0.5 V p-p
70
95
125
ps
70
95
125
ps
15
fs/°C
ps
VID = 0.5 V
10
ps
VID = 0.5 V
35
7.5
ps
GHz
6.5
GHz
fs rms
ps
VID = 0.5 V
>0.8 V differential output swing,
VCC = 3.3 V ± 10%
>0.8 V differential output swing,
VCC = 2.5 V ± 5%
VID = 1600 mV, 8 V/ns, VICM = 1.85 V
20%/80%
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10 Hz offset
@100 Hz offset
@1 kHz offset
@10 kHz offset
@100 kHz offset
>1 MHz offset
@10 Hz offset
@100 Hz offset
@1 kHz offset
@10 kHz offset
@100 kHz offset
>1 MHz offset
50
6
RJ
tR/tF
Test Conditions/Comments
60
30
85
−138
−144
−152
−159
−161
−161
−135
−145
−153
−160
−161
−161
Rev. B | Page 3 of 16
ADCLK905/ADCLK907/ADCLK925
Parameter
POWER SUPPLY
Supply Voltage Requirement
Power Supply Current
ADCLK905
Negative Supply Current
Positive Supply Current
ADCLK907
Negative Supply Current
Positive Supply Current
ADCLK925
Negative Supply Current
Positive Supply Current
Power Supply Rejection 1
Output Swing Supply Rejection 2
1
2
Data Sheet
Symbol
Min
VCC − VEE
2.375
IVEE
IVCC
IVEE
IVCC
IVEE
IVCC
PSRVCC
PSRVCC
Typ
24
25
47
48
48
50
94
96
29
31
76
77
3
26
Change in TPD per change in VCC.
Change in output swing per change in VCC.
Rev. B | Page 4 of 16
Max
Unit
Test Conditions/Comments
3.63
V
2.5 V − 5% to 3.3 V + 10%
Static
mA
mA
mA
mA
VCC − VEE = 2.5 V
VCC − VEE = 3.3 V ± 10%
VCC − VEE = 2.5 V
VCC − VEE = 3.3 V ± 10%
mA
mA
mA
mA
VCC − VEE = 2.5 V
VCC − VEE = 3.3 V ± 10%
VCC − VEE = 2.5 V
VCC − VEE = 3.3 V ± 10%
mA
mA
mA
mA
ps/V
dB
VCC − VEE = 2.5 V
VCC − VEE = 3.3 V ± 10%
VCC − VEE = 2.5 V
VCC − VEE = 3.3 V ± 10%
VCC − VEE = 3.0 V ± 20%
VCC − VEE = 3.0 V ± 20%
40
63
80
126
51
97
Data Sheet
ADCLK905/ADCLK907/ADCLK925
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Supply Voltage
VCC − VEE
Input Voltage
D (D1, D2), D (D1, D2)
D1, D2, D1, D2 to VT Pin
(CML or PECL Termination)
D (D1, D2) to D (D1, D2)
Maximum Voltage on Output Pins
Maximum Output Current
Input Termination, VT to D (D1, D2), D (D1, D2)
Voltage Reference, VREF
Temperature
Operating Temperature Range, Ambient
Operating Temperature, Junction
Storage Temperature Range
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Rating
6.0 V
Table 3. Thermal Resistance
Package Type
16-Lead LFCSP
VEE − 0.5 V to
VCC + 0.5 V
±40 mA
ESD CAUTION
±1.8 V
VCC + 0.5 V
35 mA
±2 V
VCC − VEE
−40°C to +125°C
150°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 5 of 16
θJA
70
Unit
°C/W
ADCLK905/ADCLK907/ADCLK925
Data Sheet
13 VCC
14 VEE
16 VT
15 VREF
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D 1
12 Q
D 2
ADCLK905
11 Q
NC 3
TOP VIEW
(Not to Scale)
10 NC
9
NC
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. EXPOSED PAD. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CIRCUIT.
IT CAN BE LEFT FLOATING FOR OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE
AND THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE APPLICATION BOARD IF IMPROVED
THERMAL AND/OR MECHANICAL STABILITY IS DESIRED. EXPOSED METAL AT THE CORNERS OF THE PACKAGE
IS CONNECTED TO THIS EXPOSED PAD. ALLOW SUFFICIENT CLEARANCE TO VIAS AND OTHER COMPONENTS.
06318-004
VCC 8
VEE 7
NC 6
NC 5
NC 4
Figure 4. ADCLK905 Pin Configuration
Table 4. Pin Function Descriptions for 1:1 ADCLK905 Buffer
Pin No.
1
2
3, 4, 5, 6,
9, 10
7, 14
8, 13
11
12
15
16
Mnemonic
D
D
NC
Description
Noninverting Input.
Inverting Input.
No Connect. No physical connection to the die.
VEE
VCC
Q
Q
VREF
VT
EPAD
Negative Supply Voltage.
Positive Supply Voltage.
Inverting Output.
Noninverting Output.
Reference Voltage. Reference voltage for biasing ac-coupled inputs.
Center Tap. Center tap of 100 Ω input resistor.
Exposed Pad. The exposed pad is not electrically connected to any part of the circuit. It can be left floating for
optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to
the application board if improved thermal and/or mechanical stability is desired. Exposed metal at the corners
of the package is connected to this exposed pad. Allow sufficient clearance to vias and other components.
Rev. B | Page 6 of 16
13 VCC
14 VEE
16 VT1
ADCLK905/ADCLK907/ADCLK925
15 VREF 1
Data Sheet
D1 1
12 Q1
D1 2
ADCLK907
11 Q1
D2 3
TOP VIEW
(Not to Scale)
10 Q2
9
NOTES
1. EXPOSED PAD. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CIRCUIT.
IT CAN BE LEFT FLOATING FOR OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE
AND THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE APPLICATION BOARD IF IMPROVED
THERMAL AND/OR MECHANICAL STABILITY IS DESIRED. EXPOSED METAL AT THE CORNERS OF THE PACKAGE
IS CONNECTED TO THIS EXPOSED PAD. ALLOW SUFFICIENT CLEARANCE TO VIAS AND OTHER COMPONENTS.
06318-005
VEE 7
Q2
VCC 8
VT2 5
VREF2 6
D2 4
Figure 5. ADCLK907 Pin Configuration
Table 5. Pin Function Descriptions for Dual 1:1 ADCLK907 Buffer
Pin No.
1
2
3
4
5
6
7, 14
8, 13
9
10
11
12
15
16
Mnemonic
D1
D1
D2
D2
VT2
VREF2
VEE
VCC
Q2
Q2
Q1
Q1
VREF1
VT1
EPAD
Description
Noninverting Input 1.
Inverting Input 1.
Noninverting Input 2.
Inverting Input 2.
Center Tap 2. Center tap of 100 Ω input resistor, Channel 2.
Reference Voltage 2. Reference voltage for biasing ac-coupled inputs, Channel 2.
Negative Supply Voltage.
Positive Supply Voltage. Pin 8 and Pin 13 are not strapped internally.
Inverting Output 2.
Noninverting Output 2.
Inverting Output 1.
Noninverting Output 1.
Reference Voltage 1. Reference voltage for biasing ac-coupled inputs, Channel 1.
Center Tap 1. Center tap of 100 Ω input resistor, Channel 1.
Exposed Pad. The exposed pad is not electrically connected to any part of the circuit. It can be left floating for
optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to
the application board if improved thermal and/or mechanical stability is desired. Exposed metal at the corners
of the package is connected to this exposed pad. Allow sufficient clearance to vias and other components.
Rev. B | Page 7 of 16
13 VCC
14 VEE
16 VT
Data Sheet
15 VREF
ADCLK905/ADCLK907/ADCLK925
D 1
12 Q1
D 2
ADCLK925
11 Q1
NC 3
TOP VIEW
(Not to Scale)
10 Q2
9
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. EXPOSED PAD. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CIRCUIT.
IT CAN BE LEFT FLOATING FOR OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE
AND THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE APPLICATION BOARD IF IMPROVED
THERMAL AND/OR MECHANICAL STABILITY IS DESIRED. EXPOSED METAL AT THE CORNERS OF THE PACKAGE
IS CONNECTED TO THIS EXPOSED PAD. ALLOW SUFFICIENT CLEARANCE TO VIAS AND OTHER COMPONENTS.
06318-006
VEE 7
Q2
VCC 8
NC 5
NC 6
NC 4
Figure 6. ADCLK925 Pin Configuration
Table 6. Pin Function Descriptions for 1:2 ADCLK925 Buffer
Pin No.
1
2
3, 4, 5, 6
7, 14
8, 13
9
10
11
12
15
16
Mnemonic
D
D
NC
VEE
VCC
Q2
Q2
Q1
Q1
VREF
VT
EPAD
Description
Noninverting Input.
Inverting Input.
No Connect. No physical connection to the die.
Negative Supply Voltage.
Positive Supply Voltage.
Inverting Output 2.
Noninverting Output 2.
Inverting Output 1.
Noninverting Output 1.
Reference Voltage. Reference voltage for biasing ac-coupled inputs.
Center Tap. Center tap of 100 Ω input resistor.
Exposed Pad. The exposed pad is not electrically connected to any part of the circuit. It can be left floating for
optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to
the application board if improved thermal and/or mechanical stability is desired. Exposed metal at the corners
of the package is connected to this exposed pad. Allow sufficient clearance to vias and other components.
Rev. B | Page 8 of 16
Data Sheet
ADCLK905/ADCLK907/ADCLK925
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0.0 V, TA = 25°C, outputs terminated 50 Ω to VCC − 2 V, unless otherwise noted.
2.37V
Q
Q
1.37V
200ps/DIV
100ps/DIV
Figure 7. Output Waveform, VCC = 3.3 V
Figure 10. Output Waveform, VCC = 3.3 V
–90
–90
AGILENT E5500
CARRIER: 122.88MHz
NO SPURS
–110
–120
–120
L[f] (dBc/Hz)
–110
–130
–140
–130
–140
–150
–150
–160
–160
100
1k
10k
100k
1M
10M
100M
f (Hz)
–170
10
06318-008
–170
10
AGILENT E5500
CARRIER: 622.08MHz
NO SPURS
–100
100
100k
10k
1M
10M
100M
f (Hz)
Figure 11. Phase Noise at 622.08 MHz
Figure 8. Phase Noise at 122.88 MHz
300
–90
–100
1k
06318-011
–100
06318-010
06318-007
Q
1.37V
L[f] (dBc/Hz)
Q
100mV/DIV
100mV/DIV
2.37V
AGILENT E5500
CARRIER: 245.76MHz
NO SPURS
250
RMS JITTER (fs)
–120
–130
–140
200
150
100
–150
50
–170
10
100
1k
10k
100k
1M
f (Hz)
10M
100M
0
0
1
2
3
4
5
6
INPUT SLEW RATE (V/ns)
Figure 12. RMS Jitter vs. Input Slew Rate
Figure 9. Phase Noise at 245.76 MHz
Rev. B | Page 9 of 16
7
8
06318-012
–160
06318-009
L[f] (dBc/Hz)
–110
ADCLK905/ADCLK907/ADCLK925
Data Sheet
1.1
0.09
+125°C
0.8
0.7
+25°C
0.6
–55°C
0.5
+25°C
0.07
–55°C
0.06
0.05
0.04
0.03
+125°C
0.02
0.01
0.4
1
2
3
4
SUPPLY VOLTAGE (V)
+25°C
–55°C
0
0
1
2
3
4
SUPPLY VOLTAGE (V)
Figure 13. VOD vs. Power Supply Voltage
06318-016
POWER SUPPLY CURRENT (A)
0.9
06318-013
Figure 16. Power Supply Current vs. Supply Voltage, ADCLK925
0.07
100
0.06
99
+125°C
0.05
98
+25°C
0.03
tPD (ps)
–55°C
0.04
97
+125°C
96
–55°C
0
2.5
3.0
3.5
4.0
POWER SUPPLY VOLTAGE (V)
94
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
06318-017
95
06318-018
0.01
+25°C
06318-014
0.02
11.5
OUTPUT SWING (V)
1.0
POWER SUPPLY CURRENT (A)
+125°C
0.08
VID (V)
Figure 14. Power Supply Current vs. Power Supply Voltage, ADCLK905
Figure 17. Propagation Delay vs. VID
110
1.8
1.4
105
1.2
VOD (V)
+125°C
100
1.0
0.8
+25°C
0.6
95
0.4
–55°C
12.5
9.5
8.5
7.5
6.5
5.5
10.5
INPUT COMMON MODE (V)
Figure 15. Propagation Delay vs. VICM; Input Swing = 200 mV
0
4.5
3.6
3.5
3.1
2.5
2.6
1.5
2.1
0.5
0.2
90
1.6
06318-015
PROPAGATION DELAY (ps)
1.6
FREQUENCY (GHz)
Figure 18. Toggle Rate, Differential Output Swing vs. Frequency
Rev. B | Page 10 of 16
Data Sheet
ADCLK905/ADCLK907/ADCLK925
1
1
C4
C4
2
2
06318-023
3
06318-019
17ps/DIV
58ps/DIV
3
Figure 19. 2.488 Gbps PRBS 223 − 1 with OC-48/STM-16 Mask,
Measured p-p Jitter 8.1 ps, Source p-p Jitter 3.5 ps
Figure 22. 8.50 Gbps PRBS 223 − 1 with FC8500E ABS Beta Rx Mask,
Measured p-p Jitter 10.9 ps, Source p-p Jitter 4.4 ps
1
1
C4
C4
2
3
58ps/DIV
06318-022
15ps/DIV
3
Figure 20. 9.95 Gbps PRBS 223 − 1 with OC-193/STM-64 Mask,
Measured p-p Jitter 10.5 ps, Source p-p Jitter 6.0 ps
06318-021
2
Figure 23. 2.5 Gbps PRBS 223 − 1 with PCI Express 2.5 Rx Mask,
Measured p-p Jitter 8.1 ps, Source p-p Jitter 3.5 ps
1
1
C4
C4
3
29ps/DIV
06318-020
34ps/DIV
3
Figure 21. 4.25 Gbps PRBS 223 − 1 with FC4250 (Optical) Mask,
Measured p-p Jitter 8.2 ps, Source p-p Jitter 3.4 ps
06318-024
2
2
Figure 24. 5.0 Gbps PRBS 223 − 1 with PCI Express 5.0 Rx Mask,
Measured p-p Jitter 8.7 ps, Source p-p Jitter 3.5 ps
Rev. B | Page 11 of 16
ADCLK905/ADCLK907/ADCLK925
Data Sheet
APPLICATIONS INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
OPTIMIZING HIGH SPEED PERFORMANCE
The ADCLK905/ADCLK907/ADCLK925 buffers are designed
for very high speed applications. Consequently, high speed design
techniques must be used to achieve the specified performance.
It is critically important to use low impedance supply planes for
both the negative supply (VEE) and the positive supply (VCC) planes
as part of a multilayer board. Providing the lowest inductance
return path for switching currents ensures the best possible
performance in the target application.
As with any high speed circuit, proper design and layout
techniques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and cause oscillation. Discontinuities along input and output
transmission lines can also severely limit the specified jitter
performance by reducing the effective input slew rate.
It is also important to adequately bypass the input and output
supplies. A 1 µF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.001 µF bypass capacitors
should be placed as close as possible to each of the VEE and VCC
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should be strictly avoided to maximize the
effectiveness of the bypass at high frequencies.
OUTPUT STAGES
The specified performance can be achieved only by using proper
transmission line terminations. The outputs of the ADCLK905/
ADCLK907/ADCLK925 buffers are designed to directly drive
800 mV into 50 Ω cable or microstrip/stripline transmission
lines terminated with 50 Ω referenced to VCC − 2 V. The PECL
output stage is shown in Figure 25. The outputs are designed for
best transmission line matching. If high speed signals must be
routed more than a centimeter, either the microstrip or the
stripline technique is required to ensure proper transition times
and to prevent excessive output ringing and pulse widthdependent propagation delay dispersion.
VCC
In a 50 Ω environment, input and output matching have a
significant impact on performance. The buffer provides internal
50 Ω termination resistors for both D and D inputs. The return
side should normally be connected to the reference pin provided.
The termination potential should be carefully bypassed, using
ceramic capacitors to prevent undesired aberrations on the
input signal due to parasitic inductance in the termination
return path. If the inputs are directly coupled to a source, care
must be taken to ensure the pins are within the rated input
differential and common-mode ranges.
If the return is floated, the device exhibits 100 Ω cross termination,
but the source must then control the common-mode voltage
and supply the input bias currents.
There are ESD/clamp diodes between the input pins to prevent
the application of excessive offsets to the input transistors. ESD
diodes are not optimized for best ac performance. When a
clamp is desired, it is recommended that appropriate external
diodes be used.
BUFFER RANDOM JITTER
The ADCLK905/ADCLK907/ADCLK925 are specifically
designed to minimize added random jitter over a wide input
slew rate range. Provided sufficient voltage swing is present,
random jitter is affected most by the slew rate of the input signal.
Whenever possible, excessively large input signals should be
clamped with fast Schottky diodes because attenuators reduce the
slew rate. Input signal runs of more than a few centimeters
should be over low loss dielectrics or cables with good high
frequency characteristics.
Q
VEE
06318-025
Q
Figure 25. Simplified Schematic Diagram of
the ADCLK905/ADCLK907/ADCLK925 PECL Output Stage
Rev. B | Page 12 of 16
Data Sheet
ADCLK905/ADCLK907/ADCLK925
TYPICAL APPLICATION CIRCUITS
VCC
VREF
VREF
VT
D
D
D
D
CONNECT VT TO VREF .
NOTES
1. PLACING A BYPASS CAPACITOR
FROM VT TO GROUND CAN IMPROVE
THE NOISE PERFORMANCE.
Figure 26. Interfacing to CML Inputs
06318-029
CONNECT VT TO VCC.
06318-026
VT
Figure 28. AC Coupling Differential Signals
VREF
VREF
VT
VT
D
D
D
D
CONNECT VT, VREF , AND D. PLACE A BYPASS
CAPACITOR FROM VT TO GROUND.
ALTERNATIVELY, VT, VREF , AND D CAN BE
CONNECTED, GIVING A CLEANER LAYOUT AND
A 180º PHASE SHIFT.
06318-030
CONNECT VT TO VCC − 2V.
06318-028
VCC – 2V
Figure 29. Interfacing to AC-Coupled Single-Ended Inputs
Figure 27. Interfacing to PECL
Rev. B | Page 13 of 16
C27
1
1
RED
TP3
2.2UF
BLK
VEE
C24
TP4
.1UF
VEE
J10
.1UF
C22
C23
Solder bridges will be completed
by end user if desired.
.1UF
J7
C21
D2_B
D2
CAL_2
C17
C19
1 D1
4 D2
3 D2
2 D1
LFCSP16-3X3
ADCLK9XX
matched length ×2
C25
J1
2.2UF
0Ω resistors are NOT to be installed.
.1UF
D1_B
C1
D1
.1UF
J2
.1UF
.1UF
C11
C12
VT1
R1
16
VT 1
5 VT2
R2
VT2
C15
VREF1
15
0
VREF1
.1UF
7
VREF2
6
C2
.1UF
C9
C10
.1UF
C14
0
VREF2
C26
.1UF
.1UF
VEE
14
VEE_14
VCC
13
VCC_13
VEE_7
VEE
.1UF
.1UF
VCC
Q1
Q1_B
.01UF
VEE
VCC
C16
.1UF
Q2_B
Q2
matched lengths
PAD
VAL
C45
PAD
Q2 9
Q2 10
Q1 11
Q1 12
A1
C4
J8
C5
Solder bridges will be completed
by end user if desired.
.1UF
8
VCC
C44
C6
C13
.1UF
C3
.01UF
.1UF
0Ω resistors are NOT to be installed.
C7
matched length ×2
.1UF
VCC_8
.1UF
RED
TP2
J9
J4
1
C8
TP1
BLK
J3
J5
Solder bridges will be completed
by end user if desired.
Jumpers are NOT to be installed.
J6
J12
VT2
1
1
1
1
0
0
0
0
VREF2
C39
VT1
C40
JP4
JP3
JP2
JP1
2
2
2
2
VREF2
VT2
C28
C32
CAL_1
.1UF
C38
C41
.1UF
J11
1
Figure 30. Evaluation Board Schematic
.1UF
.1UF
.1UF
C29
C33
.1UF
VREF2
.1UF
.1UF
.1UF
C18
.1UF
C20
VREF1
VT1
VT2
C37
VT1
C42
C30
C34
.1UF
.1UF
.1UF
.1UF
1
1
1
1
.1UF
.1UF
0
0
0
0
JP5
JP6
JP7
JP8
.1UF
2
2
2
2
RED
TP8
RED
TP5
1
C36
C43
.1UF
VREF1
RED
TP7
RED
TP6
.1UF
.1UF
1
1
C31
1
C35
Rev. B | Page 14 of 16
.1UF
VREF1
ADCLK905/ADCLK907/ADCLK925
Data Sheet
EVALUATION BOARD SCHEMATIC
06318-031
Data Sheet
ADCLK905/ADCLK907/ADCLK925
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.30
0.25
0.20
0.50
BSC
PIN 1
INDICATOR
16
13
1
12
1.65
1.50 SQ
1.45
EXPOSED
PAD
9
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
4
8
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
01-26-2012-A
3.10
3.00 SQ
2.90
Figure 31. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-27)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADCLK905BCPZ-WP
ADCLK905BCPZ-R7
ADCLK905BCPZ-R2
ADCLK907BCPZ-WP
ADCLK907BCPZ-R7
ADCLK907BCPZ-R2
ADCLK925BCPZ-WP
ADCLK925BCPZ-R7
ADCLK925BCPZ-R2
ADCLK905/PCBZ
ADCLK907/PCBZ
ADCLK925/PCBZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
Rev. B | Page 15 of 16
Package Option
CP-16-27
CP-16-27
CP-16-27
CP-16-27
CP-16-27
CP-16-27
CP-16-27
CP-16-27
CP-16-27
Branding
Y03
Y03
Y03
Y06
Y06
Y06
Y08
Y08
Y08
ADCLK905/ADCLK907/ADCLK925
Data Sheet
NOTES
©2007–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06318-0-2/17(B)
Rev. B | Page 16 of 16
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