ADCMP567BCPZ

Dual Ultrafast Voltage Comparator ADCMP567 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM 250 ps propagation delay input to output 50 ps propagation delay dispersion Differential PECL compatible outputs Differential latch control Robust input protection Input common-mode range −2.0 V to +3.0 V Input differential range ±5 V ESD protection >3 kV HBM, >200 V MM Power supply sensitivity >65 dB 200 ps minimum pulse width 5 GHz equivalent input rise time bandwidth Typical output rise/fall of 165 ps NONINVERTING INPUT INVERTING INPUT Q OUTPUT ADCMP567 Q OUTPUT LATCH ENABLE INPUT LATCH ENABLE INPUT 03632-0-001 Figure 1. APPLICATIONS High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers and signal restoration Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero-crossing detectors Clock drivers Automatic test equipment GENERAL DESCRIPTION The ADCMP567 is an ultrafast voltage comparator fabricated on Analog Devices, Inc., proprietary XFCB process. The device features 250 ps propagation delay with less than 35 ps overdrive dispersion. Overdrive dispersion, a particularly important characteristic of high speed comparators, is a measure of the difference in propagation delay under differing overdrive conditions. A fast, high precision differential input stage permits consistent propagation delay with a wide variety of signals in the commonmode range from −2.0 V to +3.0 V. Outputs are complementary digital signals fully compatible with PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Ω to VDD − 2 V. A latch input is included, which permits tracking, track-andhold, or sample-and-hold modes of operation. The ADCMP567 is available in a 32-lead LFCSP package. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADCMP567 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Timing Information ..........................................................................8  Applications ...................................................................................... 1  Applications Information ................................................................9  Functional Block Diagram .............................................................. 1  Clock Timing Recovery ................................................................9  General Description ......................................................................... 1  Optimizing High Speed Performance ........................................9  Revision History ............................................................................... 2  Comparator Propagation Delay Dispersion..............................9  Specifications .................................................................................... 3  Comparator Hysteresis .............................................................. 10  Electrical Characteristics ............................................................. 3  Minimum Input Slew Rate Requirement ............................... 10  Absolute Maximum Ratings ........................................................... 5  Typical Application Circuits ......................................................... 11  Thermal Considerations.............................................................. 5  Typical Performance Characteristics .......................................... 12  ESD Caution.................................................................................. 5  Outline Dimensions ....................................................................... 14  Pin Configuration and Function Descriptions ............................ 6  Ordering Guide .......................................................................... 14  REVISION HISTORY 12/2020—Rev. A to Rev. B Changed CP-32-8 to CP-32-7 ...................................... Throughout Changes to Figure 2.......................................................................... 6 Updated Outline Dimensions ....................................................... 14 Change to Ordering Guide............................................................ 14 1/2015—Rev. 0 to Rev. A Changes to Figure 2 and Table 3 .................................................... 6 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 10/2003—Revision 0: Initial Version Rev. B | Page 2 of 14 Data Sheet ADCMP567 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCC = +5.0 V, VEE = −5.2 V, VDD = +3.3 V, TA = 25°C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS1 Input Common-Mode Range Input Differential Voltage Input Offset Voltage Input Offset Voltage Channel Matching Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Capacitance Input Resistance, Differential Mode Input Resistance, Common-Mode Open Loop Gain Common-Mode Rejection Ratio Hysteresis LATCH ENABLE CHARACTERISTICS Latch Enable Common-Mode Range Latch Enable Differential Input Voltage Input High Current Input Low Current Latch Setup Time Latch to Output Delay Latch Pulse Width Latch Hold Time OUTPUT CHARACTERISTICS Output Voltage—High Level Output Voltage—Low Level Rise Time Fall Time AC PERFORMANCE Propagation Delay Propagation Delay Propagation Delay Tempco Prop Delay Skew—Rising Transition to Falling Transition Within Device Propagation Delay Skew— Channel to Channel Propagation Delay Dispersion vs. Duty Cycle Propagation Delay Dispersion vs. Overdrive Propagation Delay Dispersion vs. Overdrive Propagation Delay Dispersion vs. Slew Rate Propagation Delay Dispersion vs. Common-Mode Voltage Symbol Condition VCM Min VOS −2.0 −5 −5.0 DVOS/dT IBC −10 −8.0 CIN CMRR VCM = −2.0 V to +3.0 V VLCM VLD tS tPLOH, tPLOL tPL tH at 0.0 V at −2.0 V 250 mV overdrive 250 mV overdrive 250 mV overdrive 250 mV overdrive VOH VOL tR tF PECL 50 Ω to −2.0 V PECL 50 Ω to −2.0 V 20% to 80% 20% to 80% tPD tPD 1 V overdrive 20 mV overdrive 50 mV to 1.5 V 20 mV to 1.5 V 0 V to 1 V swing, 20% to 80%, 50 ps and 600 ps 1 V swing, −1.5 V to 2.5 VCM Rev. B | Page 3 of 14 VDD − 2.0 0.4 −12 −12 Typ ±1.0 ±1.0 10.0 +24 10.0 ±0.5 0.75 100 600 60 69 ±1.0 Max Unit +3.0 +5 +5.0 V V mV mV μV/°C μA nA/°C μA pF kΩ kΩ dB dB mV +42 +8.0 VDD 2.0 +12 +12 V V μA μA ps ps ps ps VDD − 0.81 VDD − 1.54 175 140 V V ps ps 250 300 0.5 ±10 ps ps ps/°C ps ±10 ps ±10 ps 35 50 50 ps ps ps 5 ps +6 +6 50 300 150 90 VDD − 1.1 VDD − 1.95 ADCMP567 Parameter AC PERFORMANCE (continued) Equivalent Input Rise Time Bandwidth Toggle Rate Minimum Pulse Width Unit to Unit Propagation Delay Skew POWER SUPPLY Positive Supply Current 1 Data Sheet Symbol Condition Min Typ BW 0 V to 1 V swing, 20% to 80%, 50 ps tR, tF >50% output swing tPD from 10 ns to 200 ps < ±25 ps 3500 5000 MHz 5 200 Gbps ps ±10 ps PW Max Unit IVCC at +5.0 V 7 13 20 mA Negative Supply Current IVEE at −5.2 V 60 78 95 mA Logic Supply Current IVDD at 3.3 V, without load 8 13 18 mA Logic Supply Current IVDD at 3.3 V, with load 50 65 80 mA Positive Supply Voltage Negative Supply Voltage Logic Supply Voltage Power Dissipation Power Dissipation Power Supply Sensitivity—VCC VCC VEE VDD Dual Dual Dual Dual, without load Dual, with load 4.75 −4.96 2.5 415 5.25 −5.45 5.0 615 675 PSSVCC 5.0 −5.2 3.3 515 575 69 V V V mW mW dB Power Supply Sensitivity—VEE PSSVEE 85 dB Power Supply Sensitivity—VDD PSSVDD 70 dB Under no circumstances should the input voltages exceed the supply voltages. Rev. B | Page 4 of 14 Data Sheet ADCMP567 ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS Table 2. Parameter Supply Voltages Positive Supply Voltage (VCC to GND) Negative Supply Voltage (VEE to GND) Logic Supply Voltage (VDD to GND) Ground Voltage Differential Input Voltages Input Common-Mode Voltage Differential Input Voltage Input Voltage, Latch Controls Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range The ADCMP567 LFCSP 32-lead package option has a θJA (junction-to-ambient thermal resistance) of 27.2°C/W in still air. Rating −0.5 V to +6.0 V −6.0 V to +0.5 V −0.5 V to +6.0 V −0.5 V to +0.5 V ESD CAUTION −3.0 V to +4.0 V −7.0 V to +7.0 V −0.5 V to +5.5 V 30 mA −40°C to +85°C 125°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 5 of 14 ADCMP567 Data Sheet 32 31 30 29 28 27 26 25 GND LEA LEA NC VDD QA QA VDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADCMP567 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 VEE NC VEE VCC VCC VEE NC VEE NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE RECOMMENDED CONNECTION FOR THE EXPOSED PAD IS GROUND. 03632-002 GND LEB LEB NC VDD QB QB VDD 9 10 11 12 13 14 15 16 GND –INA +INA VCC VCC +INB –INB GND Figure 2. ADCMP567 Pin Configuration Table 3. ADCMP567 Pin Function Descriptions Pin No. 1 2 Mnemonic GND −INA 3 +INA 4 5 6 VCC VCC +INB 7 −INB 8 9 10 GND GND LEB 11 LEB 12 13 14 NC VDD QB 15 QB 16 17 18 19 20 21 22 23 VDD VEE NC VEE VCC VCC VEE NC Function Analog Ground. Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven in conjunction with the noninverting A input. Noninverting analog input of the differential input stage for Channel A. The noninverting A input must be driven in conjunction with the inverting A input. Positive Supply Terminal. Positive Supply Terminal. Noninverting analog input of the differential input stage for Channel B. The noninverting B input must be driven in conjunction with the inverting B input. Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven in conjunction with the noninverting B input. Analog Ground. Analog Ground. One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the output will track changes at the input of the comparator. In the latch mode (logic high), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven in conjunction with LEB. One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the output will track changes at the input of the comparator. In the latch mode (logic low), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven in conjunction with LEB. No Connect. Do not connect to this pin. Logic Supply Terminal. One of two complementary outputs for Channel B. QB will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEB description (Pin 11) for more information. One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEB description (Pin 11) for more information. Logic Supply Terminal. Negative Supply Terminal. No Connect. Do not connect to this pin. Negative Supply Terminal. Positive Supply Terminal. Positive Supply Terminal. Negative Supply Terminal. No Connect. Do not connect to this pin. Rev. B | Page 6 of 14 Data Sheet Pin No. 24 25 26 Mnemonic VEE VDD QA 27 QA 28 29 30 VDD NC LEA 31 LEA 32 GND EPAD ADCMP567 Function Negative Supply Terminal. Logic Supply Terminal. One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEA description (Pin 30) for more information. One of two complementary outputs for Channel A. QA will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEA description (Pin 30) for more information. Logic Supply Terminal. No Connect. Do not connect to this pin. One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the output will track changes at the input of the comparator. In the latch mode (logic low), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the output will track changes at the input of the comparator. In the latch mode (logic high), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. Analog Ground. Exposed Pad. The recommended connection for the exposed pad is ground. Rev. B | Page 7 of 14 ADCMP567 Data Sheet TIMING INFORMATION LATCH ENABLE 50% LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VIN VREF ± VOS VOD tPDL tPLOH Q OUTPUT 50% tF tPDH 50% Q OUTPUT tPLOL tR 03633-0-003 Figure 3. System Timing Diagram The timing diagram in Figure 3 shows the ADCMP567 compare and latch features. Table 4 describes the terms in the diagram. Table 4. Timing Descriptions Symbol tPDH tPDL tPLOH tPLOL tH Timing Input to output high delay Input to output low delay Latch enable to output high delay Latch enable to output low delay Minimum hold time tS Minimum latch enable pulse width Minimum setup time tR Output rise time tF Output fall time VOD Voltage overdrive tPL Description Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to the 50% point of an output low-to-high transition Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to the 50% point of an output high-to-low transition Minimum time after the negative transition of the Latch Enable signal that the input signal must remain unchanged to be acquired and held at the outputs Minimum time that the Latch Enable signal must be high to acquire an input signal change Minimum time before the negative transition of the Latch Enable signal that an input signal change must be present to be acquired and held at the outputs Amount of time required to transition from a low to a high output as measured at the 20% and 80% points Amount of time required to transition from a high to a low output as measured at the 20% and 80% points Difference between the differential input and reference input voltages Rev. B | Page 8 of 14 Data Sheet ADCMP567 APPLICATIONS INFORMATION The ADCMP567 comparators are very high speed devices. Consequently, high speed design techniques must be employed to achieve the best performance. The most critical aspect of any ADCMP567 design is the use of a low impedance ground plane. A ground plane, as part of a multilayer board, is recommended for proper high speed performance. Using a continuous conductive plane over the surface of the circuit board can create this, allowing breaks in the plane only for necessary signal paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board. It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 μF electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors will reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close as possible from the power supply pins on the ADCMP567 to ground. These capacitors act as a charge reservoir for the device during high frequency switching. The LATCH ENABLE input is active low (latched). If the latching function is not used, the LATCH ENABLE input should be attached to VDD (VDD is a PECL logic high), and the complementary input, LATCH ENABLE, should be tied to VDD − 2.0 V. This will disable the latching function. Occasionally, one of the two comparator stages within the ADCMP567 will not be used. The inputs of the unused comparator should not be allowed to float. The high internal gain may cause the output to oscillate (possibly affecting the comparator that is being used) unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also appropriately connecting the LATCH ENABLE and LATCH ENABLE inputs as described above. The best performance is achieved with the use of proper PECL terminations. The open emitter outputs of the ADCMP567 are designed to be terminated through 50 Ω resistors to VDD −2.0 V, or any other equivalent PECL termination. If high speed PECL signals must be routed more than a centimeter, microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing. CLOCK TIMING RECOVERY Comparators are often used in digital systems to recover clock timing signals. High speed square waves transmitted over a distance, even tens of centimeters, can become distorted due to stray capacitance and inductance. Poor layout or improper termination can also cause reflections on the transmission line, further distorting the signal waveform. A high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay. OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator amplifier, proper design and layout techniques should be used to ensure optimal performance from the ADCMP567. The performance limits of high speed circuitry can easily be a result of stray capacitance, improper ground impedance, or other layout issues. Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the ADCMP567. Source resistance in combination with equivalent input capacitance could cause a lagged response at the input, thus delaying the output. The input capacitance of the ADCMP567 in combination with stray capacitance from an input pin to ground could result in several picofarads of equivalent capacitance. A combination of 3 kΩ source resistance and 5 pF of input capacitance yields a time constant of 15 ns, which is significantly slower than the sub 500 ps capability of the ADCMP567. Source impedances should be significantly less than 100 Ω for best performance. Sockets should be avoided due to stray capacitance and inductance. If proper high speed techniques are used, the ADCMP567 should be free from oscillation when the comparator input signal passes through the switching threshold. COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP567 has been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mV to 1 V. Propagation delay overdrive dispersion is the change in propagation delay that results from a change in the degree of overdrive (how far the switching point is exceeded by the input). The overall result is a higher degree of timing accuracy since the ADCMP567 is far less sensitive to input variations than most comparator designs. Propagation delay dispersion is a specification that is important in critical timing applications such as ATE, bench instruments, and nuclear instrumentation. Overdrive dispersion is defined Rev. B | Page 9 of 14 ADCMP567 Data Sheet +VH 2 –VH 2 as the variation in propagation delay as the input overdrive conditions are changed (see Figure 4). For the ADCMP567, overdrive dispersion is typically 35 ps as the overdrive is changed from 100 mV to 1 V. This specification applies for both positive and negative overdrive since the ADCMP567 has equal delays for positive and negative going inputs. 0V INPUT 1 The 35 ps propagation delay overdrive dispersion of the ADCMP567 offers considerable improvement of the 100 ps dispersion of other similar series comparators. 1.5V OVERDRIVE 0 INPUT VOLTAGE OUTPUT 20mV OVERDRIVE VREF ± VOS 03633-0-005 Figure 5. Comparator Hysteresis Transfer Function 60 DISPERSION 50 Q OUTPUT The addition of hysteresis to a comparator is often useful in a noisy environment or where it is not desirable for the comparator to toggle between states when the input signal is at the switching threshold. The transfer function for a comparator with hysteresis is shown in Figure 5. If the input voltage approaches the threshold from the negative direction, the comparator will switch from a 0 to a 1 when the input crosses +VH/2. The new switching threshold becomes −VH/2. The comparator will remain in a 1 state until the threshold −VH/2 is crossed coming from the positive direction. In this manner, noise centered on 0 V input will not cause the comparator to switch states unless it exceeds the region bounded by ±VH/2. Positive feedback from the output to the input is often used to produce hysteresis in a comparator (see Figure 9). The major problem with this approach is that the amount of hysteresis varies with the output logic levels, resulting in a hysteresis that is not symmetrical around zero. Another method to implement hysteresis is generated by introducing a differential voltage between LATCH ENABLE and LATCH ENABLE inputs (see Figure 10). Hysteresis generated in this manner is independent of output swing and is symmetrical around zero. The variation of hysteresis with input voltage is shown in Figure 6. 40 30 20 10 0 –25 –20 –15 –10 –5  LATCH = LE – LEB (mV) 0 5 03632-0-006 COMPARATOR HYSTERESIS HYSTERESIS (mV) 03633-0-004 Figure 4. Propagation Delay Dispersion Figure 6. Comparator Hysteresis Transfer Function Using Latch Enable Input MINIMUM INPUT SLEW RATE REQUIREMENT As for all high speed comparators, a minimum slew rate must be met to ensure that the device does not oscillate when the input crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator and the parasitics of the package. Analog Devices recommends a slew rate of 5 V/μs or faster to ensure a clean output transition. If slew rates less than 5 V/μs are used, then hysteresis should be added to reduce the oscillation. Rev. B | Page 10 of 14 Data Sheet ADCMP567 TYPICAL APPLICATION CIRCUITS VIN VIN ADCMP567 ADCMP567 OUTPUTS OUTPUTS VREF LATCH ENABLE INPUTS VDD – 2V HYSTERESIS VOLTAGE VDD – 2V 450 ALL RESISTORS 50 ALL RESISTORS 50 UNLESS OTHERWISE NOTED 03632-0-007 03632-0-010 Figure 10. Hysteresis Using Latch Enable Input Figure 7. High Speed Sampling Circuits +VREF ADCMP567 VIN OUTPUTS VIN ADCMP567 100 50 50 50 50 100 ADCMP567 –VREF (VDD – 2)  2 03632-0-011 LATCH ENABLE INPUTS VDD – 2V ALL RESISTORS 50 03632-0-008 Figure 11. How to Interface a PECL Output to an Instrument with a 50 Ω to Ground Input Figure 8. High Speed Window Comparator VIN VREF ADCMP567 R1 OUTPUTS R2 VDD – 2V ALL RESISTORS 50 03632-0-009 Figure 9. Hysteresis Using Positive Feedback Rev. B | Page 11 of 14 ADCMP567 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VCC = +5.0 V, VEE = −5.2 V, VDD = +3.3 V, TA = 25°C, unless otherwise noted. 23.0 30 22.9 +IN INPUT BIAS CURRENT (A) (+IN = 1V, –IN = 0V) INPUT BIAS CURRENT (A) 25 20 15 10 5 22.8 22.7 22.6 22.5 22.4 22.3 22.2 03632-0-013 22.0 –40 –20 0 20 40 TEMPERATURE (°C) 60 03632-0-016 22.1 0 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0.5V) 80 Figure 15. Input Bias Current vs. Temperature Figure 12. Input Bias Current vs. Input Voltage 60 2.0 1.8 50 1.4 HYSTERESIS (mV) OFFSET VOLTAGE (mV) 1.6 1.2 1.0 0.8 40 30 20 0.6 10 0.4 20 40 TEMPERATURE (°C) 60 80 0 –25 185 185 175 175 TIME (ps) 195 165 155 135 135 60 70 5 90 155 145 10 20 30 40 50 TEMPERATURE (°C) 0 165 145 80 90 03632-0-015 TIME (ps) 195 0 –15 –10 5  LATCH = LE – LEB (mV) Figure 16. Hysteresis vs. ∆Latch Figure 13. Input Offset Voltage vs. Temperature 125 –40 –30 –20 –10 –20 03632-0-017 0 –20 03632-0-014 0 –40 03632-0-018 0.2 125 –40 –30 –20 –10 0 10 20 30 40 50 TEMPERATURE (°C) 60 Figure 17. Fall Time vs. Temperature Figure 14. Rise Time vs. Temperature Rev. B | Page 12 of 14 70 80 ADCMP567 240 236 238 235 236 PROPAGATION DELAY (ps) 234 232 230 228 10 20 30 40 50 TEMPERATURE (°C) 60 70 80 90 231 229 –2 Figure 18. Propagation Delay vs. Temperature –1 0 1 2 INPUT COMMON-MODE VOLTAGE (V) 3 Figure 21. Propagation Delay vs. Common-Mode Voltage 60 0 –5 PROPAGATION DELAY ERROR (ps) 50 40 30 20 10 0 0.2 0.4 0.6 0.8 1.0 1.2 OVERDRIVE VOLTAGE (V) 1.4 1.6 03632-0-020 PROPAGATION DELAY ERROR (ps) 232 03632-0-022 0 03632-0-019 224 –40 –30 –20 –10 Figure 19. Propagation Delay Error vs. Overdrive Voltage 2.3 2.1 1.9 1.7 1.1 1.2 1.3 1.4 1.5 1.6 TIME (ns) 1.7 1.8 1.9 2.0 03632-0-021 1.5 1.3 1.0 –10 –15 –20 –25 –30 –35 –40 0.15 2.15 4.15 6.15 PULSEWIDTH (ns) 8.15 Figure 22. Propagation Delay Error vs. Pulse Width 2.5 OUTPUT RISE AND FALL (V) 233 230 226 0 234 Figure 20. Rise and Fall of Outputs vs. Time Rev. B | Page 13 of 14 03632-0-023 PROPAGATION DELAY (ps) Data Sheet ADCMP567 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 25 P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 32 24 1 0.50 BSC 3.25 3.10 SQ 2.95 EXPOSED PAD 17 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-003898 SEATING PLANE 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 8 9 16 BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD 09-12-2018-A PIN 1 INDICATOR AREA 5.10 5.00 SQ 4.90 Figure 23. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model1 ADCMP567BCPZ 1 Temperature Range −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP] Z = RoHS Compliant Part ©2003–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03632-12/20(B) Rev. B | Page 14 of 14 Package Option CP-32-7