ADCMP573BCPZ-RL7

Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators ADCMP572/ADCMP573 Data Sheet FUNCTIONAL BLOCK DIAGRAM 3.3 V/5.2 V single-supply operation 150 ps propagation delay 15 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 80 ps minimum pulse width 35 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ) On-chip terminations at both input pins Robust inputs with no output phase reversal Resistor-programmable hysteresis Differential latch control Extended industrial −40°C to +125°C temperature range VCCI VCCO VTP TERMINATION VP NONINVERTING INPUT VN INVERTING INPUT Q OUTPUT ADCMP572 ADCMP573 CML/ RSPECL Q OUTPUT VTN TERMINATION LE INPUT HYS LE INPUT 04409-025 FEATURES Figure 1. APPLICATIONS Clock and data signal restoration and level shifting Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry GENERAL DESCRIPTION The ADCMP572 and ADCMP573 are ultrafast comparators fabricated on Analog Devices, Inc., proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP572 features CML output drivers and latch inputs, and the ADCMP573 features reduced swing PECL (RSPECL) output drivers and latch inputs. Both devices offer 150 ps propagation delay and 80 ps minimum pulse width for 10 Gbps operation with 200 fs rms random jitter (RJ). Overdrive and slew rate dispersion are typically less than 15 ps. A flexible power supply scheme allows both devices to operate with a single 3.3 V positive supply and a −0.2 V to +1.2 V input signal range or with split input/output supplies to support a wider −0.2 V to +3.2 V input signal range and an independent range of output levels. 50 Ω on-chip termination resistors are Rev. B provided at both inputs with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance inputs. The CML output stage is designed to directly drive 400 mV into 50 Ω transmission lines terminated to between 3.3 V to 5.2 V. The RSPECL output stage is designed to drive 400 mV into 50 Ω terminated to VCCO − 2 V and is compatible with several commonly used PECL logic families. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided. The ADCMP572 and ADCMP573 are available in a 16-lead LFCSP package and have been characterized over an extended industrial temperature range of −40°C to +125°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADCMP572/ADCMP573 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power/Ground Layout and Bypassing ........................................9 Applications ....................................................................................... 1 CML/RSPECL Output Stage ........................................................9 Functional Block Diagram .............................................................. 1 Using/Disabling the Latch Feature..............................................9 General Description ......................................................................... 1 Optimizing High Speed Performance ..................................... 10 Revision History ............................................................................... 2 Comparator Propagation Delay Dispersion ........................... 10 Electrical Characteristics ................................................................. 3 Comparator Hysteresis .............................................................. 11 Absolute Maximum Ratings............................................................ 5 Minimum Input Slew Rate Requirements .............................. 11 Thermal Considerations .............................................................. 5 Typical Application Circuits ......................................................... 12 ESD Caution .................................................................................. 5 Timing Information ....................................................................... 13 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 14 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 14 Applications Information ................................................................ 9 REVISION HISTORY 3/15—Rev. A to Rev. B Changes to Figure 2 and Table 3 ..................................................... 6 Changes to Figure 23 ...................................................................... 12 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 4/09—Rev. 0 to Rev. A Changes to Figure 26 ...................................................................... 12 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 4/05—Revision 0: Initial Version Rev. B | Page 2 of 14 Data Sheet ADCMP572/ADCMP573 ELECTRICAL CHARACTERISTICS VCCI = VCCO = 3.3 V, TA = −40°C to +125°C, typical at TA = +25°C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Input Voltage Range Input Differential Voltage Input Offset Voltage Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Impedance Input Resistance, Differential Input Resistance, Common-Mode Active Gain Common-Mode Rejection Power Supply Rejection—VCCI Hysteresis LATCH ENABLE CHARACTERISTICS ADCMP572 Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time ADCMP573 Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time Latch Enable Input Impedance Latch to Output Delay Latch Minimum Pulse Width DC OUTPUT CHARACTERISTICS ADCMP572 (CML) Output Impedance Output Voltage High Level Output Voltage Low Level Output Voltage Differential ADCMP573 (RSPECL) Output Voltage High −40°C Output Voltage High +25°C Output Voltage High +125°C Output Voltage Low −40°C Output Voltage Low +25°C Output Voltage Low +125°C Output Voltage Differential Symbol Conditions Min VP, VN VCCI = 3.3 V, VCCO = 3.3 V VCCI = 5.2 V, VCCO = 3.3 V −0.2 −0.2 −1.2 −5.0 VOS ∆VOS/dT IP, IN Open termination −50.0 Open termination Open termination AV CMRR PSRVCCI VCCI = 3.3 V, VCCO = 3.3 V, VCM = 0.0 V to 1.0 V VCCI = 5.2 V, VCCO = 3.3 V, VCM = 0.0 V to 3.0 V VCCI = 3.3 V ± 5%, VCCO = 3.3 V RHYS = ∞ 2.8 0.2 tS tH VOD = 100 mV VOD = 100 mV 1.8 0.2 Typ ±2.0 10.0 −25.0 50.0 ±2.0 50 50 500 54 65 Max Unit +1.2 +3.1 +1.2 +5.0 V V V mV μV/°C μA nA/°C μA Ω kΩ kΩ dB dB 0.0 65 dB 74 ±1 dB mV 0.4 15 5 0.4 90 100 50.0 150 100 VCCO + 0.2 0.5 V V ps ps VCCO − 0.6 0.5 V V ps ps Ω ps ps tS tH VOD = 100 mV VOD = 100 mV tPLOH, tPLOL tPL VOD = 100 mV VOD = 100 mV ZOUT VOH VOL −8 mA < IOUT < 8 mA 50 Ω terminate to VCCO 50 Ω terminate to VCCO 50 Ω terminate to VCCO VCCO − 0.10 VCCO − 0.60 300 50.0 VCCO − 0.05 VCCO − 0.45 375 VCCO VCCO − 0.30 450 Ω V V mV VOH VOH VOH VOL VOL VOL 50 Ω terminate to VCCO − 2.0 50 Ω terminate to VCCO − 2.0 50 Ω terminate to VCCO − 2.0 50 Ω terminate to VCCO − 2.0 50 Ω terminate to VCCO − 2.0 50 Ω terminate to VCCO − 2.0 50 Ω terminate to VCCO − 2.0 VCCO − 1.14 VCCO − 1.10 VCCO − 1.04 VCCO − 1.54 VCCO − 1.50 VCCO − 1.44 300 VCCO − 1.02 VCCO − 0.98 VCCO − 0.92 VCCO − 1.39 VCCO − 1.35 VCCO − 1.29 375 VCCO − 0.90 VCCO − 0.86 VCCO − 0.80 VCCO − 1.24 VCCO − 1.20 VCCO − 1.14 450 V V V V V V mV Rev. B | Page 3 of 14 ADCMP572/ADCMP573 Parameter AC PERFORMANCE Propagation Delay Propagation Delay Tempco Prop Delay Skew—Rising Transition to Falling Transition Overdrive Dispersion Data Sheet Symbol Conditions tPD VCCI = 3.3 V, VOD = 200 mV VCCI = 3.3 V, VOD = 20 mV VCCI = 5.2 V, VOD = 200 mV ∆tPD/dT VOD = 200 mV, 5 V/ns Slew Rate Dispersion Pulse Width Dispersion 10% – 90% Duty Cycle Dispersion Common-Mode Dispersion Equivalent Input Bandwidth1 Toggle Rate Deterministic Jitter RMS Random Jitter Minimum Pulse Width Rise Time Fall Time POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential ADCMP572 (CML) Positive Supply Current Device Power Dissipation ADCMP573 (RSPECL) Positive Supply Current Device Power Dissipation 1 Min BWEQ DJ RJ PWMIN PWMIN tR tF 50 mV < VOD < 0.2 V, 5 V/ns 10 mV < VOD < 0.2 V, 5 V/ns 2 V/ns to 10 V/ns, 250 mV OD 100 ps to 5 ns, 250 mV OD VCCI = 3.3 V, 1 V/ns, 250 mV OD VCCI = 5.2 V, 1 V/ns, 250 mV OD VOD = 0.2 V, 0.0 V < VCM < 2.9 V 0.0 V to 250 mV input tR = tF = 17 ps, 20/80 >50% Output Swing VOD = 200 mV, 5 V/ns, PRBS31 − 1 NRZ, 4 Gbps VOD = 200 mV, 5 V/ns, PRBS31 − 1 NRZ, 10 Gbps VOD = 200 mV, 5 V/ns, 1.25 GHz ∆tPD/∆PW < 5 ps, 200 mV OD ∆tPD/∆PW < 10 ps, 200 mV OD 20/80 20/80 VCCI VCCO VCCI − VCCO IVCCI + IVCCO PD IVCCI + IVCCO PD Typ Max Unit 150 165 145 0.5 10 Ps Ps Ps ps/°C Ps 15 15 15 5 5 10 5 8.0 Ps Ps Ps Ps Ps ps/V GHz 12.5 10 Gbps Ps 20 Ps 0.2 100 80 35 35 Ps Ps Ps Ps Ps 3.1 3.1 −0.2 5.4 5.4 +2.3 V V V mA VCCI = 3.3 V, VCCO = 3.3 V, terminate 50 Ω to VCCO VCCI = 5.2 V, VCCO = 5.2 V, terminate 50 Ω to VCCO VCCI = 3.3 V, VCCO = 3.3 V, terminate 50 Ω to VCCO VCCI = 5.2 V, VCCO = 5.2 V, terminate 50 Ω to VCCO 44 52 44 52 140 165 230 265 VCCI = 3.3 V, VCCO = 3.3 V, 50 Ω to VCCO − 2 V VCCI = 5.2 V, VCCO = 5.2 V, 50 Ω to VCCO – 2 V VCCI = 3.3 V, VCCO = 3.3 V, 50 Ω to VCCO − 2 V VCCI = 5.2 V, VCCO = 5.2 V, 50 Ω to VCCO − 2 V 62 80 64 80 110 160 146 230 mW mA mW Equivalent input bandwidth assumes a simple first-order response and is calculated with the following formula: BWEQ = 0.22/√(trCOMP2−trIN2), where trIN is the 20/80 transition time of a quasi-Gaussian signal applied to the comparator input, and trCOMP is the effective transition time digitized by the comparator. Rev. B | Page 4 of 14 Data Sheet ADCMP572/ADCMP573 ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS Table 2. Parameter SUPPLY VOLTAGE Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI − VCCO) INPUT VOLTAGE Input Voltage Differential Input Voltage Input Voltage, Latch Enable HYSTERESIS CONTROL PIN Applied Voltage (HYS to GND) Maximum Input/Output Current OUTPUT CURRENT ADCMP572 (CML) ADCMP573 (RSPECL) TEMPERATURE Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range The ADCMP572/ADCMP573 LFCSP 16-lead package has a θJA (junction-to-ambient thermal resistance) of 70°C/W in still air. Rating −0.5 V to +6.0 V ESD CAUTION −0.5 V to +6.0 V −0.5 V to +3.5 V −0.5 V to VCCI + 0.5 V ±(VCCI + 0.5 V) −0.5 V to VCCO + 0.5 V −0.5 V to +1.5 V ±1 mA ±20 mA −35 mA −40°C to +125°C +150°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 5 of 14 ADCMP572/ADCMP573 Data Sheet 13 GND 14 HYS 16 VCCI 15 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VTP 1 VN 3 12 VCCO ADCMP572 ADCMP573 TOP VIEW 11 Q 10 Q 9 LE 7 VCCO VCCO /VTT 8 LE 6 VCCI 5 VTN 4 NOTES 1. LEAVE EPAD FLOATING UNLESS IMPROVED THERMAL OR MECHANICAL STABILITY IS DESIRED, IN WHICH CASE SOLDER IT TO THE APPLICATION BOARD. 04409-026 VP 2 Figure 2. ADCMP572/ADCMP573 Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5, 16 6 Mnemonic VTP VP VN VTN VCCI LE 7 LE 8 VCCO/VTT 9, 12 13, 15 10 VCCO GND Q 11 Q 14 HYS Isolated Heat Sink EPAD Description Termination Resistor Return Pin for VP Input. Noninverting Analog Input. Inverting Analog Input. Termination Resistor Return Pin for VN Input. Positive Supply Voltage for Input Stage. Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator’s being placed into latch mode. LE must be driven in complement with LE. Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being placed into latch mode. LE must be driven in complement with LE. Termination Return Pin for the LE/LE Input Pins. For the ADCMP572 (CML output stage), this pin is internally connected to and also should be externally connected to the positive VCCO supply. For the ADCMP573 (RSPECL output stage), this pin should normally be connected to the VCCO – 2 V termination potential. Positive Supply Voltage for the CML/RSPECL Output Stage. Ground. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided the comparator is in compare mode. See the LE/LE descriptions (Pins 6 and 7) for more information. Noninverting Output. Q is at logic high if the analog voltage at the noninverting input VP is greater than the analog voltage at the inverting input, VN, provided the comparator is in compare mode. See the LE/LE descriptions (Pins 6 and 7) for more information. Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of RHYS hysteresis control resistor. The metallic back surface of the package is not electrically connected to any part of the circuit, and it can be left floating for best electrical isolation between the package handle and the substrate of the die. However, it can be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal at package corners is connected to the heat sink paddle. Exposed Pad. Leave EPAD floating unless improved thermal or mechanical stability is desired, in which case solder it to the application board. Rev. B | Page 6 of 14 Data Sheet ADCMP572/ADCMP573 TYPICAL PERFORMANCE CHARACTERISTICS VCCI = VCCO = 3.3 V, TA = 25°C, unless otherwise noted. 39.0 38.5 RISE/FALL TIME (ps) 15 10 38.0 37.5 37.0 5 0 50 100 150 200 250 INPUT OVERDRIVE VOLTAGE (mV) 36.0 –60 158.5 60 158.0 50 157.5 40 HYSTERESIS (mV) 20 40 60 80 100 157.0 156.5 30 20 10 0.2 0.4 0.6 0.8 1.0 1.2 INPUT COMMON-MODE VOLTAGE (V) 0 04409-040 0 0 1 2 3 4 5 6 RHYS (k) Figure 4. Propagation Delay vs. Input Common-Mode Figure 7. Hysteresis vs. RHYS Control Resistor 160 80 158 70 60 HYSTERESIS (mV) 156 154 152 50 40 30 150 20 148 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 04409-041 146 –60 10 Figure 5. Propagation Delay vs. Temperature 0 –600 04409-047 PROPAGATION DELAY (ps) 0 Figure 6. Rise/Fall Time vs. Temperature 156.0 PROPAGATION DELAY (ps) –20 TEMPERATURE (°C) Figure 3. Propagation Delay vs. Input Overdrive 155.5 –40 04409-043 0 04409-042 36.5 04409-039 PROPAGATION DELAY ERROR (ps) 20 –500 –400 –300 –200 RHYS SINK CURRENT (A) Figure 8. Hysteresis vs. RHYS Sink Current Rev. B | Page 7 of 14 –100 0 Data Sheet –15.0 380 –15.5 379 –16.0 378 OUTPUT LEVELS (mV) –16.5 –17.0 –17.5 377 376 375 374 –18.5 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 04409-044 –18.0 1.5 VP INPUT VOLTAGE (VN = –0.2V) 373 –60 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 12. Output Levels vs. Temperature Figure 9. Input Bias Current vs. Input Differential –16.2 496.0mV –16.4 –16.5 –16.6 –16.7 –16.8 –20 0 20 40 60 80 100 04409-045 –40 TEMPERATURE (°C) 504.0mV 60.00ps/DIV 04409-049 M1 –16.9 –60 Figure 13. ADCMP572 Eye Diagram at 2.5 Gbps Figure 10. Input Bias Current vs. Temperature 0.5 500.0mV 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.4 –0.5 –50 –25 0 25 50 TEMPERATURE (C) 75 100 500.0mV 125 25.00ps/DIV Figure 14. ADCMP572 Eye Diagram at 6.5 Gbps Figure 11. Input Offset Voltage vs. Temperature Rev. B | Page 8 of 14 04409-050 –0.3 04409-024 OFFSET (mV) INPUT BIAS CURRENT (A) –16.3 04409-046 INPUT BIAS CURRENT (A) ADCMP572/ADCMP573 Data Sheet ADCMP572/ADCMP573 APPLICATIONS INFORMATION VCCO 50 Q It is important to adequately bypass the input and output supplies. A 1 μF electrolytic bypass capacitor should be placed within several inches of each power supply pin to ground. In addition, multiple high quality 0.01 μF bypass capacitors should be placed as close as possible to each of the VCCI and VCCO supply pins and should be connected to the GND plane with redundant vias. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should be avoided to maximize the effectiveness of the bypass at high frequencies. If the input and output supplies are connected separately such that VCCI ≠ VCCO, care should be taken to bypass each of these supplies separately to the GND plane. A bypass capacitor should not be connected between them. It is recommended that the GND plane separate the VCCI and VCCO planes when the circuit board layout is designed to minimize coupling between the two supplies and to take advantage of the additional bypass capacitance from each respective supply to the ground plane. This enhances the performance when split input/output supplies are used. If the input and output supplies are connected together for single-supply operation such that VCCI = VCCO, coupling between the two supplies is unavoidable; however, every effort should be made to keep the supply plane adjacent to the GND plane to maximize the additional bypass capacitance this arrangement provides. CML/RSPECL OUTPUT STAGE Specified propagation delay dispersion performance can be achieved only by using proper transmission line terminations. The outputs of the ADCMP572 are designed to directly drive 400 mV into 50 Ω cable, microstrip, or strip line transmission lines properly terminated to the VCCO supply plane. The CML output stage is shown in the simplified schematic diagram of Figure 15. The outputs are each back terminated with 50 Ω for best transmission line matching. The RSPECL outputs of the ADCMP573 are illustrated in Figure 16 and should be terminated to VCCO − 2 V. As an alternative, Thevenin equivalent termination networks can be used in either case if the direct termination voltage is not readily available. If high speed output signals must be routed more than a centimeter, microstrip or strip line techniques are essential to ensure proper transition times and to Q 16mA GND Figure 15. Simplified Schematic Diagram of the ADCMP572 CML Output Stage VCCO Q Q GND 04409-038 The ADCMP572/ADCMP573 comparators are very high speed SiGe devices. Consequently, it is essential to use proper high speed design techniques to achieve the specified performance. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. prevent output ringing and pulse width dependent propagation delay dispersion. For the most timing critical applications where transmission line reflections pose the greatest risk to performance, the ADCMP572 provides the best match to 50 Ω output transmission paths. 04409-037 POWER/GROUND LAYOUT AND BYPASSING Figure 16. Simplified Schematic Diagram of the ADCMP573 RSPECL Output Stage USING/DISABLING THE LATCH FEATURE The latch inputs (LE/LE) are active low for latch mode and are internally terminated with 50 Ω resistors to Pin 8. This pin corresponds to and is internally connected to the VCCO supply for the CML-compatible ADCMP572. With the aid of these resistors, the ADCMP572 latch function can be disabled by connecting the LE pin to GND with an external pull-down resistor and leaving the LE pin unconnected. To avoid excessive power dissipation, the resistor should be 750 Ω when VCCO = 3.3 V, and 1.2 kΩ when VCCO = 5.2 V. In the PECL-compatible ADCMP573, the VTT pin should be connected externally to the PECL termination supply at VCCO – 2 V. The latch can then be disabled by connecting the LE pin to VCCO with an external 500 Ω resistor and leaving the LE pin disconnected. In this case, the resistor value does not depend on the VCCO supply voltage. Rev. B | Page 9 of 14 ADCMP572/ADCMP573 Data Sheet As with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. Discontinuities along input and output transmission lines can severely limit the specified pulse width dispersion performance. For applications working in a 50 Ω environment, input and output matching has a significant impact on data dependent (or deterministic) jitter (DJ) and on pulse width dispersion performance. The ADCMP572/ADCMP573 comparators provide internal 50 Ω termination resistors for both the VP and VN inputs, and the ADCMP572 provides 50 Ω back terminated outputs. The return side for each input termination is pinned out separately with the VTP and VTN pins, respectively. If a 50 Ω termination is desired at one or both of the VP/VN inputs, then the VTP and VTN pins can be connected (or disconnected) to (from) the desired termination potential as required. The termination potential should be carefully bypassed using high quality bypass capacitors as discussed earlier to prevent undesired aberrations on the input signal due to parasitic inductance in the circuit board layout. If a 50 Ω input termination is not desired, either one or both of the VTP/VTN termination pins can be left disconnected. In this case, the pins should be left floating with no external pull-downs or bypassing capacitors. The ADCMP572/ADCMP573 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to 500 mV. Propagation delay dispersion is variation in the propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold). Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications such as data communication, automatic test and measurement, instrumentation, and event driven applications such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions vary (Figure 17 and Figure 18). For the ADCMP572/ADCMP573, dispersion is typically