ADD5203

8-String, White LED Driver with SMBus and PWM Input for LCD Backlight Applications ADD5203 FEATURES White LED driver based on inductive boost converter Integrated 50 V MOSFET with 2.9 A peak current limit Input voltage range: 6 V to 21 V Maximum output adjustable up to 45 V 350 kHz to 1 MHz adjustable operating frequency Overvoltage protection (OVP) up to typical 47.5 V Built-in soft start for boost converter Drives up to eight LED current strings LED current adjustable up to 30 mA for each channel Headroom control to maximize efficiency Adjustable dimming frequency: 200 Hz to 10 kHz LED open and short fault protection Selectable dimming control interface methods PWM input SMBus serial input Selectable dimming modes Fixed delay PWM dimming control with 8-bit resolution No delay PWM dimming control with 8-bit resolution Direct PWM dimming control DC current dimming control with 8-bit resolution General Thermal shutdown Undervoltage lockout 28-lead, 4 mm × 4 mm × 0.75 mm LFCSP_WQ FUNCTIONAL BLOCK DIAGRAM STEP-UP SWITCHING REGULATOR EIGHT CURRENT SOURCES PWM DUTY EXTRACTOR 8-BIT BRIGHTNESS CONTROL LOGIC FIXED DELAY/NO DELAY DIRECT PWM/ DC CURRENT DIMMING CONTROL WITH PWM AND/OR SMBus INTERFACE Figure 1. APPLICATIONS Notebook PCs, UMPCs, and monitor displays GENERAL DESCRIPTION The ADD5203 is a white LED driver for backlight applications based on high efficiency, current-mode, step-up converter technology. It is designed with a 0.15 Ω, 2.9 A internal switch and a pin-adjustable operating frequency between 350 kHz and 1 MHz. The ADD5203 contains eight regulated current sources for uniform brightness intensity. Each current source can be driven up to 30 mA, and the LED driving current is pin adjustable by an external resistor. The ADD5203 drives up to eight parallel strings of multiple series connected LEDs with a ±1.5% current matching between strings. The ADD5203 provides various dimming modes. Each dimming mode is selectable with an external dimming mode selection pin. The LED dimming control interface can be achieved through PWM input and/or SMBus. The device provides adjustable output dimming frequency range from 200 Hz to 10 kHz by an external resistor and capacitor. The ADD5203 operates over an input voltage range of 6 V to 21 V, but the device can function with a voltage as low as 5.6 V. The ADD5203 also has multiple safety protection features to prevent damage during fault conditions. If any LED is open or short, the device automatically disables the faulty current source. The internal soft start prevents inrush current during startup. Thermal shutdown protection prevents thermal damage. The ADD5203 is available in a low profile, thermally enhanced, 4 mm × 4 mm × 0.75 mm, 28-lead, RoHS-compliant lead frame chip scale package (LFCSP_WQ) and is specified over the industrial temperature range of −25°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. 08717-001 UNDERVOLTAGE LOCKOUT INTERNAL SOFT START THERMAL PROTECTION OVERVOLTAGE PROTECTION AUTODISABLE FOR LED OPEN/SHORT ADD5203 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Circuit Diagram ................................................................................ 3 Specifications..................................................................................... 4 Step-Up Switching Regulator Specifications............................. 4 LED Current Regulation Specifications .................................... 4 SMBus Specifications ................................................................... 5 General Specifications ................................................................. 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 11 Current-Mode, Step-Up Switching Regulator Operation ..... 11 Internal 3.3 V Regulator ............................................................ 11 Boost Converter Switching Frequency .................................... 11 Dimming Frequency (fPWM) ...................................................... 11 Current Source............................................................................ 11 Dimming Control Interface ...................................................... 11 PWM Dimming Mode .............................................................. 12 Safety Features ............................................................................ 12 SMBus Interface.......................................................................... 13 SMBus Register Description ..................................................... 15 External Component Selection Guide ..................................... 17 Layout Guidelines....................................................................... 18 Typical Application Circuits ......................................................... 20 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23 REVISION HISTORY 5/10—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADD5203 CIRCUIT DIAGRAM VIN 26 VDDIO 4 SHDN 25 NC 16 OVP 22 LINEAR REGULATOR SHUTDOWN VOLTAGE REFERENCE UVP COMP UVP REF ERROR AMP GM LL REF TSD FAULT THERMAL SHUTDOWN OCP FAULT OCP REF 23 ADD5203 OVP REF LIGHT LOAD R Q PWM COMP S SW 24 SW REF COMP 28 DREF DCOMP OSC 27 FSLCT + ∑ + CURRENT SENSE SOFT START HEADROOM CONTROL CURRENT REFERENCE LED OPEN/SHORT FAULT DETECTOR RSENSE ISET 17 20 PGND PGND TSD FAULT FB1 7 CURRENT SOURCE 1 OCP FAULT 21 FB2 8 CURRENT SOURCE 2 BRIGHTNESS CONTROL REGISTER DEVICE CONTROL REGISTER FAULT/STATUS REGISTER ID REGISTER FB3 9 CURRENT SOURCE 3 SMBus INTERFACE DUTY GENERATOR 5 SDA SCL 6 FB4 10 CURRENT SOURCE 4 FB5 12 CURRENT SOURCE 5 PWMI DUTY EXTRACTOR 1 FB6 13 PWMI CURRENT SOURCE 6 FB7 14 CURRENT SOURCE 7 OPERATION MODE SELECTION 2 3 SEL1 SEL2 FB8 15 CURRENT SOURCE 8 CURRENT SOURCE CONTROLLER PWM OSCILLATOR 19 18 C_FPWM R_FPWM 08717-002 11 AGND Figure 2. Circuit Diagram Rev. 0 | Page 3 of 24 ADD5203 SPECIFICATIONS STEP-UP SWITCHING REGULATOR SPECIFICATIONS VIN = 12 V, SHDN = high, TA = −25°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. Table 1. Parameter SUPPLY Input Voltage Range BOOST OUTPUT Output Voltage SWITCH On Resistance Leakage Current Peak Current Limit OSCILLATOR Switching Frequency Maximum Duty Cycle SOFT START Soft Start Time OVERVOLTAGE PROTECTION Overvoltage Rising Threshold on OVP Pin Overvoltage Falling Threshold on OVP Pin Symbol VIN VOUT RDS(ON) ILKG ICL fSW fSW DMAX tSS VOVPR VOVPF 1.154 1.050 VIN = 12 V, ISW = 100 mA Duty cycle (D) = DMAX RF = 150 kΩ RF = 470 kΩ RF = 470 kΩ 2.9 800 85 1000 350 92 1.5 1.20 1.12 1.267 1.188 1200 150 44 Test Conditions Min 6 Typ Max 21 45 210 70 Unit V V mΩ μA A kHz kHz % ms V V LED CURRENT REGULATION SPECIFICATIONS VIN = 12 V, SHDN = high, TA = −25°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. Table 2. Parameter CURRENT SOURCE ISET Pin Voltage Adjustable LED Current 1 Constant Current Sink of 20 mA 2 Minimum Headroom Voltage2 Current Matching Between Strings2 LED Current Accuracy2 Current Source Leakage Current FPWM GENERATOR Dimming Frequency Range Dimming Frequency LED FAULT DETECTION Open Fault Delay1 1 2 Symbol VSET ILED ILED20 VHR20 Test Conditions 6 V ≤ VIN ≤ 21 V RSET = 141.56 kΩ RSET = 141.56 kΩ RSET = 141.56 kΩ RSET = 141.56 kΩ Min 1.16 0 19.4 −1.5 −3 Typ 1.2 20 0.65 Max 1.24 30 20.6 0.85 +1.5 +3 1 10,000 1180 6.5 Unit V mA mA V % % μA Hz Hz μs fPWM TD_OPENFAULT 6 V ≤ VIN ≤ 21 V RFPWM = 50 kΩ, CFPWM = 150 pF 200 820 1000 These electrical specifications are guaranteed by design. Tested at TA = +25°C. Rev. 0 | Page 4 of 24 ADD5203 SMBUS SPECIFICATIONS VIN = 12 V, SHDN = high, TA = −25°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. Table 3. Parameter 1 SMBus INTERFACE Data, Clock Input Low Level Data, Clock Input High Level Data, Clock Output Low Level SMBus TIMING SPECIFICATIONS Clock Frequency Bus-Free Time Between Stop and Start Condition Hold Time After Start Condition 2 Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock/Data Fall Time Clock/Data Rise Time 1 2 Symbol VIL VIH VOL fSMB tBUF tHD:STA tSU:STA tSU:STO tHD:DAT tSU:DAT tLOW tHIGH tF tR Test Conditions Min Typ Max 0.8 5.5 0.4 100 Unit V V V kHz μs μs μs μs ns ns μs 2.1 10 4.7 4.0 4.7 4.0 300 250 4.7 4.0 50 300 1 μs ns us These electrical specifications are guaranteed by design. After this period, the first clock is generated. Rev. 0 | Page 5 of 24 ADD5203 GENERAL SPECIFICATIONS VIN = 12 V, SHDN = high, TA = −25°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. Table 4. Parameter SUPPLY Input Voltage Range Quiescent Current Shutdown Supply Current VDD REGULATOR VDD Regulated Output PWM INPUT PWM Voltage High PWM Voltage Low PWM Input Range THERMAL SHUTDOWN Thermal Shutdown Threshold 1 Thermal Shutdown Hysteresis1 UVLO VIN Falling Threshold VIN Rising Threshold SHDN CONTROL Input Voltage High Input Voltage Low SHDN Pin Input Current 1 Symbol VIN IQ ISD VVDD_REG VPWM_HIGH VPWM_LOW Test Conditions Min 6 Typ Max 21 6.5 160 3.42 5.5 0.8 10,000 Unit V mA μA V V V Hz °C °C V V V V μA 6 V ≤ VIN ≤ 21 V, SHDN = high 6 V ≤ VIN ≤ 21 V, SHDN = low 6 V ≤ VIN ≤ 21 V 3.18 2.2 200 4.2 40 3.3 TSD TSDHYS VUVLOF VUVLOR VIH VIL ISHDN VIN falling VIN rising 4.2 160 30 4.6 5.0 5.6 2.0 1.0 SHDN = 3.3 V 6 These electrical specifications are guaranteed by design. Rev. 0 | Page 6 of 24 ADD5203 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VIN SW SHDN, SDA, SCL, PWMI, SEL1, and SEL2 ISET, FSLCT, COMP, R_FPWM, and C_FPWM VDDIO FB1, FB2, FB3, FB4, FB5, FB6, FB7, and FB8 OVP Maximum Junction Temperature (TJ max) Operating Temperature Range (TA) Storage Temperature Range (TS) Reflow Peak Temperature (20 sec to 40 sec) Rating −0.3 V to +23 V −0.3 V to +50 V −0.3 V to +6 V −0.3 V to +3.6 V −0.3 V to +3.7 V −0.3 V to +50 V −0.3 V to +3 V 150°C −25°C to +85°C −65°C to +150°C 260°C THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance Package Type 28-Lead LFCSP_WQ θJA 32.6 θJC 1.4 Unit °C/W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 24 ADD5203 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 27 FSLCT 26 VIN 28 COMP 25 SHDN 24 SW 22 OVP 21 PGND 20 PGND 19 C_FPWM 18 R_FPWM 17 ISET 16 NC 15 FB8 PWMI 1 SEL1 2 SEL2 3 VDDIO 4 SDA 5 SCL 6 FB1 7 ADD5203 TOP VIEW (Not to Scale) 8 9 AGND 11 FB4 10 FB5 12 FB6 13 23 SW NOTES 1. NC = NO CONNECT. 2. CONNECT THE EXPOSED PADDLE TO GND. FB7 14 FB2 FB3 Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic PWMI SEL1 SEL2 VDDIO SDA SCL FB1 FB2 FB3 FB4 AGND FB5 FB6 FB7 FB8 NC ISET R_FPWM C_FPWM PGND PGND OVP SW SW SHDN VIN FSLCT COMP EP Description PWM Signal Input. Dimming Mode Selection 1. Dimming Mode Selection 2. Internal Linear Regulator Output. This regulator provides power to the ADD5203. Serial Data Input/Output. Serial Clock Input. Regulated Current Sink. Connect the bottom cathode of the LED string to this pin. Regulated Current Sink. Connect the bottom cathode of the LED string to this pin. Regulated Current Sink. Connect the bottom cathode of the LED string to this pin. Regulated Current Sink. Connect the bottom cathode of the LED string to this pin. Analog Ground. Regulated Current Sink. Connect the bottom cathode of the LED string to this pin. If unused, connect to GND. Regulated Current Sink. Connect the bottom cathode of the LED string to this pin. If unused, connect to GND. Regulated Current Sink. Connect the bottom cathode of the LED string to this pin. If unused, connect to GND. Regulated Current Sink. Connect the bottom cathode of the LED string to this pin. If unused, connect to GND. No Connection. Full-Scale LED Current Set. A resistor from this pin to ground sets the LED current up to 30 mA. Dimming frequency adjustment pin with an external resistor. Dimming frequency adjustment pin with an external capacitor. Power Ground. Power Ground. Overvoltage Protection. Drain Connection of the Internal Power FET. Drain Connection of the Internal Power FET. Shutdown Control for PWM Input Operation Mode. Active low. Supply Input. Must be locally bypassed with a capacitor to ground. Frequency Select. A resistor from this pin to ground sets the boost switching frequency from 350 kHz to 1 MHz. Compensation for Boost Converter. A capacitor and a resistor are connected in series between ground and this pin for stable operation and an optional capacitor can be connected from this pin to ground. Exposed Paddle. Connect the exposed paddle to ground. Rev. 0 | Page 8 of 24 08717-003 ADD5203 TYPICAL PERFORMANCE CHARACTERISTICS 94 25 ILED = 20mA BRIGHTNESS = 100% fSW = 600kHz 8 PARALLEL × 8 SERIES 10 PARALLEL × 8 SERIES BOOST CONVERTER EFFICIENCY (%) 92 90 88 86 84 82 80 20 LED CURRENT (mA) 08717-004 15 10 5 5 10 15 INPUT VOLTAGE (V) 20 25 0 25 50 75 100 125 150 175 200 225 250 SMBus BRIGHTNESS SETTING Figure 4. Boost Converter Efficiency vs. Input Voltage 32 30 28 26 Figure 7. LED Current vs. SMBus Brightness Setting 25 20 LED CURRENT (mA) LED CURRENT (mA) 24 22 20 18 16 14 12 10 08717-005 15 10 5 105 125 145 165 185 RSET (kΩ) 205 225 245 265 5 10 15 INPUT VOLTAGE (V) 20 Figure 5. LED Current vs. RSET Figure 8. LED Current vs. Input Voltage (ILED = 20 mA) 20 VIN = 15V BRIGHTNESS = 100% LEDs = 12 SERIES × 8 PARALLEL VOUT 20V/DIV LED CURRENT (mA) 15 VSW 20V/DIV SHDN 3V/DIV 10 5 0 10 20 30 40 50 60 70 PWM DUTY CYCLE (%) 80 90 100 08717-006 0 Figure 6. LED Current vs. PWM Input Duty Cycle Figure 9. Start-Up Waveforms (Brightness = 100%) Rev. 0 | Page 9 of 24 08717-009 IL 1A/DIV 08717-008 8 85 0 08717-007 78 0 ADD5203 VOUT 200mV/DIV AC VSW 20V/DIV PWM 3V/DIV VFB1 5V/DIV IL 500mA/DIV VIN = 7V, fSW = 1MHz BRIGHTNESS = 100% LEDs = 10 SERIES × 8 PARALLEL Figure 10. Switching Waveforms (VIN = 7 V) Figure 12. LED Current Waveforms (Brightness = 0.39%) VOUT 200mV/DIV AC VSW 20V/DIV PWM 3V/DIV VFB1 5V/DIV IL 500mA/DIV VIN = 21V, VSW = 1MHz BRIGHTNESS = 100% LEDs = 10 SERIES × 8 PARALLEL VIN = 12V BRIGHTNESS = 25% LEDs = 10 SERIES × 8 PARALLEL IFB1 10mA/DIV 08717-011 Figure 11. Switching Waveforms (VIN = 21 V) Figure 13. LED FBx Waveforms (Brightness = 10%) Rev. 0 | Page 10 of 24 08717-013 08717-012 08717-010 VIN = 12V BRIGHTNESS = 0.39% LEDs = 10 SERIES × 8 PARALLEL IFB1 10mA/DIV ADD5203 THEORY OF OPERATION CURRENT-MODE, STEP-UP SWITCHING REGULATOR OPERATION The ADD5203 uses a current-mode PWM boost regulator to provide the minimal voltage needed to enable the LED string at the programmed LED current. The current-mode regulation system allows fast transient response while maintaining a stable output voltage. By selecting the proper resistor-capacitor network from COMP to GND, the regulator response can be optimized for a wide range of input voltages, output voltages, and load conditions. The ADD5203 can provide a 45 V maximum output voltage and drive up to 13 LEDs (3.4 V/30 mA type of LEDs) for each channel. Table 8. RFPWM and CFPWM Recommendation Dimming Freq (fPWM) 200 Hz 500 Hz 1 kHz 5 kHz 10 kHz RFPWM (kΩ) 110 75 50 18 13 CFPWM (pF) 390 200 150 47 20 CURRENT SOURCE The ADD5203 contains eight current sources to provide accurate current sinking for each LED string. String-to-string tolerance is kept within ±1.5% at 20 mA. Each LED string current is adjusted up to 30 mA by an external resistor. The ADD5203 contains an LED open and short fault protection circuit for each channel. If the headroom voltage of the current source remains below 200 mV while the boost converter output reaches the OVP level, the ADD5203 recognizes that the current source has an open load fault for the current source, and the current source is disabled. If the headroom voltage of the current source goes above 7.2 V, the current source is disabled for short protection. If an application requires four LED strings, each LED string should be connected using FB1 to FB4. Tie the unused FB pins (FB5 to FB8) to GND. The ADD5203 contains hysteresis to prevent the LED current change that is caused by a ±0.195% jitter of the PWM input. INTERNAL 3.3 V REGULATOR The ADD5203 contains a 3.3 V linear regulator. The regulator is used for biasing internal circuitry. The internal regulator requires a 1 μF bypass capacitor. Place this bypass capacitor between VDDIO (Pin 4) and GND, as close as possible to Pin VDDIO. BOOST CONVERTER SWITCHING FREQUENCY The ADD5203 boost converter switching frequency is user adjustable, between 350 kHz to 1 MHz, by using an external resistor, RF. A frequency of 350 kHz is recommended to optimize the regulator for high efficiency, and a frequency of 1 MHz is recommended for small external components. See Figure 14 for considerations when selecting a switching frequency and an adjustment resistor (RF). 1100 1000 900 800 700 600 500 400 08717-014 Programming the LED Current As shown in Figure 2, the ADD5203 has an LED current set pin (ISET). A resistor (RSET) from this pin to ground adjusts the LED current up to 30 mA. LED current level can be set with the following equation: ILED = 2831 ( A) R SET SWITCHING FREQUENCY (kHz) DIMMING CONTROL INTERFACE The ADD5203 dimming control interface method is selectable between the SMBus serial input and/or the external PWM input. The LED dimming modes supported by ADD5203 can be controlled externally through these dimming control interfaces. The SEL1 and SEL2 pins should be set based on the application conditions (see Table 9). Table 9. Brightness Control Mode Selection SEL1 High Open Low SEL2 High Low High Low High Open Low Dimming Mode Fixed delay PWM No delay PWM Fixed delay PWM No delay PWM DC current DC current Direct PWM Interface SMBus SMBus PWM PWM SMBus PWM PWM 300 120 170 220 270 320 RF (kΩ) 370 420 470 Figure 14. Switching Frequency vs. RF DIMMING FREQUENCY (fPWM) The ADD5203 contains an internal oscillator to generate the PWM dimming signal for LED brightness control. The LED dimming frequency (fPWM) is adjustable, in the fPWM range of 200 Hz to 10 kHz, by using an external resistor (RFPWM) and capacitor (CFPWM). The RFPWM should be in the range of 13 kΩ to 110 kΩ, and the CFPWM should be in the range of 20 pF to 390 pF. Rev. 0 | Page 11 of 24 ADD5203 PWM DIMMING MODE The ADD5203 supports an 8-bit resolution to control brightness; therefore, the LED dimming duty is generated with 256 steps through the PWM input duty value in the range of 0% to 100%. In addition, if the PWM input duty cycle is 0% longer than 10 ms, the ADD5203 is disabled. Note that the ADD5203 has immunity when the PWM input duty cycle is converted to 256 steps. Even the PWM input has ±0.195% jitter. Direct PWM Dimming Direct PWM mode is selected when SEL1 is low and SEL2 is low for a PWM application. In this mode, the PWM input controls the ADD5203 LED dimming logic. It turns the current sources on and off without any duty extraction. In addition, each current source has no phase delay in this mode. The LED brightness is changed by the PWM input duty ratio. DUTY = 60% PWMI DUTY = 60% Fixed Delay PWM Dimming Fixed delay PWM mode is selected when SEL1 is open and SEL2 is high for a PWM application, or when SEL1 is high and SEL2 is high for an SMBus application. In this mode, each current source has a fixed turn-on time delay between adjacent strings. The fixed delay time is set by the FPWM frequency. Each channel delay time is set by the following equation: ILED1 ILED2 ILED3 08717-017 ILED8 tD = 2 × t FPWM 256 DUTY = 60% Figure 17. Direct PWM Dimming Timing DC Current Dimming DC current mode is selected when SEL1 is low and SEL2 is open for a PWM application, or when SEL1 is low and SEL2 is high for an SMBus application. In this mode, the maximum LED current is set by the value of RSET. Once the maximum LED current is set, the LED current can be changed with 256 steps through PWM input or SMBus. DUTY = 80% DUTY = 60% DUTY = 40% DUTY = 20% where tFPWM = 1/fPWM, and fPWM is the LED dimming frequency. PWMI tFPWM (DUTY = 60%) tOFF tON fPWM ILED1 tD ILED2 08717-015 PWMI ILED MAX 0.8 × ILED MAX 0.6 × ILED MAX 0.4 × ILED MAX 08717-018 ILED8 7 × tD ILED Figure 15. Fixed-Delay PWM Dimming Timing 0.2 × ILED MAX No Delay PWM Dimming No-delay PWM mode is selected when SEL1 is open and SEL2 is low for a PWM application or when SEL1 is high and SEL2 is low for an SMBus application. In this mode, each current source turns on and off at the same time without any phase delay. DUTY = 60% 0A Figure 18. DC Current Dimming Timing SAFETY FEATURES The ADD5203 contains several safety features to provide stable operation. Soft Start The ADD5203 contains an internal soft start function to reduce inrush current at startup. The soft start time is typically 1.5 ms. PWMI DUTY = 60% fPWM ILED1 ILED2 tON tOFF Overvoltage Protection (OVP) The ADD5203 contains OVP circuits to prevent boost converter damage if the output voltage becomes excessive for any reason. To keep a safe output level, the integrated OVP circuit monitors the output voltage. When the OVP pin voltage is reached by the OVP rising threshold, the boost converter stops switching, causing the output voltage to drop. When the OVP pin voltage goes lower than the OVP falling threshold, the boot converter begins switching, causing the output to rise. There is about 7.5% hysteresis between the rising and falling thresholds. The OVP level can be calculated with the following equation: ILED8 Figure 16. No Delay PWM Dimming Timing Rev. 0 | Page 12 of 24 08717-016 ADD5203 VOVP = 1.2 V R1 × (R1 + R2) Thermal Overload Protection Thermal overload protection prevents excessive power dissipation from overheating the ADD5203. When the junction temperature (TJ) exceeds 160°C, a thermal sensor immediately activates the fault protection, which shuts down the device, allowing the IC to cool. The device self-starts when the junction temperature (TJ) of the die falls below 130°C. In general, the suitable OVP level is 5 V higher than the nominal boost switching regulator output. Large resistors, up to 1 MΩ, can be used for R2 to minimize power loss. In addition, some applications require C1 to prevent noise interference at the OVP pin in the range of 10 pF to 30 pF. VOVP R2 OVP DETECTION OVP COMP 22 R1 C1 08717-019 SMBUS INTERFACE SMBus mode can be selected using the SEL1 and SEL2 mode selection pins. When in SMBus mode, the ADD5203 can be controlled with an SMBus serial interface. Read Byte As shown in Figure 21, the read byte protocol is four bytes long and starts with the slave address followed by the command code, which translates to the register index. Then, the bus direction turns around with the rebroadcast of the slave address, with Bit 0 indicating a read cycle. The fourth byte contains the data being returned by the backlight controller. The byte value in the data byte should reflect the value of the register being queried at the command code index. Note the bus directions, which are shaded in Figure 21 and are used on cycles where the slaved backlight controller drives the data line. All other cycles are driven by the host master. OVP REF Figure 19. Overvoltage Protection Circuit Open Load Protection (OLP) The ADD5203 contains a headroom control circuit to minimize power loss at each current source. Therefore, the minimum feedback voltage is achieved by regulating the output voltage of the boost converter. If any LED string is opened during normal operation, the current source headroom voltage (VHR) is pulled to GND. In this condition, open load protection (OLP) is activated if VHR is less than 200 mV until the boost converter output voltage rises up to the OVP level. Write Byte The write byte protocol is only three bytes long. The first byte starts with the slave address followed by the command code, which translates to the register index being written. The third byte contains the data byte that must be written into the register selected by the command code. Note the bus directions, which are shaded in Figure 22 and are used on cycles where the slaved backlight controller drives the data line. All other cycles are driven by the host master. Short-Circuit Protection (SCP) The ADD5203 contains the short circuit protection (SCP). If a few LEDs at any strings are shorted during normal operation, the current source headroom voltage (VHR) is increasing. In this condition, SCP is activated if VHR is higher than 7.2 V; therefore, the string that includes short LEDs is disabled. Undervoltage Lockout (UVLO) An undervoltage lockout circuit is included with built-in hysteresis. The ADD5203 turns on when VIN rises above 5 V (typical) and shuts down when VIN falls below 4.6 V (typical). Rev. 0 | Page 13 of 24 ADD5203 Slave Device Address As shown in Figure 23, the ADD5203 address consists of seven address bits plus one read/write (R/W) bit. If the device is in write mode, the LSB is set to 0 and the slave address byte is 0x58. If the tLOW VIH VIL device is in read mode, the LSB is set to 1 and the slave address byte is 0x59. tR tF SCL tHD:DAT tHD:STA SDA VIH VIL P tHIGH tSU:STA tSU:DAT tSU:STO tBUF S S P Figure 20. SMBus Interface S SLAVE ADDRESS MASTER TO SLAVE SLAVE TO MASTER W A COMMAND CODE A S SLAVE ADDRESS R A DATA BYTE A P Figure 21. Read Byte Protocol S SLAVE ADDRESS MASTER TO SLAVE SLAVE TO MASTER W A COMMAND CODE A DATA BYTE A P Figure 22. Write Byte Protocol 0 1 0 1 1 0 0 R/W 08717-023 Figure 23. Slave Address Definition Rev. 0 | Page 14 of 24 08717-022 08717-021 08717-020 ADD5203 SMBUS REGISTER DESCRIPTION The ADD5203 has four registers to control and monitor brightness, fault status, identifications, and operating mode. Those registers are one byte wide and accessible via the SMBus read/write byte protocols. The PWM_MD bit selects the manner in which the PWM input is to be interpreted. When this bit is 0, the PWM input reflects a percent change in the current brightness (that is, DPST mode) and should be as follows: DPST Brightness = CBT × (PWM) Brightness Control Register (Address 0x00) This register consists of eight bits, BRT7 to BRT0, which are used to control the LED brightness level in 256 steps. An SMBus write byte cycle to this register sets the brightness level if the device is in SMBus mode. In addition, a write byte cycle to this register sets the brightness level if the device is in SMBus mode. Furthermore, a write byte cycle to this register has no effect when the device is in a mode other than SMBus mode. The operating mode is selected by the device control register (Address 0x01). An SMBus read byte cycle to this register returns the current brightness level, regardless of the value of PWM_SEL. An SMBus setting of 0xFF for this register sets the device to the maximum brightness output, and a setting of 0x00 sets the device to the minimum brightness output. This register is both readable and writable for all bits. The default value is 0xFF. where: CBT is the current brightness setting from SMBus without influence from the PWM. PWM is the percent duty cycle. The PWM signal starts from 100% when operating in DPST mode. When PWM_MD is 1, the PWM input has no effect on the brightness setting, unless the ADD5203 is in PWM mode. In addition, when operating in PWM mode, this bit is a do not care (see Table 10). The PWM_SEL bit determines whether the SMBus or PWM input should drive brightness. The relationship between these two control bits can be thought of as specifying an operating mode for the ADD5203. The defined modes are shown in Table 10. Note that depending on the setting of some bits, other bits have no effect and are do not cares, shown as X in Table 10. Table 10. Operating Modes Selected by Device Control Register Bit 1 and Bit 2 PWM_SEL (Bit 1) 1 0 0 1 Device Control Register (Address 0x01) This register has three bits. Two bits control the operation mode of the device, and a single bit controls the backlight on/off state. This register is both readable and writable for Bit 0 to Bit 2. Bit 0, named BL_CTL, is used as on/off control for the output LEDs. Bit 1 and Bit 2, named PWM_SEL and PWM_MD, control the operating mode of the device, respectively. If the BL_CRT bit is set to 1, the device turns on the backlight within 10 ms after the write cycle. If the BL_CRT bit is set to 0, the device turns off the backlight immediately. The ADD5203 output operating mode is selected by the combination of Bit 1 and Bit 2 (see Table 10). PWM_MD1 (Bit 2) X 1 0 Mode PWM mode SMBus mode SMBus mode with DPST X is don’t care. All reserved bits return to 0 when read, and the bits are ignored when written. This default value of the register is 0x00. Table 11. Brightness Control Register (Address 0x00) Bit Map MSB Bit 7 (R/W) BRT7 LSB Bit 6 (R/W) BRT6 Bit 5 (R/W) BRT5 Bit 4 (R/W) BRT4 Bit 3 (R/W) BRT3 Bit 2 (R/W) BRT2 Bit 1 (R/W) BRT1 Bit 0 (R/W) BRT0 Default Value 0xFF Table 12. Brightness Control Register (Address 0x00) Bit Description Bit Name BRT[7:0] Description 256 steps of brightness levels Table 13. Device Control Register (Address 0x01) Bit Map MSB Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 (R/W) PWM_MD Bit 1 (R/W) PWM_SEL Bit 0 (R/W) BL_CTL LSB Default Value 0x00 Rev. 0 | Page 15 of 24 ADD5203 Table 14. Device Control Register (Address 0x01) Bit Description Bit Name PWM_MD PWM_SEL BL_CTL Description PWM mode select 1 = absolute brightness, 0 = percent change (default) Brightness control select 1 = control by PWM, 0 = control by SMBus (default) Backlight on/off 1 = on, 0 = off (default) Fault/Status Register (Address 0x02) This register has six status bits that allow monitoring of the ADD5203 operating state. Bit 0, named fault, is a logical OR of all fault codes to simplify error detection. In the operation of the ADD5203, Bit 1, named THRM_SHDN, is set to 1 when a thermal shutdown event occurs. Bit 3, named BL_STAT, is the backlight status indicator. This bit is set to 1 whenever the backlight is on and is set to 0 whenever the backlight is off. Bit 4, named 1_CH_SD, is set to 1 if one or more current sources are disabled. In addition, Bit 5, named 2_CH_SD, is set to 1 if two or more current sources are disabled due to an LED open event during normal operation. All reserved bits return to 0 when read and ignore the bit value when written. All of the bits in this register are read only. The default value for Register 0x02 is 0x00. Table 15. Fault/Status Register (Address 0x02) Bit Map MSB Bit 7 Reserved Bit 6 Reserved Bit 5 (R) 2_CH_SD Bit 4 (R) 1_CH_SDS Bit 3 (R) BL_STAT Identification Register (Address 0x03) The ID register contains two bit fields to denote the manufacturer and silicon revision of the ADD5203. The bit field widths were chosen to allow up to 16 vendors with up to eight silicon revisions each. To ensure that the number of silicon revisions remains low, the revision field should not be updated until the part is sent to the factory of the end-customer. Therefore, if during the engineering development process, three silicon spins are needed before the device is released to the factory of the end-customer, the next available revision ID is used for these three spins. The manufacturer ID of Analog Devices, Inc., is 6 (Bit[6:3] = 0110b). In addition, the initial value of REVx is 0, and subsequent REVx values are incremented by 1. This register is read only. Bit 2 (R) OV_CURR Bit 1 (R) THRM_SHDN Bit 0 (R) Fault LSB Default Value 0x00 Table 16. Fault/Status Register (Address 0x01) Bit Description Bit Name 2_CH_SD_, 1_CH_SD BL_STAT OV_CURR THRM_SHDN Fault Description The number of faulted strings is reported in these bits. 00 = no faults, 01 = one string fault, 11 = two or more strings faulted. Backlight status. 1 = backlight on, 0 = backlight off (default). Input overcurrent. 1 = overcurrent condition, 0 = current ok (default). Thermal shutdown. 1 = thermal fault, 0 = thermal ok (default). Fault occurred. Logic OR of all the fault conditions. Table 17. Identification Register (Address 0x03) Bit Map MSB Bit 7 LED panel Bit 6 MFG3 Bit 5 (R) MFG2 Bit 4 (R) MFG1 Bit 3 (R) MFG0 Bit 2 (R) REV2 Bit 1 (R) REV1 Bit 0 (R) REV0 LSB Default Value 0xB0 Table 18. Identification Register (Address 0x03) Bit Description Bit Name LED Panel MFG[3:0] REV[2:0] Description Display panel using LED backlight, Bit 7 = 1. Manufacturer ID (Analog Devices ID is 6). Silicon revision (Revision 0 to Revision 7 are allowed for silicon spins). Rev. 0 | Page 16 of 24 ADD5203 EXTERNAL COMPONENT SELECTION GUIDE Inductor Selection The inductor is an integral part of the step-up converter. It stores energy during the switch-on time and transfers that energy to the output through the output diode during the switch-off time. An inductor in the range of 4.7 μH to 22 μH is recommended. In general, lower inductance values result in higher saturation current and lower series resistance for a given physical size. However, lower inductance results in higher peak current, which can lead to reduced efficiency and greater input and/or output ripple and noise. Peak-to-peak inductor ripple current at close to 30% of the maximum dc input current typically yields an optimal compromise. The input (VIN) and output (VOUT) voltages determine the switch duty cycle (D), which in turn can be used to determine the inductor ripple current. are preferred because of their low ESR characteristics. Alternatively, use a high value, medium ESR capacitor in parallel with a 0.1 μF low ESR capacitor as close as possible to the ADD5203. The output capacitor maintains the output voltage and supplies current to the load while the ADD5203 switch is on. The value and characteristics of the output capacitor greatly affect the output voltage ripple and stability of the regulator. Use a low ESR output capacitor; ceramic dielectric capacitors are preferred. For very low ESR capacitors, such as ceramic capacitors, the ripple current due to the capacitance is calculated as follows. Because the capacitor discharges during the on time (tON), the charge removed from the capacitor (QC) is the load current multiplied by the on time. Therefore, the output voltage ripple (ΔVOUT) is ΔVOUT = QC C OUT = I L × t ON C OUT D= VOUT − V IN VOUT Use the duty cycle and switching frequency (fSW) to determine the on time. where: COUT is the output capacitance. IL is the average inductor current. Using the duty cycle and switching frequency (fSW), users can determine the on time with the following equation: t ON = D f SW The inductor ripple current (ΔIL) in a steady state is t ON = D f SW V ×t ΔI L = IN ON L Solve for the inductance value (L). The input (VIN) and output (VOUT) voltages determine the switch duty cycle (D) with the following equation: D= VOUT − V IN VOUT L= V IN × t ON ΔI L Make sure that the peak inductor current (that is, the maximum input current plus half of the inductor ripple current) is less than the rated saturation current of the inductor. In addition, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator. For duty cycles greater than 50% that occur with input voltages greater than half the output voltage, slope compensation is required to maintain stability of the current-mode regulator. The inherent open-loop stability causes subharmonic instability when the duty ratio is greater than 50%. To avoid subharmonic instability, the slope of the inductor current should be less than half of the compensation slope. Inductor manufacturers include Coilcraft, Inc., Sumida Corporation, and Toko. Choose the output capacitor based on the following equation: C OUT ≥ I L × (VOUT − V IN ) f SW × VOUT × ΔVOUT Capacitor manufacturers include Murata Manufacturing Co., Ltd., AVX, Sanyo, and Taiyo Yuden Co., Ltd. Diode Selection The output diode conducts the inductor current to the output capacitor and loads while the switch is off. For high efficiency, minimize the forward voltage drop of the diode. Schottky diodes are recommended. However, for high voltage, high temperature applications, where the Schottky diode reverse leakage current becomes significant and can degrade efficiency, use an ultrafast junction diode. The output diode for a boost regulator must be chosen depending on the output voltage and the output current. The diode must be rated for a reverse voltage equal to or greater than the output voltage used. The average current rating must be greater than the maximum load current expected, and the peak current rating must be greater than the peak inductor current. Using Schottky diodes with lower forward voltage drop decreases power dissipation and increases efficiency. The diode must be rated to handle the average output load current. Many diode Input and Output Capacitors Selection The ADD5203 requires input and output bypass capacitors to supply transient currents while maintaining a constant input and output voltage. Use a low effective series resistance (ESR) 10 μF or greater capacitor for the input capacitor to prevent noise at the ADD5203 input. Place the input between the VIN and GND, as close as possible to the ADD5203. Ceramic capacitors Rev. 0 | Page 17 of 24 ADD5203 manufacturers derate the current capability of the diode as a function of the duty cycle. Verify that the output diode is rated to handle the average output load current with the minimum duty cycle. The minimum duty cycle of the ADD5203 is LAYOUT GUIDELINES When designing a high frequency, switching, regulated power supply, layout is very important. Using a good layout can solve many problems associated with these types of supplies. The main problems are loss of regulation at high output current and/or large input-to-output voltage differentials, excessive noise on the output and switch waveforms, and instability. Using the following guidelines can help minimize these problems. Make all power (high current) traces as short, direct, and thick as possible. It is good practice on a standard printed circuit board (PCB) to make the traces an absolute minimum of 15 mil (0.381 mm) per ampere. Place the inductor, output capacitors, and output diode as close to each other as possible. This helps reduce the EMI radiated by the power traces that are due to the high switching currents through them. This also reduces lead inductance and resistance, which, in turn, reduce noise spikes, ringing, and resistive losses that produce voltage errors. The grounds of the IC, input capacitors, output capacitors, and output diode (if applicable), should be connected close together, directly to a ground plane. It is also a good idea to have a ground plane on both sides of the PCB. This reduces noise by reducing ground loop errors and by absorbing more of the EMI radiated by the inductor. For multilayer boards of more than two layers, a ground plane can be used to separate the power plane (power traces and components) and the signal plane (feedback, compensation, and components) for improved performance. On multilayer boards, the use of vias is required to connect traces and different planes. If a trace needs to conduct a significant amount of current from one plane to the other, it is good practice to use one standard via per 200 mA of current. Arrange the components so that the switching current loops curl in the same direction. Due to how switching regulators operate, there are two power states: one state when the switch is on, and one when the switch is off. During each state, there is a current loop made by the power components currently conducting. Place the power components so that the current loop is conducting in the same direction during each of the two states. This prevents magnetic field reversal caused by the traces between the two half cycles and reduces radiated EMI. D MIN = VOUT − V IN_MAX VOUT where VIN_MAX is the maximum input voltage. For example, DMIN is 0.5 when VOUT is 30 V and VIN_MAX is 15 V. Schottky diode manufacturers include ON Semiconductor, Diodes Incorporated, Central Semiconductor Corp., and Sanyo. Loop Compensation The external inductor, output capacitor, and the compensation resistor and capacitor determine the loop stability. The inductor and output capacitor are chosen based on performance, size, and cost. The compensation resistor (RC) and compensation capacitor (CC ) at the COMP pin are selected to optimize control loop stability. For most applications, the compensation resistor should be in the range of 500 Ω to 30 kΩ , and the compensation capacitor should be in the range of 100 pF to 330 nF. REF VHR GMEA RC CC C2 08717-024 Figure 24. Compensation Components A step-up converter produces an undesirable right-half plane zero in the regulation feedback loop. Capacitor C2 is chosen to cancel the zero introduced by output capacitance ESR. Solving for C2 C2 = ESR × C OUT RC For low ESR output capacitance, such as with a ceramic capacitor, C2 is optional. Rev. 0 | Page 18 of 24 ADD5203 Layout Procedure To achieve high efficiency, good regulation, and stability, a good PCB layout is required. It is recommended that the reference board layout be followed as closely as possible because it is already optimized for high efficiency and low noise. Use the following general guidelines when designing PCBs: • • • • • • • • Keep CIN close to the VIN and GND leads of the ADD5203. Keep the high current path from CIN (through L1) to the SW and GND leads as short as possible. Keep the high current path from CIN (through L1), D1, and COUT as short as possible. Keep high current traces as short and wide as possible. Keep nodes connected to SW away from sensitive traces, such as COMP, to prevent coupling of the traces. If such traces need to be run near each other, place a ground trace between the two as a shield. • Place the compensation components as close as possible to the COMP pin. Place the LED current setting resistors as close as possible to each pin to prevent noise pickup. Avoid routing noise sensitive traces near high current traces and components, especially the LED current setting node (ISET). Use a thermal pad size that is the same dimension as the exposed pad on the bottom of the package. Heat Sinking When using a surface-mount power IC or external power switches, the PCB can often be used as the heat sink. This is accomplished by using the copper area of the PCB to transfer heat from the device. Users should maximize this area to optimize thermal performance. Rev. 0 | Page 19 of 24 ADD5203 TYPICAL APPLICATION CIRCUITS VIN 6V TO 21V NC 25 23 24 22 L1 10µH D1 R1 1.2MΩ R2 40kΩ C3 30pF C4 4µF VOUT UP TO 45V C1 2µF C2 0.1µF SHDN 26 VIN 1 6 5 4 SW SW OVP PWMI SCL SDA VDDIO NC 16 C3 1µF ADD5203 FB1 7 FB2 8 FB3 9 FB4 10 FB5 12 R7 10kΩ 2 3 SEL1 SEL2 19 C_FPWM R_FPWM FB6 13 FB7 14 FB8 15 PGND 20 C7 20pF R6 15kΩ 18 27 FSLCT ISET 17 R5 470kΩ PGND 21 COMP 28 AGND 11 R3 150kΩ Figure 25. Typical Application Circuit for SMBus Interface with No Delay Dimming Mode Rev. 0 | Page 20 of 24 08717-025 C5 100nF R4 5.6kΩ C6 OPEN ADD5203 VIN 6V TO 21V NC 25 23 24 22 L1 10µH D1 R1 1.2MΩ R2 40kΩ C3 30pF C4 4µF VOUT UP TO 45V C1 2µF C2 0.1µF NC NC C8 1µF SHDN 26 VIN 1 6 5 4 SW SW OVP PWMI SCL SDA VDDIO NC 16 ADD5203 FB1 7 FB2 8 FB3 9 FB4 10 FB5 12 FB6 13 FB7 14 FB8 15 2 3 SEL1 SEL2 19 C_FPWM R_FPWM C7 20pF R6 15kΩ 18 27 FSLCT PGND 20 PGND 21 ISET 17 R5 470kΩ COMP 28 AGND 11 R3 150kΩ Figure 26. Typical Application Circuit for PWM Interface with DPWM Dimming Mode Rev. 0 | Page 21 of 24 08717-026 C5 100nF R4 5.6kΩ C6 OPEN ADD5203 VIN 6V TO 21V NC 25 23 24 22 L1 10µH D1 R1 1.2MΩ R2 40kΩ C3 30pF C4 4µF VOUT UP TO 45V C1 2µF C2 0.1µF NC NC C8 1µF SHDN 26 VIN 1 6 5 4 SW SW OVP PWMI SCL SDA VDDIO NC 16 ADD5203 FB1 7 FB2 8 FB3 9 FB4 10 FB5 12 FB6 13 FB7 14 FB8 15 2 SEL1 SEL2 NC 3 19 C_FPWM R_FPWM C7 20pF R6 15kΩ 18 27 FSLCT PGND 20 PGND 21 ISET 17 R5 470kΩ COMP 28 AGND 11 R3 150kΩ Figure 27. Typical Application Circuit for PWM Interface with DC Current Dimming Mode Rev. 0 | Page 22 of 24 08717-027 C5 100nF R4 5.6kΩ C6 OPEN ADD5203 OUTLINE DIMENSIONS PIN 1 INDICATOR 4.00 BSC SQ 0.25 0.20 0.15 22 28 1 PIN 1 INDICATOR 0.40 BSC 21 EXPOSED PAD 2.70 2.60 SQ 2.50 7 15 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.45 0.40 0.35 14 8 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGE. Figure 28. 28-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm × 0.75 mm Body, Very Very Thin Dual (CP-28-5) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADD5203ACPZ-RL 1 Temperature Range −25°C to +85°C Package Description 28-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 112108-A Package Option CP-28-5 Z = RoHS Compliant Part. Rev. 0 | Page 23 of 24 ADD5203 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08717-0-5/10(0) Rev. 0 | Page 24 of 24