a
Complete Low Cost
12-Bit D/A Converters
ADDAC80/ADDAC85/ADDAC87
FEATURES
Single Chip Construction
On-Board Output Amplifier
Low Power Dissipation: 300 mW
Monotonicity Guaranteed over Temperature
Guaranteed for Operation with 12 V Supplies
Improved Replacement for Standard DAC80, DAC800
Hl-5680
High Stability, High Current Output
Buried Zener Reference
Laser Trimmed to High Accuracy
1/2 LSB Max Nonlinearity
Low Cost Plastic Packaging
FUNCTIONAL BLOCK DIAGRAM
(MSB) BIT 1 1
REF
CONTROL
CIRCUIT
BIT 2 2
BIT 3 3
BIT 4 4
BIT 5 5
BIT 6 6
5k
VREF OUT
23
GAIN ADJUST
22
+VS
21
COMMON
20
SUMMING JUNCTION
19
20V RANGE
18
10V RANGE
17
BIPOLAR OFFSET
16
REF INPUT
5k
TE
BIT 7 7
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
24
BIT 8 8
BIT 9 9
6.3k
–
BIT 10 10
15
VOUT
14
–VS
13
NC/+VL*
+
BIT 11 11
ADDAC80
(LSB) BIT 12 12
PRODUCT DESCRIPTION
LE
*NC = CBI VERSIONS
5V – CCD VERSIONS
The ADDAC80 Series is a family of low cost 12-bit digital-toanalog converters with both a high stability voltage reference
and output amplifier combined on a single monolithic chip.
The ADDAC80 Series is recommended for all low cost 12-bit D/A
converter applications where reliability and cost are of paramount
importance.
(MSB) BIT 1 1
BIT 2 2
BIT 3 3
BIT 4 4
BIT 5 5
B
SO
Advanced circuit design and precision processing techniques
result in significant performance advantages over conventional
DAC80 devices. Innovative circuit design reduces the total
power consumption to 300 mW, which not only improves reliability, but also improves long term stability.
O
The ADDAC80 incorporates a fully differential, nonsaturating
precision current switching cell structure which provides greatly
increased immunity to supply voltage variation. This same structure also reduces nonlinearities due to thermal transients as the
various bits are switched; nearly all critical components operate
at constant power dissipation. High stability, SiCr thin film
resistors are trimmed with a fine resolution laser, resulting in
lower differential nonlinearity errors. A low noise, high stability,
subsurface Zener diode is used to produce a reference voltage
with excellent long term stability, high external current capability and temperature drift characteristics which challenge the
best discrete Zener references.
The ADDAC80 Series is available in three performance grades
and three package types. The ADDAC80 is specified for use
over the 0°C to 70°C temperature range and is available in
both plastic and ceramic DIP packages. The ADDAC85 and
ADDAC87 are available in hermetically sealed ceramic packages
and are specified for the –25°C to +85°C and –55°C to +125°C
temperature ranges.
REF
CONTROL
CIRCUIT
BIT 6 6
BIT 7 7
BIT 8 8
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
BIT 9 9
2k
5k
5k
24
VREF OUT
23
GAIN ADJUST
22
+VS
21
COMMON
20
SCALING NETWORK
19
SCALING NETWORK
18
SCALING NETWORK
17
BIPOLAR OFFSET
16
REF INPUT
6.3k
BIT 10 10
15
IOUT
BIT 11 11
14
–VS
13
NC/+VL*
(LSB) BIT 12 12
*NC = CBI VERSIONS
5V – CCD VERSIONS
PRODUCT HIGHLIGHTS
1. The ADDAC80 series of D/A converters directly replaces all
other devices of this type with significant increases in performance.
2. Single chip construction and low power consumption provides the optimum choice for applications where low cost
and high reliability are major considerations.
3. The high speed output amplifier has been designed to settle
within 1/2 LSB for a 10 V full scale transition in 2.0 µs, when
properly compensated.
4. The precision buried Zener reference can supply up to 2.5 mA
for use elsewhere in the application.
5. The low TC binary ladder guarantees that all units are monotonic over the specified temperature range.
6. System performance upgrading is possible without redesign.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
(TA = 25C, rated power supplies
unless otherwise noted.)
ADDAC80/ADDAC85/ADDAC87–SPECIFICATIONS
Min
TECHNOLOGY
ADDAC80
Typ
Max
Min
Monolithic
5.5
0.8
250
100
2.0
0
5.5
0.8
250
100
± 1/2
± 1/4
± 3/4
0
+70
± 0.1
± 0.05
–25
CONVERSION SPEED
Voltage Model (V)5
Settling Time to ± 0.01% of FSR for
FSR Change (2 kΩ储500 pF load)
with 10 kΩ Feedback
with 5 kΩ Feedback
For LSB Change
Slew Rate
3
2
1
± 0.12
± 0.08
4
3
3
2
1
O
–CCD
Output Current
Output Impedance (dc)
Short Circuit Current
Internal Reference Voltage (VR)
Output Impedance
Max External Current6
Tempco of Drift
6.3
1.5
± 10
POWER SUPPLY SENSITIVITY
± 15 V ± 10%, 5 V supply when applicable
± 12 V ± 5%
POWER SUPPLY REQUIREMENTS
Rated Voltages
Range
Analog Supplies
Logic Supplies
Supply Drain
+12 V, +15 V
–12 V, –15 V
6.23
2.5
± 20
6.3
1.5
± 10
± 15
5
14
± 11.47
10
20
LSB1
LSB
LSB
± 3/4
±1
± 0.2
± 0.1
LSB
LSB
LSB
%FSR3
%FSR3
+125
°C
± 30
ppm of FSR/°C
% of FSR
% of FSR
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
4
3
3
2
1
4
3
µs
µs
µs
V/µs
10
± 2.5, ± 5,
± 10, +5,
10
2.5
± 20
2.5
± 10
V
V
V
V
mA
Ω
mA
V
Ω
mA
ppm of VR/°C
0.002
0.002
0.002
0.002
% of FSR/%VS
% of FSR/%VS
0.05
40
6.37
6.23
6.3
1.5
40
6.37
± 15
± 16.5
5
14
–2–
± 1/2
± 0.3
± 0.24
± 20
± 10
±3
± 10
± 15
± 16.5
V
V
µA
µA
±5
0.002
0.002
± 11.47
–55
0.05
40
6.37
5.5
0.8
250
100
± 0.18
± 0.14
±5
0.05
6.23
± 0.1
± 0.05
±2.5, ±5,
± 10, +5,
10
±5
Bits
Digits
± 0.2
± 0.12
± 20
± 10
±3
± 10
10
±2.5, ±5,
± 10, +5,
10
12
± 3/4
± 20
± 0.15
± 0.10
± 30
±7
±3
± 10
10
ANALOG OUTPUT
Voltage Models
Ranges–CBI
± 1/2
±1
± 0.2
± 0.1
+85
± 20
± 0.08
± 0.06
± 15
±4
±1
±5
± 1/2
± 3/4
± 3/4
± 0.3
± 0.15
± 0.1
± 0.05
2.0
0
± 1/2
± 1/2
± 1/4
Unit
Monolithic
12
B
SO
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error @ 25°C
CBI
CCD
TA @ TMIN to TMAX
Differential Linearity Error @ 25°C
CBI
CCD
TA @ TMIN to TMAX
Gain Error2
Offset Error2
Temperature Range for Guaranteed
Monotonicity
DRIFT (TMIN to TMAX)
Total Bipolar Drift, max (includes gain,
offset, and linearity drifts)
Total Error (TMIN to TMAX)4
Unipolar
Bipolar
Gain Including Internal Reference
Gain Excluding Internal Reference
Unipolar Offset
Bipolar Offset
ADDAC87
Typ
Max
Monolithic
12
2.0
0
Min
LE
DIGITAL INPUT
Binary–CBI
BCD–CCD
Logic Levels (TTL Compatible)
VIH (Logic “1”)
VIL (Logic “0”)
IIH (VIH = 5.5 V)
IIL (VIL = 0.8 V)
ADDAC85
Typ
Max
TE
Model
10
20
± 11.47
5
14
V
± 16.5
V
V
10
20
mA
mA
REV. B
ADDAC80/ADDAC85/ADDAC87
Model
Min
TEMPERATURE RANGE
Specifications
Operating
Storage
0
–25
–25
ADDAC80
Typ
Max
+70
+85
+125
Min
ADDAC85
Typ
Max
–25
–55
–65
+85
+125
+150
Min
ADDAC87
Typ
Max
–55
–55
–65
+125
+125
+150
Unit
°C
°C
°C
NOTES
1
Least Significant Bit.
2
Adjustable to zero with external trim potentiometer.
3
FSR means “Full Scale Range” and is 20 V for the ± 10 V range and 10 V for the ± 5 V range.
4
Gain and offset errors adjusted to zero at 25°C.
5
CF = 0, see Figure 3a.
6
Maximum with no degradation of specification, must be a constant load.
7
A minimum of ± 12.3 V is required for a ± 10 V full scale output and ± 11.4 V is required for all other voltage ranges.
Specifications subject to change without notice.
Min
TECHNOLOGY
DIGITAL INPUT
Binary–CBI
BCD–CCD
Logic Levels (TTL Compatible)
VIH (Logic “1”)
VIL (Logic “0”)
IIH (VIH = 5.5 V)
IIL (VIL = 0.8 V)
Min
Hybrid
12
3
2.0
0
5.5
0.8
REV. B
± 1/2
± 1/4
± 1/2
± 1/2
± 1/4
± 3/4
± 1/2
±1
± 0.3
± 0.15
0
10
+70
ADDAC87
Typ
Max
2.0
0
5.5
0.8
± 1/4
± 1/2
± 1/2
± 0.1
± 0.05
0
Unit
Hybrid
2.0
0
250
–100
± 1/4
± 1/8
± 1/4
± 0.1
± 0.05
Min
12
3
250
–100
O
CONVERSION SPEED
Voltage Model (V)5
Settling Time to ± 0.01% of FSR for
FSR Change (2 kΩ储500 pF load)
with 10 kΩ Feedback
with 5 kΩ Feedback
For LSB Change
Slew Rate
Current Model (I)
Settling time to ± 0.01% of FSR for
FSR Change
10 Ω to 100 Ω Load
for 1 kΩ
ADDAC85
Typ
Max
Hybrid
B
SO
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error @ 25°C
CBI
CCD
TA @ TMIN to TMAX
Differential Linearity Error @ 25°C
CBI
CCD
TA @ TMIN to TMAX
Gain Error2
Offset Error2
Temperature Range for Guaranteed
Monotonicity
DRIFT (TMIN to TMAX)
Total Bipolar Drift, max (includes gain,
offset, and linearity drifts)
Total Error (TMIN to TMAX)4
Unipolar
Bipolar
Gain
Including Internal Reference
Excluding Internal Reference
Unipolar Offset
Bipolar Offset
ADDAC80
Typ
Max
LE
Model
TE
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Bits
Digits
5.5
0.8
V
V
µA
µA
± 1/2
± 1/4
± 1/2
LSB1
LSB
LSB
±1
LSB
LSB
LSB
%FSR3
%FSR3
+85
°C
250
–100
± 1/2
± 1/4
± 1/2
± 1/2
± 1/2
± 1/2
±1
+70
12
3
± 0.1
± 0.05
–25
± 20
ppm of FSR/°C
± 0.08
± 0.06
± 0.15
± 0.10
% of FSR
% of FSR
± 15
±5
±1
±5
± 30
±7
±3
± 10
±1
± 20
± 10
± 10
±1
± 20
± 10
± 10
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
5
3
1.5
15
5
3
1.5
20
5
3
1.5
20
µs
µs
µs
V/µs
300
1
300
1
300
1
ns
µs
–3–
ADDAC80/ADDAC85/ADDAC87–SPECIFICATIONS (continued)
ANALOG OUTPUT
Voltage Models
Ranges–CBI
Ranges–CCD
Output Current
Output Impedance (dc)
Short Circuit Duration
Current Models
Ranges–Unipolar
Ranges–Bipolar
Output Impedance
Bipolar
Unipolar
Compliance
Internal Reference Voltage (VR)
Output Impedance
Max External Current6
Tempco of Drift
±5
6.17
Min
±5
ADDAC85
Typ
Max
± 2.5, ± 5,
± 10, +5,
+10
+10
0.05
Indefinite to Common
±5
ADDAC87
Typ
Max
± 2.5, ± 5,
± 10, +5,
+10
+10
0.05
Indefinite to Common
Unit
V
V
mA
Ω
–2.0
± 1.0
–2.0
± 1.0
mA
mA
3.2
6.6
–1.5, +10
6.3
6.43
1.5
2.5
± 10
± 20
3.2
6.6
–2.5, +10
6.3
6.43
1.5
2.5
± 10
± 20
3.2
6.6
–2.5, +10
6.3
6.43
1.5
2.5
± 10
± 20
kΩ
kΩ
V
V
Ω
mA
ppm of VR/°C
6.17
6.17
± 0.002
± 0.002
± 0.002
% of FSR/%VS
± 15, +5
± 15, +5
± 15, +5
V
± 14
4.5
± 16
16
10
20
8
0
–25
–55
Min
–2.0
± 1.0
± 14.5
4.5
20
35
20
± 15.5
15.5
15
25
15
B
SO
TEMPERATURE RANGE
Specifications
Operating
Storage
± 2.5, ± 5,
± 10, +5,
+10
± 10
0.05
Indefinite to Common
POWER SUPPLY SENSITIVITY
± 15 V ± 10%, 5 V Supply When Applicable
POWER SUPPLY REQUIREMENTS
Rated Voltages
Range
Analog Supplies
Logic Supplies
Supply Drain7
+15 V
–15 V
+5 V8
ADDAC80
Typ
Max
TE
Min
LE
Model
+70
+85
+130
0
–25
–65
± 14.5
4.5
20
30
20
+70
+85
+150
–25
–55
–65
15
25
15
± 15.5
15.5
V
V
20
30
20
mA
mA
mA
+85
+125
+150
°C
°C
°C
NOTES
1
Least Significant Bit.
2
Adjustable to zero with external trim potentiometer.
3
FSR means “Full Scale Range” and is 20 V for the ± 10 V range and 10 V for the ± 5 V range.
4
Gain and offset errors adjusted to zero at 25°C.
5
CF = 0, see Figure 3a.
6
Maximum with no degradation of specification, must be a constant load.
7
Including 5 mA load.
8
5 V supply required only for CCD versions.
O
Specifications subject to change without notice.
–4–
REV. B
ADDAC80/ADDAC85/ADDAC87
ADDAC85LD
Min
Typ
Max
TECHNOLOGY
Hybrid
12
2.0
0
5.5
0.8
2.0
0
250
–100
–25
± 1/2
± 3/4
± 0.1
± 0.05
–55
±1
O
ANALOG OUTPUT
Voltage Models
Ranges–CBI
POWER SUPPLY SENSITIVITY
±15 V ± 10%, 5 V supply when applicable
REV. B
5.5
0.8
V
V
µA
µA
± 1/2
± 3/4
LSB1
LSB
LSB
±1
± 0.2
± 0.1
LSB
LSB
LSB
%FSR3
%FSR3
+125
°C
± 15
± 30
ppm of FSR/°C
± 0.13
± 0.12
± 0.30
± 0.24
% of FSR
% of FSR
± 10
±5
±1
±5
± 25
± 10
±3
± 10
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
± 1/4
± 1/2
±1
+125
± 0.1
± 0.05
–55
± 20
±5
Bits
Digits
2.0
0
± 1/2
+85
12
250
–100
± 1/2
± 10
CONVERSION SPEED
Voltage Model (V)5
Settling Time to ± 0.01% of FSR
for FSR change (2 kΩ储500 pF load)
with 10 kΩ Feedback
with 5 kΩ Feedback
For LSB Change
Slew Rate
Current Model (I)
Settling Time to ± 0.01% of FSR
for FSR Change
10 Ω to 100 Ω Load
for 1 kΩ
Ranges–CCD
Output Current
Output Impedance (dc)
Short Circuit Duration
Current Models
Ranges–Unipolar
Ranges–Bipolar
Output Impedance
Bipolar
Unipolar
Compliance
Internal Reference Voltage (VR)
Output Impedance
Max External Current6
Tempco of Drift
5.5
0.8
± 1/2
±1
±2
± 10
5
3
1.5
20
5
3
1.5
20
5
3
1.5
20
µs
µs
µs
V/µs
300
1
300
1
300
1
ns
µs
± 2.5, ± 5,
± 10, +5,
+10
± 2.5, ± 5,
± 10, +5,
+10
± 2.5, ± 5,
± 10, +5,
+10
±5
±5
±5
0.05
Indefinite to Common
0.05
Indefinite to Common
0.05
Indefinite to Common
6.17
Unit
Hybrid
250
–100
± 1/2
± 0.1
± 0.05
ADDAC87
Typ
Max
12
B
SO
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error @ 25°C
CBI
CCD
TA @ TMIN to TMAX
Differential Linearity Error @ 25°C
CBI
CCD
TA @ TMIN to TMAX
Gain Error2
Offset Error2
Temperature Range for Guaranteed
Monotonicity
DRIFT (TMIN to TMAX)
Total Bipolar Drift, max (includes gain,
offset, and linearity drifts)
Total Error (TMIN to TMAX)4
Unipolar
Bipolar
Gain
Including Internal Reference
Excluding Internal Reference
Unipolar Offset
Bipolar Offset
Hybrid
Min
LE
DIGITAL INPUT
Binary–CBI
BCD–CCD
Logic Levels (TTL Compatible)
VIH (Logic “1”)
VIL (Logic “0”)
IIH (VIH = 5.5 V)
IIL (VIL = 0.8 V)
ADDAC85MIL
Min
Typ
Max
TE
Model
–2.0
± 1.0
–2.0
± 1.0
3.2
6.6
–2.5, +10
6.3
6.43
1.5
2.5
± 10
± 20
3.2
6.6
–2.5, +10
6.3
6.43
1.5
2.5
± 10
± 20
6.17
± 0.002
± 0.002
–5–
2.5
5.0
6.17
V
V
mA
Ω
–2.0
± 1.0
mA
mA
3.2
4.1
6.6
8.2
–1.5, +10
6.3
6.43
1.5
2.5
±5
± 10
kΩ
kΩ
V
V
Ω
mA
ppm of VR/°C
± 0.002 ± 0.003
% of FSR/%VS
ADDAC80/ADDAC85/ADDAC87–SPECIFICATIONS (continued)
ADDAC85LD
Min
Typ
Max
Model
POWER SUPPLY REQUIREMENTS
Rated Voltages
Range
Analog Supplies
Logic Supplies
Supply Drain7
+15 V
–15 V
+5 V8
ADDAC85MIL
Min
Typ
Max
± 15, 5
ADDAC87
Typ
Max
± 15, 5
± 14.5
+4.5
± 15.5
± 15.5
15
25
15
TEMPERATURE RANGE
Specification
Operating
Storage
Min
± 14.5
+4.5
20
30
20
–25
–55
–55
+85
+125
+125
± 15, 5
± 15.5
+15.5
15
25
15
–55
–55
–55
Unit
± 13.5
+4.5
20
30
20
+125
+125
+125
V
10
20
10
–55
–55
–65
± 16.5
± 16.5
V
V
20
35
20
mA
mA
mA
+125
+125
+150
°C
°C
°C
TE
NOTES
1
Least Significant Bit.
2
Adjustable to zero with external trim potentiometer.
3
FSR means “Full-Scale Range” and is 20 V for the ± 10 V range and 10 V for the ± 5 V range.
4
Gain and offset errors adjusted to zero at 25°C.
5
CF = 0, see Figure 3a.
6
Maximum with no degradation of specification, must be a constant load.
7
Including 5 mA load.
8
5 V supply required only for CCD versions.
LE
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
(MSB) BIT 1 1
BIT 2 2
BIT 3 3
BIT 4 4
REF
CONTROL
CIRCUIT
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
O
BIT 5 5
B
SO
+VS to Power Ground . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
–VS to Power Ground . . . . . . . . . . . . . . . . . . . . 0 V to –18 V
Digital Inputs (Pins 1 to 12) to Power Ground . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7 V
Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . ± 12 V
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . ± 12 V
10 V Span R to Reference Ground . . . . . . . . . . . . . . . ± 12 V
20 V Span R to Reference Ground . . . . . . . . . . . . . . . ± 24 V
Ref Out . . . . . . . . . Indefinite Short to Power Ground or +VS
BIT 6 6
BIT 7 7
BIT 8 8
BIT 9 9
BIT 10 10
5k
VREF OUT
23
GAIN ADJUST
BIT 2 2
22
+VS
BIT 3 3
21
COMMON
BIT 4 4
20
SUMMING JUNCTION
BIT 5 5
19
20V RANGE
BIT 6 6
18
10V RANGE
BIT 7 7
17
BIPOLAR OFFSET
BIT 8 8
16
REF INPUT
BIT 9 9
15
VOUT
BIT 10 10
15
IOUT
14
–VS
BIT 11 11
14
–VS
13
NC/+VL*
13
NC/+VL*
5k
6.3k
–
+
BIT 11 11
(LSB) BIT 12 12
24
ADDAC80
(MSB) BIT 1 1
REF
CONTROL
CIRCUIT
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
2k
5k
5k
VREF OUT
23
GAIN ADJUST
22
+VS
21
COMMON
20
SCALING NETWORK
19
SCALING NETWORK
18
SCALING NETWORK
17
BIPOLAR OFFSET
16
REF INPUT
6.3k
(LSB) BIT 12 12
*NC = CBI VERSIONS
5V – CCD VERSIONS
24
*NC = CBI VERSIONS
5V – CCD VERSIONS
Figure 1. Voltage Model Function Diagram
and Pin Configuration
Figure 2. Current Model Functional Diagram
and Pin Configuration
–6–
REV. B
ADDAC80/ADDAC85/ADDAC87
ORDERING GUIDE
Input
Code
Output
Mode
Technology
Temperature
Range
Linearity
Error
Package
Option1
ADDAC80N-CBI-V
ADDAC80D-CBI-V
ADDAC85D-CBI-V
ADDAC87D-CBI-V
ADDAC80-CBI-V
ADDAC80-CBI-I
ADDAC80-CCD-V
ADDAC80-CCD-I
ADDAC80Z-CBI-V2
ADDAC80Z-CBI-I2
ADDAC80Z-CCD-V2
ADDAC80Z-CCD-I2
ADDAC85C-CBI-V3
ADDAC85C-CBI-I
ADDAC85-CBI-V3
ADDAC85-CBI-I3
ADDAC85LD-CBI-V3
ADDAC85LD-CBI-I3
ADDAC85MIL-CBI-V3
ADDAC85MIL-CBI-I3
ADDAC85C-CCD-V3
ADDAC85C-CCD-I3
ADDAC85-CCD-V3
ADDAC85-CCD-I3
ADDAC85MILCBII8
ADDAC85MILCBIV8
ADDAC87-CBI-V3
ADDAC87-CBI-I3
ADDAC87-CBII883
ADDAC87-CBIV883
Binary
Binary
Binary
Binary
Binary
Binary
Binary Coded Decimal
Binary Coded Decimal
Binary
Binary
Binary Coded Decimal
Binary Coded Decimal
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary Coded Decimal
Binary Coded Decimal
Binary Coded Decimal
Binary Coded Decimal
Binary
Binary
Binary
Binary
Binary
Binary
Voltage
Voltage
Voltage
Voltage
Voltage
Current
Voltage
Current
Voltage
Current
Voltage
Current
Voltage
Current
Voltage
Current
Voltage
Current
Voltage
Current
Voltage
Current
Voltage
Current
Current
Voltage
Voltage
Current
Current
Voltage
Monolithic
Monolithic
Monolithic
Monolithic
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
0°C to 70°C
0°C to 70°C
–25°C to +85°C
–55°Cto +125°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
0°C to 70°C
0°C to 70°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/4 LSB
± 1/4 LSB
± 1/2 LSB
± 1/2 LSB
± 1/4 LSB
± 1/4 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/4 LSB
± 1/4 LSB
± 1/4 LSB
± 1/4 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
N-24A
D-24
D-24
D-24
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
DH-24A
B
SO
LE
TE
Model
NOTES
1
For outline information see Package Information section.
2
Z-Suffix devices guarantee performance of 0 V to +5 V and ± 5 V spans with minimum supply voltages of ± 11.4 V.
3
These models have been discontinued. This is for historical information only.
PRODUCT OFFERING
O
Analog Devices has developed a number of technologies to
support products within the data acquisition market. In serving
the market new products are implemented with the technology
best suited to the application. The DAC80 series of products was
first implemented in hybrid form and now it is available in a single
monolithic chip. We will provide both the hybrid and monolithic versions of the family so that in existing designs changes to
documentation or product qualification will not have to be done.
Specifications and ordering information for both versions are
delineated in this data sheet.
DIGITAL INPUT CODES
Digital Input
MSB
LSB
000000000000
011111111111
100000000000
111111111111
Analog Input
CSB
Compl.
Straight
Binary
COB
Compl.
Offset
Binary
CTC*
Compl.
Two’s
Compl.
+Full-Scale
+1/2 Full-Scale
Midscale
Zero
+Full-Scale
Zero
–1 LSB
–Full-Scale
–1 LSB
–Full-Scale
+Full-Scale
Zero
*Invert the MSB of the COB code with an external inverter to obtain CTC code.
The ADDAC80 Series accepts complementary digital input
code in binary (CBI) format. The CBI model may be connected
by the user for anyone of three complementary codes: CSB,
COB or CTC.
REV. B
Table I. Digital Input Codes
–7–
ADDAC80/ADDAC85/ADDAC87
ACCURACY
18
Accuracy error of a D/A converter is the difference between the
analog output that is expected when a given digital code is
applied and the output that is actually measured with that code
applied to the converter. Accuracy error can be caused by gain
error, zero error, linearity error, or any combination of the three.
Of these three specifications, the linearity error specification is
the most important since it cannot be corrected. Linearity error
is specified over its entire temperature range. This means that
the analog output will not vary by more than its maximum
specification, from an ideal straight line drawn between the
end points (inputs all “1”s and all “0”s) over the specified
temperature range.
10V
1–12
DATA
IN
SUMMING
JUNCTION
VOUT
15
2k
TEKTRONIX
7A13
100pF
20
CF
25pF
10V
HP6216A
Figure 3a. Voltage Model Settling Time Circuit
>1mV
Differential linearity error of a D/A converter is the deviation
from an ideal 1 LSB voltage change from one adjacent output
state to the next. A differential linearity error specification of
± 1/2 LSB means that the output voltage step sizes can range
from 1/2 LSB to 1 1/2 LSB when the input changes from one
adjacent input state to the next.
5V
100
TE
90
10
0%
DRIFT
Gain Drift
5V
Figure 3b. Voltage Model Settling Time CF = 25 pF
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a power
supply change on the D/A converter output. It is defined as a
percent of FSR per percent of change in either the positive or
negative supplies about the nominal power supply voltages.
B
SO
Offset Drift
LE
A measure of the change in the full scale range output over
temperature expressed in parts per million of full scale range
per °C (ppm of FSR/°C). Gain drift is established by: 1) testing
the end point differences for each ADDAC80 model at the
lowest operating temperature, 25°C and the highest operating
temperature; 2) calculating the gain error with respect to the
25°C value and; 3) dividing by the temperature change.
500ns
A measure of the actual change in output with all “1”s on the
input over the specified temperature range. The maximum
change in offset is referenced to the offset at 25°C and is
divided by the temperature range. This drift is expressed in
parts per million of full scale range per °C (ppm of FSR/°C).
REFERENCE SUPPLY
All models are supplied with an internal 6.3 V reference voltage
supply. This voltage (Pin 24) is accurate to ± 1% and must be
connected to the Reference Input (Pin 16) for specified operation. This reference may also be used externally with external
current drain limited to 2.5 mA. An external buffer amplifier is
recommended if this reference is to be used to drive other system components. Otherwise, variations in the load driven by the
reference will result in gain variations. All gain adjustments
should be made under constant load conditions.
SETTLING TIME
Settling time for each model is the total time (including slew
time) required for the output to settle within an error band
around its final value after a change in input.
Voltage Output Models
Three settling times are specified to 0.01% of full scale range
(FSR); two for maximum full scale range changes of 20 V, 10 V
and one for a 1 LSB change. The 1 LSB change is measured at
the major carry (0 1 1 1 . . . 1 1 to 1 0 0 0 . . . 0 0), the point at
which the worst case settling time occurs. The settling time
characteristic depends on the compensation capacitor selected,
the optimum value is 25 pF as shown in Figure 3a.
O
ANALYZING DEVICE ACCURACY OVER THE
TEMPERATURE RANGE
For the purposes of temperature drift analysis, the major device
components are shown in Figure 4. The reference element and
buffer amplifier drifts are combined to give the total reference
temperature coefficient. The input reference current to the
DAC, IREF, is developed from the internal reference and will
show the same drift rate as the reference voltage. The DAC
output current, IDAC, which is a function of the digital input
codes, is designed to track IREF; if there is a slight mismatch in
these currents over temperature, it will contribute to the gain
T.C. The bipolar offset resistor, RBP, and gain setting resistor,
RGAIN, also have temperature coefficients that contribute to
system drift errors. The input offset voltage drift of the output
amplifier, OA, also contributes a small error.
Current Output Models
Two settling times are specified to ± 0.01% of FSR. Each is given
for current models connected with two different resistive loads:
10 Ω to 100 Ω and 1000 Ω to 1875 Ω. Internal resistors are provided
for connecting nominal load resistances of approximately 1000 Ω
to 1800 Ω for output voltage ranges of ±1 V and 0 V to –2 V.
–8–
REV. B
ADDAC80/ADDAC85/ADDAC87
RGAIN
RBP
6.3V 6.3k
+
–
OA
+
–
IREF
IDAC
DAC
V–
Figure 4. Bipolar Configuration
There are three types of drift errors over temperature: offset,
gain, and linearity. Offset drift causes a vertical translation of
the entire transfer curve; gain drift is a change in the slope of the
curve; and linearity drift represents a change in the shape of the
curve. The combination of these three drifts results in the complete specification for total error over temperature.
Note that if the DAC and application resistors track perfectly,
the bipolar offset drift will be zero even if the reference drifts. A
change in the reference voltage, which causes a shift in the bipolar
offset, will also cause an equivalent change in IREF and thus IDAC,
so that IDAC will always be exactly balanced by IBP with the MSB
turned on. This effect is shown in Figure 5. The net effect of the
reference drift then is simply to cause a rotation in the transfer
around bipolar zero. However, consideration of second order
effects (which are often overlooked) reveals the errors in the
bipolar mode. The unipolar offset drifts previously discussed
will have the same effect on the bipolar offset. A mismatch of RBP
to the DAC resistors is usually the largest component of bipolar
drift, but in the ADDAC80 this error is held to 10 ppm/°C max.
Gain drift in the DAC also contributes to bipolar offset drift,
as well as full-scale drift, but again is held to 10 ppm/°C max.
TE
15V
ACTUAL
O
Temperature error analysis in the unipolar mode is straightforward:
there is an offset drift and a gain drift. The offset drift (which
comes from leakage currents and drift in the output amplifier
(OA)) causes a linear shift in the transfer curve as shown in
Figure 5. The gain drift causes a change in the slope of the
curve and results from reference drift, DAC drift, and drift in
RGAIN relative to the DAC resistors.
BIPOLAR RANGE ERRORS
The analysis is slightly more complex in the bipolar mode. In
this mode RBP is connected to the summing node of the output
amplifier (see Figure 4) to generate a current that exactly balances
the current of the MSB so that the output voltage is zero with
only the MSB on.
REV. B
UNIPOLAR
INPUT
GAIN SHIFT
OUTPUT
LE
B
SO
MONOTONICITY AND LINEARITY
UNIPOLAR ERRORS
IDEAL
OFFSET (ZERO) SHIFT
Several new design concepts not previously used in DAC80-type
devices contribute to a reduction in all the error factors over
temperature. The incorporation of low temperature coefficient
silicon-chromium thin-film resistors deposited on a single chip,
a patented, fully differential, emitter weighted, precision current
steering cell structure, and a T.C. trimmed buried Zener diode
reference element results in superior wide temperature range
performance. The gain setting resistors and bipolar offset resistor are also fabricated on the chip with the same SiCr material
as the ladder network, resulting in low gain and offset drift.
The initial linearity error of ± 1/2 LSB max and the differential
linearity error of ±3/4 LSB max guarantee monotonic performance
over the specified range. It can therefore be assumed that linearity
errors are insignificant in computation of total temperature errors.
GAIN SHIFT
OUTPUT
Total error is defined as the deviation from a true straight line
transfer characteristic from exactly zero at a digital input that
calls for zero output to a point that is defined as full-scale. A
specification for total error over temperature assumes that both
the zero and full-scale points have been trimmed for zero error
at 25°C. Total error is normally expressed as a percentage of the
full-scale range. In the bipolar situation, this means the total
range from –VFS to +VFS.
INPUT
OFFSET SHIFT
BIPOLAR (IDEAL CASE)
Figure 5. Unipolar and Bipolar Drifts
USING THE ADDAC80 SERIES
POWER SUPPLY CONNECTIONS
For optimum performance power supply decoupling capacitors
should be added as shown in the connection diagrams. These
capacitors (1 µF electrolytic recommended) should be located
close to the ADDAC80. Electrolytic capacitors, if used, should
be paralleled with 0.01 µF ceramic capacitors for optimum high
frequency performance.
EXTERNAL OFFSET AND GAIN ADJUSTMENT
Offset and gain may be trimmed by installing external OFFSET
and GAIN potentiometers. These potentiometers should be
connected as shown in the block diagrams and adjusted as
described below. TCR of the potentiometers should be 100 ppm/°C
or less. The 3.9 MΩ and 10 MΩ resistors (20% carbon or better)
should be located close to the ADDAC80 to prevent noise pickup.
If it is not convenient to use these high-value resistors, a functionally equivalent “T” network, as shown in Figure 8 may be
substituted in each case. The gain adjust (Pin 23) is a high
impedance point and a 0.01 µF ceramic capacitor should be
connected from this pin to common to prevent noise pickup.
–9–
ADDAC80/ADDAC85/ADDAC87
+VS
+VS
1
24
REF
CONTROL
CIRCUIT
3
6
7
8
22
0.01F
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
2k
3k
19
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
6
7
17
8
6.3k
10
15
11
14
12
13
22
5k
19
3.9M
10k
TO
100k
5k
+VS
18
1F
17
6.3k
16
–
10
15
+
–VS
1F
Figure 6. External Adjustment and Voltage Supply
Connection Diagram, Current Model
11
14
12
13
–VS
1F
Figure 7. External Adjustment and Voltage Supply
Connection Diagram, Voltage Model
Offset Adjustment
10M
270k
270k
7.8k
3.9M
180k
LE
For unipolar (CSB) configurations, apply the digital input code
that should produce zero potential output and adjust the
OFFSET potentiometer for zero output. For bipolar (COB, CTC)
configurations, apply the digital input code that should produce
the maximum negative output voltage. Example: If the FULL
SCALE RANGE is connected for 20 V, the maximum negative
output voltage is –10 V. See Table II for corresponding codes.
Gain Adjustment
10k
TO
100k
–VS
20
9
3.9M
0.01F
21
5
+VS
18
23
4
1F
5k
16
9
3
10k
TO
100k
20
10M
REF
CONTROL
CIRCUIT
2
–VS
21
4
5
23
24
TE
2
1
10k
TO
100k
10M
180k
10k
Figure 8. Equivalent Resistances
B
SO
For either unipolar or bipolar configurations, apply the digital
input that should give the maximum positive voltage output.
Adjust the GAIN potentiometer for this positive full-scale voltage.
See Table II for positive full-scale voltages.
Table II. Digital Input Analog Output
Digital Input
12-Bit Resolution
MSB
LSB
000000000000
011111111111
100000000000
111111111111
l LSB
Analog Output
Voltage*
0 to +10 V
+9.9976 V
+5.0000 V
+4.9976 V
0.0000 V
2.44 mV
10 V
+9.9951 V
0.0000 V
4.88 mV
–10.0000 V
–0.0049 V
Current
0 to –2 mA
–1.9995 mA
–1.0000 mA
–0.9995 mA
0.0000 mA
0.488 µA
1 mA
–0.9995 mA
0.0000 mA
+0.0005 mA
–1.00 mA
0.488 µA
O
*To obtain values for other binary ranges 0 to 5 V range: divide 0 to 10 values by 2; ± 5 V range: divide
± 10 V range values by 2; ± 2.5 V range: divide ± 10 V range values by 4.
–10–
REV. B
ADDAC80/ADDAC85/ADDAC87
VOLTAGE OUTPUT MODELS
TO REF CONTROL CIRCUIT
Internal scaling resistors provided in the ADDAC80 may be
connected to produce bipolar output voltage ranges of ± 10 V,
± 5 V or ± 2.5 V or unipolar output voltage ranges of 0 V to +5 V
or 0 V to +10 V (see Figure 9).
REF IN
2k
19
5k
15
20
16
6.3k
17
BIPOLAR
OFFSET
21
COM
Figure 10. Internal Scaling Resistors
BIPOLAR OFFSET
SUMMING
JUNCTION
20
REFERENCE
INPUT
18
5k
5k
TO REF
CONTROL
CIRCUIT
16
15
19
I
0 TO 2mA
OUTPUT
–
15
+
6.3k
17
TE
FROM
WEIGHTED
RESISTOR
NETWORK
17
3k
18
REF
INPUT
TO REF
CONTROL
CIRCUIT
6.3k
16
6.6k
21
–
COMMON
V 6.3V
Figure 9. Output Amplifier Voltage Range Scaling Circuit
+
24
REFERENCE OUT
Figure 11. ADDAC80 Current Model Equivalent Output Circuit
Internal resistors are provided to scale an external op amp or to
configure a resistive load to offer two output voltage ranges of ±1 V
or 0 V to –2 V. These resistors (RLI TCR = 20 ppm/°C) are an
integral part of the ADDAC80 and maintain gain and bipolar
offset drift specifications. If the internal resistors are not used, external RL (or RF) resistors should have a TCR of ± 25 ppm/°C or
less to minimize drift. This will typically add ± 50 ppm/°C + the
TCR of RL (or RF) to the total drift.
LE
Gain and offset drift are minimized in the ADDAC80 because
of the thermal tracking of the scaling resistors with other device
components. Connections for various output voltage ranges are
shown in Table III. Settling time is specified for a full-scale
range change: 4 s for a 10 kΩ feedback resistor; 3 s for a 5 kΩ
feedback resistor when using the compensation capacitor shown
in Figure 3a.
IOUT
B
SO
The equivalent resistive scaling network and output circuit of
the current model are shown in Figures 10 and 11. External RLS
resistors are required to produce exactly 0 V to –2 V or ± 1 V
output. TCR of these resistors should be ± 100 ppm/°C or less
to maintain the ADDAC80 output specifications. If exact output
ranges are not required, the external resistors are not needed.
Table III. Output Voltage Range Connections, Voltage Model ADDAC80
Digital
Input Codes
Connect
Pin 15 to
Connect
Pin 17 to
Connect
Pin 19 to
Connect
Pin 16 to
± 10 V
±5 V
± 2.5 V
0 V to 10 V
0 V to 5 V
0 V to 10 V
COB or CTC
COB or CTC
COB or CTC
CSB
CSB
CCD
19
18
18
18
18
19
20
20
20
21
21
NC
15
NC
20
NC
20
15
24
24
24
24
24
24
O
Output
Range
NC = No Connect
DRIVING A RESISTIVE LOAD UNIPOLAR
15
A load resistance, RL = RLI, + RLS, connected as shown in
Figure 12 will generate a voltage range, VOUT, determined by:
VOUT
6.6 kΩ × RL
= –2 mA
6.6 kΩ + RL
0 TO
2mA
RLI
968
6.6k
18
+
RLS
21 COMMON
(1)
VOUT
–
CURRENT CONTROLLED
BY DIGITAL INPUT
where RL max = 1.54 kΩ and VOUT max = –2.5 V
To achieve specified drift, connect the internal scaling resistor
(RLI) as shown in Table IV to an external metal film trim resistor
(RLS) to provide full scale output voltage range of 0 V to –2 V.
With RLS = 0 V, VOUT = –1.69 V.
REV. B
Figure 12. Equivalent Circuit ADDAC80-CBI-I Connected
for Unipolar Voltage Output with Resistive Load
–11–
ADDAC80/ADDAC85/ADDAC87
DRIVING A RESISTOR LOAD BIPOLAR
R × 3.22 kΩ
VOUT = ±1 mA L
RL + 3.22 kΩ
20V RANGE
19
The equivalent output circuit for a bipolar output voltage range
is shown in Figure 13, RL = RLI + RLS. VOUT is determined by:
5k CBI
18
10V RANGE
5k
15
(2)
I
0 TO 2mA
where RL max = 11.18 kΩ and VOUT max = ± 2.5 V
A
6.6k
AD509KH*
VOUT
21
To achieve specified drift, connect the internal scaling resistors
(RLI) as shown in Table IV for the COB or CTC codes and add
an external metal film resistor (RLS) in series to obtain a full scale
output range of ± 1 V. In this configuration, with RLS equal to
zero, the full scale range will be ± 0.874 V.
*FOR FAST SETTLING TIME
Figure 14. External Op Amp Using Internal
Feedback Resistors
OUTPUT LARGER THAN 20 V RANGE
1mA
RLI
1.2k
3.22k
20
For output voltage ranges larger than ± 10 V, a high voltage op
amp may be employed with an external feedback resistor. Use
IOUT values of ± l mA for bipolar voltage ranges and –2 mA for
unipolar voltage ranges (see Figure 15). Use protection diodes
when a high voltage op amp is used.
TE
15
+
RLS
21 COMMON
VOUT
–
CURRENT CONTROLLED
BY DIGITAL INPUT
The feedback resistor, RF, should have a temperature coefficient
as low as possible. Using an external feedback resistor, overall
drift of the circuit increases due to the lack of temperature tracking between RF and the internal scaling resistor network. This will
typically add 50 ppm/°C + RF drift to total drift.
LE
Figure 13. ADDAC80-CBI-I Connected for Bipolar
Output Voltage with Resistive Load
DRIVING AN EXTERNAL OP AMP
The current model ADDAC80 will drive the summing junction
of an op amp used as a current to voltage converter to produce
an output voltage. As seen in Figure 14,
VOUT = I OUT × R F
17
RF
6.3k
B
SO
(3)
where IOUT is the ADDAC80 output current and RF is the feedback resistor. Using the internal feedback resistors of the current
model ADDAC80 provides output voltage ranges the same as
the voltage model ADDAC80. To obtain the desired output
voltage range when connecting an external op amp, refer to
Table V and Figure 14.
I
0 TO 2mA
16
15
171K*
6.6k
VOUT
21
–
V
+
VREF
6.3V
24
*FOR OUTPUT VOLTAGE SWINGS UP TO 140V p-p
Figure 15. External Op Amp Using External
Feedback Resistors
O
Table IV. Current Model/Resistive Load Connections
1%
Metal Film
RLI Connections
Reference
Bipolar Offset
Internal
External
Resistance Resistance Connect Connect
Connect Connect
Connect
RLI (k)
RLS
Pin 15 to Pin 18 to
Pin 20 to Pin 16 to
Pin 17 to
RLS
Digital
Input Codes
Output
Range
CSB
0 to –2 V 0.968
COB or CTC ± 1 V
CCD
1.2
0 to ± 2 V 3
210 Ω
20
19 and RLS 15
24
Com (21)
249 Ω
18
19
RLS
24
15
N/A
NC
21
NC
24
NC
–12–
Between
Pin 18 and
Com (21)
Between
Pin 20 and
Com (21)
N/A
REV. B
ADDAC80/ADDAC85/ADDAC87
Table V. External Op Amp Voltage Mode Connections
Output
Range
Digital
Input Codes
Connect
A to
Connect
Pin 17 to
Connect
Pin 19 to
Connect
Pin 16 to
± 10 V
±5 V
± 2.5 V
0 V to 10 V
0 V to 5 V
COB or CTC
COB or CTC
COB or CTC
CSB
CSB
19
18
18
18
18
15
15
15
21
21
A
NC
15
NC
15
24
24
24
24
24
OUTLINE DIMENSIONS
TE
Dimensions shown in inches and (mm).
24-Lead Plastic DIP (N-24A)
1.290 (32.70)
1.150 (29.30)
24
13
1
PIN 1
LE
0.580 (14.73)
0.485 (12.32)
12
0.625 (15.87)
0.600 (15.24)
0.060 (1.52)
0.015 (0.38)
0.250
(6.35)
MAX
0.200 (5.05)
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.150
(3.81)
MIN
0.100
(2.54)
BSC
0.015 (0.381)
0.008 (0.204)
0.070 (1.77) SEATING
0.030 (0.77) PLANE
B
SO
0.022 (0.558)
0.014 (0.356)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS: INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
24-Lead Ceramic DIP (D-24)
SEE NOTE 5
0.098 (2.49) MAX
0.005 (0.13) MIN
24
13
0.610 (15.49)
0.500 (12.70)
O
SEE NOTE 4
PIN 1
SEE NOTE 1
0.225 (5.72)
MAX
1
12
SEE NOTE 4
1.290 (32.77) MAX
SEE NOTE 3
0.075 (1.91)
0.015 (0.38)
0.150
(3.81)
0.200 (5.08)
MIN
0.120 (3.05)
SEATING
0.023 (0.58) 0.110 (2.79) 0.070 (1.78)
PLANE
0.014 (0.36) 0.090 (2.29) 0.030 (0.76)
0.620 (15.75)
0.590 (14.99)
0.015 (0.38)
0.008 (0.20)
SEE NOTE 6
SEE NOTE 7 SEE NOTE 2, 6
NOTES
1. INDEX AREA; A NOTCH OR A LEAD ONE IDENTIFICATION MARK IS LOCATED ADJACENT TO LEAD ONE.
2. THE MINIMUM LIMIT FOR DIMENSION MAY BE 0.023" (0.58 mm) FOR ALL FOUR CORNER LEADS ONLY.
3. DIMENSION SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
4. THIS DIMENSION ALLOWS FOR OFF-CENTER LID, MENISCUS AND GLASS OVERRUN.
5. APPLIES TO ALL FOUR CORNERS.
6. ALL LEADS — INCREASE MAXIMUM LIMIT BY 0.003" (0.08 mm) MEASURED AT THE CENTER OF THE FLAT,
WHEN HOT SOLDER DIP LEAD FINISH IS APPLIED.
7. TWENTY TWO SPACES.
8. CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER
EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. B
–13–
ADDAC80/ADDAC85/ADDAC87
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Side Brazed Ceramic DIP for Hybrid (DH-24A)
SEE NOTE 5
24
0.098 (2.49) MAX
13
PIN 1
SEE NOTE 1
1
12
SEE NOTE 3
0.075 (1.91)
1.212 (29.69) MAX
0.015 (0.38)
0.225 (5.72)
MAX
0.180
(4.57)
0.200 (5.08)
MIN
0.120 (3.05)
0.023 (0.58) 0.100 (2.54) 0.070 (1.78) SEATING
BSC
0.030 (0.76) PLANE
0.014 (0.36)
SEE NOTE 4, 7 SEE NOTE 2
0.600 (14.70)
0.580 (14.21)
0.015 (0.38)
0.008 (0.20)
TE
0.005 (0.13) MIN
0.620 (15.75)
0.590 (14.99)
SEE NOTE 6
O
B
SO
LE
NOTES
1. INDEX AREA; A NOTCH OR A LEAD ONE IDENTIFICATION MARK IS LOCATED ADJACENT TO LEAD ONE.
2. THE MINIMUM LIMIT FOR DIMENSION MAY BE 0.023" (0.58 mm) FOR ALL FOUR CORNER LEADS ONLY.
3. DIMENSION SHALL BE MEASURED FROM THE SEATING PLANE TO THE BASE PLANE.
4. THE BASIC PIN SPACING IS 0.100" (2.54 mm) BETWEEN CENTERLINES.
5. APPLIES TO ALL FOUR CORNERS.
6. SHALL BE MEASURED AT THE CENTERLINE OF THE LEADS.
7. TWENTY TWO SPACES.
8. CONTROLLING DIMENSIONS ARE IN MILLIMETERS: INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER
EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
–14–
REV. B
ADDAC80/ADDAC85/ADDAC87
Revision History
Location
Page
Data Sheet changed from REV. A to REV. B.
O
B
SO
LE
TE
Update OUTLINE DIMENSION drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
REV. B
–15–
–16–
PRINTED IN U.S.A.
TE
LE
B
SO
O
C00381–0–1/02(B)
工商网监
湘ICP备2023018690号
