ADDI9023BBCZRL

Vertical Driver for CCD Cameras ADDI9023 Data Sheet FEATURES GENERAL DESCRIPTION 12-channel vertical driver 8 three-level drivers 4 two-level drivers Substrate clock driver Input logic supports a 1.6 V to 3.6 V range Output drivers support a −9.5 V to +15.5 V range 6 mm × 6 mm CSP_BGA package with 0.65 mm pitch The ADDI9023 is a 12-channel vertical driver for charge-coupled device (CCD) imaging applications. It includes eight three-level drivers and four two-level drivers. The input configuration can support up to nine individual vertical timing phases and eight shift gate signals. A separate substrate clock channel (SUBCK) is also included. Typical load drive capability for each channel is 3 nF. The ADDI9023 is specified over an operating temperature range of −25°C to +85°C. APPLICATIONS Digital still cameras Industrial cameras Surveillance cameras Medical imaging FUNCTIONAL BLOCK DIAGRAM VDD VH VM VL ADDI9023 XSG1 + V1A + V1B + V2A + V2B + V3A + V3B + V4 + V5 XV1 XSG2 XSG3 XV2 XSG4 XSG5 THREE-LEVEL OUTPUTS XV3 XSG6 XSG7 XV4 XV5 XSG8 XV6 V6 XV7 V7 XV8 V8 XV9 V9 SUBCK XSUBCK 10693-004 TWO-LEVEL OUTPUTS VLL Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. ADDI9023 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................6 Applications ....................................................................................... 1 Input/Output Logic States ................................................................8 General Description ......................................................................... 1 Applications Information .............................................................. 10 Functional Block Diagram .............................................................. 1 Power-Up Sequence ................................................................... 10 Revision History ............................................................................... 2 Power-Down Sequence .............................................................. 10 Specifications..................................................................................... 3 Circuit Layout Information....................................................... 11 Output Driver Specifications ...................................................... 4 Outline Dimensions ....................................................................... 12 Absolute Maximum Ratings ............................................................ 5 Ordering Guide .......................................................................... 12 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 REVISION HISTORY 4/12—Revision 0: Initial Version Rev. 0 | Page 2 of 12 Data Sheet ADDI9023 SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage V-DRIVER POWER SUPPLY VOLTAGES VDD VH VL VM VLL VH to VL, VLL DC POWER SUPPLY CURRENTS IVDD IVH IVL IVM IVLL DIGITAL INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Test Conditions/Comments Min Typ −25 −65 Input logic supply V-driver high supply V-driver low supply V-driver midsupply SUBCK V-driver low supply Maximum voltage from VH to VL, VLL VH = +15 V, VM = 0 V, VL = VLL = −7.5 V XVx = XSGx = 0 V XVx = XSGx = VDD XVx = XSGx = 0 V XVx = XSGx = VDD XVx = XSGx = 0 V XVx = XSGx = VDD XVx = XSGx = 0 V XVx = XSGx = VDD XSUBCK = 0 V XSUBCK = VDD VDD = 1.6 V to 3.6 V 1.6 11.0 −9.5 −1.5 −9.5 3.0 15.0 −7.5 0.0 −7.5 Max Unit +85 +150 °C °C 3.6 15.5 −5.5 +1.5 −5.5 24 V V V V V V 0.5 0.5 0.4 3.3 2.1 0.1 0.3 0.2 0.3 0.1 mA mA mA mA mA mA mA mA mA mA 0.6 50 50 V V µA µA pF VDD − 0.6 10 10 10 Rev. 0 | Page 3 of 12 ADDI9023 Data Sheet OUTPUT DRIVER SPECIFICATIONS VH = 15 V, VM = 0 V, VL, VLL = −7.5 V, TA = 25°C. Table 2. Parameter V1A TO V5 Delay Time, VL to VM and VM to VL Delay Time, VM to VH and VH to VM Rise Time, VL to VM Rise Time, VM to VH Fall Time, VM to VL Fall Time, VH to VM Output Currents On Resistance VH VM VL V6 TO V9 Delay Time, VL to VM and VM to VL Rise Time, VL to VM Fall Time, VM to VL Output Currents On Resistance VM VL SUBCK OUTPUT Delay Time, VLL to VH Delay Time, VH to VLL Rise Time, VLL to VH Fall Time, VH to VLL Output Currents Symbol Test Conditions/Comments tPLM, tPML tPMH, tPHM tRLM tRMH tFML tFHM Min Typ Unit Load circuit: 20 Ω + 3 nF to GND Load circuit: 20 Ω + 3 nF to GND Load circuit: 20 Ω + 3 nF to GND Load circuit: 20 Ω + 3 nF to GND 37 43 110 240 180 130 ns ns ns ns ns ns V1A to V5 = −7.25 V V1A to V5 = −0.25 V V1A to V5 = +0.25 V V1A to V5 = +14.75 V 14 −23 23 −10 mA mA mA mA RON 23 11 17 tPLM, tPML tRLM tFML 35 20 25 Ω Ω Ω Load circuit: 20 Ω + 3 nF to GND Load circuit: 20 Ω + 3 nF to GND 37 110 180 ns ns ns V6 to V9 = −7.25 V V6 to V9 = −0.25 V 14 −23 mA mA RON 11 17 tPLH tPHL tRLH tFHL Load circuit: 1 nF to GND Load circuit: 1 nF to GND SUBCK = −7.25 V SUBCK = +14.75 V RON V-DRIVER INPUT 50% 50% tRLM, tRMH, tRLH 90% V-DRIVER OUTPUT tPML, tPHM, tPHL 90% tPLM, tPMH, tPLH 10% tFML, tFHM, tFHL 10% Figure 2. Definition of V-Driver Timing Specifications Rev. 0 | Page 4 of 12 10693-002 VLL On Resistance Max 20 25 Ω Ω 47 47 45 45 ns ns ns ns 23 −22 10 mA mA Ω 17 Data Sheet ADDI9023 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter VDD to VSS VH to VL, VLL VH to VSS VL to VSS VM to VSS VMM to VSS VLL to VSS V1A to V9 to VSS VDREN to VSS Junction Temperature Lead Temperature (Soldering, 10 sec) θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.3 V to +3.9 V −0.3 V to +25.0 V −0.3 V to +17.0 V −17.0 V to +0.3 V −6.0 V to +3.0 V −6.0 V to +3.0 V −17.0 V to +0.3 V VL − 0.3 V to VH + 0.3 V −0.3 V to VDD + 0.3 V 150°C 350°C Table 4. Thermal Resistance Package Type 40-Lead CSP_BGA ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 5 of 12 θJA 46 Unit °C/W ADDI9023 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 A VM VL VH VDREN XSG8 XSG5 XSG6 A B V8 V7 V9 XSG7 XSG2 XSG3 XSG4 B C V6 V5 XV8 XSG1 C D V4 V3B XV7 XV9 D XV5 XV6 E ADDI9023 TOP VIEW E V2B V3A F V1B V2A XSUBCK XV1 XV2 XV3 XV4 F G V1A SUBCK VMM VLL VDD VSS VSS G 1 2 3 4 5 6 7 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 C1 C2 C6 C7 D1 D2 D6 D7 E1 E2 E6 E7 Mnemonic VM VL VH VDREN XSG8 XSG5 XSG6 V8 V7 V9 XSG7 XSG2 XSG3 XSG4 V6 V5 XV8 XSG1 V4 V3B XV7 XV9 V2B V3A XV5 XV6 Type 1 P P P DI DI DI DI VO2 VO2 VO2 DI DI DI DI VO2 VO3 DI DI VO3 VO3 DI DI VO3 VO3 DI DI Description V-Driver Midsupply. V-Driver Low Supply. V-Driver High Supply. V-Driver Enable. Active high. Vertical Input. Vertical Input. Vertical Input. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock. Vertical Input. Vertical Input. Vertical Input. Vertical Input. CCD Vertical Transfer Clock. CCD Vertical Transfer Clock (XV5 + XSG8). Vertical Input. Vertical Input. CCD Vertical Transfer Clock (XV4 + XSG7). CCD Vertical Transfer Clock (XV3 + XSG6). Vertical Input. Vertical Input. CCD Vertical Transfer Clock (XV2 + XSG4). CCD Vertical Transfer Clock (XV3 + XSG5). Vertical Input. Vertical Input. Rev. 0 | Page 6 of 12 10693-003 (Not to Scale) Data Sheet Pin No. F1 F2 F3 F4 F5 F6 F7 G1 G2 G3 G4 G5 G6 G7 1 Mnemonic V1B V2A XSUBCK XV1 XV2 XV3 XV4 V1A SUBCK VMM VLL VDD VSS VSS ADDI9023 Type 1 VO3 VO3 DI DI DI DI DI VO3 VO2 P P P P P Description CCD Vertical Transfer Clock (XV1 + XSG2). CCD Vertical Transfer Clock (XV2 + XSG3). XSUBCK Input to SUBCK Buffer. Vertical Input. Vertical Input. Vertical Input. Vertical Input. CCD Vertical Transfer Clock (XV1 + XSG1). CCD Substrate Clock Output. SUBCK Output Driver Ground. V-Driver Low Supply for SUBCK Output. Digital Logic Supply. Digital Logic Ground. Digital Logic Ground. DI = digital input; P = power; VO2 = vertical driver output, two-level; VO3 = vertical driver output, three-level. Rev. 0 | Page 7 of 12 ADDI9023 Data Sheet INPUT/OUTPUT LOGIC STATES Table 6. V1A Output Polarity Vertical Driver Input XV1 XSG1 L L L H H L H H Table 11. V3B Output Polarity V1A Output VH VM VL VL XV3 L L H H Vertical Driver Input XSG6 L H L H Table 7. V1B Output Polarity Table 12. V4 Output Polarity Vertical Driver Input XV1 XSG2 L L L H H L H H Vertical Driver Input XV4 XSG7 L L L H H L H H V1B Output VH VM VL VL Table 8. V2A Output Polarity Vertical Driver Input XV2 XSG3 L L L H H L H H V2A Output VH VM VL VL XV5 L L H H Vertical Driver Input XSG8 L H L H V5 Output VH VM VL VL Table 14. V6 to V9 Output Polarity V2B Output VH VM VL VL Table 10. V3A Output Polarity Vertical Driver Input XV3 XSG5 L L L H H L H H V4 Output VH VM VL VL Table 13. V5 Output Polarity Table 9. V2B Output Polarity Vertical Driver Input XV2 XSG4 L L L H H L H H V3B Output VH VM VL VL V3A Output VH VM VL VL Vertical Driver Input XV6, XV7, XV8, or XV9 L H V6, V7, V8, or V9 Output VM VL Table 15. SUBCK Output Polarity Vertical Driver Input XSUBCK L H Rev. 0 | Page 8 of 12 SUBCK Output VH VLL Data Sheet ADDI9023 XV1, XV2, XV3, XV4, XV5 XSG1, XSG2, XSG3, XSG4, XSG5, XSG6, XSG7, XSG8 VH VM 10693-005 V1A, V1B, V2A, V2B, V3A, V3B, V4, V5 VL Figure 4. Three-Level V-Driver Output Polarities XV6, XV7, XV8, XV9 10693-006 VM V6, V7, V8, V9 VL Figure 5. Two-Level V-Driver Output Polarities XSUBCK VH 10693-007 SUBCK VLL Figure 6. SUBCK Output Polarity Rev. 0 | Page 9 of 12 ADDI9023 Data Sheet APPLICATIONS INFORMATION POWER-UP SEQUENCE When the ADDI9023 is powered up, the following sequence is recommended (refer to Figure 7 for each step). Note that VH is powered on before VL but, depending on CCD restrictions, VH and VL can also be powered on simultaneously. 2. Turn on the VDD power supply, either 1.8 V or 3.3 V. After VDD settles, the logic inputs from the timing generator (XV, XSG, XSUBCK) can become active. Keep VDREN low during this time. Turn on the VH power supply, typically +12 V to +15 V. 1 2 3 Turn on the VL/VLL power supply, typically −6 V to −9 V. Take the VDREN pin high to enable the V-driver outputs. VDREN must remain high throughout normal vertical timing operation. POWER-DOWN SEQUENCE When the ADDI9023 is powered down, reverse the procedure shown in Figure 7. 1. 2. 3. Take the VDREN pin low to disable the V-driver outputs. Turn off the VL/VLL and VH power supplies. Turn off the VDD power supply. 4 VH SUPPLY VDD POWER SUPPLIES 0V VM VL, VLL SUPPLY VDD XV, XSG, 0V XSUBCK (INPUT) DON’T CARE VDD VDREN V-DRIVER OUTPUTS ACTIVE WHEN VDREN IS HIGH 0V VH V1A TO V9 0V (OUTPUT) VM VL/VLL (SUBCK ONLY) Figure 7. Recommended Power-Up Sequence Rev. 0 | Page 10 of 12 10693-008 1. 3. 4. Data Sheet ADDI9023 CIRCUIT LAYOUT INFORMATION additional bypass capacitor, such as a 1.0 µF to 22 µF capacitor, depending on CCD and performance requirements. Connect the ground pins (VSS, VM, and VMM) to a common ground plane. The recommended circuit configuration is shown in Figure 8. Each supply pin should have a high quality 0.1 µF capacitor connected to ground. The VH and VL supplies should have an VH SUPPLY 0.1µF 25V 1.0µF 25V +3.3V SUPPLY VL SUPPLY 0.1µF 10V + 4.7µF 10V G5 A3 G4 A2 VDD VH VLL VL 0.1µF LOGIC INPUTS (FROM TIMING GENERATOR) G1 F1 F2 E1 E2 D2 D1 C2 C1 B2 B1 B3 G2 V1A V1B V2A V2B V3A V3B V4 V5 V6 V7 V8 V9 SUBCK 13 A4 VDREN V-DRIVER OUTPUTS (TO CCD) V-DRIVER OUTPUT ENABLE ACTIVE HIGH (FROM GENERAL-PURPOSE OUTPUT) 10693-009 18 ADDI9023 (Not to Scale) A1 G3 G6 G7 XSG7 XV5 XSG8 XV6 XV7 XV8 XV9 XSUBCK C7 F4 B5 B6 F5 B7 A6 F6 A7 F7 B4 E6 A5 E7 D6 C6 D7 F3 VM VMM VSS VSS XSG1 XV1 XSG2 XSG3 XV2 XSG4 XSG5 XV3 XSG6 XV4 Figure 8. Typical Circuit Configuration Rev. 0 | Page 11 of 12 ADDI9023 Data Sheet OUTLINE DIMENSIONS A1 BALL CORNER 6.10 6.00 SQ 5.90 A1 BALL CORNER 7 6 5 4 3 2 1 A B 3.90 BSC SQ 0.65 BSC C D E F G TOP VIEW 1.05 REF BOTTOM VIEW *0.76 DETAIL A DETAIL A 0.30 NOM 0.25 MIN SEATING PLANE 0.45 0.40 0.35 BALL DIAMETER *COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. 0.66 0.56 COPLANARITY 0.10 04-30-2012-A *1.04 0.96 0.81 Figure 9. 40-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-40-1 Dimensions shown in millimeters ORDERING GUIDE Model 1 ADDI9023BBCZ ADDI9023BBCZRL 1 Temperature Range −25°C to +85°C −25°C to +85°C Package Description 40-Lead CSP_BGA 40-Lead CSP_BGA Z = RoHS Compliant Part. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10693-0-4/12(0) Rev. 0 | Page 12 of 12 Package Option BC-40-1 BC-40-1