Preliminary Technical Data
GENERAL FEATURES
Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver ADE7566/ADE7569
MICROPROCESSOR FEATURES
8052-based core Single-cycle 4 MIPS 8052 core 8052-compatible instruction set 32.768 kHz external crystal with on-chip PLL Two external interrupt sources External reset pin Real-time clock Counter for seconds, minutes, and hours Automatic battery switchover for RTC backup Ultralow battery supply current < 1.5 μA Software clock calibration with temperature and offset compensation Integrated LCD driver 108 segment with 2, 3, or 4 multiplexers 3 V/5 V driving capability Internally generated LCD drive voltages Temperature and supply compensated drive voltages Low power battery mode Wake-up from I/O and UART LCD driver capability On-chip peripherals UART, SPI, or I2C Watchdog timer Power supply monitoring with user-selectable levels Memory: 16 kB flash memory, 512 bytes RAM Development tools Single-pin emulation IDE-based assembly and C-source debugging
Wide supply voltage operation: 2.4 V to 3.7 V Battery supply input with automatic switchover Reference: 1.2 V ± 1% (drift 50 ppm/°C maximum) 64-lead RoHS package options Lead frame chip scale package (LFCSP) Low profile quad flat package (LQFP) Operating temperature range: −40°C to +85°C
ENERGY MEASUREMENT FEATURES
High accuracy, active, reactive, and apparent energy measurement IC Supports IEC 62053-21, IEC 62053-22, IEC 62053-23 One differential input with PGAs support shunts, current transformers, and di/dt current sensors Selectable digital integrator support di/dt current sensor Digital parameters for gain, offset, and phase compensation Selectable no-load threshold level for W, VA, and VAR creep protection Less than 0.1% error on active energy over a dynamic range of 1000 to 1 @ 25°C Less than 0.5% error on reactive energy over a dynamic range of 1000 to 1 @ 25°C Less than 0.5% error on rms measurements over a dynamic range of 500 to 1 for current and 100 to 1 for voltage @ 25°C High frequency outputs supply proportional to Irms, active, reactive, or apparent power Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time Temperature monitoring
GENERAL DESCRIPTION
The ADE7566/ADE75691 integrate Analog Devices Inc. Energy (ADE) metering IC analog front end and fixed function DSP solution with an enhanced 8052 MCU core, an RTC, an LCD driver, and all the peripherals to make an electronic energy meter with an LCD display in a single part. The ADE measurement core includes active, reactive, and apparent energy calculations, as well as voltage and current rms measurements. This information is ready to use for energy billing by using built-in energy scalars. Many power line supervisory features such as SAG, peak, and zero-crossing are included in the energy measurement DSP to simplify energy meter design.
1
The microprocessor functionality includes a single cycle 8052 core, a real-time clock with a power supply backup pin, a UART, and an SPI or I2C interface. The ready-to-use information from the ADE core reduces the program memory size requirement, making it easy to integrate complicated design into 16 kB of flash memory. The ADE7566/ADE7569 also include a 108-segment LCD driver. This driver generates voltages capable of driving 5 V LCDs.
Patents pending.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADE7566/ADE7569 TABLE OF CONTENTS
General Features ............................................................................... 1 Energy Measurement Features........................................................ 1 Microprocessor Features.................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Timing Specifications....................................................................... 9 Absolute Maximum Ratings.......................................................... 16 Thermal Resistance .................................................................... 16 ESD Caution................................................................................ 16 Pin Configuration and Function Descriptions........................... 17 Typical Performance Characteristics ........................................... 19 Terminology .................................................................................... 21 SFR Mapping ................................................................................... 22 Power Management........................................................................ 23 Power Management Register Details ....................................... 23 Power Supply Architecture........................................................ 26 Battery Switchover...................................................................... 26 Power Supply Monitor Interrupt (PSM).................................. 27 Using the Power Supply Features ............................................. 29 Operating Modes ............................................................................ 31 PSM0 (Normal Mode) ............................................................... 31 PSM1 (Battery Mode) ................................................................ 31 PSM2 (Sleep Mode).................................................................... 31 3.3 V Peripherals and Wake-Up Events................................... 32 Transitioning Between Operating Modes ............................... 33 Using the Power Management Features .................................. 33 Energy Measurement ..................................................................... 34 Access to Energy Measurement SFRs ...................................... 34 Access to Internal Energy Measurement Registers................ 34 Energy Measurement Registers ................................................ 36 Energy Measurement Internal Registers Details.................... 37 Analog Inputs.............................................................................. 41 Analog-to-Digital Conversion.................................................. 42 di/dt Current Sensor and Digital Integrator for the ADE7569......................................................................... 44 Power Quality Measurements................................................... 46 Phase Compensation.................................................................. 48 RMS Calculation......................................................................... 48 Active Power Calculation .......................................................... 50
Preliminary Technical Data
Active Energy Calculation ........................................................ 52 Reactive Power Calculation for the ADE7569 ....................... 55 Reactive Energy Calculation for the ADE7569 ...................... 56 Apparent Power Calculation..................................................... 60 Apparent Energy Calculation ................................................... 61 Ampere-Hour Accumulation ................................................... 62 Energy-to-Frequency Conversion............................................ 63 Energy Register Scaling ............................................................. 63 Energy Measurement Interrupts .............................................. 64 Temperature, Battery, and Supply Voltage Measurements........ 65 Temperature Measurement ....................................................... 67 Battery Measurement................................................................. 67 External Voltage Measurement ................................................ 68 8052 MCU CORE Architecture.................................................... 70 MCU Registers............................................................................ 70 Basic 8052 Registers ................................................................... 72 Standard 8052 SFRs.................................................................... 73 Memory Overview ..................................................................... 73 Addressing Modes...................................................................... 74 Instruction Set ............................................................................ 76 Read-Modify-Write Instructions ............................................. 78 Instructions That Affect Flags .................................................. 78 Interrupt System ............................................................................. 80 Standard 8051 Interrupt Architecture ..................................... 80 Interrupt Architecture ............................................................... 80 Interrupt Registers...................................................................... 80 Interrupt Priority........................................................................ 81 Interrupt Flags ............................................................................ 82 Interrupt Vectors ........................................................................ 84 Interrupt Latency........................................................................ 84 Context Saving............................................................................ 84 Watchdog Timer ............................................................................. 85 LCD Driver...................................................................................... 87 LCD Registers ............................................................................. 87 LCD Setup ................................................................................... 90 LCD Timing and Waveforms.................................................... 90 BLINK Mode............................................................................... 91 Display Element Control........................................................... 91 Voltage Generation .................................................................... 92 LCD External Circuitry ............................................................. 92
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Preliminary Technical Data
LCD Function in PSM2..............................................................92 Flash Memory ..................................................................................94 Overview ......................................................................................94 Flash Memory Organization......................................................95 Using the Flash Memory ............................................................95 Protecting the Flash ....................................................................98 In-Circuit Programming ............................................................99 Timers ............................................................................................ 100 Timer SFR Registers ................................................................ 100 Timer 0 and Timer 1................................................................ 102 Timer 2 ...................................................................................... 103 PLL ................................................................................................. 105 PLL SFR Register List .............................................................. 105 Real Time Clock ........................................................................... 107 RTC SFR Register List ............................................................. 107 Read and Write Operations .................................................... 110 RTC Modes ............................................................................... 110 RTC Interrupts ......................................................................... 110 RTC Calibration ....................................................................... 111 UART Serial Interface.................................................................. 112 UART SFR Registers ................................................................ 112 UART Operation Modes ......................................................... 115 UART Baud Rate Generation ................................................. 116
2
ADE7566/ADE7569
UART Additional Features ......................................................118 Serial Peripheral Interface (SPI)..................................................119 SPI SFR Register List ................................................................119 SPI Pins.......................................................................................122 SPI Master Operating Modes ..................................................123 SPI Interrupt and Status Flags .................................................124 I C Compatible Interface..............................................................125 Serial Clock Generation ...........................................................125 Slave Addresses..........................................................................125 I2C SFR Register List.................................................................125 Read and Write Operations .....................................................126 I2C Receive and Transmit FIFOs.............................................127 Dual Data Pointers........................................................................128 I/O Ports .........................................................................................129 Parallel I/O.................................................................................129 I/O SFR Register List ................................................................130 Port 0...........................................................................................133 Port 1...........................................................................................133 Port 2...........................................................................................133 Determining the Version of the ADE7566/ADE7569..............134 Outline Dimensions......................................................................135 Ordering Guide .........................................................................136
Rev. PrA | Page 3 of 136
ADE7566/ADE7569 FUNCTIONAL BLOCK DIAGRAM
P0.3 (CF2) P0.4 (MOSI/SDATA) P0.5 (MISO) P0.6 (SCLK/T0) P0.7 (SS/T1) P0.0 (BCTRL/INT1)
Preliminary Technical Data
P1.3 (T2EX/FP24)
P1.4 (T2/FP23)
MOSI/SDATA
P1.5 (FP22) P1.6 (FP21)
8
P0.1 (FP19)
P1.0 (RxD) P1.1 (TxD) P1.2 (FP25)
57
43 42
38 39 40 41
39 38 7
8
45 11 43 42 41 40 39 38
37 36 5
6
7
9 10 12 P2.0 (FP18) 13 P2.1 (FP17)
1.20V REF IP 52 IN 53 + PGA1 – ADC
SPI/I2C SERIAL INTERFACE
3 × 16-BIT COUNTER TIMERS
ADE7566/ADE7569
P1.7 (FP20)
REFIN/OUT
MISO
T2EX
CF2
T2
P0.2 (CF1)
CF1
SS
SCLK
T0
T1
14 P2.2 (FP16) 44 P2.3 (SDEN) 19 16
LCDVP1 LCDVP2 LCDVA LCDVB LCDVC COM0
3V/5V LCD CHARGE PUMP ENERGY MEASUREMENT DSP 108 SEGMENTS LCD DRIVER PROGRAM MEMORY 16kB FLASH USER RAM 256 BYTES SINGLE CYCLE 8052 MCU WATCHDOG TIMER
18 17 15 4
VN 50
...
1
VP 49
+ PGA2 –
ADC
...
COM3
35 FP0
...
FP16 FP17 FP18 FP19 FP20 FP21 FP22 FP23 FP24 FP25 FP26
DGND 63 AGND 54
TEMP SENSOR BATTERY ADC
TEMP ADC
USER XRAM 256 BYTES
VBAT 58
DOWNLOADER DEBUGGER 1-PIN EMULATOR PLL UART TIMER UART SERIAL PORT
POWER SUPPLY CONTROL AND MONITORING
VDCIN ADC POR LDO LDO
RTC
OSC
64
60
61
62
59
56
51
44
36
37
47
46
48
45
VSWOUT
XTAL1
XTAL2
VINTA
VINTD
TxD
EA
VDCIN
RESET
SDEN
INT0
INT1
VDD
RxD
.. .
14 13 12 11 10 9 8 7
20 FP15
6
5 55
Figure 1. Functional Block Diagram
Rev. PrA | Page 4 of 136
06353-001
Preliminary Technical Data SPECIFICATIONS
ADE7566/ADE7569
VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTAL = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted. Table 1.
Parameter ENERGY METERING MEASUREMENT ACCURACY 1 Phase Error Between Channels PF = 0.8 Capacitive PF = 0.5 Inductive Active Energy Measurement Error 2 AC Power Supply Rejection2 Output Frequency Variation DC Power Supply Rejection2 Output Frequency Variation Active Energy Measurement Bandwidth1, 2 Reactive Energy Measurement Error2 Vrms Measurement Error2 Vrms Measurement Bandwidth1, 2 Irms Measurement Error2 Irms Measurement Bandwidth1, 2 ANALOG INPUTS Maximum Signal Levels Input Impedance (DC) ADC Offset Error2 Gain Error2 Current Channel Voltage Channel Gain Error Match2 CF1 AND CF2 PULSE OUTPUT Maximum Output Frequency Duty Cycle Active High Pulse Width ANALOG PERIPHERALS INTERNAL ADCs (Battery, Temperature, VDCIN) Power Supply Operating Range No Missing Codes1 AC Power Supply Rejection1 DC Power Supply Rejection1 Conversion Delay 3 Temperature Sensor Accuracy1 VDCIN ANALOG INPUT Maximum Signal Levels Input Impedance (DC) Low VDCIN Detection Threshold Min Typ Max Unit Test Conditions/Comments
±0.05 ±0.05 0.1
Degrees Degrees % of reading % % kHz % of reading % of reading kHz % of reading kHz ±500 mV peak kΩ mV % % % kHz % ms
Phase lead 37° Phase lag 60° Over a dynamic range of 1000 to 1 @ 25°C VDD = 3.3 V + 100 mV rms/120 Hz IP = VP = ±100 mV rms VDD = 3.3 V ± 117 mV dc
0.01 0.01 14 0.5 0.5 14 0.5 14
Over a dynamic range of 1000 to 1 @ 25°C Over a dynamic range of 100 to 1 @ 25°C
Over a dynamic range of 500 to 1 @ 25°C
VP − VN and IAP − IN Differential input
TBD 1 ±4 ±4 ±3 21.1 50 90
Current channel = 0.5 V dc Voltage channel = 0.5 V dc
VP − VN = IAP − IN = 500 mV peak sine wave If CF1 or CF2 frequency > 5.55 Hz If CF1 or CF2 frequency < 5.55 Hz
2.3 8
3.7 TBD TBD 1
−1 −4 0 1.08 1 1.2
+1 +4 3.3 1.32
V bits dB dB ms °C °C V MΩ V
Measured on VSWOUT
At 25°C Between −40°C and +85°C
Rev. PrA | Page 5 of 136
ADE7566/ADE7569
Parameter POWER-ON RESET (POR) VDD POR Detection Threshold POR Active Timeout Period Strobe Period in Battery Operation VSWOUT POR Detection Threshold POR Active Timeout Period VINTD POR Detection Threshold POR Active Timeout Period VINTA POR Detection Threshold POR Active Timeout Period BATTERY SWITCH OVER Voltage Operating Range (VSWOUT) VDD to VBAT Switching Switching Threshold (VDD) Switching Delay Switching Delay VBAT to VDD Switching Switching Threshold (VDD) Switching Delay VSWOUT To VBAT Leakage Current LCD, CHARGE PUMP ACTIVE Charge Pump Capacitance Between LCDVP1 and LCDVP2 LCDVA, LCDVB, LCDVC Decoupling Capacitance LCDVA LCDVB LCDVB LCDVC LCD Stand-By Current V1 Segment Line Voltage V2 Segment Line Voltage V3 Segment Line Voltage DC Voltage Across Segment and COM Pin LCD, RESISTOR LADDER ACTIVE Leakage Current V1 Segment Line Voltage V2 Segment Line Voltage V3 Segment Line Voltage ON-CHIP REFERENCE Reference Error Power Supply Rejection Temperature Coefficient1 Min Typ Max Unit
Preliminary Technical Data
Test Conditions/Comments
1.6 TBD TBD 1.8 TBD 2.25 TBD 2.25 TBD 2.4 2.75 10 30 2.75 130
2.9
V ms ms V ms V ms V ms V V ns ms V ms nA nF nF
2.2
2.4
2.4
3.7 TBD
When VDD to VBAT switch activated by VDD When VDD to VBAT switch activated by VDCIN
TBD 1
Based on VDD > 2.75V
100 470 0 0 0 0 100 LCDVA − 0.1 LCDVB − 0.1 LCDVC − 0.1 LCDVA LCDVB LCDVC 50 1.7 4.0 3.4 5.1
V V V V nA V V V mV
1/2 bias modes 1/3 bias modes 1/3 bias mode 1/2 and 1/3 bias modes Current on segment line = −2 μA Current on segment line = −2 μA Current on segment line = −2 μA LCDVC − LCDVB, LCDVC − LCDVA, or LCDVB − LCDVA 1/2 and 1/3 bias modes, no load Current on segment line = −2 μA Current on segment line = −2 μA Current on segment line = −2 μA
LCDVA − 0.1 LCDVB − 0.1 LCDVC − 0.1
±20 LCDVA LCDVB LCDVC ±0.9 80 35 50
nA V V V mV dB ppm/°C
Rev. PrA | Page 6 of 136
Preliminary Technical Data
Parameter DIGITAL INTERFACE LOGIC INPUTS All Inputs Except XTAL1, XTAL2, BCTRL, INT0, INT1, RESET Input High Voltage, VINH Input Low Voltage, VINL BCTRL, INT0, INT1, RESET Input High Voltage, VINH Input Low Voltage, VINL Input Currents RESET Port 0, Port 1, Port 2 Min Typ Max Unit
ADE7566/ADE7569
Test Conditions/Comments
2.0 0.4 1.3 0.4 ±10 100 ±100 −5 10 10,000 20 30 32 50 33.5
V V V V μA μA nA μA pF Cycles Years kΩ kHz pF pF MHz kHz V μA V mA μA pF ms μs μs RESET = 0 V RESET = VSWOUT = 3.3 V Internal pull-up disabled, input = 0 V or VOUT Internal pull-up enabled, input = 0 V, VSWOUT = 3.3 V All digital inputs
Input Capacitance FLASH MEMORY Endurance 4 Data Retention 5 CRYSTAL OSCILLATOR Crystal Equivalent Series Resistance Crystal Frequency XTAL1 Input Capacitance XTAL2 Output Capacitance MCU CLOCK RATE (fCORE) LOGIC OUTPUTS Output High Voltage, VOH ISOURCE Output Low Voltage, VOL 6 ISINK Floating State Leakage Current Floating State Output Capacitance START-UP TIME 7 At Power-On From Power-Saving Mode 2 (PSM2) From Power-Saving Mode 1 (PSM1) POWER SUPPLY INPUTS VDD VBAT POWER SUPPLY OUTPUTS VBAT to VSWOUT On Resistance VDD to VSWOUT On Resistance VSWOUT Output Current Drive VINTA, VINTD VINTA Power Supply Rejection VINTD Power Supply Rejection
TJ = 85°C
32.768 12 12 4.096 32
Crystal = 32.768 kHz and CD[2:0] = 0 Crystal = 32.768 kHz and CD[2:0] = 0b111 VDD = 3.3 V ± 5% VDD = 3.3 V ± 5%
2.4 80 0.4 2 ±10 TBD TBD TBD TBD 3.0 2.3 3.3 3.3 3.6 3.7 25 6.1 6 2.75
V V Ω Ω mA V dB dB VBAT = 2.4 V VDD = 3 V
1 2.25 80 60
Rev. PrA | Page 7 of 136
ADE7566/ADE7569
Parameter POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) Min Typ 3.5 TBD TBD TBD TBD Current in PSM1 880 TBD TBD TBD 1.5 Max TBD Unit mA mA mA mA mA μA μA μA μA μA
Preliminary Technical Data
Test Conditions/Comments fCORE = 4.096 MHz, LCD and meter active fCORE = 1.024 MHz, LCD and meter active fCORE = 32.768 kHz, LCD and Meter active fCORE = 4.096 MHz, LCD and meter DSP active, metering ADC powered down fCORE = 4.096 MHz, LCD active, metering ADC and DSP powered down fCORE = 4.096 MHz, LCD active fCORE = 1.024 MHz, LCD active fCORE = 4.096 MHz, LCD inactive LCD active with charge pump at 3.3 V + RTC RTC only
TBD TBD TBD TBD TBD TBD
Current in PSM2
1 2
These numbers are not production tested but are guaranteed by design and/or characterization data on production release. See the Terminology section for definition. 3 Delay between ADC conversion request and interrupt set. 4 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 5 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 6 Test carried out with a maximum of TBD I/Os set to a low output level. 7 Delay between power supply valid and execution of first instruction by 8052 core.
Rev. PrA | Page 8 of 136
Preliminary Technical Data TIMING SPECIFICATIONS
AC inputs during testing are driven at VSWOUT − 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements are made at VIH minimum for Logic 1 and VIL maximum for Logic 0 as shown in Figure 2. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to Table 2. Clock Input (External Clock Driven XTAL1) Parameter
Parameter tCK tCKL tCKH tCKR tCKF 1/tCORE
1
ADE7566/ADE7569
float when a 100 mV change from the loaded VOH/VOL level occurs as shown in Figure 2. CLOAD for all outputs = 80 pF, unless otherwise noted. VDD = 2.7 V to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted.
Description XTAL1 period XTAL1 width low XTAL1 width high XTAL1 rise time XTAL1 fall time Core clock frequency 1
Min
0.032768
32.768 kHz External Crystal Typ Max 30.52 6.26 6.26 9 9 1.024 4.096
Unit μs μs μs ns ns MHz
The ADE7566/ADE7569 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple defined by the CD[2:0] bits, selected via the POWCON SFR.
DVDD – 0.5V
0.45V
VLOAD + 0.1V
VLOAD – 0.1V
Figure 2. Timing Waveform Characteristics
Rev. PrA | Page 9 of 136
06353-002
0.2DVDD + 0.9V TEST POINTS 0.2DV DD – 0.1V
VLOAD – 0.1V VLOAD
TIMING REFERENCE POINTS
VLOAD – 0.1V VLOAD
ADE7566/ADE7569
Table 3. I2C-Compatible Interface Timing Parameters (400 kHz)
Parameter tL tH tSHD tDSU tDHD tRSU tPSU tR tF tSUP 1
1
Preliminary Technical Data
Description SCLK low pulse width SCLK high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Rise time of both SCLK and SDATA Fall time of both SCLK and SDATA Pulse width of spike suppressed Typ 1.36 1.14 251.35 740 400 12.5 400 200 300 50 Unit μs μs μs ns ns ns ns ns ns ns
Input filtering on both the SCLK and SDATA inputs suppresses noise spikes less than 50 ns.
tBUF
SDATA (I/O) MSB
tSUP
LSB ACK
tR
MSB
tDSU tPSU
SCLK (I)
PS STOP START CONDITION CONDITION
tDHD tSHD
1 2–7 8
tDSU tH
9
tDHD tRSU
tF tR
1
06353-003
tL
tSUP
S(R) REPEATED START
tF
Figure 3. I2C-Compatible Interface Timing
Rev. PrA | Page 10 of 136
Preliminary Technical Data
Table 4. SPI Master Mode Timing (SPICPHA = 1) Parameters
Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF
1
ADE7566/ADE7569
Min Typ (SPIR + 1) × tCORE 1 (SPIR +1 ) × tCORE1 Max Unit ns ns ns ns ns ns ns ns ns
Description SCLK low pulse width SCLK high pulse width Data output valid after SCLK Edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time
25 TBD TBD 5 5 5 5 12.5 12.5 12.5 12.5
tCORE depends on the clock divider or CD bits of the POWCON SFR, tCORE = 2CD/4.096 MHz.
SCLK (SPICPOL = 0) SCLK (SPICPOL = 1)
tSH
tSL tSR tSF
tDAV
MOSI MSB
tDF
tDR
BITS 6–1 LSB
MISO
MSB IN
BITS 6–1
LSB IN
06353-004
tDSU
tDHD
Figure 4. SPI Master Mode Timing (SPICPHA = 1)
Rev. PrA | Page 11 of 136
ADE7566/ADE7569
Table 5. SPI Master Mode Timing (SPICPHA = 0) Parameters
Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF
1
Preliminary Technical Data
Min Typ (SPIR + 1) × tCORE 1 (SPIR + 1) × tCORE1 Max Unit ns ns ns ns ns ns ns ns ns ns
Description SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data output setup before SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time
25 75 TBD TBD 5 5 5 5 12.5 12.5 12.5 12.5
tCORE depends on the clock divider or CD bits of the POWCON SFR, tCORE = 2CD/4.096 MHz.
SCLK (SPICPOL = 0) SCLK (SPICPOL = 1)
tSH
tSL tSR tSF
tDAV tDOSU
MOSI MSB BITS 6–1 LSB
tDF
tDR
MISO
MSB IN
BITS 6–1
LSB IN
06353-005
tDSU
tDHD
Figure 5. SPI Master Mode Timing (SPICPHA = 0)
Rev. PrA | Page 12 of 136
Preliminary Technical Data
Table 6. SPI Slave Mode Timing (SPICPHA = 1) Parameters
Parameter tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS
1
ADE7566/ADE7569
Min 0 Typ (SPIR + 1) × tCORE 1 (SPIR + 1) × tCORE1 25 TBD TBD 5 5 5 5 0 12.5 12.5 12.5 12.5 Max Unit ns ns ns ns ns ns ns ns ns ns ns
Description SS to SCLK edge SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time SS high after SCLK edge
tCORE depends on the clock divider or CD bits of the POWCON SFR, tCORE = 2CD/4.096 MHz.
SS tSFS
tSS
SCLK (SPICPOL = 0)
tSH
tSL tSR tSF
SCLK (SPICPOL = 1)
tDAV
MISO MSB
tDF
tDR
BITS 6–1 LSB
MOSI
MSB IN
BITS 6–1
LSB IN
06353-006
tDSU
tDHD
Figure 6. SPI Slave Mode Timing (SPICPHA = 1)
Rev. PrA | Page 13 of 136
ADE7566/ADE7569
Table 7. SPI Slave Mode Timing (SPICPHA = 0) Parameters
Parameter tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOSS tSFS
1
Preliminary Technical Data
Min 0 Typ (SPIR + 1) × tCORE 1 (SPIR + 1) × tCORE1 25 TBD TBD 5 5 5 5 0 12.5 12.5 12.5 12.5 25 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns
Description SS to SCLK edge SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time Data output valid after SS edge SS high after SCLK edge
tCORE depends on the clock divider or CD bits of the POWCON SFR, tCORE = 2CD/4.096 MHz.
SS tSFS
tSS
SCLK (SPICPOL = 0)
tSH
SCLK (SPICPOL = 1)
tSL tSR tSF
tDAV
tDOSS
MISO MSB
tDF
tDR
BITS 6–1 LSB
MOSI
MSB IN
BITS 6–1
LSB IN
06353-007
tDSU
tDHD
Figure 7. SPI Slave Mode Timing (SPICPHA= 0)
Rev. PrA | Page 14 of 136
Preliminary Technical Data
Table 8. UART Timing (Shift Register Mode) Parameters
Parameter tXLXL tQVXH tDVXH tXHDX tXHQX
1
ADE7566/ADE7569
4.096 MHz Core Clock Typ Max 2.93 Variable Core Clock Typ Max 12 × tCORE 1
Description Serial port clock cycle time Output data setup to clock Input data setup to clock Input data hold after clock Output data hold after clock
Min TBD TBD TBD TBD
Min
Unit μs μs μs μs μs
tCORE depends on the clock divider or CD bits of the POWCON SFR, tCORE = 2CD/4.096 MHz.
tXLXL
TxD (OUTPUT CLOCK)
tQVXH tXHQX
RxD (OUTPUT DATA) LSB BIT 1 BIT 6
SET RI OR SET TI
tDVXH
RxD (INPUT DATA) LSB BIT 1
tXHDX
BIT 6 MSB
06353-008
Figure 8. UART Timing in Shift Register Mode
Rev. PrA | Page 15 of 136
ADE7566/ADE7569 ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Table 9.
Parameter VDD to DGND VBAT to DGND VDCIN to DGND Input LCD Voltage to AGND, LCDVA, LCDVB, LCDVC1 Analog Input Voltage to AGND, VP, VN, IAP, and IN Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range (Industrial) Storage Temperature Range 64-Lead LQFP, Power Dissipation Lead Temperature Soldering Time
1
Preliminary Technical Data
Rating −0.3 V to +3.7 V −0.3 V to +3.7 V −0.3 V to VSWOUT + 0.3 V −0.3 V to VSWOUT + 0.3 V −2 V to +2 V −0.3 V to VSWOUT + 0.3 V −0.3 V to VSWOUT + 0.3 V −40°C to +85°C −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 10. Thermal Resistance
Package Type 64-Lead LQFP 64-Lead LFCSP θJA 60 27.1 θJC 20.5 2.3 Unit °C/W °C/W
300°C 30 sec
When used with external resistor divider.
ESD CAUTION
Rev. PrA | Page 16 of 136
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REFIN/OUT VSWOUT RESET FP26 DGND AGND VDCIN VINTD VINTA VBAT VDD EA VN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ADE7566/ADE7569
COM3/FP27 COM2/FP28 COM1 COM0 P1.2/FP25 P1.3/T2EX/FP24 P1.4/T2/FP23 P1.5/FP22 P1.6/FP21
VP
IN
IP
1 2 3 4 5 6 7 8 9 PIN 1
48 47 46 45 44 43 42
INT0 XTAL1 XTAL2 BCTRL/INT1/P0.0 SDEN/P2.3 P0.2/CF1/RTCCAL P0.3/CF2 P0.4/MOSI/SDATA P0.5/MISO P0.6/SCLK/T0 P0.7/SS/T1 P1.0/RxD P1.1/TxD FP0 FP1 FP2
ADE7566/ADE7569
TOP VIEW (Not to Scale)
41 40 39 38 37 36 35 34 33
P1.7/FP20 10 P0.1/FP19 11 P2.0/FP18 12 P2.1/FP17 13 P2.2/FP16 14 LCDVC 15 LCDVP2 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
LCDVA
FP9
FP8
FP7
FP6
FP5
FP4
FP15
FP14
FP13
FP12
FP11
LCDVP1
LCDVB
FP10
FP3
Figure 9. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17, 18 19 35 to 20 36 37 38 39 40 41 42 Mnemonic COM3/FP27 COM2/FP28 COM1 COM0 P1.2/FP25 P1.3/T2EX/FP24 P1.4/T2/FP23 P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16 LCDVC LCDVP2 LCDVB, LCDVA LCDVP1 FP0 to F15 P1.1/TxD P1.0/RxD P0.7/SS/T1 P0.6/SCLK/T0 P0.5/MISO P0.4/MOSI/SDATA P0.3/CF2 Description Common Output. COM3 is used for LCD backplane. / LCD Segment Output 27. Common Output. COM2 is used for LCD backplane. / LCD Segment Output 28. Common Output. COM1 is used for LCD backplanes. Common Output. COM0 is used for LCD backplanes. General-Purpose Digital I/O Port 1.2. / LCD Segment Output 25. General-Purpose Digital I/O Port 1.3. / Timer 2 Control Input. / LCD Segment Output 24. General-Purpose Digital I/O Port 1.4. / Timer 2 Input. / LCD Segment Output 23. General-Purpose Digital I/O Port 1.5. / LCD Segment Output 22. General-Purpose Digital I/O Port 1.6. / LCD Segment Output 21. General-Purpose Digital I/O Port 1.7. / LCD Segment Output 20. General-Purpose Digital I/O Port 0.1. / LCD Segment Output 19. General-Purpose Digital I/O Port 2.0. / LCD Segment Output 18. General-Purpose Digital I/O Port 2.1. / LCD Segment Output 17. General-Purpose Digital I/O Port 2.2. / LCD Segment Output 16. Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor. Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP1 for the internal LCD charge pump device. Output Port for LCD Levels. These pins should be decoupled with a 470 nF capacitor. Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP2 for the internal LCD charge pump device. LCD Segment Output 0 to LCD Segment Output 15. General-Purpose Digital I/O Port 1.1. / Transmitter Data Output 1 (Asynchronous). General-Purpose Digital I/O Port 1.0. / Receiver Data Input 1 (Asynchronous). General-Purpose Digital I/O Port 0.7. / Slave Select when SPI is in Slave Mode. / Timer 1 Input. General-Purpose Digital I/O Port 0.6. / Clock Output for I2C or SPI Port. / Timer 0 Input. General-Purpose Digital I/O Port 0.5. / Data in for SPI Port. General-Purpose Digital I/O Port 0.4. / Data Line I2C-Compatible. / Data Out for SPI Port. General-Purpose Digital I/O Port 0.3. / Calibration Frequency Logic Output. The CF2 logic output gives instantaneous active, reactive, or apparent power information.
Rev. PrA | Page 17 of 136
06353-010
ADE7566/ADE7569
Pin No. 43 Mnemonic P0.2/CF1/RTCCAL
Preliminary Technical Data
Description General-Purpose Digital I/O Port 0.2. / Calibration Frequency Logic Output. The CF1 logic output gives instantaneous active, reactive, or apparent power information / RTC Calibration Frequency Logic Output. The RTCCAL logic output gives access to the calibrated RTC output. This pin is used to enable serial download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input and the status of the pin is sampled. If there is no pulldown resistor in place, the pin momentarily goes high and then user code is executed. If a pull-down resistor is in place, the embedded serial download/debug kernel executes and this pin remains low during internal program execution. / General-Purpose Digital I/O Port 2.3. Digital Input for Battery Control. This logic input connects VDD or VBAT to VSW internally when set to logic high or low, respectively. When left open, the connection between VDD or VBAT and VSW is selected internally. / External Interrupt Input. / General-Purpose Digital I/O Port 0.0. A crystal can be connected across this pin and XTAL1 (see XTAL1 description below) to provide a clock source for the ADE7566/ADE7569. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator circuit. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across XTAL1 and XTAL2 to provide a clock source for the ADE7566/ADE7569. The clock frequency for specified operation is 32.768 kHz. Interrupt Input. Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±500 mV for specified operation. This channel also has an internal PGA. This pin is used as an input for emulation. When held high, this input enables the device to fetch code from internal program memory locations. The ADE7566/ADE7569 do not support external code memory. This pin should not be left floating. Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±500 mV for specified operation. This channel also has an internal PGA. This pin provides the ground reference for the analog circuitry. LCD Segment Output 26. Reset Input, Active Low. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.2 V ± 8% and a typical temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor. 3.3 V Power Supply Input from the Battery. This pin is connected internally to VDD when the battery is selected as the power supply for the ADE7566/ADE7569. This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VDD when the regulator is selected as the power supply for the ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. This pin provides the ground reference for the digital circuitry. Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is 3.3 V with respect to AGND. This pin is used to monitor the pre-regulated dc voltage.
44
SDEN/P2.3
45
BCTRL/INT1/P0.0
46
XTAL2
47
XTAL1
48 49, 50 51
INT0 VP, VN EA
52, 53 54 55 56 57
IP, IN AGND FP26 RESET REFIN/OUT
58 59 60
VBAT VINTA VDD
61
VSWOUT
62 63 64
VINTD DGND VDCIN
Rev. PrA | Page 18 of 136
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
ADE7566/ADE7569
Figure 10.
Figure 13.
Figure 11.
Figure 14.
Figure 12.
Figure 15.
Rev. PrA | Page 19 of 136
ADE7566/ADE7569
Preliminary Technical Data
Figure 16.
Figure 19.
Figure 17.
Figure 20.
Figure 18.
Figure 21.
Rev. PrA | Page 20 of 136
Preliminary Technical Data TERMINOLOGY
Measurement Error The error associated with the energy measurement made by the ADE7566/ADE7569 is defined by the following formula:
ADE7566/ADE7569
For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading. ADC Offset Error This is the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection (see the Typical Performance Characteristics section). However, when HPF1 is switched on, the offset is removed from the current channel and the power calculation is not affected by this offset. The offsets can be removed by performing an offset calibration (see the Analog Inputs section). Gain Error Gain Error is the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC and Voltage Channel ADC sections). It is measured for each of the gain setting on the current channel (1, 2, 4, 8, and 16). The difference is expressed as a percentage of the ideal code.
⎛ Energy Register − True Energy ⎞ ⎟ × 100% Percentage Error = ⎜ ⎜ ⎟ True Energy ⎝ ⎠
Phase Error Between Channels The digital integrator and the high-pass filter (HPF) in the current channel have a non-ideal phase response. To offset this phase response and equalize the phase response between channels, two phase-correction networks are placed in the current channel: one for the digital integrator and the other for the HPF. The phase correction networks correct the phase response of the corresponding component, and ensure a phase match between current channel and voltage channel to within ±0.1° over a range of 45 Hz to 65 Hz with the digital integrator off. With the digital integrator on, the phase is corrected to within ±0.4° over a range of 45 Hz to 65 Hz. Power Supply Rejection (PSR) This quantifies the ADE7566/ADE7569 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac (100 mV rms/120 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading (see the Measurement Error definition).
Rev. PrA | Page 21 of 136
ADE7566/ADE7569 SFR MAPPING
Table 12.
Mnemonic IPSMF STRBPER BATVTH SCRATCH1 SCRATCH2 SCRATCH3 SCRATCH4 INTPR B DIFFPROG PERIPH BATPR RTCCOMP TEMPCAL SPIMOD1 I2CMOD SPIMOD2 I2CADR SPISTAT SPI2CSTAT IPSME LCDSEGE2 VDCINADC ACC WAV1L WAV1M WAV1H WAV2L WAV2M WAV2H ADCGO MIRQENL MIRQENM MIRQENH MIRQSTL MIRQSTM MIRQSTH BATADC PSW VRMSL VRMSM VRMSH IRMSL IRMSM IRMSH TEMPADC T2CON RCAP2L RCAP2H TL2 TH2 WDCON KYREG POWCON Address 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF 0xF0 0xF3 0xF4 0xF5 0xF6 0xF7 0xE8 0xE8 0xE9 0xE9 0xEA 0xEA 0xEC 0xED 0xEF 0xE0 0xE2 0xE3 0xE4 0xE5 0xE7 0xE7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xC8 0xCA 0xCB 0xCC 0xCD 0xC0 0xC1 0xC5 Details Table 15 Table 45 Table 48 Table 19 Table 20 Table 21 Table 22 Table 14 Table 52 Table 46 Table 17 Table 16 Table 122 Table 123 Table 136 Table 141 Table 137 Table 142 Table 138 Table 143 Table 18 Table 84 Table 49 Table 28 Table 28 Table 28 Table 28 Table 28 Table 28 Table 28 Table 47 Table 39 Table 40 Table 41 Table 36 Table 37 Table 38 Table 50 Table 53 Table 28 Table 28 Table 28 Table 28 Table 28 Table 28 Table 51 Table 101 Table 109 Table 108 Table 107 Table 106 Table 71 Table 112 Table 23 Mnemonic EADRL EADRH IP ECON FLSHKY PROTKY EDATA PROTB0 PROTB1 PROTR LCDCONY PINMAP0 PINMAP1 PINMAP2 IE IEIP2 LCDPTR LCDDAT CFG P2 TIMECON HTHSEC SEC MIN HOUR INTVAL DPCON SCON SBUF SPI2CTx SPI2CRx LCDCONX SBAUDF SBAUDT EPCFG P1 MADDPT MDATL MDATM MDATH LCDCON LCDCLK LCDSEGE TCON TMOD TL0 TL1 TL0 TH1 P0 SP DPL DPH PCON
Preliminary Technical Data
Address 0xC6 0xC7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xB1 0xB2 0xB3 0xB4 0xA8 0xA9 0xAC 0xAE 0xAF 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x80 0x81 0x82 0x83 0x87
Details Table 95 Table 96 Table 65 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 77 Table 147 Table 148 Table 149 Table 64 Table 66 Table 82 Table 83 Table 59 Table 152 Table 116 Table 117 Table 118 Table 119 Table 120 Table 121 Table 144 Table 128 Table 129 Table 134 Table 135 Table 75 Table 131 Table 130 Table 146 Table 151 Table 28 Table 28 Table 28 Table 28 Table 74 Table 78 Table 81 Table 100 Table 99 Table 103 Table 105 Table 102 Table 104 Table 150 Table 58 Table 55 Table 56 Table 54
Rev. PrA | Page 22 of 136
Preliminary Technical Data POWER MANAGEMENT
ADE7566/ADE7569
The ADE7566/ADE7569 have an elaborate power management circuitry that manages the regular power supply to battery switchover and power supply failures. The power management functionalities can be accessed directly through the 8052 SFRs (see Table 13). Table 13. Power Management SFRs
SFR Address 0xEC 0xF5 0xF8 0xFF 0xF4 0xC5 0xFB 0xFC 0xFD 0xFE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic IPSME BATPR IPSMF INTPR PERIPH POWCON SCRATCH1 SCRATCH2 SCRATCH3 SCRATCH4 Description Power Management Interrupt Enable. See Table 18. Battery Switchover Configuration. See Table 16. Power Management Interrupt Flag. See Table 15. Interrupt Wake-Up Configuration. See Table 14. Peripheral Configuration SFR. See Table 17. Power Control. See Table 23. Scratch Pad 1. See Table 19. Scratch Pad 2. See Table 20. Scratch Pad 3. See Table 21. Scratch Pad 4. See Table 22.
POWER MANAGEMENT REGISTER DETAILS
Table 14. Interrupt Pins Configuration SFR (INTPR, 0xFF)
Bit No. 7 6 to 5 Mnemonic RTCCAL FSEL[1:0] Default 0 00 Description Controls RTC calibration output. When set, the RTC calibration frequency selected by FSEL[1:0] is output on the P0.2/CF1/RTCCAL pin. Sets RTC calibration output frequency and calibration window. FSEL[1:0] Result (Calibration window, frequency) 00 30.5 sec, 1 Hz 01 30.5 sec, 512 Hz 10 0.244 sec, 500 Hz 11 0.244 sec, 16.384 kHz Controls the function of INT1. INT1PRG[2:0] X00 X01 01X 11X 0 INT0PRG 0 INT0PRG 0 1 Result GPIO enabled BCTRL enabled INT1 input disabled INT1 input enabled Result INT0 input disabled INT0 input enabled
4 3 to 1
Reserved INT1PRG[2:0]
000
Controls the function of INT0.
Writing to the Interrupt Pins Configuration SFR (INTPR, 0xFF)
To protect the RTC from runaway code, a key must be written to the Key SFR (KYREG, 0xC1) to obtain write access to the Interrupt Pins Configuration SFR (INTPR, 0xFF). KYREG should be set to 0xEA to unlock this SFR and reset to zero after a timekeeping register is written to. The RTC registers can be written using the following 8052 assembly code: MOV MOV KYREG, #0EAh INTPR, #080h
Rev. PrA | Page 23 of 136
ADE7566/ADE7569
Table 15. Power Management Interrupt Flag SFR (IPSMF, 0xF8)
Bit No. 7 6 5 4 3 2 1 0 Address 0xFF 0xFE 0xFD 0xFC 0xFB 0xFA 0xF9 0xF8 Mnemonic FPSR FPSM FSAG RESERVED FVADC FBAT FBSO FVDCIN Default 0 0 0 0 0 0 0 0
Preliminary Technical Data
Description Power Supply Restored Interrupt Flag. Set when the VDD power supply has been restored. This occurs when the source of VSW changes from VBAT to VDD. PSM Interrupt Flag. Set when an enabled PSM interrupt condition occurs. Voltage SAG Interrupt Flag. Set when an ADE energy measurement SAG condition occurs. This bit must be kept cleared for proper operation. VDCIN Monitor Interrupt Flag. Set when VDCIN changes by VDCIN_DIFF or when VDCIN measurement is ready. VBAT Monitor Interrupt Flag. Set when VBAT falls below BATVTH or when VBAT measurement is ready. Battery Switchover Interrupt Flag. Set when VSW switches from VDD to VBAT. VDCIN Monitor Interrupt Flag. Set when VDCIN falls below 1.2 V.
Table 16. Battery Switchover Configuration SFR (BATPR, 0xF5)
Bit No. 7 to 2 1 to 0 Mnemonic Reserved BATPRG[1:0] Default 00 00 Description These bits must be kept to 0 for proper operation. Control Bits for Battery Switchover. BATPRG[1:0] Result 00 Battery switchover enabled on low VDD 01 Battery switchover enabled on low VDD and low VDCIN 1X Battery switchover disabled
Table 17. Peripheral Configuration SFR (PERIPH, 0xF4)
Bit No. 7 6 5 4 3 2 1 to 0 Mnemonic RXFLAG VSWSOURCE VDD_OK PLL_FLT REF_BAT_EN Reserved RXPROG[1:0] Default 0 1 1 0 0 0 00 Description If set, indicates that an Rx edge event triggered wake-up from PSM2. Indicates the power supply that is internally connected to VSW (0 VSW = VBAT, 1 VSW = VDD). If set, indicates that VDD power supply is ready for operation. If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the fault and clear the PLL_FLT bit. If set, internal voltage reference enabled in PSM2 mode. This bit should be set if LCD is on in PSM2 mode. This bit should be kept to zero. Controls the function of the P1.0/RxD pin. RXPROG[1:0] Result 00 GPIO 01 RxD with wake-up disabled 11 RxD with wake-up enabled
Table 18. Power Management Interrupt Enable SFR (IPSME, 0xEC)
Bit No. 7 6 5 4 3 2 1 0 Interrupt Enable Bit EPSR RESERVED ESAG RESERVED EVSW EBAT EBSO EVDCIN Default 0 0 0 0 0 0 0 0 Description Enables a PSM interrupt when the power supply restored flag (FPSR) is set. Reserved. Enables a PSM interrupt when the voltage SAG flag (FSAG) is set. This bit must be kept cleared for proper operation. Enables a PSM interrupt when the VSW monitor flag (FVSW) is set. Enables a PSM interrupt when the VBAT monitor flag (FBAT) is set. Enables a PSM interrupt when the battery switchover flag (BSFO) is set. Enables a PSM interrupt when the VDCIN monitor flag (FVDCIN) is set.
Rev. PrA | Page 24 of 136
Preliminary Technical Data
Table 19. Scratch Pad 1 SFR (SCRATCH1, 0xFB)
Bit No. 7 to 0 Mnemonic SCRATCH1 Default 0
ADE7566/ADE7569
Description Value can be written/read in this register. This value is maintained in all the power-saving modes.
Table 20. Scratch Pad 2 SFR (SCRATCH2, 0xFC)
Bit No. 7 to 0 Mnemonic SCRATCH2 Default 0 Description Value can be written/read in this register. This value is maintained in all the power-saving modes.
Table 21. Scratch Pad 3 SFR (SCRATCH3, 0xFD)
Bit No. 7 to 0 Mnemonic SCRATCH3 Default 0 Description Value can be written/read in this register. This value is maintained in all the power-saving modes.
Table 22. Scratch Pad 4 SFR (SCRATCH4, 0xFE)
Bit No. 7 to 0 Mnemonic SCRATCH4 Default 0 Description Value can be written/read in this register. This value is maintained in all the power-saving modes.
Table 23. Power Control SFR (POWCON, 0xC5)
Bit No. 7 6 5 4 3 2 to 0 Mnemonic RESERVED METER_OFF RESERVED COREOFF RESERVED CD[2:0] Default 0 0 0 0 0 010 Description Reserved. Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering functions are not needed in PSM0. Reserved. Set this bit to shut down the core if in the PSM1 operating mode. Reserved. Controls the core clock frequency, fCORE. fCORE = 4.096 MHz/2CD. CD[2:0] Result (fCORE in MHz) 000 4.096 001 2.048 010 1.024 011 0.512 100 0.256 101 0.128 110 0.064 111 0.032
Writing to the Power Control SFR (POWCON, 0xC5)
Writing data to the POWCON SFR involves a double instruction sequence. Global interrupts must first be disabled to ensure that the two instructions occur consecutively. The Key SFR (KYREG, 0xC1) is set to 0xA7 and is immediately followed by a write to the POWCON SFR. For example: CLR EA MOV KYREG,#0A7h MOV POWCON, #10H NOP NOP ;Disable Interrupts while configuring to WDT ;Write KYREG to 0xA7 to get write access to the POWCON SFR ;Shutdown the core
Rev. PrA | Page 25 of 136
ADE7566/ADE7569
POWER SUPPLY ARCHITECTURE
Each ADE7566/ADE7569 have two power supply inputs, VDD and VBAT, and require only a single 3.3 V power supply at VDD for full operation. A battery backup, or secondary power supply, with a maximum of 3.6 V can be connected to the VBAT input. Internally, the ADE7566/ADE7569 connect VDD or VBAT to VSW, which is used to derive power for the ADE7566/ADE7569 circuitry. The VSWOUT output pin reflects the voltage at VSW and has a maximum output current of 6 mA. This pin can also be used to power a limited number of peripheral components. The 2.5 V analog supply (VINTA) and the 2.5 V supply for the core logic (VINTD) are derived by on-chip linear regulators from VSW. Figure 22 shows the power supply architecture of ADE7566/ADE7569. The ADE7566/ADE7569 provide automatic battery switchover between VDD and VBAT based on the voltage level detected at VDD or VDCIN. Additionally, the BCTRL input can be used to trigger a battery switchover. The conditions for switching VSW from VDD to VBAT and back to VDD are described in the Battery Switchover section. VDCIN is an input pin that can be connected to a 0 V to 3.3 V dc signal. This input is intended for power supply supervisory purposes and does not provide power to the ADE7566/ ADE7569 circuitry (see the Battery Switchover section).
VDCIN VDD VBAT VSWOUT
Preliminary Technical Data
The battery switchover functionality provided by the ADE7566/ADE7569 allows a seamless transition from VDD to VBAT. An automatic battery switchover option ensures a stable power supply to the ADE7566/ADE7569, as long as the external battery voltage is above 2.75 V. It allows continuous code execution even while the internal power supply is switching from VDD to VBAT and back. Note that the energy metering ADCs are not available when VBAT is being used for VSW. Power supply monitor (PSM) interrupts can be enabled to indicate when battery switchover occurs and when the VDD power supply is restored (see the Power Supply Monitor Interrupt (PSM) section.)
Switching from VDD to VBAT
The following three events switch the internal power supply (VSW) from VDD to VBAT: • VDCIN < 1.2 V. When VDCIN falls below 1.2V, VSW switches from VDD to VBAT. This event is enabled when the BATPRG[1:0] bits in the Battery Switchover Configuration SFR (BATPR, 0xF5) = 0b01. Setting these bits disables switchover based on VDCIN. Battery switchover on low VDCIN is disabled by default. VDD < 2.75 V. When VDD falls below 2.75 V, VSW switches from VDD to VBAT. This event is enabled when BATPRG[1:0] in the Battery Switchover Configuration SFR (BATPR, 0xF5) are cleared. Rising edge on BCTRL. When the battery control pin, BCTRL, goes high, VSW switches from VDD to VBAT. This external switchover signal can trigger a switchover to VBAT at any time. Setting bits INT1PRG[4:2] to 0bx01 in the Interrupt Pins Configuration SFR (INTPR, 0xFF) enables the battery control pin.
•
ADC LDO BCTRL POWER SUPPLY MANAGEMENT VSW LDO ADC
VINTD
MCU
VINTA
ADE
•
SPI/I2C SCRATCHPAD LCD RTC UART TEMPERATURE ADC 3.3V 2.5V
06353-011
Switching from VBAT to VDD
To switch VSW back from VBAT to VDD, all of the following events that are enabled to force battery switchover must be false: • VDCIN < 1.2 V and VDD < 2.75 V enabled. If the low VDCIN condition is enabled, VSW switches to VDD after VDCIN remains above 1.2 V and VDD remains above 2.75 V. VDD < 2.75 V enabled. VSW switches back to VDD after VDD has been above 2.75 V. BCTRL enabled. VSW switches back to VDD after BCTRL is low and the first or second bullet point is satisfied.
Figure 22. Power Supply Architecture
BATTERY SWITCHOVER
The ADE7566/ADE7569 monitor VDD, VBAT, and VDCIN. Automatic battery switchover from VDD to VBAT can be configured based on the status of VDD, VDCIN, or the BCTRL pin. Battery switchover is enabled by default. Setting Bit 1 in the Battery Switchover Configuration SFR (BATPR, 0xF5) disables battery switchover so that VDD is always connected to VSW. The source of VSW is indicated by Bit 6 in the Peripheral Configuration SFR (PERIPH, 0xF4), which is set when VSW is connected to VDD and cleared when VSW is connected to VBAT.
• •
Rev. PrA | Page 26 of 136
Preliminary Technical Data
POWER SUPPLY MONITOR INTERRUPT (PSM)
The power supply monitor interrupt (PSM) alerts the 8052 core of power supply events. The PSM interrupt is disabled by default. Setting the EPSM bit in the Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9) enables the PSM interrupt.
ADE7566/ADE7569
The Power Management Interrupt Enable SFR (IPSME, 0xEC) controls the events that result in a PSM interrupt. Figure 23 is a diagram illustrating how the PSM interrupt vector is shared among the PSM interrupt sources. The PSM interrupt flags are latched and must be cleared by writing to the flag register.
EPSR FPSR ESAG FSAG EVSW FVSW EBAT FBAT EBSO FBSO EVDCIN FVDCIN FPSM EPSM TRUE? PENDING PSM INTERRUPT
IPSME ADDR. 0xEC
EPSR
RESERVED
ESAG
RESERVED
EVSW
EBAT
EBSO
EVDCIN
IPSMF ADDR. 0xF8
FPSR
FPSM
FSAG
RESERVED
FVSW
FBAT
FBSO
FVDCIN
IEIP2 ADDR. 0xA9
RESERVED
PTI
RESERVED
PSI
EADE
ETI
EPSM
ESI
06353-012
NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN
Figure 23. PSM Interrupt Sources
Rev. PrA | Page 27 of 136
ADE7566/ADE7569
Battery Switchover and Power Supply Restored PSM Interrupt
The ADE7566/ADE7569 can be configured to generate a PSM interrupt when the source of VSW changes from VDD to VBAT, indicating battery switchover. Setting the EBSO bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. The ADE7566/ADE7569 can also be configured to generate an interrupt when the source of VSW changes from VBAT to VDD, indicating that the VDD power supply has been restored. Setting the EPSR bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. The flags in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) for these interrupts, FBSO and FPSR, are set regardless of whether the respective enable bits have been set. The battery switchover and power supply restore event flags, FBSO and FPSR, are latched. These events must be cleared by writing a 0 to these bits. Bit 6 in the Peripheral Configuration SFR (PERIPH, 0xF4), VSWSOURCE, tracks the source of VSW. The bit is set when VSW is connected to VDD and cleared when VSW is connected to VBAT.
Preliminary Technical Data
See the External Voltage Measurement section for details on how VDCIN is measured.
VBAT Monitor PSM Interrupt
The VBAT voltage is measured using a dedicated ADC. These measurements take place in the background at intervals to check the change in VBAT. The FBAT bit is set when the battery level is lower than the threshold set in the Battery Detection Threshold SFR (BATVTH, 0xFA) or when a new measurement is ready in the Battery ADC Value SFR (BATADC, 0xDF). See the Battery Measurement section for more information. Setting the EBAT bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt.
VDCIN Monitor PSM Interrupt
The VDCIN voltage is monitored by a comparator. The FVDCIN bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is set when the VDCIN input level is lower than 1.2 V. Setting the EVDCIN bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. This event, which is associated with the SAG monitoring, can be used to detect a power supply (VDD) being compromised and to trigger further actions prior to deciding a switch of VDD to VBAT .
VDCIN ADC PSM Interrupt
The ADE7566/ADE7569 can be configured to generate a PSM interrupt when VDCIN changes magnitude by more than a configurable threshold. This threshold is set in the Temperature and Supply Delta SFR (DIFFPROG, 0xF3). See the External Voltage Measurement section for more information. Setting the EVDCIN bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. The VDCIN voltage is measured using a dedicated ADC. These measurements take place in the background at intervals to check the change in VDCIN. Conversions can also be initiated by writing to the Start ADC Measurement SFR (ADCGO, 0xD8). The FVDCIN flag indicates when a VDCIN measurement is ready.
SAG Monitor PSM Interrupt
The ADE7566/ADE7569 energy measurement DSP monitors the ac voltage input at the VP and VN input pins. The SAGLVL register is used to set the threshold for a line voltage SAG event. The FSAG bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is set if the line voltage stays below the level set in the SAGLVL register for the number of line cycles set in the SAGCYC register. See the Line Voltage Sag Detection section for more information. Setting the ESAG bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt.
Rev. PrA | Page 28 of 136
Preliminary Technical Data
USING THE POWER SUPPLY FEATURES
In an energy meter application, the 3.3 V power supply (VDD), is typically generated from the ac line voltage and regulated to 3.3 V by a voltage regulator IC. The pre-regulated dc voltage, typically 5 V to 12 V, can be connected to VDCIN through a resistor divider. A 3.6 V battery can be connected to VBAT. Figure 24 shows how the ADE7566/ADE7569 power supply inputs would be set up in this application. Figure 25 shows the sequence of events that would occur if the main power supply generated by the PSU started to fail in the power meter application shown in Figure 24. The SAG detection can provide the earliest warning of a potential
ADE7566/ADE7569
problem on VDD. When a SAG event occurs, the user code can be configured to backup data and prepare for battery switchover if desired. The relative spacing of these interrupts depends on the design of the power supply. Figure 26 shows the sequence of events that would occur if the main power supply started to fail in the power meter application shown in Figure 24, with battery switchover on low VDCIN or low VDD enabled. Finally, the transition between VDD and VBAT and the different Power Supply Modes (see the Operating Modes section) are represented in Figure 28.
(240V, 220V, 110V TYPICAL) AC INPUT
BCTRL 45 VP
49
VN
50
SAG DETECTION
5V TO 12V DC
VDCIN
64
VOLTAGE SUPERVISORY
VOLTAGE SUPERVISORY 3.3V REGULATOR VDD
60
POWER SUPPLY MANAGEMENT
IPSMF SFR (ADDR. 0xF8)
PSU
VSW VSWOUT 61
06353-013
VBAT 58
Figure 24. Power Supply Management for Energy Meter Application
VP – VN SAG LEVEL TRIP POINT SAGCYC = 1
VDCIN 1.2V
VDD 2.75V
t1
t2
SAG EVENT (FSAG = 1) VDCIN EVENT (FVDCIN = 1) IF SWITCHOVER ON LOW VDD IS ENABLED, AUTOMATIC BATTERY SWITCHOVER VSW CONNECTED TO VBAT
BSO EVENT (FBSO = 1)
Figure 25. Power Supply Management Interrupts and Battery Switchover with Only VDD Enabled for Battery Switchover
Rev. PrA | Page 29 of 136
06353-014
ADE7566/ADE7569
VP – VN SAG LEVEL TRIP POINT SAGCYC = 1
Preliminary Technical Data
VDCIN 1.2V
t3
VDD 2.75V
t1
SAG EVENT (FSAG = 1)
VDCIN EVENT (FVDCIN = 1)
IF SWITCHOVER ON LOW VDCIN IS ENABLED, AUTOMATIC BATTERY SWITCHOVER VSW CONNECTED TO VBAT
BSO EVENT (FBSO = 1)
Figure 26. Power Supply Management Interrupts and Battery Switchover with VDD or VDCIN Enabled for Battery Switchover
Table 24. Power Supply Event Timing Operating Modes
Parameter t1 t2 t3 t4 Time 10 ns min 10 ns min 30 ms 130 ms Description Time between when VDCIN goes below 1.2 V and when VSWF is raised. Time between when VDD falls below 2.75 V and when battery switchover occurs. Time between when VDCIN falls below 1.2 V and when battery switchover occurs if VDCIN is enabled to cause battery switchover. Time between when power supply restore conditions are met (VDCIN above 1.2 V and VDD above 2.75 V if BATPR[1:0] = 0b01 or VDD above 2.75 V if BATPR[1:0] = 0b00) and when VSW switches to VDD.
VP − VN SAG LEVEL TRIP POINT
VDCIN 1.2V
SAG EVENT
VDCIN EVENT
VDCIN EVENT
t3
VBAT VDD 2.75V
t4
VSW BATTERY SWITCH ENABLED ON LOW VDCIN VSW BATTERY SWITCH ENABLED ON LOW VDD
PSM0 PSM1 OR PSM2
PSM0
PSM0
t2
t4
PSM0
PSM1 OR PSM2
Figure 27. Power Supply Management Transitions Between Modes
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06353-016
06353-015
Preliminary Technical Data OPERATING MODES
PSM0 (NORMAL MODE)
In PSM0, normal operating mode, VSW is connected to VDD. All of the analog and digital circuitry powered by VINTD and VINTA are enabled by default. In normal mode, the default clock frequency, fCORE, established during a power-on reset or software reset, is 1.024 MHz. • •
ADE7566/ADE7569
The RAM in the MCU is no longer valid. The program counter for the 8052, also held in volatile memory, becomes invalid when the 2.5 V supply is shut down. Therefore, the program does not resume from where it left off, but always starts from the power-on reset vector when the ADE7566/ADE7569 come out of PSM2.
PSM1 (BATTERY MODE)
In PSM1, battery mode, VSW is connected to VBAT. In this operating mode, the 8052 core and all of the digital circuitry are enabled by default. The analog circuitry for the ADE energy metering DSP powered by VINTA is disabled. This analog circuitry automatically restarts once the VDD supply is above 2.75 V and if the PWRDN bit in the MODE1 Register (0x0B) is cleared. The default fCORE for PSM1, established during a power-on reset or software reset, is 1.024 MHz.
The 3.3 V peripherals (temperature ADC, VDCIN ADC, RTC, and LCD) are active in PSM2. They can be enabled or disabled to reduce power consumption and are configured for PSM2 operation when the MCU core is active (see Table 26 for more information about the individual peripherals and their PSM2 configuration). The ADE7566/ADE7569 remain in PSM2 until an event occurs to wake it up. In PSM2, the ADE7566/ADE7569 provide four scratch pad RAM SFRs that are maintained during this mode. These SFRs can be used to save data from PSM0 or PSM1 when entering PSM2 (see Table 18 to Table 22). In PSM2, the ADE7566/ADE7569 maintain some SFRs (see Table 25). The SFRs that are not listed in this table should be restored when the part enters PSM0 or PSM1 from PSM2.
PSM2 (SLEEP MODE)
PSM2 is a low power consumption sleep mode for use in battery operation. In this mode, VSW is connected to VBAT. All of the 2.5 V digital and analog circuitry powered through VINTA and VINTD are disabled, including the MCU core, resulting in the following:
Table 25. SFR Maintained in PSM2
I/O Configuration Interrupt Pins Configuration SFR (INTPR, 0xFF) Peripheral Configuration SFR (PERIPH, 0xF4) Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2) Port 1 Weak Pull-Up Enable SFR (PINMAP1, 0xB3) Port 2 Weak Pull-Up Enable SFR (PINMAP2, 0xB4) Scratch Pad 1 SFR (SCRATCH1, 0xFB) Scratch Pad 2 SFR (SCRATCH2, 0xFC) Scratch Pad 3 SFR (SCRATCH3, 0xFD) Scratch Pad 4 SFR (SCRATCH4, 0xFE) Power Supply Monitoring Battery Detection Threshold SFR (BATVTH, 0xFA) Battery Switchover Configuration SFR (BATPR, 0xF5) Battery ADC Value SFR (BATADC, 0xDF) Peripheral ADC Strobe Period SFR (STRBPER, 0xF9) Temperature and Supply Delta SFR (DIFFPROG, 0xF3) VDCIN ADC Value SFR (VDCINADC, 0xEF) Temperature ADC Value SFR (TEMPADC, 0xD7) – – RTC Peripherals RTC Nominal Compensation SFR (RTCCOMP, 0xF6) RTC Temperature Compensation SFR (TEMPCAL, 0xF7) RTC Configuration SFR (TIMECON, 0xA1) Hundredths of a Second Counter SFR (HTHSEC, 0xA2) Seconds Counter SFR (SEC, 0xA3) Minutes Counter SFR (MIN, 0xA4) Hours Counter SFR (HOUR, 0xA5) Alarm Interval SFR (INTVAL, 0xA6) – LCD Peripherals LCD Segment Enable 2 SFR (LCDSEGE2, 0xED) LCD Configuration Y SFR (LCDCONY, 0xB1) LCD Configuration X SFR (LCDCONX, 0x9C) LCD Configuration SFR (LCDCON, 0x95) LCD Clock SFR (LCDCLK, 0x96) LCD Segment Enable SFR (LCDSEGE, 0x97) LCD Pointer SFR (LCDPTR, 0xAC) LCD Data SFR (LCDDAT, 0xAE) –
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ADE7566/ADE7569
3.3 V PERIPHERALS AND WAKE-UP EVENTS
Preliminary Technical Data
Some of the 3.3 V peripherals are capable of waking the ADE7566/ADE7569 from PSM2. The events that can cause the ADE7566/ADE7569 to wake up from PSM2 are listed in the wake-up events column in Table 26. Table 26. 3.3 V Peripherals and Wake-up Events
3.3 V Peripheral Temperature ADC Comments The temperature ADC can wake-up the 8052 if the ITADC flag is set. This flag is set according to the description in the Temperature Measurement section. This wake-up event can be disabled by disabling temperature measurements in the Temperature and Supply Delta SFR (DIFFPROG, 0xF3) in PSM2. Maskable VSWF IPSM The VSW measurement can wake up the 8052. The VSWF is set ΔV according to the description in the External Voltage Measurement section. This wake-up event can be disabled by clearing the EVSW in the Power Management Interrupt Enable SFR (IPSME, 0xEC). PSR Nonmaskable PSR IPSM The 8052 wakes up if the power supply is restored (if VSW switches to be connected to VDD). The VSWSOURCE flag, Bit 6 of the Peripheral Configuration SFR (PERIPH, 0xF4) SFR, is set to indicate that VSW is connected to VDD.. Midnight Nonmaskable Midnight IRTC The ADE7566/ADE7569 wakes up at midnight every day to update its calendar. Alarm Maskable Alarm IRTC Set an alarm to wake the ADE7566/ADE7569 after the desired amount of time. The RTC alarm is enabled by setting the ALARM bit in the RTC Configuration SFR (TIMECON, 0xA1). All I/O pins are treated as inputs. The weak pull-up on each I/O pin can be disabled individually in the Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2), Port 1 Weak Pull-Up Enable SFR (PINMAP1, 0xB3), and Port 2 Weak Pull-Up Enable SFR (PINMAP2, 0xB4) to decrease current consumption. The interrupts can be enabled/disabled. INT0PRG = 1 – IE0 The edge of the interrupt is selected by Bit IT0 in the TCON register. INT0 The IE0 flag bit in the TCON register is not affected. INT1PRG[2:0] = – IE1 The edge of the interrupt is selected by Bit IT1 in the TCON register. INT1 11x The IE1 flag bit in the TCON register is not affected. Rx Edge RXPROG[1:0] = PERIPH.7 – An Rx edge event occurs if a rising or falling edge is detected on the 11 (RXFG) Rx line. RESET Nonmaskable – If the RESET pin is brought low while the ADE7566/ADE7569 is in – PSM2, it wakes up to PSM1. – – – – The LCD can be enabled/disabled in PSM2. The LCD data memory remains intact. – – – – The 4 SCRATCHx registers remain intact in PSM2. Wake-Up Event ∆T Wake-Up Enable Bits Maskable Flag – Interrupt Vector ITADC
VSW ADC
Power Supply Management
RTC
I/O Ports
External Reset LCD Scratch Pad
Rev. PrA | Page 32 of 136
Preliminary Technical Data
TRANSITIONING BETWEEN OPERATING MODES
The operating mode of the ADE7566/ADE7569 is determined by the power supply connected to VSW. Therefore, changes in the power supply such as when VSW switches from VDD to VBAT, or when VSW switches to VDD, alters the operating mode. This section describes events that change the operating mode.
ADE7566/ADE7569
Automatic Switch to VDD (PSM1 to PSM0)
If the conditions to switch VSW from VBAT to VDD occur (see the Battery Switchover section), the operating mode switches to PSM0. When this switch occurs, the analog circuitry used in the ADE energy measurement DSP automatically restarts. Note that code execution continues normally. A software reset can be performed to start PSM0 code execution at the power-on reset vector.
Automatic Battery Switchover (PSM0 to PSM1)
If any of the enabled battery switchover events occur (see the Battery Switchover section), VSW switches to VBAT. This switchover results in a transition from the PSM0 to PSM1 operating mode. When battery switchover occurs, the analog circuitry used in the ADE energy measurement DSP is disabled. To reduce power consumption, the user code can initiate a transition to PSM2.
USING THE POWER MANAGEMENT FEATURES
Because program flow is different for each operating mode, the status of VSW must be known at all times. The FVSW bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) indicates what VSW is connected to. This bit can be used to control program flow on wake-up. Because code execution always starts at the power-on reset vector, Bit 6 of the Peripheral Configuration SFR (PERIPH, 0xF4) can be tested to determine which power supply is being used and to branch to normal code execution, or to wake up event code execution. Power supply events can also occur when the MCU core is active. To be aware of the events that change what VSW is connected to, use the following guidelines: • • Enable the battery switchover interrupt (EVSW) if VSW = VDD at power-up. Enable the power supply restored interrupt (EPSR) if VSW = VBAT at power-up.
Entering Sleep Mode (PSM1 to PSM2)
To reduce power consumption when VSW is connected to VBAT, user code can initiate sleep mode, PSM2, by setting Bit 4 in the Power Control SFR (POWCON, 0xC5) to shut down the MCU core. Events capable of waking the MCU can be enabled (see the 3.3 V Peripherals and Wake-Up Events section).
Servicing Wake-Up Events (PSM2 to PSM1)
The ADE7566/ADE7569 may need to wake up from PSM2 to service wake-up events (see the 3.3 V Peripherals and Wake-Up Events section). PSM1 code execution begins at the power-on reset vector. After servicing the wake-up event, the ADE7566/ ADE7569 can return to PSM2 by setting Bit 4 in the Power Control SFR (POWCON, 0xC5) to shut down the MCU core.
Automatic Switch to VDD (PSM2 to PSM0)
If the conditions to switch VSW from VBAT to VDD occur (see the Battery Switchover section), the operating mode switches to PSM0. When this switch occurs, the MCU core and the analog circuitry used in the ADE energy measurement DSP automatically restarts. PSM0 code execution begins at the power-on reset vector.
POWER SUPPLY RESTORED
An early warning that battery switchover is about to occur is provided by SAG detection and possibly low VDCIN detection (see the Battery Switchover section). For a user-controlled battery switchover, enable automatic battery switchover on low VDD only. Then, enable the low VDCIN event to generate the PSM interrupt. When a low VDCIN event occurs, start data backup. Upon completion of the data backup, enable battery switchover on low VDCIN. Battery switchover occurs 30 ms later.
PSMO
NORMAL MODE VSW CONNECTED TO VDD
AUTOMATIC BATTERY SWITCHOVER
PSM1
BATTERY MODE VSW CONNECTED TO VBAT
POWER SUPPLY RESTORED
WAKEUP EVENT USER CODE DIRECTS MCU TO SHUTDOWN CORE AFTER SERVICING WAKE-UP EVENT
PSM2
06353-017
SLEEP MODE VSW CONNECTED TO VBAT
Figure 28. Transitioning Between Operating Modes
Rev. PrA | Page 33 of 136
ADE7566/ADE7569 ENERGY MEASUREMENT
The ADE7566/ADE7569 offer a fixed function, energy measurement, digital processing core that provides all the information needed to measure energy in single-phase energy meters. The part provides two ways to access the energy measurements: direct access through SFRs for time sensitive information and indirect access through address and data SFR registers for the majority of energy measurements. The Irms, Vrms, interrupts, and waveform registers are readily available through SFRs as shown in Table 27. Other energy measurement information is mapped to a page of memory that is accessed indirectly through the MADDPT, MDATL, MDATM, and MDATH SFRs. The address and data registers act as pointers to the energy measurement internal registers.
Preliminary Technical Data
Writing to the Internal Energy Measurement Registers
When Bit 7 of the Energy Measurement Pointer Address SFR (MADDPT, 0x91) is set, the content of the MDATx SFRs (MDATL, MDATM, and MDATH) is transferred to the internal energy measurement register designated by the address in the MADDPT SFR. If the internal register is 1 byte long, only the MDATL SFR content is copied to the internal register, while the MDATM SFR and MDATH SFR contents are ignored. The energy measurement core functions with an internal clock of 4.096 MHz ∕ 5 or 819.2 kHz. Because the 8052 core functions with another clock, 4.096MHz ∕ 2CD, synchronization between the two clock environments when CD = 0 or 1 is an issue. When data is written to the internal energy measurement, a small wait period needs to be implemented before another read or write to these registers can take place. Sample 8051 code to write 0x0155 to the 2-byte SAGLVL register located at 0x14 in the energy measurement memory space is shown below. MOV MOV MOV MOV DJNZ MDATM,#01h MDATL,#55h MADDPT,#SAGLVL_W (address 0x94) A, #05h ACC, $
ACCESS TO ENERGY MEASUREMENT SFRs
Access to the energy measurement SFRs is achieved by reading or writing to the SFR addresses detailed in Table 28. The internal data for the MIRQx SFRs are latched byte by byte into the SFR when the SFR is read. The WAV1x, WAV2x, VRMSx, and IRMSx registers are all 3-byte SFRs. The 24-bit data is latched into these SFRs when the high byte is read. Reading the low or medium byte before the high byte results in reading the data from the previous latched sample. Sample 8051 code to read the Vrms register is shown below. MOV MOV MOV R1, VRMSH R2, VRMSM R3, VRMSL //latches data in VrmsH, VrmsM and VrmsL SFR
;Next Write or read to Energy Measurement SFR can be done after this.
Reading the Internal Energy Measurement Registers
When Bit 7 of Energy Measurement Pointer Address SFR (MADDPT, 0x91) is cleared, the content of the internal energy measurement register designated by the address in MADDPT is transferred to the MDATx SFRs. If the internal register is 1 byte long, only the MDATL SFR content is updated with a new value, while the MDATM SFR and MDATH SFR contents are reset to 0x00. The energy measurement core functions with an internal clock of 4.096 MHz ∕ 5 or 819.2 kHz. Because the 8052 core functions with another clock, 4.096MHz ∕ 2CD, synchronization between the two clock environments when CD = 0 or 1 is an issue. When data is read from the internal energy measurement, a small wait period needs to be implemented before the MDATx SFRs are transferred to another SFR. Sample 8051 code to read the peak voltage in the 2-byte VPKLVL register located at 0x16 into the data pointer is shown below. MOV MOV DJNZ MOV MOV MADDPT,#VPKLVL_R (address 0x16) A, #05h ACC, $ DPH, MDATM DPL, MDATL
ACCESS TO INTERNAL ENERGY MEASUREMENT REGISTERS
Access to the internal energy measurement registers is achieved by writing to the Energy Measurement Pointer Address SFR (MADDPT, 0x91). This SRF selects the energy measurement register to be accessed and determines if a read or a write is performed (see Table 27). Table 27. Energy Measurement Pointer Address SFR (MADDPT, 0x91)
Bit Number 7 6 to 1 Description 1 = write, 0 = read Energy measurement internal register address
Rev. PrA | Page 34 of 136
Preliminary Technical Data
Table 28. Energy Measurement SFRs
Address 0x91 0x92 0x93 0x94 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 R/W R/W R/W R/W R/W R R R R R R R/W R/W R/W R/W R/W R/W R R R R R R Name MADDPT MDATL MDATM MDATH VRMSL VRMSM VRMSH IRMSL IRMSM IRMSH MIRQENL MIRQENM MIRQENH MIRQSTL MIRQSTM MIRQSTH WAV1L WAV1M WAV1H WAV2L WAV2M WAV2H Description Energy Measurement Pointer Address. Energy Measurement Pointer Data LSByte. Energy Measurement Pointer Data Middle Byte. Energy Measurement Pointer Data MSByte. Vrms Measurement LSByte. Vrms Measurement Middle Byte. Vrms Measurement MSByte. Irms Measurement LSByte. Irms Measurement Middle Byte. Irms Measurement MSByte. Energy Measurement Interrupt Enable LSByte. Energy Measurement Interrupt Enable Middle Byte. Energy Measurement Interrupt Enable MSByte. Energy Measurement Interrupt Status LSByte. Energy Measurement Interrupt Status Middle Byte. Energy Measurement Interrupt Status MSByte. Selection 1 Sample LSByte. Selection 1 Sample Middle Byte. Selection 1 Sample MSByte. Selection 2 Sample LSByte. Selection 2 Sample Middle Byte. Selection 2 Sample MSByte.
ADE7566/ADE7569
IAP I IN
×1, ×2, ×4, ×8, ×16 {GAIN[2:0]} PGA1
INTEGRATOR MULTIPLIER ADC dt HPF π 2 LPF2
WGAIN[11:0]
CF1NUM[15:0] WATTOS[15:0] VARGAIN[11:0] DFC LPF2 CF1DEN[15:0] IRMSOS[11:0]
×2
PHCAL[7:0] Ф
CF1
VAROS[15:0] VAGAIN[11:0]
CF2NUM[15:0]
LPF VRMSOS[11:0] VARDIV[7:0]
DFC
CF2
VP VN
PGA2
ADC
HPF
×2
CF2DEN[15:0] LPF VADIV[7:0] % % % WDIV[7:0]
06353-092
METERING SFRs
Figure 29. Energy Metering Block Diagram
Rev. PrA | Page 35 of 136
ADE7566/ADE7569
ENERGY MEASUREMENT REGISTERS
Table 29. Energy Measurement Register List
Address MADDPT[6:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 Mnemonic Reserved WATTHR RWATTHR LWATTHR VARHR 1 RVARHR1 LVARHR1 VAHR RVAHR LVAHR PER_FREQ MODE1 MODE2 WAVMODE NLMODE ACCMODE PHCAL ZXTOUT LINCYC SAGCYC SAGLVL IPKLVL VPKLVL IPEAK RSTIPEAK VPEAK RSTVPEAK GAIN Reserved WGAIN VARGAIN1 VAGAIN WATTOS VAROS1 IRMSOS VRMSOS WDIV VARDIV VADIV R/W – R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W – R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Length (Bits) – 24 24 24 24 24 24 24 24 24 16 8 8 8 8 8 8 12 16 8 16 16 16 24 24 24 24 8 – 12 12 12 16 16 12 12 8 8 8 U U U U U U U U U U – S S S S S S S U U U Signed/ Unsigned – S S S S S S S S S U U U U U U S Default – 0 0 0 0 0 0 0 0 0 0 0x06 0x40 0 0 0 0x40 0x0FFF 0xFFFF 0xFF 0 0xFFFF 0xFFFF 0 0 0 0 0 – 0 0 0 0 0 0 0 0 0 0
Preliminary Technical Data
Description – Reads Wh accumulator without reset. Reads Wh accumulator with reset. Reads Wh accumulator synchronous to line cycle. Reads VARh accumulator without reset. Reads VARh accumulator with reset. Reads VARh accumulator synchronous to line cycle. Reads VAh accumulator without reset. Reads VAh accumulator with reset. Reads VAh accumulator synchronous to line cycle. Reads line period or frequency register depending on Mode2 register. Sets basic configuration of energy measurement (see Table 30). Sets basic configuration of energy measurement (see Table 31). Sets configuration of Waveform Sample 1 and Waveform Sample 2 (see Table 32). Sets level of energy no-load thresholds (see Table 33). Sets configuration of W, VAR accumulation and various tamper alarms (see Table 34). Sets phase calibration register (see the Phase Compensation section). Sets timeout for zero-crossing timeout detection (see the Zero-Crossing Timeout section). Sets number of half-line cycles for LWATTHR, LVARHR, and LVAHR accumulators. Sets number of half-line cycles for SAG detection (see the Line Voltage Sag Detection section). Sets detection level for SAG detection (see the Line Voltage Sag Detection section). Sets peak detection level for current peak detection (see the Peak Detection section). Sets peak detection level for voltage peak detection (see the Peak Detection section). Reads current peak level without reset (see the Peak Detection section). Reads current peak level with reset (see the Peak Detection section). Reads voltage peak level without reset (see the Peak Detection section). Reads voltage peak level with reset (see the Peak Detection section. Sets PGA gain of analog inputs (see Table 35). Reserved. Sets watt gain register. Sets VAR gain register. Sets VA gain register. Sets watt offset register. Sets VAR offset register. Sets current rms offset register. Sets voltage rms offset register. Sets watt energy scaling register. Sets VAR energy scaling register. Sets VA energy scaling register.
Rev. PrA | Page 36 of 136
Preliminary Technical Data
Address MADDPT[6:0] 0x27 0x28 0x29 0x2A
1
ADE7566/ADE7569
Signed/ Unsigned U U U U Default 0 0x003F 0 0x003F Description Sets CF1 numerator register. Sets CF1 denominator register. Sets CF2 numerator register. Sets CF2 denominator register.
Mnemonic CF1NUM CF1DEN CF2NUM CF2DEN
R/W R/W R/W R/W R/W
Length (Bits) 16 16 16 16
This function is not available in the ADE7566 part.
ENERGY MEASUREMENT INTERNAL REGISTERS DETAILS
Table 30. MODE1 Register (0x0B)
Bit No. 7 6 5 4 3 2 1 0 Mnemonic SWRST DISZXLPF INTE SWAPBITS PWRDN DISCF2 DISCF1 DISHPF Default 0 0 0 0 0 1 1 0 Description Setting this bit resets all of the energy measurement registers to their default values. Setting this bit disables the zero-crossing low-pass filter. Setting this bit enables the digital integrator for use with a di/dt sensor. Setting this bit swaps CH1 ADC and CH2 ADC. Setting this bit powers down voltage and current ADCs. Setting this bit disables Frequency Output CF2. Setting this bit disables Frequency Output CF1. Setting this bit disables the HPFs in voltage and current channels.
Table 31. MODE2 Register (0x0C)
Bit No. 7 to 6 Mnemonic CF2SEL[1:0] Default 01 Description Configuration Bits for CF2 Output. CF2SEL[1:0] 00 01 1x 5 to 4 CF1SEL[1:0] 00 CF1SEL[1:0] 00 01 1x 3 VARMSCFCON 0 Result CF2 frequency is proportional to active power. CF2 frequency is proportional to reactive power. 1 CF2 frequency is proportional to apparent power or Irms. Result CF1 frequency is proportional to active power. CF1 frequency is proportional to reactive power.1 CF1 frequency is proportional to apparent power or Irms.
Configuration Bits for CF1 Output.
Configuration Bits for Apparent Power or Irms for CF1 and CF2 Outputs. Note that CF1 cannot be proportional to VA if CF2 is proportional to Irms, and vice versa. VARMSCFCON Result 0 1 If CF1SEL[1:0] = 1x, CF1 is proportional to VA. If CF2SEL[1:0] = 1x, CF2 is proportional to VA. If CF1SEL[1:0] = 1x, CF1 is proportional to Irms. If CF2SEL[1:0] = 1x, CF2 is proportional to Irms.
2 1
ZXRMS FREQSEL
0
Logic 1 enables update of RMS values synchronously to voltage ZX. Configuration Bits to Select Period or Frequency Measurement for PER_FREQ Register (0x0A). FREQSEL 0 1 Result PER_FREQ register holds a period measurement. PER_FREQ register holds a frequency measurement.
0
1
Reserved
1
This bit should be kept to 1.
This function is not available in the ADE7566 part.
Rev. PrA | Page 37 of 136
ADE7566/ADE7569
Table 32. WAVMODE Register (0x0D)
Bit No. 7 to 5 Mnemonic WAV2SEL[2:0] Default 000
Preliminary Technical Data
Description Waveform 2 Selection for Samples Mode. WAV2SEL[2:0] Source 000 Current 001 Voltage 010 Active power multiplier output 011 Reactive power multiplier output 1 100 VA multiplier output 101 Irms LPF output Others Reserved Waveform 1 Selection for Samples Mode. WAV1SEL[2:0] Source 000 Current 001 Voltage 010 Active power multiplier output 011 Reactive power multiplier output1 100 VA multiplier output 101 Irms LPF output (low 24-bit) Others Reserved Waveform Samples Output Data Rate. DTRT[1:0] Update Rate (Clock = fCORE/5 = 819.2 kHz) 00 25.6 kSPS (clock/32) 01 12.8 kSPS (clock/64) 10 6.4 kSPS (clock/128) 11 3.2 kSPS (clock/256)
4 to 2
WAV1SEL[2:0]
000
1 to 0
DTRT[1:0]
00
1
This function is not available in the ADE7566 part.
Table 33. NLMODE Register (0x0E)
Bit No. 7 6 5 to 4 Mnemonic DISVARCMP 1 IRMSNOLOAD VANOLOAD[1:0] Default 0 0 00 Description Setting this bit disables fundamental VAR gain compensation over line frequency. Logic 1 enables Irms no-load threshold detection. The level is defined by the setting of the VANOLOAD bits. Apparent Power No-Load Threshold. VANOLOAD[1:0] Result 00 No-load detection disabled 01 No-load enabled with threshold = 0.030% of full scale 10 No-load enabled with threshold = 0.015% of full scale 11 No-load enabled with threshold = 0.0075% of full scale Reactive Power No-Load Threshold VARNOLOAD[1:0] Result 00 No-load detection disabled 01 No-load enabled with threshold = 0.015% of full scale 10 No-load enabled with threshold = 0.0075% of full scale 11 No-load enabled with threshold = 0.0037% of full scale Active Power No-Load Threshold. APNOLOAD[1:0] Result 00 No-load detection disabled 01 No-load enabled with threshold = 0.015% of full scale 10 No-load enabled with threshold = 0.0075% of full scale 11 No-load enabled with threshold = 0.0037% of full scale
3 to 2
VARNOLOAD[1:0]1
00
1 to 0
APNOLOAD[1:0]
00
1
This function is not available in the ADE7566 part. Rev. PrA | Page 38 of 136
Preliminary Technical Data
Table 34. ACCMODE Register (0x0F)
Bit No. 7 to 6 5 Mnemonic Reserved VARSIGN 1 Default 0 0
ADE7566/ADE7569
4
APSIGN
0
3 2
ABSVARM1 SAVARM1
0 0
1 0
1
POAM ABSAM
0 0
Description Reserved. Configuration bit to select event that triggers a reactive power sign interrupt. If set to 0, VARSIGN interrupt occurs when reactive power changes from positive to negative. If set to 1, VARSIGN interrupt occurs when reactive power changes from negative to positive. Configuration bit to select event that triggers an active power sign interrupt. If set to 0, APSIGN interrupt occurs when active power changes from positive to negative. If set to 1, APSIGN interrupt occurs when active power changes from negative to positive. Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output. Logic 1 enables reactive power accumulation depending on the sign of the active power. If active power is positive, VAR is accumulated as it is. If active power is negative, the sign of the VAR is reversed for the accumulation. This accumulation mode affects both the VAR registers (VARHR, RVARHR, LVARHR) and the pulse output when connected to VAR.1 Logic 1 enables positive only accumulation of active power in energy register and pulse output. Logic 1 enables absolute value accumulation of active power in energy register and pulse output.
This function is not available in the ADE7566 part.
Table 35. GAIN Register (0x1B)
Bit No. 7 to 5 Mnemonic PGA2[2:0] Default 000 Description These bits define the voltage channel input gain. PGA2[2:0] Result 000 Gain = 1 001 Gain = 2 010 Gain = 4 011 Gain = 8 100 Gain = 16 Reserved. This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is implemented. CFSIGN_OPT Result 0 Filtered power signal 1 On a per CF pulse basis These bits define the current channel input gain. PGA1[2:0] Result 000 Gain = 1 001 Gain = 2 010 Gain = 4 011 Gain = 8 100 Gain = 16
4 3
Reserved CFSIGN_OPT
0 0
2 to 0
PGA1[2:0]
000
Table 36. Interrupt Status Register 1 SFR (MIRQSTL, 0xDC)
Bit No. 7 6-5 4 3 2 1 0
1
Interrupt Flag ADEIRQFLAG Reserved VARSIGN 1 APSIGN VANOLOAD RNOLOAD1 APNOLOAD
Description This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt are set. This bit is automatically cleared when all of the enabled ADE status flags are cleared. Reserved. Logic 1 indicates that the reactive power sign has changed according to the configuration of ACCMODE register. Logic 1 indicates that the active power sign has changed according to the configuration of ACCMODE register. Logic 1 indicates that an interrupt has been caused by apparent power no-load detected. This interrupt is also used to reflect the part entering the Irms no load mode. Logic 1 indicates that an interrupt has been caused by reactive power no-load detected. Logic 1 indicates that an interrupt has been caused by active power no-load detected.
This function is not available in the ADE7566 part. Rev. PrA | Page 39 of 136
ADE7566/ADE7569
Table 37. Interrupt Status Register 2 SFR (MIRQSTM, 0xDD)
Bit No. 7 6 5 4 3 2 1 0
1
Preliminary Technical Data
Interrupt Flag CF2 CF1 VAEOF REOF 1 AEOF VAEHF REHF1 AEHF
Description Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if CF2 pulse output is not enabled by clearing Bit 2 of MODE1 register. Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if CF1 pulse output is not enabled by clearing Bit 1 of MODE1 register. Logic 1 indicates that the VAHR register has overflowed. Logic 1 indicates that the VARHR register has overflowed. Logic 1 indicates that the WATTHR register has overflowed. Logic 1 indicates that the VAHR register is half-full. Logic 1 indicates that the VARHR register is half-full. Logic 1 indicates that the WATTHR register is half-full.
This function is not available in the ADE7566 part.
Table 38. Interrupt Status Register 3 SFR (MIRQSTH, 0xDE)
Bit No. 7 6 5 4 3 2 1 0 Interrupt Flag RESET – WFSM PKI PKV CYCEND ZXTO ZX Description Indicates the end of a reset (for both software and hardware reset). Reserved. Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7). Logic 1 indicates that current channel has exceeded the IPKLVL value Logic 1 indicates that voltage channel has exceeded the VPKLVL value. Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles. Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles. Logic 1 indicates detection of a zero crossing in the voltage channel.
Table 39. Interrupt Enable Register 1 SFR (MIRQENL, 0xD9)
Bit No. 7 to 5 4 3 2 1 0
1
Interrupt Enable Bit Reserved VARSIGN 1 APSIGN VANOLOAD RNOLOAD1 APNOLOAD
Description Reserved. When set, the VARSIGN bit set creates a pending ADE interrupt to the 8052 core. When set, the APSIGN bit set creates a pending ADE interrupt to the 8052 core. When set, the VANOLOAD bit set creates a pending ADE interrupt to the 8052 core. When set, the RNOLOAD bit set creates a pending ADE interrupt to the 8052 core. When set, the APNOLOAD bit set creates a pending ADE interrupt to the 8052 core.
This function is not available in the ADE7566 part.
Table 40. Interrupt Enable Register 2 SFR (MIRQENM, 0xDA)
Bit No. 7 6 5 4 3 2 1 0
1
Interrupt Enable Bit CF2 CF1 VAEOF REOF 1 AEOF VAEHF REHF1 AEHF
Description When this bit is set, a CF2 pulse creates a pending ADE interrupt to the 8052 core. When this bit is set, a CF1 pulse creates a pending ADE interrupt to the 8052 core. When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
This function is not available in the ADE7566 part.
Rev. PrA | Page 40 of 136
Preliminary Technical Data
Table 41. Interrupt Enable Register 3 SFR (MIRQENH, 0xDB)
Bit No. 7 to 6 5 4 3 2 1 0 Interrupt Enable Bit – WFSM PKI PKV CYCEND ZXTO ZX
ADE7566/ADE7569
Description Reserved When this bit is set, the WFSM flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the PKI flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the PKV flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core.
GAIN[7:0] 432 0 0 0
ANALOG INPUTS
The ADE7566/ADE7569 has two fully differential voltage input channels. The maximum differential input voltage for input pairs VP/VN and IP/IN is ±0.5 V. In addition, the maximum signal level on analog inputs for VP/VN and IP/IN is ± 0.5 V with respect to AGND. Each analog input channel has a programmable gain amplifier (PGA) with possible gain selections of 1, 2, 4, 8, and 16. The gain selections are made by writing to the GAIN register in the Energy Measurement Register List (see Table 35 and Figure 31). Bit 0 to Bit 2 select the gain for the PGA in the current channel, and Bit 5 to Bit 7 select the gain for the PGA in the voltage channel. Figure 30 shows how a gain selection for the current channel is made using the gain register. In addition to the PGA, Channel 1 also has a full-scale input range selection for the ADC. The gain register also selects the ADC analog input range (see Figure 31). As mentioned previously, the maximum differential input voltage is 0.5 V.
7 0
6 0
5 0
1 0
0 0
GAIN (K) SELECTION VP1
VIN
K × VIN
06353-018
VN1
Figure 30. PGA in Current Channel
GAIN REGISTER* CURRENT AND VOLTAGE CHANNELS PGA CONTROL 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 ADDR: 0x1B
PGA 2 GAIN SELECT 000 = × 1 001 = × 2 010 = × 4 011 = × 8 100 = × 16
PGA 1 GAIN SELECT 000 = × 1 001 = × 2 010 = × 4 011 = × 8 100 = × 16
06353-019
CFSIGN_OPT RESERVED *REGISTER CONTENTS SHOW POWER-ON DEFAULTS.
Figure 31. Analog Gain Register
Rev. PrA | Page 41 of 136
ADE7566/ADE7569
ANALOG-TO-DIGITAL CONVERSION
Each ADE7566/ADE7569 has two Σ-Δ analog-to-digital converters (ADCs). The outputs of these ADCs are mapped directly to waveform sampling SFRs (Address 0xE2 to Address 0xE7) and are used for energy measurement internal digital signal processing. In PSM1 (battery mode) and PSM2 (sleep mode), the ADCs are powered down to minimize power consumption. For simplicity, the block diagram in Figure 33 shows a firstorder Σ-Δ ADC. The converter is made up of the Σ-Δ modulator and the digital low-pass filter. A Σ-∆ modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. In the ADE7566/ADE7569, the sampling clock is equal to MCLK/5. The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC output (and therefore, the bit stream) can approach that of the input signal level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. Only when a large number of samples are averaged is a meaningful result obtained. This averaging is carried into the second part of the ADC, the digital low-pass filter. By averaging a large number of bits from the modulator, the low-pass filter can produce 24-bit datawords that are proportional to the input signal level. The Σ-Δ converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The first is oversampling. Oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE7566/ ADE7569 is MCLK/5 (819.2 kHz), and the band of interest is
Preliminary Technical Data
40 Hz to 2 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered (see Figure 32). However, oversampling alone is not efficient enough to improve the signal-to-noise ratio (SNR) in the band of interest. For example, an oversampling ratio of four is required to increase the SNR by only 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. In the Σ-Δ modulator, the noise is shaped by the integrator, which has a high-pass-type response for the quantization noise. The result is that most of the noise is at the higher frequencies where it can be removed by the digital low-pass filter. This noise shaping is shown in Figure 32.
DIGITAL FILTER ANTI ALIAS FILTER (RC) SHAPED NOISE SAMPLING FREQUENCY
SIGNAL
NOISE
0
2
409.6 FREQUENCY (kHz)
819.2
SIGNAL
HIGH RESOLUTION OUTPUT FROM DIGITAL LPF
NOISE
06353-021
0
2
409.6 FREQUENCY (kHz)
819.2
Figure 32. Noise Reduction Due to Oversampling and Noise Shaping in the Analog Modulator
MCLK/5 ANALOG LOW-PASS FILTER R C + – 24 VREF INTEGRATOR LATCHED COMPARATOR DIGITAL LOW-PASS FILTER
1-BIT DAC
Figure 33. First-Order Σ-∆ ADC
Rev. PrA | Page 42 of 136
06353-020
... 10100101 ...
Preliminary Technical Data
Anti-Aliasing Filter
Figure 33 also shows an analog low-pass filter (RC) on the input to the modulator. This filter is present to prevent aliasing, an artifact of all sampled systems. Aliasing means that frequency components in the input signal to the ADC, which are higher than half the sampling rate of the ADC, appear in the sampled signal at a frequency below half the sampling rate. Figure 34 illustrates the effect. Frequency components (the black arrows) above half the sampling frequency (also know as the Nyquist frequency, that is, 409.6 kHz) are imaged or folded back down below 409.6 kHz. This happens with all ADCs regardless of the architecture. In the example shown, only frequencies near the sampling frequency (819.2 kHz) move into the band of interest for metering (40 Hz to 2 kHz). This allows the use of a very simple LPF (low-pass filter) to attenuate high frequency (near 819.2 kHz) noise and prevents distortion in the band of interest. For conventional current sensors, a simple RC filter (single-pole LPF) with a corner frequency of 10 kHz produces an attenuation of approximately 40 dB at 819.2 kHz (see Figure 34). The 20 dB per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensors. However, for a di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per decade gain. This neutralizes the −20 dB per decade attenuation produced by one simple LPF. Therefore, when using a di/dt sensor, care should be taken to offset the 20 dB per decade gain. One simple approach is to cascade two RC filters to produce the −40 dB per decade attenuation needed.
ALIASING EFFECTS
ADE7566/ADE7569
IMAGE FREQUENCIES
SAMPLING FREQUENCY
0
2
409.6 FREQUENCY (kHz)
819.2
Figure 34. ADC and Signal Processing in Current Channel Outline Dimensions
ADC Transfer Function
Both ADCs in the ADE7566/ADE7569 are designed to produce the same output code for the same input signal level. With a full-scale signal on the input of 0.5 V, and an internal reference of 1.2 V, the ADC output code is nominally 2,684,354 or 0x28F5C2. The maximum code from the ADC is ±4,194,304; this is equivalent to an input signal level of ±0.794 V. However, for specified performance, it is recommended that the full-scale input signal level of 0.5 V not be exceeded.
Current Channel ADC
Figure 35 shows the ADC and signal processing chain for the current channel. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 25.6 kSPS (MCLK/160). With the specified full-scale analog input signal of 0.5 V, the ADC produces an output code that is approximately between 0x28F5C2 (+2,684,354d) and 0xD70A3E (–2,684,354d).
MODE1[5] CURRENT RMS (I rms) CALCULATION WAVEFORM SAMPLE REGISTER ACTIVE AND REACTIVE POWER CALCULATION
×1, ×2, ×4 ×8, ×16 {GAIN[2:0]} IAP I IN PGA1
REFERENCE DIGITAL INTEGRATOR* ADC HPF dt
50Hz V1 0.5V, 0.25V, 0.125V, 62.5mV, 31.3mV 0V CURRENT CHANNEL WAVEORM DATA RANGE 0x28F5C2 ANALOG INPUT RANGE 0x000000 0xD70A3E 0x2B7850 0x000000 0xD487B0 *WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED. 60Hz 0xCBD330 CURRENT CHANNEL WAVEORM DATA RANGE AFTER INTEGRATOR (60Hz) 0x342CD0 0x000000
CURRENT CHANNEL WAVEORM DATA RANGE AFTER INTEGRATOR (50Hz)
Figure 35. ADC and Signal Processing in Current Channel
Rev. PrA | Page 43 of 136
06353-023
06353-022
ADE7566/ADE7569
VP V2 VN 0.5V, 0.25V, 0.125V, 62.5mV, 31.3mV V2 LPF1
×1, ×2, ×4, ×8, ×16 {GAIN[7:5]}
Preliminary Technical Data
REFERENCE
ACTIVE AND REACTIVE POWER CALCULATION
HPF PGA2 ADC
VOLTAGE RMS (V rms) CALCULATION
WAVEFORM SAMPLE REGISTER VOLTAGE PEAK DETECT ZX DETECTION
0V
VOLTAGE CHANNEL WAVEFORM DATA RANGE ANALOG INPUT RANGE 0x28F5 0x0000
f–3dB = 63.7Hz
ZX SIGNAL DATA RANGE FOR 60Hz SIGNAL 0x1DD0 0x0000 0xE230
MODE1[6]
0xD70B
ZX SIGNAL DATA RANGE FOR 50Hz SIGNAL 0x2037 0x0000 0xDFC9
06353-024
*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED.
Figure 36. ADC and Signal Processing in Voltage Channel
Voltage Channel ADC
Figure 36 shows the ADC and signal processing chain for the voltage channel. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 25.6 kSPS (MCLK/160). The ADC produces an output code that is approximately between 0x28F5 (+10,485d) and 0xD70B (−10,485d).
di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR FOR THE ADE7569
A di/dt sensor, a feature available for the AD7569, but not for the AD7566, detects changes in the magnetic field caused by accurrents. Figure 37 shows the principle of a di/dt current sensor.
Channel Sampling
The waveform samples of the current ADC and voltage ADC can also be routed to the waveform registers to be read by the MCU core. The active, reactive, apparent power, and energy calculation remain uninterrupted during waveform sampling. When in waveform sampling mode, one of four output sample rates can be chosen by using Bits DTRT[1:0] of the WAVMODE register (see Table 32). The output sample rate can be 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS. If the WFSM enable bit is set in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB), the 8052 core has a pending ADE interrupt. The sampled signals selected in the WAVMODE register are latched into the Waveform SFRs when the waveform high byte (WAV1H or WAV2H) is read. The ADE interrupt stays active until the WFSM status bit is cleared (see the Energy Measurement Interrupts section).
MAGNETIC FIELD CREATED BY CURRENT (DIRECTLY PROPORTIONAL TO CURRENT)
Figure 37. Principle of a di/dt Current Sensor
The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. The changes in the magnetic flux density passing through a conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal that is proportional to the di/dt of the current. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current-carrying conductor and the di/dt sensor. The current signal needs to be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form.
Rev. PrA | Page 44 of 136
06353-026
+ EMF (ELECTROMOTIVE FORCE) – INDUCED BY CHANGES IN MAGNETIC FLUX DENSITY (di/dt)
Preliminary Technical Data
The ADE7569 has a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on the current channel is switched off by default when the ADE7569 is powered up. Setting INTE bit in the MODE1 Register (0x0B) turns on the integrator. Figure 38 to Figure 41 show the magnitude and phase response of the digital integrator.
10
–1.0 –1.5 –2.0 –2.5
ADE7566/ADE7569
GAIN (dB)
–3.0 –3.5 –4.0 –4.5 –5.0
0
–10
–5.5 45 50 55 60 FREQUENCY (Hz) 65 70
06353-029
06353-030
GAIN (dB)
–20
–6.0 40
–30
Figure 40. Combined Gain Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
–89.70 –89.75 100 FREQUENCY (Hz) 1000
06353-027
–40
–50
–89.80
PHASE (Degrees)
Figure 38. Combined Gain Response of the Digital Integrator and Phase Compensator
–88.0
–89.85 –89.90 –89.95 –90.00 –90.05
–88.5
PHASE (Degrees)
–89.0 40 –89.5 45 50 55 60 FREQUENCY (Hz) 65 70
Figure 41. Combined Phase Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
–90.0
102 FREQ FREQUENCY (Hz)
103
Figure 39. Combined Phase Response of the Digital Integrator and Phase Compensator
06353-093
–90.5
Note that the integrator has a−20 dB/dec attenuation and an approximately −90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. The di/dt sensor has a 20 dB/dec gain associated with it. It also generates significant high frequency noise. Therefore, a more effective anti-aliasing filter is needed to avoid noise due to aliasing (see the Anti-Aliasing Filter section). When the digital integrator is switched off, the ADE7569 can be used directly with a conventional current sensor such as a current transformer (CT) or with a low resistance current shunt.
Rev. PrA | Page 45 of 136
ADE7566/ADE7569
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
Each ADE7566/ADE7569 has a zero-crossing detection circuit on the voltage channel. This zero crossing is used to produce an external zero-crossing signal (ZX) and is used in calibration mode. The zero-crossing is generated by default from the output of LPF1. This filter has a low cut-off frequency and is intended for 50 Hz and 60 Hz systems. If needed, this filter can be disabled to allow a higher frequency signal to be detected or to limit the group delay of the detection. If the voltage input fundamental frequency is below 60 Hz, and a time delay in ZX detection is acceptable, it is recommended to enable LPF1. Enabling LPF1 limits the variability in the ZX detection by eliminating the high frequency components. Figure 42 shows how the zero-crossing signal is generated.
×1, ×2, ×4, ×8, ×16 VP V2 VN ZERO CROSS LPF1 f–3dB = 63.7Hz
ZX
Preliminary Technical Data
this register is 0xFFF. If the internal register decrements to 0 before a zero crossing is detected in the Interrupt Status Register 3 SFR (MIRQSTH, 0xDE), and the ZXTO bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the ZXTO status bit is cleared (see the Energy Measurement Interrupts section). The ZXOUT register (Address 0x11) can be written or read by the user (see the Energy Measurement Register List section). The resolution of the register is 160/MCLK sec per LSB. Thus, the maximum delay for an interrupt is 0.16 sec (128/MCLK × 212) when MCLK = 4.096 MHz. Figure 43 shows the mechanism of the zero-crossing timeout detection when the line voltage stays at a fixed dc level for more than CLKIN/160 × ZXTOUT sec.
12-BIT INTERNAL REGISTER VALUE ZXTOUT
REFERENCE HPF ADC 2
{GAIN [7:5]} PGA2
VOLTAGE CHANNEL
MODE1[6] 1.0 0.73 43.24° @ 60Hz ZX
06353-032
ZXTO FLAG BIT
Figure 43. Zero-Crossing Timeout Detection
Period or Frequency Measurements
V2 LPF1
Figure 42. Zero-Crossing Detection on Voltage Channel
The zero-crossing signal ZX is generated from the output of LPF1 (bypassed or not). LPF1 has a single pole at 63.7 Hz (at MCLK = 4.096 MHz). As a result, there is a phase lag between the analog input signal V2 and the output of LPF1. The phase lag response of LPF1 results in a time delay of approximately 2 ms (@ 60 Hz) between the zero crossing on the analog inputs of the voltage channel and ZX detection. The zero-crossing detection also drives the ZX flag in the Interrupt Status Register 3 SFR (MIRQSTH, 0xDE). If the ZX bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the ZX status bit is cleared (see the Energy Measurement Interrupts section).
The ADE7566/ADE7569 provide the period or frequency measurement of the line. The period or frequency measurement is selected by clearing or setting FREQSEL bit in the MODE2 Register (0x0C). The period/frequency register, PER_FREQ Register (0x0A), is an unsigned 16-bit register that is updated every period. If LPF1 is enabled, a settling time of 1.8 sec is associated with this filter before the measurement is stable. When the period measurement is selected, the measurement has a 2.44 μs/LSB (MCLK/10) when MCLK = 4.096 MHz, which represents 0.014% when the line frequency is 60 Hz. When the line frequency is 60 Hz, the value of the period register is approximately 0d6827. The length of the register enables the measurement of line frequencies as low as 12.5 Hz. The period register is stable at ±1 LSB when the line is established and the measurement does not change. When the frequency measurement is selected, the measurement has a 0.0625 Hz/LSB resolution when MCLK = 4.096 MHz, which represents 0.104% when the line frequency is 60 Hz. When the line frequency is 60 Hz, the value of the frequency register is 0d960. The frequency register is stable at ±4 LSB when the line is established and the measurement does not change.
Zero-Crossing Timeout
The zero-crossing detection also has an associated timeout register, ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB) every 160/MCLK sec. The register is reset to its user programmed, full-scale value every time a zero crossing is detected on the voltage channel. The default power-on value in
Rev. PrA | Page 46 of 136
06353-031
Preliminary Technical Data
Line Voltage Sag Detection
In addition to the detection of the loss of the line voltage signal (zero crossing), the ADE7566/ADE7569 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value for a number of line cycles. This condition is illustrated in Figure 44.
VOLTAGE CHANNEL FULL SCALE SAGLVL [15:0]
ADE7566/ADE7569
V2
VPKLVL[15:0]
PKV INTERRUPT FLAG READ RSTSTATUS REGISTER
SAG RESET LOW WHEN VOLTAGE CHANNEL EXCEEDS SAGLVL [15:0] AND SAG FLAG RESET
06353-033
PKV RESET LOW WHEN RSTSTATUS REGISTER IS READ
Figure 45. Peak Level Detection
SAG FLAG
SAGCYC [7:0] = 0x04 3 LINE CYCLES
Figure 44. SAG Detection
Figure 44 shows the line voltage falling below a threshold that is set in the SAG level register (SAGLVL[15:0]) for three line cycles. The quantities 0 and 1 are not valid for the SAGCYC register, and the contents represent one more than the desired number of full line cycles. For example, when the SAG cycle (SAGCYC[7:0]) contains 0x04, FSAG in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is set at the end of the third line cycle after the line voltage falls below the threshold. If the SAG enable bit (ESAG) in the Power Management Interrupt Enable SFR (IPSME, 0xEC) is set, the 8052 core has a pending power supply monitoring interrupt. The PSM interrupt stays active until the ESAG bit is cleared (see the Power Supply Monitor Interrupt (PSM) section). In Figure 44, the SAG flag (FSAG) is set on the fifth line cycle after the signal on the voltage channel first dropped below the threshold level.
Figure 45 shows a line voltage exceeding a threshold that is set in the voltage peak register (VPKLVL[15:0]). The voltage peak event is recorded by setting the PKV flag in the Interrupt Status Register 3 SFR (MIRQSTH, 0xDE). If the PKV enable bit is set in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB), the 8052 core has a pending ADE interrupt. Similarly, the current peak event is recorded by setting the PKI flag in Interrupt Status Register 3 SFR (MIRQSTH, 0xDE). The ADE interrupt stays active until the PKV or PKI status bit is cleared (see the Energy Measurement Interrupts section).
Peak Level Set
The contents of the VPKLVL and IPKLVL registers are compared to the absolute value of the voltage and current channels 2 MSBs, respectively. Thus, for example, the nominal maximum code from the Current Channel ADC with a full-scale signal is 0x28F5C2 (see the Current Channel ADC section). Therefore, writing 0x28F5 to the IPKLVL register puts the current channel, peak detection level at full scale and sets the current peak detection to its least sensitive value. Writing 0x00 puts the current channel detection level at 0. The detection is done by comparing the contents of the IPKLVL register to the incoming current channel sample. The PKI flag indicates that the peak level is exceeded. If the PKI or PKV bit is set in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB), the 8052 core has a pending ADE interrupt.
Sag Level Set
The 2-byte contents of the SAG level register (SAGLVL, 0x14) are compared to the absolute value of the output from LPF1. Therefore, when LPF1 is enabled, writing 0x2038 to the SAG level register puts the SAG detection level at full scale (see Figure 36). Writing 0x00 or 0x01 puts the SAG detection level at 0. The SAG level register is compared to the input of the ZX detection, and detection is made when the contents of the SAG level register are greater.
Peak Level Record
Each ADE7566/ADE7569 records the maximum absolute value reached by the voltage and current channels in two different registers, IPEAK and VPEAK, respectively. Each register is a 24bit unsigned register that is updated each time the absolute value of the waveform sample from the corresponding channel is above the value stored in the VPEAK or IPEAK register. The contents of the VPEAK register correspond to the maximum absolute value observed on the voltage channel input. The contents of IPEAK and VPEAK represent the maximum absolute value observed on the current and voltage input, respectively. Reading the RSTVPEAK and RSTIPEAK registers clears their respective contents after the read operation.
Peak Detection
The ADE7566/ADE7569 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value. Figure 45 illustrates the behavior of the peak detection for the voltage channel. Both voltage and current channels are monitored at the same time.
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ADE7566/ADE7569
PHASE COMPENSATION
The ADE7566/ADE7569 must work with transducers that can have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7566/ADE7569 provide a means of digitally calibrating these small phase errors. The part allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors. Because the compensation is in time, this technique should only be used for small phase errors in the range of 0.1° to 0.5°. Correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics. The phase calibration register (PHCAL[7:0]) is a twos complement, signed, single-byte register that has values ranging from 0x82 (−126d) to 0x68 (104d). The PHCAL register is centered at 0x40, meaning that writing 0x40 to the register gives 0 delay. By changing this register, the time delay in the voltage channel signal path can change from −231.93 μs to +48.83 μs (MCLK = 4.096 MHz). One LSB is equivalent to 1.22 μs (MCLK/5) time delay or advance. A line frequency of 60 Hz gives a phase resolution of 0.026° at the fundamental (that is, 360° × 1.22 μs × 60 Hz). Figure 46 illustrates how the phase compensation is used to remove a 0.1° phase lead in current channel due to the external transducer. To cancel the lead (0.1°) in current channel, a phase lead must also be introduced into voltage channel. The resolution of the phase adjustment allows the introduction of a phase lead in increments of 0.026°. The phase lead is achieved by introducing a time advance into voltage channel. A time advance of 4.88 μs is made by writing −4 (0x3C) to the time delay block, thus reducing the amount of time delay by 4.88 μs, or equivalently, a phase lead of approximately 0.1° at a line frequency of 60 Hz (0x3C represents −4 because the register is centered with 0 at 0x40).
IAP I IN PGA1 ADC 1 24 LPF2 HPF 24
Preliminary Technical Data
RMS CALCULATION
The root mean square (rms) value of a continuous signal V(t) is defined as
Vrms =
1 × V 2 (t ) dt T
T
∫
0
(3)
For time sampling signals, rms calculation involves squaring the signal, taking the average, and obtaining the square root. The ADE7566/ADE7569 implement this method by serially squaring the input, averaging them, and then taking the root square of the average. The averaging part of this signal processing is done by implementing a low-pass filter (LPF3 in Figure 47, Figure 48 Figure 49). This LPF has a −3dB cut-off frequency of 2 Hz when MCLK = 4.096 MHz.
V (t ) = 2 × V sin(ωt ) where V is the rms voltage.
(4)
V 2 (t ) = V 2 − V 2 cos(2ωt )
(5)
When this signal goes through LPF3, the cos(2ωt) term is attenuated and only the DC term Vrms2 goes through (see Figure 47).
V 2 (t ) = V 2 – V 2 cos (2ωt ) V (t ) = √2 × V sin(ωt ) LPF3 INPUT V
V 2 (t ) = V 2
Figure 47. RMS Signal Processing
The rms signals can be read from the waveform register by setting the WAVMODE Register (0x0D) and setting the WFSM bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB). Like the current and voltage channels waveform sampling modes, the waveform date is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS. It is important to note that when the current input is larger than 40% of full scale, the Irms waveform sample register does not represent the true processed rms value. The rms value processed with this level of input is larger than the 24-bit read by the waveform register, making the value read truncated on the high end.
VP V VN V 0.1° I PGA2 ADC 2
1
DELAY BLOCK 1.22µs/LSB 7 0
CHANNEL 2 DELAY REDUCED BY 4.48µs (0.1°LEAD AT 60Hz) 0x0B IN PHCAL[7:0] V I
1 0010111 PHCAL[7:0] –231.93µs TO +48.83µs
60Hz
Figure 46. Phase Calibration
Rev. PrA | Page 48 of 136
06353-035
60Hz
06353-036
Preliminary Technical Data
Current Channel RMS Calculation
Each ADE7566/ADE7569 simultaneously calculates the rms values for the current and voltage channels in different registers. Figure 48 shows the detail of the signal processing chain for the rms calculation on the current channel. The current channel rms value is processed from the samples used in the current channel waveform sampling mode and is stored in an unsigned 24-bit register (Irms) . One LSB of the current channel rms register is equivalent to one LSB of a current channel waveform sample. The update rate of the current channel rms measurement is MCLK/5. To minimize noise in the reading of the register, the Irms register can also be configured to update only with the zero crossing of the voltage input. This configuration is done by setting the ZXRMS bit in the MODE2 Register (0x0C). With the specified full-scale analog input signal of 0.5 V, the ADC produces an output code that is approximately ±0d2,684,354 (see the Current Channel ADC section). The equivalent rms value of a full-scale ac signal is 0d1,898,124 (0x1CF68C). The current rms measurement provided in the ADE7566/ADE7569 is accurate to within 0.5% for signal inputs
60Hz
ADE7566/ADE7569
between full scale and full scale/1000. The conversion from the register value to amps must be done externally in the microprocessor using an amps/LSB constant.
Current Channel RMS Offset Compensation
The ADE7566/ADE7569 incorporate a current channel rms offset compensation register (IRMSOS). This is a 12-bit signed register that can be used to remove offset in the current channel rms calculation. An offset can exist in the rms calculation due to input noises that are integrated in the dc component of V2(t). The offset calibration allows the content of the Irms register to be maintained at 0 when no input is present on current channel. One LSB of the current channel rms offset is equivalent to 16,384 LSBs of the square of the current channel rms register. Assuming that the maximum value from the current channel rms calculation is 0d1,898,124 with full-scale ac inputs, then 1 LSB of the current channel rms offset represents 0.23% of measurement error at −60 dB down of full scale.
I rms = I rms 0 2 + IRMSOS × 32768
(6)
where Irms0 is the rms measurement without offset correction.
CURRENT CHANNEL WAVEFORM DATA RANGE WITH INTEGRATOR ON (60Hz)
0x2B7850 0x000000 0xD487B0
MODE1[5] IA HPF sgn 225 DIGITAL INTEGRATOR* dt HPF1 LPF3
IRMSOS[11:0] 226 227 218 217 216
Irms(t)
0x00
24
+
24
Irms[23:0]
IB
HPF
CURRENT CHANNEL WAVEFORM DATA RANGE WITH INTEGRATOR OFF 0x28F5C2 0x000000 0xD70A3E
06353-037
Figure 48. Current Channel RMS Signal Processing
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ADE7566/ADE7569
VOLTAGE SIGNAL (V(t)) 0x28F5 0x0 0xD70B LPF1 VOLTAGE CHANNEL LPF3 + VRMOS[11:0] sgn 216 215
Preliminary Technical Data
28 27 26 +
Vrms[23:0] 0x28F5C2
06353-038
0x00
Figure 49. Voltage Channel RMS Signal Processing
Voltage Channel RMS Calculation
Figure 49 shows details of the signal processing chain for the rms calculation on the voltage channel. The voltage channel rms value is processed from the samples used in the voltage channel waveform sampling mode and is stored in the unsigned 24-bit Vrms register. The update rate of the voltage channel rms measurement is MCLK/5. To minimize noise in the reading of the register, the Vrms register can also be configured to update only with the zero crossing of the voltage input. This configuration is done by setting ZXRMS bit in the MODE2 Register (0x0C). With the specified full-scale ac analog input signal of 0.5 V, the output from the LPF1 in Figure 49 swings between 0x28F5 and 0xD70B at 60 Hz (see the Voltage Channel ADC section). The equivalent rms value of this full-scale ac signal is approximately 0d1,898,124 (0x1CF68C) in the Vrms register. The voltage rms measurement provided in the ADE7566/ADE7569 is accurate to within ±0.5% for signal input between full scale and full scale/20. The conversion from the register value to volts must be done externally in the microprocessor using a V/LSB constant.
The unit of power is the watt or joules/sec. Equation 10 gives an expression for the instantaneous power signal in an ac system.
v (t ) = 2 × V sin(ωt ) i (t ) = 2 × I sin(ωt )
(8) (9)
where: v is the rms voltage. i is the rms current.
p (t ) = v (t ) × i (t )
p(t ) = VI − VI cos(2ωt )
(10)
The average power over an integral number of line cycles (n) is given by the expression in Equation 11.
P= where:
1 nT
∫0
nT
p(t )dt = VI
(11)
T is the line cycle period. P is referred to as the active or real power. Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 11, that is, VI. This is the relationship used to calculate active power in the ADE7566/ADE7569. The instantaneous power signal p(t) is generated by multiplying the current and voltage signals. The dc component of the instantaneous power signal is then extracted by LPF2 (low-pass filter) to obtain the active power information. This process is illustrated in Figure 50.
INSTANTANEOUS POWER SIGNAL 0x19999A ACTIVE REAL POWER SIGNAL = v × i p(t) = v × i – v × i × cos(2ωt)
Voltage Channel RMS Offset Compensation
The ADE7566/ADE7569 incorporate a voltage channel rms offset compensation register (VRMSOS). This is a 12-bit signed register that can be used to remove offset in the voltage channel rms calculation. An offset can exist in the rms calculation due to input noises and dc offset in the input samples. The offset calibration allows the contents of the Vrms register to be maintained at 0 when no voltage is applied. One LSB of the voltage channel rms offset is equivalent to 64 LSBs of the rms register. Assuming that the maximum value from the voltage channel rms calculation is 0d1,898,124 with full-scale ac inputs, then 1 LSB of the voltage channel rms offset represents 3.37% of measurement error at −60 dB down of full scale. Vrms = Vrms0 + 64 × VRMSOS where Vrms0 is the rms measurement without offset correction. (7)
VI 0xCCCCD
ACTIVE POWER CALCULATION
Active power is defined as the rate of energy flow from source to load. It is the product of the voltage and current waveforms. The resulting waveform is called the instantaneous power signal and is equal to the rate of energy flow at every instant of time.
0x00000 CURRENT i(t) = √2 × i × sin(ωt) VOLTAGE v(t) = √2 × v × sin(ωt)
06353-039
Figure 50. Active Power Calculation
Rev. PrA | Page 50 of 136
Preliminary Technical Data
Because LPF2 does not have an ideal brick wall, frequency response (see Figure 51), the active power signal has some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because of its sinusoidal nature, the ripple is removed when the active power signal is integrated to calculate energy (see the Active Energy Calculation section).
0
ADE7566/ADE7569
active power register to be maintained at 0 when no power is being consumed. The 256 LSBs (WATTOS = 0x0100) written to the active power offset register are equivalent to 1 LSB in the waveform sample register. Assuming the average value, output from LPF2 is 0xCCCCD (838,861d) when inputs on the voltage and current channels are both at full scale. At −60 dB down on the current channel (1/1000 of the current channel full-scale input), the average word value output from LPF2 is 838.861 (838,861/1,000). One LSB in the LPF2 output has a measurement error of 1/838.861 × 100% = 0.119% of the average value. The active power offset register has a resolution equal to 1/256 LSB of the waveform register. Therefore, the power offset correction resolution is 0.000464%/LSB (0.119%/256) at −60 dB.
–4
–8
(dB)
–12
–16
Active Power Sign Detection
The ADE7566/ADE7569 detect a change of sign in the active power. The APSIGN flag in the Interrupt Status Register 1 SFR (MIRQSTL, 0xDC) records when a change of sign has occurred according to Bit APSIGN in the ACCMODE Register (0x0F). If APSIGN flag is set in the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the APSIGN status bit is cleared (see the Energy Measurement Interrupts section). When APSIGN in the ACCMODE Register (0x0F) is cleared (default), the APSIGN flag in the Interrupt Status Register 1 SFR (MIRQSTL, 0xDC) is set when a transition from positive– to-negative active power has occurred. When APSIGN in the ACCMODE Register (0x0F) is set, the APSIGN flag in the Interrupt Status Register 1 SFR (MIRQSTL, 0xDC) is set when a transition from negative-to-positive active power has occurred.
–20
1
3
10 FREQUENCY (Hz)
30
100
Figure 51. Frequency Response of LPF2
Active Power Gain Calibration
Figure 52 shows the signal processing chain for the active power calculation in the ADE7566/ADE7569. As explained previously, the active power is calculated by filtering the output of the multiplier with a low-pass filter. Note that when reading the waveform samples from the output of LPF2, the gain of the active energy can be adjusted by using the multiplier and watt gain register (WGAIN[11:0]). The gain is adjusted by writing a twos complement 12-bit word to the watt gain register. Equation 12 shows how the gain adjustment is related to the contents of the watt gain register.
06353-040
–24
Active Power No-Load Detection
The ADE7566/ADE7569 include a no-load threshold feature on the active energy that eliminates any creep effects in the meter. The part accomplishes this by not accumulating energy if the multiplier output is below the no-load threshold. When the active power is below the no-load threshold, the APNOLOAD flag in the Interrupt Status Register 1 SFR (MIRQSTL, 0xDC) is set. If the APNOLOAD bit is set in the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the APNOLOAD status bit is cleared (see the Energy Measurement Interrupts section). The no-load threshold level is selectable by setting the APNOLOAD bits in the NLMODE Register (0x0E). Setting these bits to 0b00 disable the no-load detection and setting them to 0b01, 0b10, or 0b11 set the no-load detection threshold to 0.015%, 0.0075%, or 0.0037% of the multiplier’s full-scale output frequency, respectively. The IEC 62053-21 specification states that the meter must start up with a load equal to or less than 0.4% IB, which translates to .0167% of the full-scale output frequency of the multiplier.
⎛ ⎧ WGAIN ⎫ ⎞ Output WGAIN = ⎜ Active Power × ⎨1 + ⎬⎟ ⎜ ⎟ 212 ⎭ ⎠ ⎩ ⎝
(12)
For example, when 0x7FF is written to the watt gain register, the power output is scaled up by 50% (0x7FF = 2047d, 2047/212 = 0.5). Similarly, 0x800 = −2048d (signed, twos complement) and power output is scaled by –50%. Each LSB scales the power output by 0.0244%. The minimum output range is given when the watt gain register contents are equal to 0x800 and the maximum range is given by writing 0x7FF to the watt gain register. This can be used to calibrate the active power (or energy) calculation in the ADE7566/ADE7569.
Active Power Offset Calibration
The ADE7566/ADE7569 also incorporate an active power offset register (WATTOS[15:0]). It is a signed, twos complement, 16-bit register that can be used to remove offsets in the active power calculation (see Figure 50). An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration allows the contents of the
Rev. PrA | Page 51 of 136
ADE7566/ADE7569
FOR WAVEFORM SAMPLING 23
Preliminary Technical Data
WATTHR[23:0] UPPER 24 BITS ARE ACCESSIBLE THROUGH WATTHR[23:0] REGISTER 0
WATTOS[15:0] sgn 26 25 CURRENT CHANNEL
LPF2 2–6 2–7 2–8 WDIV[7:0] + + VOLTAGE CHANNEL ACTIVE POWER SIGNAL WGAIN[11:0] OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INTEGRATED) IN THE INTERNAL ACTIVE ENERGY REGISTER 48 0
+
+
%
TO DIGITAL-TO-FREQUENCY CONVERTER WAVEFORM REGISTER VALUES
T
OUTPUT LPF2
5 CLKIN
TIME (nT)
Figure 52. Active Energy Calculation
ACTIVE ENERGY CALCULATION
As stated in the Active Power Calculation section, power is defined as the rate of energy flow. This relationship can be expressed mathematically in Equation 13.
P= dE dt
The active power signal in the waveform register is continuously added to the internal active energy register. The active energy accumulation depends on the setting of the POAM and ABSAM bits in the ACCMODE Register (0x0F). When both bits are cleared, the addition is signed and, therefore, negative energy is subtracted from the active energy contents. When both bits are set, the ADE7566/ADE7569 are set to be in the more restrictive mode, the positive only accumulation mode. When POAM in the ACCMODE Register (0x0F) is set, only positive power contributes to the active energy accumulation. When ABSAM in the ACCMODE Register (0x0F) is set, the absolute active power is used for the active energy accumulation (see the Watt Absolute Accumulation Mode section). The output of the multiplier is divided by the value in the WDIV register. If the value in the WDIV register is equal to 0, the internal active energy register is divided by 1. WDIV is an 8-bit unsigned register. After dividing by WDIV, the active energy is accumulated in a 49-bit internal energy accumulation register. The upper 24 bits of this register are accessible through a read to the active energy register (WATTHR[23:0]). A read to the RWATTHR register returns the content of the WATTHR register, and the upper 24 bits of the internal register are cleared. As shown in Figure 52, the active power signal is accumulated in an internal 49-bit signed register. The active power signal can be read from the waveform register by setting the WAVMODE Register (0x0D) and setting the WFSM bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB). Like the current and voltage channels waveform sampling modes, the waveform date is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS.
(13)
where: P is power. E is energy. Conversely, energy is given as the integral of power.
E = ∫ P (t )dt
(14)
The ADE7566/ADE7569 achieve the integration of the active power signal by continuously accumulating the active power signal in an internal, non readable, 49-bit energy register. The active energy register (WATTHR[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 15 expresses the relationship.
⎧∞ ⎫ E = ∫ p(t )dt = Lim⎨∑ p(nT ) × T ⎬ t →0 ⎩n =1 ⎭ where: n is the discrete time sample number. T is the sample period.
(15)
The discrete time sample period (T) for the accumulation register in the ADE7566/ADE7569 is 1.22 μs (5/MCLK). In addition to calculating the energy, this integration removes any sinusoidal components that may be in the active power signal. Figure 52 shows this discrete time integration or accumulation.
Rev. PrA | Page 52 of 136
06353-041
Preliminary Technical Data
Figure 53 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three displayed curves illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are 0x7FF, 0x000, and 0x800. The watt gain register is used to carry out power calibration in the ADE7566/ADE7569. As shown, the fastest integration time occurs when the watt gain register is set to maximum full scale, that is, 0x7FF.
WATTHR[23:0] 0x7F,FFFF
ADE7566/ADE7569
Time =
0 xFFFF, FFFF, FFFF × 1.22 μs = 409.6 sec = 6.82 min 0 xCCCCD (16)
When WDIV is set to a value different than 0, the integration time varies, as shown in Equation 17. Time = TimeWDIV = 0 × WDIV (17)
Active Energy Accumulation Modes Watt Signed Accumulation Mode
The ADE7566/ADE7569 active energy default accumulation mode is a watt-signed accumulation based on the active power information.
WGAIN = 0x7FF WGAIN = 0x000 WGAIN = 0x800
0x3F,FFFF
Watt Positive-Only Accumulation Mode
0x00,0000 3.41 6.82 10.2 13.7 TIME (Minutes)
0x40,0000
0x80,0000
Figure 53. Energy Register Rollover Time for Full-Scale Power (Minimum and Maximum Power Gain)
The ADE7566/ADE7569 are placed in watt positive-only accumulation mode by setting the POAM bit in the ACCMODE Register (0x0F). In this mode, the energy accumulation is only done for positive power, ignoring any occurrence of negative power above or below the no-load threshold (see Figure 54). The CF pulse also reflects this accumulation method when in this mode. The default setting for this mode is off. Detection of the transitions in the direction of power flow and detection of no-load threshold are active in this mode.
Note that the energy register contents roll over to full-scale negative (0x800000) and continue to increase in value when the power or energy flow is positive (see Figure 53). Conversely, if the power is negative, the energy register underflows to fullscale positive (0x7FFFFF) and continues to decrease in value. By using the interrupt enable register, the ADE7566/ADE7569 can be configured to issue an ADE interrupt to the 8052 core when the active energy register is half-full (positive or negative) or when an overflow or underflow occurs.
ACTIVE ENERGY
06353-042
NO-LOAD THRESHOLD ACTIVE POWER NO-LOAD THRESHOLD
Integration Time under Steady Load
As mentioned in the Active Energy Calculation section, the discrete time sample period (T) for the accumulation register is 1.22 μs (5/CLKIN). With full-scale sinusoidal signals on the analog inputs and the WGAIN register set to 0x000, the average word value from each LPF2 is 0xCCCCD (see Figure 50). The maximum positive value that can be stored in the internal 49-bit register is 248 (or 0xFFFF,FFFF,FFFF) before it overflows. The integration time under these conditions when WDIV = 0 is calculated in the following equation:
APSIGN FLAG POS NEG POS INTERRUPT STATUS REGISTERS
06353-043
Figure 54. Energy Accumulation in Positive-Only Accumulation Mode
Rev. PrA | Page 53 of 136
ADE7566/ADE7569
Watt Absolute Accumulation Mode
The ADE7566/ADE7569 are placed in watt absolute accumulation mode by setting the ABSAM bit in the ACCMODE Register (0x0F). In this mode, the energy accumulation is done using the absolute active power, ignoring any occurrence of power below the no-load threshold (see Figure 55). The CF pulse also reflects this accumulation method when in this mode. The default setting for this mode is off. Detection of the transitions in the direction of power flow, and detection of no-load threshold are active in this mode.
Preliminary Technical Data
behavior is consistent with the setting of the active energy accumulation mode in the ACCMODE Register (0x0F). The pulse output is active low and should be preferably connected to an LED as shown in Figure 66.
Line Cycle Active Energy Accumulation Mode
In line cycle active energy accumulation mode, the energy accumulation of the ADE7566/ADE7569 can be synchronized to the voltage channel zero crossing so that active energy can be accumulated over an integral number of half-line cycles. The advantage of summing the active energy over an integer number of line cycles is that the sinusoidal component in the active energy is reduced to 0. This eliminates any ripple in the energy calculation. Energy is calculated more accurately and more quickly because the integration period can be shortened. By using this mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. In the line cycle active energy accumulation mode, the ADE7566/ADE7569 accumulate the active power signal in the LWATTHR register for an integral number of line cycles, as shown in Figure 56. The number of half-line cycles is specified in the LINCYC register. The ADE7566/ADE7569 can accumulate active power for up to 65,535 half-line cycles. Because the active power is integrated on an integral number of line cycles, the CYCEND flag in the Interrupt Status Register 3 SFR (MIRQSTH, 0xDE) is set at the end of an active energy accumulation line cycle. If the CYCEND enable bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the CYCEND status bit is cleared (see the Energy Measurement Interrupts section). Another calibration cycle starts as soon as the CYCEND flag is set. If the LWATTHR register is not read before a new CYCEND flag is set, the LWATTHR register is overwritten by a new value.
ACTIVE ENERGY
NO-LOAD THRESHOLD ACTIVE POWER NO-LOAD THRESHOLD
APSIGN FLAG APNOLOAD POS NEG POS APNOLOAD INTERRUPT STATUS REGISTERS
06353-044
Figure 55. Energy Accumulation in Absolute Accumulation Mode
Active Energy Pulse Output
All of the ADE7566/ADE7569 circuitry has a pulse output whose frequency is proportional to active power (see the Active Power Calculation section). This pulse frequency output uses the calibrated signal from the WGAIN register output, and its
TO DIGITAL-TO-FREQUENCY CONVERTER
WGAIN[11:0] OUTPUT FROM LPF2 WATTOS[15:0] + +
48
0
%
WDIV[7:0] ACCUMULATE ACTIVE ENERGY IN INTERNAL REGISTER AND UPDATE THE LWATTHR REGISTER AT THE END OF LINCYC HALF LINE CYCLES
LPF1 FROM VOLTAGE CHANNEL ADC
23 ZERO-CROSSING DETECTION CALIBRATION CONTROL
LWATTHR [23:0]
0
LINCYC [15:0]
Figure 56. Line Cycle Active Energy Accumulation
Rev. PrA | Page 54 of 136
06353-046
Preliminary Technical Data
When a new half-line cycle is written in the LINCYC register, the LWATTHR register is reset, and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until LINCYC is reached . This implementation provides a valid measurement at the first CYCEND interrupt after writing to the LINCYC register (see Figure 57). The line active energy accumulation uses the same signal path as the active energy accumulation. The LSB size of these two registers is equivalent.
ADE7566/ADE7569
v(t ) = 2 V sin(ωt + θ ) i(t ) = 2 I sin(ωt ) π i ′(t ) = 2 I sin⎛ ωt + ⎞ ⎜ ⎟ 2⎠ ⎝ where: θ is the phase difference between the voltage and current channel. v is the rms voltage. i is the rms current. q(t) = v(t) × i’(t) q(t) = VI sin (θ) + VI sin (2ωt + θ) (23) (22) (21)
LWATTHR REGISTER
CYCEND IRQ
06353-045
The average reactive power over an integral number of lines (n) is given in Equation 24. Q= where: T is the line cycle period. q is referred to as the reactive power. 1 nT
nT 0
LINCYC VALUE
Figure 57. Energy Accumulation when LINCYC Changes
∫ q(t )dt = VI sin(θ)
(24)
From the information in Equation 10 and Equation 11,
⎧ ⎫ ⎪ ⎪ nT ⎪ ⎪nT VI E (t ) = ∫ VIdt − ⎨ cos(2πft )dt 2 ⎬∫ 0 ⎪ ⎛ f ⎞ ⎪0 ⎟⎪ ⎪ 1+ ⎜ ⎝ 8.9 ⎠ ⎭ ⎩ where: n is an integer. T is the line cycle period.
(18)
Note that the reactive power is equal to the dc component of the instantaneous reactive power signal q(t) in Equation 23. The instantaneous reactive power signal q(t) is generated by multiplying the voltage and current channels. In this case, the phase of the current channel is shifted by +90°. The dc component of the instantaneous reactive power signal is then extracted by a low-pass filter to obtain the reactive power information (see Figure 58). In addition, the phase-shifting filter has a non-unity magnitude response. Because the phase-shifted filter has a large attenuation at high frequency, the reactive power is primarily for calculation at line frequency. The effect of harmonics is largely ignored in the reactive power calculation. Note that because of the magnitude characteristic of the phase shifting filter, the weight of the reactive power is slightly different from the active power calculation (see the Energy Register Scaling section). The frequency response of the LPF in the reactive signal path is identical to the one used for LPF2 in the average active power calculation. Because LPF2 does not have an ideal brick wall frequency response (see Figure 51), the reactive power signal has some ripple due to the instantaneous reactive power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the reactive power signal is integrated to calculate energy. The reactive power signal can be read from the waveform register by setting the WAVMODE Register (0x0D) and the WFSM bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB). Like the current and voltage channels waveform sampling modes, the waveform date is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS.
Because the sinusoidal component is integrated over an integer number of line cycles, its value is always 0. Therefore,
E = ∫ VIdt + 0
0
nT
(19) (20)
E(t) = VInT
Note that in this mode, the 16-bit LINCYC register can hold a maximum value of 65,535. In other words, the line energy accumulation mode can be used to accumulate active energy for a maximum duration of over 65,535 half-line cycles. At a 60 Hz line frequency, it translates to a total duration of 65,535/120 Hz = 546 sec.
REACTIVE POWER CALCULATION FOR THE ADE7569
Reactive power, a function available for the AD7569, but not for the AD7566, is defined as the product of the voltage and current waveforms when one of these signals is phase-shifted by 90°. The resulting waveform is called the instantaneous reactive power signal. Equation 23 gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by 90°.
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ADE7566/ADE7569
Reactive Power Gain Calibration
Figure 58 shows the signal processing chain for the ADE7569 reactive power calculation. As explained in the Reactive Power Calculation for the ADE7569 section, the reactive power is calculated by applying a low-pass filter to the instantaneous reactive power signal. Note that when reading the waveform samples from the output of LPF2, the gain of the reactive energy can be adjusted by using the multiplier and by writing a twos complement, 12-bit word to the VAR gain register (VARGAIN[11:0]). Equation 25 shows how the gain adjustment is related to the contents of the watt gain register. Output VARGAIN =
Preliminary Technical Data
The ADE interrupt stays active until the VARSIGN status bit is cleared (see the Energy Measurement Interrupts section). When VARSIGN in the ACCMODE Register (0x0F) is cleared (default), the VARSIGN flag in the Interrupt Status Register 1 SFR (MIRQSTL, 0xDC) is set when a transition from positive to negative reactive power has occurred. When VARSIGN in the ACCMODE Register (0x0F) is set, the VARSIGN flag in the Interrupt Status Register 1 SFR (MIRQSTL, 0xDC) is set when a transition from negative to positive reactive power has occurred.
Reactive Power No-Load Detection
The ADE7569 includes a no-load threshold feature on the reactive energy that eliminates any creep effects in the meter. The ADE7569 accomplishes this by not accumulating reactive energy if the multiplier output is below the no-load threshold. When the reactive power is below the no-load threshold, the RNOLOAD flag in the Interrupt Status Register 1 SFR (MIRQSTL, 0xDC) is set. If the RNOLOAD bit is set in the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the RNOLOAD status bit is cleared (see the Energy Measurement Interrupts section). The no-load threshold level is selectable by setting the VARNOLOAD bits in the NLMODE Register (0x0E). Setting these bits to 0b00 disable the no-load detection, and setting them to 0b01, 0b10, or 0b11 set the no-load detection threshold to 0.015%, 0.0075%, and 0.0037% of the full-scale output frequency of the multiplier, respectively.
⎛ ⎧ VARGAIN ⎫ ⎞ ⎜ Reactive Power × ⎨1 + ⎬⎟ 212 ⎩ ⎭⎠ ⎝
The resolution of the VARGAIN register is the same as the WGAIN register (see the Active Power Gain Calibration section). VARGAIN can be used to calibrate the reactive power (or energy) calculation in the ADE7569.
(25)
Reactive Power Offset Calibration
The ADE7569 also incorporates a reactive power offset register (VAROS[15:0]). This is a signed, twos complement, 16-bit register that can be used to remove offsets in the reactive power calculation (see Figure 58). An offset can exist in the reactive power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration allows the contents of the reactive power register to be maintained at 0 when no power is being consumed. The 256 LSBs (VAROS = 0x100) written to the reactive power offset register are equivalent to 1 LSB in the WAVMODE register.
Sign of Reactive Power Calculation
Note that the average reactive power is a signed calculation. The phase shift filter has −90° phase shift when the integrator is enabled, and +90° phase shift when the integrator is disabled. Table 42 summarizes the relationship of the phase difference between the voltage and the current and the sign of the resulting VAR calculation.
Table 42. Sign of Reactive Power Calculation
Angle Between 0° to 90° Between –90° to 0° Between 0° to 90° Between –90° to 0° Integrator Off Off On On Sign Positive Negative Positive Negative
REACTIVE ENERGY CALCULATION FOR THE ADE7569
As for active energy, the ADE7569 achieves the integration of the reactive power signal by continuously accumulating the reactive power signal in an internal, nonreadable, 49-bit energy register. The reactive energy register (VARHR[23:0]) represents the upper 24 bits of this internal register. The VARHR register and its function is available for the AD7569, but not for the AD7566. The discrete time sample period (T) for the accumulation register in the ADE7569 is 1.22 μs (5/MCLK). As well as calculating the energy, this integration removes any sinusoidal components that may be in the active power signal. Figure 58 shows this discrete time integration or accumulation. The reactive power signal in the waveform register is continuously added to the internal reactive energy register. The reactive energy accumulation depends on the setting of the SAVARM and ABSVARM bits in the ACCMODE Register (0x0F). When both bits are cleared, the addition is signed and, therefore, negative energy is subtracted from the reactive energy contents. When both bits are set, the ADE7569 is set to be in the more restrictive mode, the absolute accumulation mode.
Reactive Power Sign Detection
The ADE7569 detects a change of sign in the reactive power. The VARSIGN flag in the Interrupt Status Register 1 SFR (MIRQSTL, 0xDC) records when a change of sign has occurred according to VARSIGN bit in the ACCMODE Register (0x0F). If the VARSIGN bit is set in the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt.
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Preliminary Technical Data
When SAVARM in the ACCMODE Register (0x0F) is set, the reactive power is accumulated depending on the sign of the active power. When active power is positive, the reactive power is added as it is to the reactive energy register. When active power is negative, the reactive power is subtracted from the reactive energy accumulator (see the VAR Anti-Tamper Accumulation Mode section). When ABSVARM in the ACCMODE Register (0x0F) is set, the absolute reactive power is used for the reactive energy accumulation (see the VAR Absolute Accumulation Mode section). The output of the multiplier is divided by VARDIV. If the value in the VARDIV register is equal to 0, the internal reactive energy register is divided by 1. VARDIV is an 8-bit, unsigned register. After dividing by VARDIV, the reactive energy is accumulated in a 49-bit internal energy accumulation register. The upper 24 bits of this register are accessible through a read to the reactive energy register (VARHR[23:0]). A read to the RVARHR register returns the content of the VARHR register, and the upper 24 bits of the internal register are cleared. As shown in Figure 58, the reactive power signal is accumulated in an internal 49-bit signed register. The reactive power signal
FOR WAVEFORM SAMPLING 90° PHASE SHIFTING FILTER VAROS[15:0] sgn 26 25 LPF2 + VOLTAGE CHANNEL + % 2–6 2–7 2–8 VARDIV[7:0] + + PHCAL[7:0] REACTIVE POWER SIGNAL TO DIGITAL-TO-FREQUENCY CONVERTER T 5 CLKIN WAVEFORM REGISTER VALUES
VARGAIN[11:0]
ADE7566/ADE7569
can be read from the waveform register by setting the WAVMODE Register (0x0D) and setting the WFSM bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB). Like the current and voltage channel waveform sampling modes, the waveform date is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS. Figure 53 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. These curves also apply for the reactive energy accumulation Note that the energy register contents rolls over to full-scale negative (0x800000) and continues to increase in value when the power or energy flow is positive. Conversely, if the power is negative, the energy register underflows to full-scale positive (0x7FFFFF) and continues to decrease in value. By using the interrupt enable register, the ADE7569 can be configured to issue an ADE interrupt to the 8052 core when the reactive energy register is half-full (positive or negative) or when an overflow or underflow occurs.
23
VARHR[23:0]
UPPER 24 BITS ARE ACCESSIBLE THROUGH VARHR[23:0] REGISTER 0
CURRENT CHANNEL
HPF
Π
2
48
0
OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INTEGRATED) IN THE INTERNAL REACTIVE ENERGY REGISTER
OUTPUT LPF2
TIME (nT)
Figure 58.. Reactive Energy Calculation
Rev. PrA | Page 57 of 136
06353-047
ADE7566/ADE7569
Integration Time Under Steady Load
As mentioned in the Active Energy Calculation, the discrete time sample period (T) for the accumulation register is 1.22 μs (5/CLKIN). With full-scale sinusoidal signals on the analog inputs and the VARGAIN and VARDIV registers set to 0x000, the integration time before the reactive energy register overflows is calculated in Equation 26. Time = 0xFFFF, FFFF, FFFF × 1.22 μs = 409.6 sec = 6.82 min (26) 0xCCCCD When VARDIV is set to a value different from 0, the integration time varies, as shown in Equation 27. Time = TimeWDIV =0 × VARDIV (27)
Preliminary Technical Data
REACTIVE ENERGY
NO-LOAD THRESHOLD
REACTIVE POWER NO-LOAD THRESHOLD
Reactive Energy Accumulation Modes VAR Signed Accumulation Mode
The ADE7569 reactive energy default accumulation mode is a signed accumulation based on the reactive power information.
NO-LOAD THRESHOLD
ACTIVE POWER NO-LOAD THRESHOLD
VAR Anti-Tamper Accumulation Mode
The ADE7569 is placed in VAR anti-tamper accumulation mode by setting the SAVARM bit in the ACCMODE Register (0x0F). In this mode, the reactive power is accumulated depending on the sign of the active power. When active power is positive, the reactive power is added as it is to the reactive energy register. When active power is negative, the reactive power is subtracted from the reactive energy accumulator (see Figure 59). The CF pulse also reflects this accumulation method when in this mode. The default setting for this mode is off. Transitions in the direction of power flow and no-load threshold are active in this mode.
APSIGN FLAG POS NEG POS INTERRUPT STATUS REGISTERS
06353-048
Figure 59. Reactive Energy Accumulation in Anti-Tamper Accumulation Mode
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Preliminary Technical Data
VAR Absolute Accumulation Mode
The ADE7569 is placed in absolute accumulation mode by setting the ABSVARM bit in the ACCMODE Register (0x0F). In absolute accumulation mode, the reactive energy accumulation is done by using the absolute reactive power and ignoring any occurrence of power below the no-load threshold for the active energy (see Figure 55). The CF pulse also reflects this accumulation method when in the absolute accumulation mode. The default setting for this mode is off. Transitions in the direction of power flow and no-load threshold are active in this mode.
ADE7566/ADE7569
Line Cycle Reactive Energy Accumulation Mode
In line cycle reactive energy accumulation mode, the energy accumulation of the ADE7569 can be synchronized to the voltage channel zero crossing so that reactive energy can be accumulated over an integral number of half-line cycles. The advantage of this mode is similar to the ones described in the Line Cycle Active Energy Accumulation Mode section. In line cycle active energy accumulation mode, the ADE7569 accumulates the reactive power signal in the LVARHR register for an integral number of line cycles, as shown in Figure 61. The number of half-line cycles is specified in the LINCYC register. The ADE7569 can accumulate active power for up to 65,535 half-line cycles. Because the reactive power is integrated on an integral number of line cycles, the CYCEND flag in the Interrupt Status Register 3 SFR (MIRQSTH, 0xDE) is set at the end of an active energy accumulation line cycle. If the CYCEND enable bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the CYCEND status bit is cleared (see the Energy Measurement Interrupts section). Another calibration cycle starts as soon as the CYCEND flag is set. If the LVARHR register is not read before a new CYCEND flag is set, the LVARHR register is overwritten by a new value. When a new half-line cycle is written in the LWATTHR register, the LVARHR register is reset, and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until LINCYC is reached. This implementation provides a valid measurement at the first CYCEND interrupt after writing to the LINCYC register. The line reactive energy accumulation uses the same signal path as the reactive energy accumulation. The LSB size of these two registers is equivalent.
REACTIVE ENERGY
NO-LOAD THRESHOLD REACTIVE POWER NO-LOAD THRESHOLD
06353-049
Figure 60. Reactive Energy Accumulation in Absolute Accumulation Mode
Reactive Energy Pulse Output
The ADE7569 provides all the circuitry with a pulse output whose frequency is proportional to reactive power (see the Energy-to-Frequency Conversion section). This pulse frequency output uses the calibrated signal after VARGAIN, and its behavior is consistent with the setting of the reactive energy accumulation mode in the ACCMODE Register (0x0F). The pulse output is active low and should preferably be connected to an LED as shown in Figure 66.
TO DIGITAL-TO-FREQUENCY CONVERTER
VARGAIN[11:0] OUTPUT FROM LPF2 VAROS[15:0]
%
+
+
48
0
VARDIV[7:0] ACCUMULATE REACTIVE ENERGY IN INTERNAL REGISTER AND UPDATE THE LVARHR REGISTER AT THE END OF LINCYC HALF LINE CYCLES
LPF1 FROM VOLTAGE CHANNEL ADC
23 ZERO-CROSSING DETECTION
CALIBRATION CONTROL LVARHR [23:0]
0
LINCYC [15:0]
Figure 61. Line Cycle Reactive Energy Accumulation Mode
Rev. PrA | Page 59 of 136
06353-050
ADE7566/ADE7569
APPARENT POWER CALCULATION
Apparent power is defined as the maximum power that can be delivered to a load. Vrms and Irms are the effective voltage and current delivered to the load, respectively. Therefore, the apparent power (AP) = Vrms × Irms. This equation is independent from the phase angle between the current and the voltage. Equation 31 gives an expression of the instantaneous power signal in an ac system with a phase shift.
v(t ) = 2 Vrms sin(ω t )
Preliminary Technical Data
The gain of the apparent energy can be adjusted by using the multiplier and by writing a twos complement, 12-bit word to the VAGAIN register (VAGAIN[11:0]). Equation 32 shows how the gain adjustment is related to the contents of the VAGAIN register. Output VAGAIN =
⎛ ⎧ VAGAIN ⎫ ⎞ ⎜ Apparent Power × ⎨1 + ⎬⎟ 2 12 ⎩ ⎭⎠ ⎝
(32)
(28) (29) (30) (31)
i (t ) = 2 I rms sin(ωt + θ)
p (t ) = v (t ) × i (t )
p(t ) = Vrms I rms cos(θ) − Vrms I rms cos(2ωt + θ)
For example, when 0x7FF is written to the VAGAIN register, the power output is scaled up by 50% (0x7FF = 2047d, 2047/212 = 0.5). Similarly, 0x800 = –2047d (signed twos complement) and power output is scaled by –50%. Each LSB represents 0.0244% of the power output. The apparent power is calculated with the current and voltage rms values obtained in the rms blocks of the ADE7566/ADE7569.
Figure 62 illustrates the signal processing for the calculation of the apparent power in the ADE7566/ADE7569. The apparent power signal can be read from the waveform register by setting the WAVMODE Register (0x0D) and setting the WFSM bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB). Like the current and voltage channel waveform sampling modes, the waveform data is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value (see the Current Channel RMS Calculation section and Voltage Channel RMS Calculation section). The voltage and current channels rms values are then multiplied together in the apparent power signal processing. Because no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. The offset compensation of the apparent power measurement is done by calibrating each individual rms measurement.
VARMSCFCON APPARENT POWER SIGNAL (P)
Irms
CURRENT RMS SIGNAL – i(t) 0x1CF68C 0x00
0x1A36E2
VAGAIN Vrms
VOLTAGE RMS SIGNAL – v(t)
0x1CF68C 0x00
TO DIGITAL-TO-FREQUENCY CONVERTER
06353-051
Figure 62. Apparent Power Signal Processing
Rev. PrA | Page 60 of 136
Preliminary Technical Data
APPARENT ENERGY CALCULATION
The apparent energy is given as the integral of the apparent power. Apparent Energy = ∫ Apparent Power(t )dt (33)
ADE7566/ADE7569
provided to read the apparent energy. This register is reset to 0 after a read operation Note that the apparent energy register is unsigned. By setting the VAEHF and VAEOF bits in the Interrupt Enable Register 2 SFR (MIRQENM, 0xDA), the ADE7566/ADE7569 can be configured to issue an ADE interrupt to the 8052 core when the apparent energy register is half-full or when an overflow occurs. The half-full interrupt for the unsigned apparent energy register is based on 24 bits as opposed to 23 bits for the signed active energy register.
The ADE7566/ADE7569 achieve the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 48-bit register. The apparent energy register (VAHR[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 34 expresses the relationship.
⎧∞ ⎫ Apparent Energy = Lim⎨ ∑ ApparentPower (nT ) × T ⎬ (34) T →0 ⎩n = 0 ⎭
Integration Times Under Steady Load
As mentioned in the Apparent Energy Calculation section, the discrete time sample period (T) for the accumulation register is 1.22 μs (5/MCLK). With full-scale sinusoidal signals on the analog inputs and the VAGAIN register set to 0x000, the average word value from the apparent power stage is 0x1A36E2 (see the Apparent Power Calculation section). The maximum value that can be stored in the apparent energy register before it overflows is 224 or 0xFF,FFFF. The average word value is added to the internal register, which can store 248 or 0xFFFF,FFFF,FFFF before it overflows. Therefore, the integration time under these conditions with VADIV = 0 is calculated as follows: Time = 0xFFFF, FFFF, FFFF × 1.22 μs = 199 sec = 3.33 min 0xD055
where: n is the discrete time sample number. T is the sample period. The discrete time sample period (T) for the accumulation register in the ADE7566/ADE7569 is 1.22 μs (5/MCLK). Figure 63 shows this discrete time integration or accumulation. The apparent power signal is continuously added to the internal register. This addition is a signed addition even if the apparent energy theoretically remains positive. The 49 bits of the internal register are divided by VADIV. If the value in the VADIV register is 0, the internal apparent energy register is divided by 1. VADIV is an 8-bit unsigned register. The upper 24 bits are then written in the 24-bit apparent energy register (VAHR[23:0]). The RVAHR register (24 bits long) is
(35)
When VADIV is set to a value different from 0, the integration time varies, as shown in Equation 36. Time = TimeWDIV = 0 × VADIV (36)
23
VAHR[23:0]
0
48
0
VADIV
%
APPARENT POWER or Irms
+ +
48
0
APPARENT POWER SIGNAL = P T
APPARENT POWER OR Irms IS ACCUMULATED (INTEGRATED) IN THE APPARENT ENERGY REGISTER
TIME (nT)
Figure 63. Apparent Energy Calculation
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06353-052
ADE7566/ADE7569
Apparent Energy Pulse Output
All the ADE7566/ADE7569 circuitry has a pulse output whose frequency is proportional to apparent power (see the Energy-toFrequency Conversion section). This pulse frequency output uses the calibrated signal after VAGAIN. This output can also be used to output a pulse whose frequency is proportional to Irms. The pulse output is active low and should preferably be connected to an LED as shown in Figure 66.
Preliminary Technical Data
the apparent energy accumulation. The LSB size of these two registers is equivalent.
Apparent Power No-Load Detection
The ADE7566/ADE7569 include a no-load threshold feature on the apparent power that eliminates any creep effects in the meter. The ADE7566/ADE7569 accomplish this by not accumulating energy if the multiplier output is below the no-load threshold. When the apparent power is below the no-load threshold, the VANOLOAD flag in the Interrupt Status Register 1 SFR (MIRQSTL, 0xDC) is set. If the VANOLOAD bit is set in the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the APNOLOAD status bit is cleared (see the Energy Measurement Interrupts section). The no-load threshold level is selectable by setting the VANOLOAD bits in the NLMODE Register (0x0E). Setting these bits to 0b00 disables the no-load detection and setting them to 0b01, 0b10, or 0b11 set the no-load detection threshold to 0.030%, 0.015%, and 0.0075% of the full-scale output frequency of the multiplier, respectively. This no-load threshold can also be applied to the Irms pulse output when selected. In this case, the level of no-load threshold is the same as for the apparent energy.
Line Apparent Energy Accumulation
The ADE7566/ADE7569 are designed with a special apparent energy accumulation mode that simplifies the calibration process. By using the on-chip, zero-crossing detection, the ADE7566/ADE7569 accumulate the apparent power signal in the LVAHR register for an integral number of half cycles, as shown in Figure 64. The line apparent energy accumulation mode is always active. The number of half-line cycles is specified in the LINCYC register, which is an unsigned 16-bit register. The ADE7566/ ADE7569 can accumulate apparent power for up to 65,535 combined half cycles. Because the apparent power is integrated on the same integral number of line cycles as the line active register and reactive energy register, these values can easily be compared. The energies are calculated more accurately because of this precise timing control and provide all the information needed for reactive power and power factor calculation. At the end of an energy calibration cycle, the CYCEND flag in the Interrupt Status Register 3 SFR (MIRQSTH, 0xDE) is set. If the CYCEND enable bit in the Interrupt Enable Register 3 SFR (MIRQENH, 0xDB) is enabled, the 8052 core has a pending ADE interrupt. As for LWATTHR, when a new half-line cycles is written in LINCYC register, the LVAHR register is reset and a new accumulation start at the next zero-crossing. The number of half-line cycles is then counted until LINCYC is reached. This implementation provides a valid measurement at the first CYCEND interrupt after writing to the LINCYC register. The line apparent energy accumulation uses the same signal path as
AMPERE-HOUR ACCUMULATION
In case of a tampering situation where no voltage is available to the energy meter, the ADE7566/ADE7569 is capable of accumulating the ampere-hour instead of apparent power into the VAHR, RVAHR, and LVAHR registers. When Bit 3 (VARMSCFCON) of the MODE2 Register (0x0C) is set, the VAHR, RVAHR, LVAHR, and the input for the digital-to-frequency converter accumulate Irms instead of apparent power. All the signal processing and calibration registers available for apparent power and energy accumulation remain the same when ampere-hour accumulation is selected. However, the scaling of Irms and apparent power require different values for gain calibration in the VAGAIN, VADIV, CFxNUM and CFxDEN registers.
APPARENT POWER or Irms
%
+
+
48
0
VADIV[7:0]
LVAHR REGISTER IS UPDATED EVERY LINCYC ZERO CROSSING WITH THE TOTAL APPARENT ENERGY DURING THAT DURATION 23 0 LVAHR [23:0]
LPF1 FROM VOLTAGE CHANNEL ADC
ZERO-CROSSING DETECTION
CALIBRATION CONTROL
LINCYC [15:0]
Figure 64. Line Cycle Apparent Energy Accumulation
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06353-053
Preliminary Technical Data
ENERGY-TO-FREQUENCY CONVERSION
The ADE7566/ADE7569 also provide two energy-to-frequency conversions for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer often verify the energy meter calibration. One convenient way to do this is for the manufacturer to provide an output frequency that is proportional to the active power, reactive power, apparent power, or Irms under steady load conditions. This output frequency can provide a simple, single-wire, optically isolated interface to external calibration equipment. Figure 65 illustrates the energy-tofrequency conversion in the ADE7566/ADE7569.
MODE2 REGISTER 0x0C VARMSCFCON CFxSEL[1:0]
ADE7566/ADE7569
is proportional to Irms, and CF1 cannot be proportional to apparent power apparent power if CF2 is proportional to Irms.
Pulse Output Characteristic
The pulse output for both DFCs stays low for 90 ms if the pulse period is longer than 180 ms (5.56 Hz). If the pulse period is shorter than 180 ms, the duty cycle of the pulse output is 50%. The pulse output is active low and should preferably be connected to an LED as shown on Figure 66.
VDD CF
Irms
VA VAR WATT DFC
Figure 66. CF Pulse Output
CFxNUM
÷
CFxDEN
CFx PULSE OUTPUT
06353-054
The maximum output frequency with ac input signals at full scale and CFxNUM = 0x00 and CFxDEN = 0x00 is approximately 21.1 kHz. The ADE7566/ADE7569 incorporate two registers per DFC, CFxNUM[15:0] and CFxDEN[15:0], to set the CFx frequency. These are unsigned 16-bit registers that can be used to adjust the CFx frequency to a wide range of values. These frequency scaling registers are 16-bit registers that can scale the output frequency by 1/216 to 1 with a step of 1/216. If the value 0 is written to any of these registers, the value 1 would be applied to the register. The ratio CFxNUM/CFxDEN should be less than 1 to ensure proper operation. If the ratio of the registers CFxNUM/CFxDEN is greater than 1, the register values are adjusted to a ratio of 1. For example, if the output frequency is 1.562 kHz while the contents of CFxDEN are 0 (0x000), the output frequency can be set to 6.1 Hz by writing 0xFF to the CFxDEN register.
Figure 65. Energy-to-Frequency Conversion
Two digital-to-frequency converters (DFC) are used to generate the pulsed outputs. When WDIV = 0 or 1, the DFC generates a pulse each time 1 LSB in the energy register is accumulated. An output pulse is generated when CFxNUM/CFxDEN number of pulses are generated at the DFC output. Under steady load conditions, the output frequency is proportional to the active power, reactive power, apparent power or Irms, depending on the CFxSEL bits in the MODE2 Register (0x0C). Both pulse outputs can be enabled or disabled by clearing or setting Bit DISCF1 and Bit DISCF2 in the MODE1 Register (0x0B), respectively. Both pulse outputs set separate flags in the Interrupt Status Register 2 SFR (MIRQSTM, 0xDD), CF1 and CF2. If the CF1 and CF2 enable bits in the Interrupt Enable Register 2 SFR (MIRQENM, 0xDA) are set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the CF1 or CF2 status bits are cleared (see the Energy Measurement Interrupts section).
ENERGY REGISTER SCALING
The ADE7566/ADE7569 provide measurements of active, reactive, and apparent energies that use separate paths and filtering for calculation. The difference in data paths can result in small differences in LSB weight between active, reactive, and apparent energy registers. These measurements are internally compensated so the scaling is nearly one to one. The relationship between these registers is show in Table 43.
Table 43. Energy Registers Scaling
Line Frequency = 50 Hz VAR = 0.9952 × WATT VA = 0.9978 × WATT VAR = 0.9997 × WATT VA = 0.9977 × WATT Line Frequency = 60 Hz VAR = 0.9949 × WATT VA = 1.0015 × WATT VAR = 0.9999 × WATT VA = 1.0015 × WATT Integrator Off Off On On
Pulse Output Configuration
The two pulse output circuits have separate configuration bits in the MODE2 Register (0x0C). Setting the CFxSEL bits to 0b00, 0b01, or 0b1x configure the DFC to create a pulse output proportional to active power, reactive power (not available in the ADE7566), or apparent power/Irms, respectively. The selection between Irms and apparent power is done by the VARMSCFCON bit in the MODE2 Register (0x0C). With this selection, CF2 cannot be proportional to apparent power if CF1
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06353-055
ADE7566/ADE7569
ENERGY MEASUREMENT INTERRUPTS
The energy measurement part of the ADE7566/ADE7569 has its own interrupt vector for the 8052 core, Vector Address 0x004B (see the Interrupt Vectors section). The bits set in the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9), Interrupt Enable Register 2 SFR (MIRQENM, 0xDA), and Interrupt Enable
Preliminary Technical Data
Register 3 SFR (MIRQENH, 0xDB) enable the energy measurement interrupts that are allowed to interrupt the 8052 core. If an event is not enabled, it cannot create a system interrupt. The ADE interrupt stays active until the status bit that has created the interrupt is cleared. The status bit is cleared when a zero is written to this register bit.
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Preliminary Technical Data TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS
The ADE7566/ADE7569 include temperature measurements as well as battery and supply voltage measurements. These measurements enable many forms of compensation. The temperature and supply voltage measurements can be used to compensate external circuitry. The RTC can be calibrated over temperature to ensure that it does not drift. Supply voltage measurements allow the LCD contrast to be maintained despite variations in voltage. Battery measurements allow low battery detection to be performed.
ADE7566/ADE7569
All ADC measurements are configured through the SFRs detailed in Table 44. The temperature, battery, and supply voltage measurements can be configured to continue functioning in PSM1 and PSM2. This is done by setting Bit RTCEN in the RTC Configuration SFR (TIMECON, 0xA1). Keeping the temperature measurement active ensures that it is not necessary to wait for the temperature measurement to settle before using it for compensation.
Table 44. Temperature, Battery, and Supply Voltage Measurement SFRs
SFR Address 0xF9 0xF3 0xD8 0xFA 0xEF 0xDF 0xD7 R/W R/W R/W R/W R/W R/W R/W R/W Name STRBPER DIFFPROG ADCGO BATVTH VDCINADC BATADC TEMPADC Description Strobing Period Configuration (see Table 45). Temperature and Supply Delta Configuration (see Table 46). ADC Start Configuration (see Table 47). Battery Threshold Configuration (see Table 48). VDCIN ADC Value (see Table 49). Battery ADC Value (see Table 50). Temperature ADC Value (see Table 51).
Table 45. Peripheral ADC Strobe Period SFR (STRBPER, 0xF9) 1
Bit No. 7 to 6 5 to 4 Mnemonic Reserved VDCIN_PERIOD[1:0] Default – 0 Description Reserved. Period for background external voltage measurements. VDCIN_PERIOD[1:0] Result 00 No VDCIN measurement 01 8 min 10 2 min 11 1 min Period for background battery level measurements. BATT_PERIOD[1:0] Result 00 No battery measurement 01 16 min 10 4 min 11 1 min Period for background temperature measurements. TEMP_PERIOD[1:0] Result 00 No temperature measurements 01 8 min 10 2 min 11 1 min
3 to 2
BATT_PERIOD[1:0]
0
1 to 0
TEMP_PERIOD[1:0]
0
1
The strobing option only works when the RTCEN bit in RTC Configuration SFR (TIMECON, 0xA1) is set.
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ADE7566/ADE7569
Table 46. Temperature and Supply Delta SFR (DIFFPROG, 0xF3)
Bit No. 7 to 6 5 to 3 Mnemonic Reserved TEMP_DIFF[2:0] Default 0 0
Preliminary Technical Data
Description Reserved. Difference threshold between last temperature measurement interrupting 8052 and new temperature measurement that should interrupt 8052. TEMP_DIFF[2:0] Result 000 No interrupt 001 1 LSB (≈ 0.8°C) 010 2 LSB (≈ 1.6°C) 011 3 LSB (≈ 2.4°C) 100 4 LSB (≈ 3.2°C) 101 5 LSB (≈ 4°C) 110 6 LSB (≈ 4.8°C) 111 Every temperature measurement Difference threshold between last external voltage measurement interrupting 8052 and new external measurement that should interrupt 8052. VDCIN_DIFF[2:0] Result 000 No interrupt 001 1 LSB (≈ 120 mV) 010 2 LSB (≈ 240 mV) 011 3 LSB (≈ 360 mV) 100 4 LSB (≈ 480 mV) 101 5 LSB (≈ 600 mV) 110 6 LSB (≈ 720 mV) 111 Every VDCIN measurement
2 to 0
VDCIN_DIFF[2:0]
0
Table 47. Start ADC Measurement SFR (ADCGO, 0xD8)
Bit No. 7 6 to 3 2 1 0 Address 0xDF 0xDE to 0xDB 0xDA 0xD9 0xD8 Mnemonic PLLACK Reserved VDCIN_ADC_GO TEMP_ADC_GO BATT_ADC_GO Default 0 0 0 0 0 Description Set this bit to clear the PLL fault bit, PLL_FLT, in the PERIPH register. A PLL fault is generated if a reset was caused because the PLL lost lock. Reserved. Set this bit to initiate an external voltage measurement. This bit is cleared when the measurement request is received by the ADC. Set this bit to initiate a temperature measurement. This bit is cleared when the measurement request is received by the ADC. Set this bit to initiate a battery measurement. This bit is cleared when the measurement request is received by the ADC.
Table 48. Battery Detection Threshold SFR (BATVTH, 0xFA)
Bit No. 7 to 0 Mnemonic BATVTH Default 0 Description The battery ADC value is compared to this register, the battery threshold register. If BATADC is lower than the threshold, an interrupt is generated.
Table 49. VDCIN ADC Value SFR (VDCINADC, 0xEF)
Bit No. 7 to 0 Mnemonic VDCINADC Default 0 Description The VDCIN ADC value in this register is updated when an ADC interrupt occurs.
Table 50. Battery ADC Value SFR (BATADC, 0xDF)
Bit No. 7 to 0 Mnemonic BATADC Default 0 Description The battery ADC value in this register is updated when an ADC interrupt occurs.
Table 51. Temperature ADC Value SFR (TEMPADC, 0xD7)
Bit No. 7 to 0 Mnemonic TEMPADC Default 0 Description The temperature ADC value in this register is updated when an ADC interrupt occurs.
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Preliminary Technical Data
TEMPERATURE MEASUREMENT
To provide a digital temperature measurement, each ADE7566/ADE7569 includes a dedicated ADC. An 8-bit Temperature ADC Value SFR (TEMPADC, 0xD7) holds the results of the temperature conversion. The resolution of the temperature measurement is 0.78°C/LSB. There are two ways to initiate a temperature conversion: a single temperature measurement or background temperature measurements.
•
ADE7566/ADE7569
Start ADC Measurement SFR (ADCGO, 0xD8). Background temperature measurements are not available. In PSM2 operating mode, the 8052 is not active. Temperature conversions are available through the background measurement mode only.
The Temperature ADC Value SFR (TEMPADC, 0xD7) is updated with a new value only when a temperature ADC interrupt occurs.
Single Temperature Measurement
Set the TEMP_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to obtain a temperature measurement. An interrupt is generated when the conversion is complete and when the temperature measurement is available in the Temperature ADC Value SFR (TEMPADC, 0xD7).
Temperature ADC Interrupt
The temperature ADC can generate an ADC interrupt when at least one of the following conditions occurs:
•
Background Temperature Measurements
Background temperature measurements are disabled by default. To configure the background temperature measurement mode, set a temperature measurement interval in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9). Temperature measurements are then performed periodically in the background (see Table 45). When a temperature conversion completes, the new temperature ADC value is compared to the last temperature ADC value that created an interrupt. If the absolute difference between the two values is greater than the setting in the TEMP_DIFF[2:0] bits in the Temperature and Supply Delta SFR (DIFFPROG, 0xF3), a TEMPADC interrupt is generated. This allows temperature measurements to take place completely in the background, only requiring MCU activity if the temperature has changed more than a configurable delta. To set up background temperature measurements, follow these steps: 1. Initiate a single temperature measurement by setting the TEMP_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8). Upon completion of this measurement, configure the TEMP_DIFF[2:0] bits to establish the change in temperature that triggers an interrupt. Set up the interval for background temperature measurements by configuring the TEMP_PERIOD[1:0] bits in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9) .
•
The difference between the new temperature ADC value and the last temperature ADC value generating an ADC interrupt is larger than the value set in the TEMP_DIFF[2:0] bits. The temperature ADC conversion, initiated by setting Start ADC Measurement SFR (ADCGO, 0xD8) finishes.
When the ADC interrupt occurs, a new value is available in the Temperature ADC Value SFR (TEMPADC, 0xD7). Note that there is no flag associated with this interrupt.
BATTERY MEASUREMENT
To provide a digital battery measurement, each ADE7566/ADE7569 includes a dedicated ADC. The battery measurement is available in an 8-bit SFR (Battery ADC Value SFR (BATADC, 0xDF)). The battery measurement has a resolution of 15 mV/LSB. A battery conversion can be initiated by two methods: a single battery measurement or background battery measurements.
Single Battery Measurement
Set the BATT_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to obtain a battery measurement. An interrupt is generated when the conversion is done and when the battery measurement is available in the Battery ADC Value SFR (BATADC, 0xDF).
Background Battery Measurements
To configure background measurements for the battery, establish a measurement interval in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9). Battery measurements are then performed periodically in the background (see Table 45). When a battery conversion completes, the battery ADC value is compared to the low battery threshold, established in the Battery Detection Threshold SFR (BATVTH, 0xFA). If the battery ADC value is below this threshold, a low battery flag is set. This low battery flag is the FBAT bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8), which is used for power supply monitoring. This low battery flag can be enabled to generate the PSM interrupt by setting the EBAT bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC). This method allows battery measurements to take place completely in the background, only requiring MCU activity if the battery drops below a user-specified threshold.
2.
3.
Temperature ADC in PSM0, PSM1, and PSM2
Depending on the operating mode of the ADE7566/ADE7569, a temperature conversion is initiated only by certain actions.
•
•
In PSM0 operating mode, the 8052 is active. Temperature measurements are available in the background measurement mode and by initiating a single measurement. In PSM1 operating mode, the 8052 is active and the part is battery powered. Single temperature measurements can be initiated by setting the TEMP_ADC_GO bit in the
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ADE7566/ADE7569
To set up background battery measurements, follow these steps: 1. Configure the Battery Detection Threshold SFR (BATVTH, 0xFA) to establish a low battery threshold. If the BATADC measurement is below this threshold, the FBAT in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is set. Set up the interval for background battery measurements by configuring the BATT_PERIOD[1:0] bits in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9) .
Preliminary Technical Data
EXTERNAL VOLTAGE MEASUREMENT
The ADE7566/ADE7569 include a dedicated ADC to provide a digital measurement of an external voltage on the VDCIN pin. An 8-bit SFR, the VDCIN ADC Value SFR (VDCINADC, 0xEF), holds the results of the conversion. The resolution of the external voltage measurement is TBD V/LSB. There are two ways to initiate an external voltage conversion: a single external voltage measurement or a background external voltage measurement.
2.
Single External Voltage Measurement
To obtain an external voltage measurement, set the VDCIN_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8). An interrupt is generated when the conversion is done and when the external voltage measurement is available in the VDCIN ADC Value SFR (VDCINADC, 0xEF).
Battery ADC in PSM0, PSM1, and PSM2
Depending on the operating mode, a battery conversion is initiated only by certain actions.
•
•
•
In PSM0 operating mode, the 8052 is active. Battery measurements are available in the background measurement mode and by initiating a single measurement. In PSM1 operating mode, the 8052 is active and the part is battery powered. Single battery measurements can be initiated by setting the BATT_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8). Background battery measurements are not available. In PSM2 operating mode, the 8052 is not active. Battery conversions are available through the background measurement mode only.
Background External Voltage Measurements
Background external voltage measurements are disabled by default. To configure the background external voltage measurement mode, set an external voltage measurement interval in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9). External voltage measurements are performed periodically in the background (see Table 45). When an external voltage conversion is complete, the new external voltage ADC value is compared to the last external voltage ADC value that created an interrupt. If the absolute difference between the two values is greater than the setting in the VDCIN_DIFF[2:0] bits in the Temperature and Supply Delta SFR (DIFFPROG, 0xF3), a VDCIN ADC flag is set. This VDCIN ADC flag is the FVDCIN in the Power Management Interrupt Flag SFR (IPSMF, 0xF8), which is used for power supply monitoring. This VDCIN ADC flag can be enabled to generate a PSM interrupt by setting the EVDCIN bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC). This method allows external voltage measurements to take place completely in the background, only requiring MCU activity if the external voltage has changed more than a configurable delta. To set up background external voltage measurements, follow these steps: 1. Initiate a single external voltage measurement by setting the VDCIN_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8). Upon completion of this measurement, configure the VDCIN_DIFF[2:0] bits to establish the change in voltage that will set the FVDCIN in the Power Management Interrupt Flag SFR (IPSMF, 0xF8). Set up the interval for background external voltage measurements by configuring the VDCIN_PERIOD[1:0] bits in the Peripheral ADC Strobe Period SFR (STRBPER, 0xF9) .
Battery ADC Interrupt
The battery ADC can generate an ADC interrupt when at least one of the following conditions occurs:
•
•
The new battery ADC value is smaller than the value set in the Battery Detection Threshold SFR (BATVTH, 0xFA), indicating a battery voltage loss. A single battery measurement initiated by setting the BATT_ADC_GO bit finishes.
When the battery flag (FBAT) is set in the Power Management Interrupt Flag SFR (IPSMF, 0xF8), a new ADC value is available in the Battery ADC Value SFR (BATADC, 0xDF). This battery flag can be enabled as a source of the PSM interrupt to generate a PSM interrupt every time the battery drops below a set voltage threshold, or after a single conversion initiated by setting the BATT_ADC_GO bit is ready. The Battery ADC Value SFR (BATADC, 0xDF) is updated with a new value only when the battery flag is set in the Power Management Interrupt Flag SFR (IPSMF, 0xF8).
2.
3.
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Preliminary Technical Data
External Voltage ADC in PSM1 and PSM2
An external voltage conversion is initiated only by certain actions that depend on the operating mode of the ADE7566/ADE7569.
•
ADE7566/ADE7569
External Voltage ADC Interrupt
The external voltage ADC can generate an ADC interrupt when at least one of the following conditions occurs:
•
•
•
In PSM0 operating mode, the 8052 is active. External voltage measurements are available in the background measurement mode and by initiating a single measurement. In PSM1 operating mode, the 8052 is active and the part is powered from battery. Single external voltage measurements can be initiated by setting the VDCIN_ADC_GO bit in the Start ADC Measurement SFR (ADCGO, 0xD8). Background external voltage measurements are not available. In PSM2 operating mode, the 8052 is not active. External voltage conversions are available through the background measurement mode only.
•
The difference between the new external voltage ADC value and the last external voltage ADC value generating an ADC interrupt is larger than the value set in the VDCIN_DIFF[2:0] bits in the Temperature and Supply Delta SFR (DIFFPROG, 0xF3). The external voltage ADC conversion initiated by setting VDCIN_ADC_GO is finishes.
When the ADC interrupt occurs, a new value is available in the VDCIN ADC Value SFR (VDCINADC, 0xEF). Note that there is no flag associated with this interrupt.
The external voltage ADC in the VDCIN ADC Value SFR (VDCINADC, 0xEF) is updated with a new value only when an external voltage ADC interrupt occurs.
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ADE7566/ADE7569 8052 MCU CORE ARCHITECTURE
The ADE7566/ADE7569 have an 8052 MCU core and use the 8051 instruction set. Some of the standard 8052 peripherals, such as the UART, have been enhanced. This section describes the standard 8052 core and its enhancements used in the ADE7566/ADE7569. The special function register (SFR) space is mapped into the upper 128 bytes of internal data memory space and is accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADE7566/ADE7569 via the SFR area is shown in Figure 67. All registers except the program counter (PC), instruction register (IR), and the four general-purpose register banks reside in the SFR area. The SFR registers include power control, configuration, and data registers that provide an interface between the CPU and all on-chip peripherals.
Preliminary Technical Data
16kB ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH/EE PROGRAM/DATA MEMORY 256 BYTES GENERAL PURPOSE RAM STACK REGISTER BANKS
ENERGY MEASUREMENT POWER MANAGEMENT RTC
8051 COMPATIBLE CORE PC IR
128-BYTE SPECIAL FUNCTION REGISTER AREA
LCD DRIVER TEMPERATURE ADC BATTERY ADC
256 BYTES XRAM
Figure 67. ADE7566/ADE7569 Block Diagram
MCU REGISTERS
The registers used by the MCU are summarized in this section.
Table 52. 8051 SFRs
SFR A B PSW PCON DPL DPH DPTR SP CFG Address 0xE0 0xF0 0xD0 0x87 0x82 0x83 0x83 and 0x82 0x81 0xAF Bit Addressable Yes Yes Yes No No No No No No Description Accumulator. Auxiliary Math Register. Program Status Word (see Table 53). Power Control Register (see Table 54). Data Pointer LSByte (see Table 55). Data Pointer MSByte (see Table 56). 16-Bit Data Pointer (see Table 57). Stack Pointer LSByte (see Table 58). Configuration (see Table 59).
Table 53. Program Status Word SFR (PSW, 0xD0)
Bit No. 7 6 5 4 to 3 Address 0xD7 0xD6 0xD5 0xD4, 0xD3 Mnemonic CY AC F0 RS1, RS0 Description Carry Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions. Auxiliary Carry Flag. Modified by ADD and ADDC instructions. General-Purpose Flag Available to the User. Register Bank Select Bits. RS1 RS0 Result (Selected Bank) 0 0 0 0 1 1 1 0 2 1 1 3 Overflow Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions. General-Purpose Flag Available to the User. Parity Bit. The number of bits set in the accumulator added to the value of the parity bit is always an even number.
2 1 0
0xD2 0xD1 0xD0
OV F1 P
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OTHER ON-CHIP PERIPHERALS: SERIAL I/O WDT TIMERS
Preliminary Technical Data
Table 54. Program Control SFR (PCON, 0x87)
Bit No. 7 6 to 0 Default 0 0 Description SMOD bit. Double baud rate control. Reserved. Should be left cleared. Bits 15 to 0 Default 0
ADE7566/ADE7569
Table 57. Data Pointer Register (DPTR, 0x82 and 0x83)
Description Contain two byte address of the data pointer. DPTR is the combination of DPH and DPL SFRs.
Table 55. Data Pointer Low SFR (DPL, 0x82)
Bits 7 to 0 Default 0 Description Contain the low byte of the data pointer.
Table 58. Stack Pointer SFR (SP, 0x81)
Bits 7 to 0 Default 7 Description Contain the 8 LSBs of the pointer for the stack.
Table 56. Data Pointer High SFR (DPH, 0x83)
Bits 7 to 0 Default 0 Description Contain the high byte of the data pointer.
Table 59. Configuration SFR (CFG, 0xAF)
Bit No. 7 6 Mnemonic Reserved EXTEN Description This bit should be left set for proper operation. Enhanced UART Enable Bit. EXTEN Result 0 Standard 8052 UART without enhanced error-checking features. 1 Enhanced UART with enhanced error checking (see the UART Additional Features section). Synchronous Communication Selection Bit. SCPS Result 0 I2C port is selected for control of the shared I2C/SPI pins and SFRs. 1 SPI port is selected for control of the shared I2C/SPI pins and SFRs. 38 kHz Modulation Enable Bit. MOD38EN Result 0 38 kHz modulation is disabled. 1 38 kHz modulation is enabled on the pins selected by the MOD38[7:0] bits in the Extended Port Configuration SFR (EPCFG, 0x9F). XRENx XREN1 OR XREN0 = 1 XREN1 AND XREN0 = 0 Result Enables MOVX instruction to use 256 bytes of extended RAM. Disables MOVX instruction.
5
SCPS
4
MOD38EN
3 to 2 1 to 0
Reserved XREN1, XREN0
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ADE7566/ADE7569
BASIC 8052 REGISTERS
Program Counter (PC)
The program counter holds the two byte address of the next instruction to be fetched. The PC is initialized with 0x00 at reset and is incremented after each instruction is performed. Note that the amount added to the PC depends on the number of bytes in the instruction, so the increment can range from 1 byte to 3 bytes. The program counter is not directly accessible to the user but can be directly modified by CALL and JMP instructions that change which part of the program is active.
Preliminary Technical Data
bits are described in Table 53. The Program Status Word SFR (PSW, 0xD0) is bit addressable.
Data Pointer (DPTR)
The data pointer is made up of two 8-bit registers: DPH (high byte) and DPL (low byte). These provide memory addresses for internal code and data access. The DPTR can be manipulated as a 16-bit register (DPTR = DPH, DPL), or as two independent 8-bit registers (DPH, DPL). See Table 55 and Table 56. The ADE7566/ADE7569 support dual data pointers. See the Dual Data Pointers section.
Instruction Register (IR)
The instruction register holds the opcode of the instruction being executed. The opcode is the binary code that results from assembling an instruction. This register is not directly accessible to the user.
Stack Pointer (SP)
The stack pointer keeps track of the current address of the top of the stack. To push a byte of data onto the stack, the stack pointer is incremented and the data is moved to the new top of the stack. To pop a byte of data off of the stack, the top byte of data is moved into the awaiting address, and the stack pointer is decremented. The stack is a last in, first out (LIFO) method of data storage because the most recent addition to the stack is the first to come off it. The stack is utilized during CALL and RET instructions to keep track of the address to move into the PC when returning from the function call. The stack is also manipulated when vectoring for interrupts to keep track of the prior state of the PC. The stack resides in the internal extended RAM, and the SP register holds the address of the stack in the extended RAM (XRAM). The advantage of this solution is that the stack is segregated to the internal XRAM. The use of the generalpurpose RAM can be limited to data storing, and the use of the extended internal RAM can be limited to the stack pointer. This separation limits the chance of data RAM corruption when the stack pointer overflows in data RAM. Data can still be stored in XRAM by using the MOVX command. To change the default starting address for the stack, move a value into the stack pointer (SP). For example, to enable the extended stack pointer and initialize it at the beginning of the XRAM space, use the following code:
MOV
0xFF
256 BYTES OF RAM (DATA)
Register Banks
There are four banks that each contain 8 byte-wide registers for a total of 32 bytes of registers. These registers are convenient for temporary storage of mathematical operands. An instruction involving the accumulator and a register can be executed in 1 clock cycle, as opposed to 2 clock cycles to perform an instruction involving the accumulator and a literal or a byte of general-purpose RAM. The register banks are located in the first 32 bytes of RAM. The active register bank is selected by the RS0 and RS1 bits in the Program Status Word SFR (PSW, 0xD0).
Accumulator
The accumulator is a working register, storing the results of many arithmetic or logical operations. The accumulator is used in more than half of the 8052 instructions where it is usually referred to as A. The program status register (PSW) constantly monitors the number of bits that are set in the accumulator to determine if it has even or odd parity. The accumulator is stored in the SFR space (see Table 52).
B Register
The B register is used by the multiply and divide instructions, MUL AB and DIV AB to hold one of the operands. Because the B register is not used for many instructions, it can be used as a scratchpad register such as those in the register banks. The B register is stored in the SFR space (see Table 52).
SP,#00H
0xFF
256 BYTES OF ON-CHIP XRAM DATA + STACK
06353-057
Program Status Word (PSW)
The PSW register reflects the status of arithmetic and logical operations through carry, auxiliary carry, and overflow flags. The parity flag reflects the parity of the accumulator contents, which can be helpful for communication protocols. The PSW
0x00
0x00
Figure 68. Extended Stack Pointer Operation
Rev. PrA | Page 72 of 136
Preliminary Technical Data
STANDARD 8052 SFRS
The standard 8052 special function registers include the Accumulator, B, PSW, DPTR, and SP SFRs described in the Basic 8052 Registers section. The standard 8052 SFRs also defines timers, the serial port interface, interrupts, I/O ports, and power-down modes.
ADE7566/ADE7569
Power Control Register (PCON, 0x87)
The 8052 core defines two power-down modes: power down and idle. The ADE7566/ADE7569 enhance the power control capability of the traditional 8052 MCU with additional power management functions. The Power Control SFR (POWCON, 0xC5) is used to define power control-specific functionality for the ADE7566/ADE7569. The Program Control SFR (PCON, 0x87) is not bit addressable. See the Power Management section. The ADE7566/ADE7569 have many other peripherals not standard to the 8052 core, including
• • • • • • • • •
Timer SFRs
The 8052 contains three 16-bit timers: the identical Timer0 and Timer1, as well as a Timer2. These timers can also function as event counters. Timer2 has a capture feature where the value of the timer can be captured in two 8-bit registers upon the assertion of an external input signal (see Table 98 and the Timers section).
Serial Port SFRs
The full-duplex serial port peripheral requires two registers, one for setting up the baud rate and other communication parameters, and another for the transmit/receive buffer. The ADE7566/ADE7569 also have enhanced serial port functionality with a dedicated timer for baud rate generation with a fractional divisor and additional error detection. See Table 127 and the UART Serial Interface section.
ADE energy measurement DSP RTC LCD driver Battery switchover/power management Temperature ADC Battery ADC SPI/I2C communication Flash memory controller Watchdog timer
Interrupt SFRs
There is a two-tiered interrupt system standard in the 8052 core. The priority level for each interrupt source is individually selectable as high or low. The ADE7566/ADE7569 enhance this interrupt system by creating, in essence, a third interrupt tier for a highest priority, the power supply management interrupt (PSM). See the Interrupt System section.
MEMORY OVERVIEW
The ADE7566/ADE7569 contain the following memory blocks:
• • •
16 kB of on-chip Flash/EE program and data memory 256 bytes of general-purpose RAM 256 bytes of internal extended RAM (XRAM)
I/O Port SFRs
The 8052 core supports four I/O ports, P0 through P3, where Port 0 and Port 2 are typically used to access external code and data spaces. The ADE7566/ADE7569, unlike standard 8052 products, provide internal nonvolatile flash memory so that an external code space is unnecessary. The on-chip LCD driver requires many pins, some of which are dedicated for LCD functionality, and others that can be configured as LCD or general-purpose inputs/outputs. Due to the limited number of I/O pins, the ADE7566/ADE7569 do not allow access to external code and data spaces. The ADE7566/ADE7569 provide 20 pins that can be used for general-purpose I/O. These pins are mapped to Port 0, Port 1, and Port 2. They are accessed through three bit-addressable 8052 SFRs, P0, P1, and P2. Another enhanced feature of the ADE7566/ADE7569 is that the weak pull-ups standard on 8052 Port 1, Port 2, and Port 3 can be disabled to make open drain outputs, as is standard on Port 0. The weak pull-ups can be enabled on a pin-by-pin basis. See the I/O Ports section.
The 256 bytes of general-purpose RAM share the upper 128 bytes of its address space with special function registers. All of the memory spaces are shown in Figure 67. The addressing mode specifies which memory space to access.
General-Purpose RAM
General-purpose RAM resides in memory locations 0x00 through 0xFF. It contains the register banks.
0x7F
GENERAL-PURPOSE AREA
0x30 0x2F
BANKS SELECTED VIA BITS IN PSW 11
BIT-ADDRESSABLE (BIT ADDRESSES)
0x20 0x1F 0x18 0x17
10
0x10 0x0F
FOUR BANKS OF EIGHT REGISTERS R0 TO R7
01
0x08 0x07
06353-058
00
RESET VALUE OF STACK POINTER
0x00
Figure 69. Lower 128 Bytes of Internal Data Memory
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ADE7566/ADE7569
Address 0x80 through Address 0xFF of general-purpose RAM are shared with the special function registers. The mode of addressing determines which memory space is accessed as shown in Figure 70.
0xFF ACCESSIBLE BY INDIRECT ADDRESSING ONLY ACCESSIBLE BY DIRECT AND INDIRECT ADDRESSING ACCESSIBLE BY DIRECT ADDRESSING ONLY
Preliminary Technical Data
The individual bits of some SFRs can be accessed for use in Boolean and program-branching instructions. These SFRs are labeled as bit-addressable and the bit addresses are given in the SFR Mapping section.
Extended Internal RAM (XRAM)
The ADE7566/ADE7569 provide 256 bytes of extended on-chip RAM. No external RAM is supported. This RAM is located in Address 0x0000 through Address 0x00FF in the extended RAM space. To select the extended RAM memory space, the extended indirect addressing modes are used. The internal XRAM is enabled in the Configuration SFR (CFG, 0xAF) by writing 01 to CFG[1:0].
0x00FF 256 BYTES OF EXTENDED INTERNAL RAM (XRAM) 0x0000
0x80 0x7F
0x00
06353-059
GENERAL PURPOSE RAM SPECIAL FUNCTION REGISTERS (SFRs)
Figure 70. General-Purpose RAM and SFR Memory Address Overlap
Both direct and indirect addressing can be used to access generalpurpose RAM from 0x00 through 0x7F. However, only indirect addressing can be used to access general-purpose RAM from 0x80 through 0xFF because this address space shares the same space with the special function registers (SFRs). The 8052 core also has the means to access individual bits of certain addresses in the general-purpose RAM and special function memory spaces. The individual bits of general-purpose RAM Address 0x20 to Address 0x2F can be accessed through their Bit Address 0x00 through Bit Address 0x7F. The benefit of bit addressing is that the individual bits can be accessed quickly without the need for bit masking, which takes more code memory and execution time. The bit addresses for general-purpose RAM Address 0x20 through Address 0x2F can be seen in Figure 71.
BYTE ADDRESS 0x2F 0x2E 0x2D 0x2C 0x2B 0x2A 0x29 0x28 0x27 0x26 0x25 0x24 0x23 0x22 0x21 0x20 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 BIT ADDRESSES (HEXA) 7E 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00
06353-060
Figure 72. Extended Internal RAM (XRAM) Space
Code Memory
Code and data memory are stored in the 16 kB flash memory space. No external code memory is supported. To access code memory, code indirect addressing is used.
ADDRESSING MODES
The 8052 core provides several addressing modes. The addressing mode determines how the core interprets the memory location or data value specified in assembly language code. There are six addressing modes as shown in Table 60.
Table 60. 8052 Addressing Modes
Addressing Mode Immediate Direct Example MOV A, #A8h MOV DPTR,#A8h MOV A, A8h MOV A, IE MOV A, R0 MOV A,@R0 MOVX A, @DPTR MOVX A, @R0 MOVC A, @A+DPTR MOVC A, @A+PC JMP @A+DPTR Bytes 2 3 2 2 1 1 1 1 1 1 1 Core Clock Cycles 2 3 2 2 1 2 4 4 4 4 3
Indirect Extended Direct Extended Indirect Code Indirect
Figure 71. Bit Addressable Area of General-Purpose RAM
Immediate Addressing
In immediate addressing, the expression entered after the number sign (#) is evaluated by the assembler and stored in the specified memory address. This number is referred to as a literal because it refers only to a value and not to a memory location. Instructions using this addressing mode is slower than those between two registers because the literal must be stored and fetched from memory. The expression can be entered as a symbolic variable or an arithmetic expression; the value is computed by the assembler.
Bit addressing can be used for instructions that involve Boolean variable manipulation and program branching (see the Instruction Set section).
Special Function Registers
Special function registers are registers that affect the function of the 8051 core or its peripherals. These registers are located in RAM in Address 0x80 through Address 0xFF. They are only accessible through direct addressing as shown in Figure 70 .
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06353-061
Preliminary Technical Data
Direct Addressing
With direct addressing, the value at the source address is moved to the destination address. Direct addressing provides the fastest execution time of all the addressing modes when an instruction is performed between registers. Note that indirect or direct addressing modes can be used to access general-purpose RAM Address 0x00 through Address 0x7F. An instruction with direct addressing that uses an address between 0x80 and 0xFF is referring to a special function memory location.
ADE7566/ADE7569
These two instructions require a total of seven clock cycles and four bytes of storage in the program memory.
Extended Indirect Addressing
The internal extended RAM is accessed through a pointer to the address in indirect addressing mode. The ADE7566/ADE7569 have 256 bytes of internal extended RAM, accessed through MOVX instructions. External memory is not supported on the devices. In extended indirect addressing mode, a register holds the address of the byte of extended RAM. The following code moves the contents of extended RAM Address 0x80 to the accumulator:
MOV MOVX R0,#80h A,@R0
Indirect Addressing
With indirect addressing, the value pointed to by the register is moved to the destination address. For example, to move the contents of internal RAM Address 0x82 to the accumulator, use the following instructions:
MOV MOV R0,#82h A,@R0
These two instructions require six clock cycles and three bytes of storage. Note that there are 256 bytes of extended RAM, so both extended direct and extended indirect addressing can cover the whole address range. There is a storage and speed advantage to using extended indirect addressing because the additional byte of addressing available through the DPTR register that is not needed is not stored. From the three examples demonstrating the access of internal RAM from 0x80 through 0xFF, and the access of extended internal RAM from 0x00 through 0xFF, it can be seen that it is most efficient to use the entire internal RAM accessible through indirect access before moving to extended RAM.
The two instructions above require a total of four clock cycles and three bytes of storage in the program memory. Indirect addressing allows addresses to be computed, which is useful for indexing into data arrays stored in RAM. Note that an instruction that refers to Address 0x00 through Address 0x7F is referring to internal RAM, and indirect or direct addressing modes can be used. An instruction with indirect addressing that uses an address between 0x80 and 0xFF is referring to internal RAM, not to an SFR.
Extended Direct Addressing
The DPTR register (see Table 57) is used to access internal extended RAM in extended indirect addressing mode. The ADE7566/ADE7569 have 256 bytes of XRAM, accessed through MOVX instructions. External memory spaces are not supported on this device. In extended direct addressing mode, the DPTR register points to the address of the byte of extended RAM. The following code moves the contents of extended RAM Address 0x100 to the accumulator:
MOV MOVX DPTR,#100h A,@DPTR
Code Indirect Addressing
The internal code memory can be accessed indirectly. This can be useful for implementing lookup tables and other arrays of constants that are stored in flash. For example, to move the data stored in flash memory at Address 0x8002 into the accumulator, use the following code:
MOV CLR MOVX DPTR,#8002h A A,@A+DPTR
The accumulator can be used as a variable index into the array of flash memory located at DPTR.
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ADE7566/ADE7569
INSTRUCTION SET
Preliminary Technical Data
Table 61 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting in a 4 MIPS peak performance.
Table 61. Instruction Set
Mnemonic ARITHMETIC ADD A,Rn ADD A,@Ri ADD A,dir ADD A,#data ADDC A,Rn 1 1 ADDC A,@Ri ADDC A,dir ADD A,#data SUBB A,Rn SUBB A,@Ri SUBB A,dir SUBB A,#data INC A INC Rn INC @ INC dir INC DPTR DEC A DEC Rn DEC @Ri DEC dir MUL AB DIV AB DA A A LOGIC ANL A,Rn ANL A,@Ri ANL A,dir ANL A,#data ANL dir,A ANL dir,#data ORL A,Rn ORL A,@Ri ORL A,dir ORL A,#data ORL dir,A ORL dir,#data XRL A,Rn XRL A,@Ri XRL A,#data XRL dir,A XRL A, XRL dir,#data CLR A CPL A SWAP A RL A Description Add Register to A. Add Indirect Memory to A. Add Direct Byte to A. Add Immediate to A. Add Register to A with Carry. Add Indirect Memory to A with Carry. Add Direct Byte to A With Carry. Add Immediate to A With Carry. Subtract Register from A with Borrow. Subtract Indirect Memory from A with Borrow. Subtract Direct from A with Borrow. Subtract Immediate from A with Borrow. Increment A. Increment Register. Ri Increment Indirect Memory. Increment Direct Byte. Increment Data Pointer. Decrement A. Decrement Register. Decrement Indirect Memory. Decrement Direct Byte. Multiply A by B. Divide A by B. Decimal Adjust A. AND Register to A. AND Indirect Memory to A. AND Direct Byte to A. AND Immediate to A. AND A to Direct Byte. AND Immediate Data to Direct Byte. OR Register to A. OR Indirect Memory to A. OR Direct Byte to A. OR Immediate to A. OR A to Direct Byte. OR Immediate Data to Direct Byte. Exclusive-OR Register to A. Exclusive-OR Indirect Memory to A. Exclusive-OR Immediate to A. Exclusive-OR A to Direct Byte. dir Exclusive-OR Indirect Memory to A. Exclusive-OR Immediate Data To Direct. Clear A. Complement A. Swap Nibbles of A. Rotate A Left.
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Bytes 1 1 2 2 1 1 2 2 1 1 2 2 1 1 1 2 1 1 1 1 2 1 1 1 1 1 2 2 2 3 1 1 2 2 2 3 1 2 2 2 2 3 1 1 1 1
Cycles 1 2 2 2 1 2 2 2 1 2 2 2 1 1 2 2 3 1 1 2 2 9 9 2 1 2 2 2 2 3 1 2 2 2 2 3 1 2 2 2 2 3 1 1 1 1
Preliminary Technical Data
Mnemonic RLC A RR A RRC A DATA TRANSFER MOV A,Rn MOV A,@Ri MOV Rn,A MOV @Ri,A MOV A,dir MOV A,#data MOV Rn,#data MOV dir,A MOV Rn,dir MOV dir,Rn MOV @Ri,#data MOV dir,@Ri MOV @Ri,dir MOV dir,dir MOV dir,#data MOV DPTR,#data MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH dir POP dir XCH A,Rn XCH A,@Ri XCHD A,@Ri XCH A,dir BOOLEAN CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit OR MOV C,bit MOV bit,C BRANCHING JMP @A+DPTR RET RETI ACALL addr11 AJMP addr11 SJMP rel JC rel Description Rotate A Left Through Carry. Rotate A Right. Rotate A Right Through Carry. Move Register to A. Move Indirect Memory to A. Move A to Register. Move A to Indirect Memory. Move Direct Byte to A. Move Immediate to A. Move Register to Immediate. Move A to Direct Byte. Move Register to Direct Byte. Move Direct To Register. Move Immediate to Indirect Memory. Move Indirect to Direct Memory. Move Direct to Indirect Memory. Move Direct Byte to Direct Byte. Move Immediate to Direct Byte. Move Immediate to Data Pointer. Move Code Byte Relative DPTR to A. Move Code Byte Relative PC to A 1. Move External (A8) Data to A. Move External (A16) Data to A. Move A to External Data (A8). Move A to External Data (A16). Push Direct Byte onto Stack. Pop Direct Byte from Stack. Exchange A and Register. Exchange A and Indirect Memory. Exchange A and Indirect Memory Nibble. Exchange A and Direct Byte. Clear Carry. Clear Direct Bit. Set Carry. Set Direct Bit. Complement Carry. Complement Direct Bit. AND Direct Bit and Carry. AND Direct Bit Inverse to Carry. OR Direct Bit And Carry. Direct Bit Inverse to Carry. Move Direct Bit to Carry. Move Carry to Direct Bit. Jump Indirect Relative to DPTR. Return from Subroutine. Return from Interrupt. Absolute Jump to Subroutine. Absolute Jump Unconditional. Short Jump (Relative Address). Jump on Carry Equal to 1.
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ADE7566/ADE7569
Bytes 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3 3 1 1 1 1 1 1 2 2 1 1 1 2 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 2 2 2 2 Cycles 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 2 3 3 3 4 4 4 4 4 4 2 2 1 2 2 2 1 2 1 2 1 2 2 2 2 2 2 2 3 4 4 3 3 3 3
ADE7566/ADE7569
Mnemonic JNC rel JZ rel JNZ rel DJNZ Rn,rel LJMP LCALL addr16 JB bit,rel JNB bit,rel JBC bit,rel CJNE A,dir,rel CJNE A,#data,rel CJNE Rn,#data,rel CJNE @Ri,#data,rel DJNZ dir,rel MISCELLANEOUS NOP Description Jump on Carry Equal to 0. Jump on Accumulator = 0. Jump on Accumulator Not Equal to 0. Decrement Register, JNZ Relative. Long Jump Unconditional. Long Jump to Subroutine. Jump on Direct Bit = 1. Jump on Direct Bit = 0. Jump on Direct Bit = 1 and Clear. Compare A, Direct JNE Relative. Compare A, Immediate JNE Relative. Compare register, Immediate JNE Relative. Compare indirect, Immediate JNE Relative. Decrement Direct Byte, JNZ Relative. No Operation.
Preliminary Technical Data
Bytes 2 2 2 2 3 3 3 3 3 3 3 3 3 3 1 Cycles 3 3 3 3 4 4 4 4 4 4 4 4 4 4 1
READ-MODIFY-WRITE INSTRUCTIONS
Some 8051 instructions read the latch while others read the pin. The state of the pin is read for instructions that input a port bit. Instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and rewrite it to the latch. Because these instructions involve modifying the port, it is assumed that the pins being modified are outputs, so the output state of the pin is read from the latch. This prevents a possible misinterpretation of the voltage level of a pin. For example, if a port pin is used to drive the base of a transistor, a 1 is written to the bit to turn the transistor on. If the CPU reads the same port bit at the pin rather than the latch, it reads the base voltage of the transistor and interprets it as Logic 0. Reading the latch rather than the pin returns the correct value of 1. The instructions that read the latch rather than the pins are called read-modify-write instructions and are listed in Table 62. When the destination operand is a port or a port bit, these instructions read the latch rather than the pin.
Table 62. Read-Modify-Write Instructions
Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV PX.Y, C1 CLR PX.Y1 SETB PX.Y1
1
INSTRUCTIONS THAT AFFECT FLAGS
Many instructions explicitly modify the carry bit, such as the MOV C bit and CLR C instructions. Other instructions that affect status flags are listed in this section.
ADD A, Source
This instruction adds the source to the accumulator. No status flags are referenced by the instruction.
Affected Status Flags
C Set if there is a carry out of Bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned. Set if there is a carry out of Bit 6 or a carry out of Bit 7, but not if both are set. Used to indicate an overflow for signed addition. This flag is set if two positive operands yield a negative result, or if two negative operands yield a positive result. Set if there is a carry out of Bit 3. Cleared otherwise.
OV
AC
Example ANL P0, A ORL P1, A XRL P2, A JBC P1.1, LABEL CPL P2.0 INC P2 DEC P2 DJNZ P0, LABEL MOV P0.0,C CLR P0.0 SETB P0.0
Description Logical AND. Logical OR. Logical EX-OR. Jump if Bit = 1 and Clear Bit. Complement Bit. Increment. Decrement. Decrement and Jump if Not Zero. Move Carry to Bit Y of Port X. Clear Bit Y of Port X. Set Bit Y of Port X.
ADDC A, Source
This instruction adds the source and the carry bit to the accumulator. The carry status flag is referenced by the instruction.
Affected Status Flags
C Set if there is a carry out of Bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned. Set if there is a carry out of Bit 6 or a carry out of Bit 7, but not if both are set. Used to indicate an overflow for signed addition. This flag is set if two positive operands yield a negative result, or if two negative operands yield a positive result. Set if there is a carry out of Bit 3. Cleared otherwise.
OV
These instructions read the port byte (all 8 bits), modify the addressed bit, and write the new byte back to the latch.
AC
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Preliminary Technical Data
SUBB A, Source
This instruction subtracts the source byte and the carry (borrow) flag from the accumulator. It references the carry (borrow) status flag.
ADE7566/ADE7569
DA A
This instruction adjusts the accumulator to hold two 4-bit digits after the addition of two binary coded decimals (BCDs) with the ADD or ADDC instructions. If the AC bit is set or if the value of Bit 0 to Bit 3 exceeds nine, 0x06 is added to the accumulator to correct the lower 4 bits. If the carry bit is set when the instruction begins, or if 0x06 is added to the accumulator in the first step, 0x60 is added to the accumulator to correct the higher 4 bits. The carry and AC status flags are referenced by this instruction.
Affected Status Flags
C Set if there is a borrow needed for Bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned. Set if there is a borrow is needed for Bit 6 or Bit 7, but not for both. Used to indicate an overflow for signed subtraction. This flag is set if a negative number subtracted from a positive yields a negative result, or if a positive number subtracted from a negative number yields a positive result. Set if a borrow is needed for Bit 3. Cleared otherwise.
OV
Affected Status Flag
C Set if the result is greater than 0x99. Cleared otherwise.
RRC A
This instruction rotates the accumulator to the right through the carry flag. The old LSB of the accumulator becomes the new carry flag, and the old carry flag is loaded into the new MSB of the accumulator. The carry status flag is referenced by this instruction.
AC
MUL AB
This instruction multiplies the accumulator by the B register. This operation is unsigned. The lower byte of the 16-bit product is stored in the accumulator and the higher byte is left in the B register. No status flags are referenced by the instruction.
Affected Status Flag
C Equal to the state of ACC.0 before execution of the instruction.
Affected Status Flags
C OV Cleared Set if the result is greater than 255. Cleared otherwise.
RLC A
This instruction rotates the accumulator to the left through the carry flag. The old MSB of the accumulator becomes the new carry flag, and the old carry flag is loaded into the new LSB of the accumulator. The carry status flag is referenced by this instruction.
DIV AB
This instruction divides the accumulator by the B register. This operation is unsigned. The integer part of the quotient is stored in the accumulator and the remainder goes into the B register. No status flags are referenced by the instruction.
Affected Status Flag
C Equal to the state of ACC.7 before execution of the instruction.
Affected Status Flags
C OV Cleared Cleared unless the B register is equal to 0, in which case the results of the division are undefined and the OV flag is set.
CJNE Destination, Source, Relative Jump
This instruction compares the source value to the destination value and branches to the location set by the relative jump if they are not equal. If the values are equal, program execution continues with the instruction after the CJNE instruction. No status flags are referenced by this instruction.
Affected Status Flag
C Set if the source value is greater than the destination value. Cleared otherwise.
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ADE7566/ADE7569 INTERRUPT SYSTEM
The unique power management architecture of the ADE7566/ADE7569 includes an operating mode (PSM2) where the 8052 MCU core is shut down. Events can be configured to wake the 8052 MCU core from the PSM2 operating mode. A distinction is drawn here between events that can trigger the wake-up of the 8052 MCU core and events that can trigger an interrupt when the MCU core is active. Events that can wake the core are referred to as wake-up events, while events that can interrupt the program flow when the MCU is active are called interrupts. See the 3.3 V Peripherals and Wake-Up Events section to learn more about events that can wake the 8052 core from PSM2. The ADE7566/ADE7569 provide 12 interrupt sources with three priority levels. The power management interrupt is alone at the highest priority level. The other two priority levels are configurable through the Interrupt Priority SFR (IP, 0xB8) and Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9).
Preliminary Technical Data
A Priority 1 interrupt can interrupt the service routine of a Priority 0 interrupt, and if two interrupts of different priorities occur at the same time, the Priority 1 interrupt is serviced first. An interrupt cannot be interrupted by another interrupt of the same priority level. If two interrupts of the same priority level occur simultaneously, a polling sequence is observed. See the Interrupt Priority section.
INTERRUPT ARCHITECTURE
The ADE7566/ADE7569 possess advanced power supply monitoring features. To ensure a fast response to time critical power supply issues, such as a loss of line power, the power supply monitoring interrupt should be able to interrupt any interrupt service routine. To enable the user to have full use of the standard 8051 interrupt priority levels, an additional priority level was added for the power supply management (PSM) interrupt. The PSM interrupt is the only interrupt at this highest interrupt priority level.
HIGH PSM
06353-063
STANDARD 8051 INTERRUPT ARCHITECTURE
The 8051 standard interrupt architecture includes two tiers of interrupts, where some interrupts are assigned a high priority and others are assigned a low priority.
HIGH
06353-062
PRIORITY 1 LOW PRIORITY 0
Figure 74. Interrupt Architecture
PRIORITY 1 PRIORITY 0
LOW
See the Power Supply Monitor Interrupt (PSM) section for more information on the PSM interrupt.
Figure 73. Standard 8051 Interrupt Priority Levels
INTERRUPT REGISTERS
The control and configuration of the interrupt system is carried out through four interrupt-related SFRs discussed in this section.
Table 63. Interrupt SFRs
SFR IE IP IEIP2 WDCON Address 0xA8 0xB8 0xA9 0xC0 Default 0x00 0x00 0xA0 0x10 Bit Addressable Yes Yes No Yes Description Interrupt Enable Register (see Table 64). Interrupt Priority Register (see Table 65). Secondary Interrupt Enable Register (see Table 66). Watchdog Timer Configuration (see Table 71 and the Writing to the Watchdog Timer SFR (WDCON, 0xC0) section).
Table 64. Interrupt Enable SFR (IE, 0xA8)
Bit No. 7 6 5 4 3 2 1 0 Address 0xAF 0xAE 0xAD 0xAC 0xAB 0xAA 0xA9 0xA8 Mnemonic EA ETEMP ET2 ES ET1 EX1 ET0 EX0 Description Enables all Interrupt Sources. Set by the user. Cleared by the user to disable all interrupt sources. Enables the Temperature ADC Interrupt. Set by the user. Enables the Timer 2 Interrupt. Set by the user. Enables the UART Serial Port Interrupt. Set by the user. Enables the Timer 1 Interrupt. Set by the user. Enables the External Interrupt 1 (INT1). Set by the user. Enables the Timer 0 Interrupt. Set by the user. Enables External Interrupt 0 (INT0). Set by the user.
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Preliminary Technical Data
Table 65. Interrupt Priority SFR (IP, 0xB8)
Bit No. 7 6 5 4 3 2 1 0 Address 0xBF 0xBE 0xBD 0xBC 0xBB 0xBA 0xB9 0xB8 Mnemonic PADE PTEMP PT2 PS PT1 PX1 PT0 PX0
ADE7566/ADE7569
Description ADE Energy Measurement Interrupt Priority (1 = high, 0 = low). Temperature ADC Interrupt Priority (1 = high, 0 = low). Timer 2 Interrupt Priority (1 = high, 0 = low). UART Serial Port Interrupt Priority (1 = high, 0 = low). Timer 1 Interrupt Priority (1 = high, 0 = low). INT1 (External Interrupt 1) Priority (1 = high, 0 = low). Timer 0 Interrupt Priority (1 = high, 0 = low). INT0 (External Interrupt 0) Priority (1 = high, 0 = low).
Table 66. Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9)
Bit No. 7 6 5 4 3 2 1 0 Mnemonic – PTI – PSI EADE ETI EPSM ESI Description – RTC Interrupt Priority (1 = high, 0 = low). – SPI/I2C Interrupt Priority (1 = high, 0 = low). Enables the Energy Metering Interrupt (ADE). Set by the user. Enables the RTC Interval Timer Interrupt. Set by the user. Enables the PSM Power Supply Management Interrupt. Set by the user. Enables the SPI/I2C Interrupt. Set by the user.
INTERRUPT PRIORITY
If two interrupts of the same priority level occur simultaneously, the polling sequence is observed (as shown in Table 67).
Table 67. Priority Within Interrupt Level
Source IPSM IRTC IADE WDT ITEMP IE0 TF0 IE1 TF1 ISPI/I2CI RI/TI TF2/EXF2 Priority 0 (Highest) 1 2 3 4 5 6 7 8 9 10 11 (Lowest) Description Power Supply Monitor Interrupt. RTC Interval Timer Interrupt. ADE Energy Measurement Interrupt. Watchdog Timer Overflow Interrupt. Temperature ADC Interrupt. External Interrupt 0. Timer/Counter 0 Interrupt. External Interrupt 1. Timer/Counter 1 Interrupt. SPI/I2C Interrupt. UART Serial Port Interrupt. Timer/Counter 2 Interrupt.
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ADE7566/ADE7569
INTERRUPT FLAGS
Preliminary Technical Data
The interrupt flags and status flags associated with the interrupt vectors are shown in Table 68 and Table 69. Most of the interrupts have flags associated with them.
Table 68. Interrupt Flags
Interrupt Source IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 ITEMP (Temperature ADC) IPSM (Power Supply) IADE (Energy Measurement DSP) Flags TCON.1 TCON.5 TCON.3 TCON.7 SCON.1 SCON.0 T2CON.7 T2CON.6 – IPSMF.6 MIRQSTL.7 Bit Address IE0 TF0 IE1 TF1 TI RI TF2 EXF2 – FPSM – Description External Interrupt 0. Timer 0. External Interrupt 1. Timer 1. Transmit Interrupt. Receive Interrupt. Timer 2 Overflow Flag. Timer 2 External Flag. Temperature ADC Interrupt. Does not have an interrupt flag associated with it. PSM Interrupt Flag. Read MIRQSTH, MIRQSTM, MIRQSTL.
Table 69. Status Flags
Interrupt Source ITEMP (Temperature ADC) ISPI/I2CI IRTC (RTC Interval Timer) WDT (Watchdog Timer) Flags – SPI2CSTAT SPI2CSTAT TIMECON.7 TIMECON.2 WDCON.2 Bit Address – – – – – WDS Description Temperature ADC Interrupt. Does not have a status flag associated with it. SPI Interrupt Status Register. I2C Interrupt Status Register. RTC Midnight Flag. RTC Alarm Flag. Watchdog Timeout Flag.
A functional block diagram of the interrupt system is shown in Figure 75. Note that the PSM interrupt is the only interrupt in the highest priority level. If an external wake-up event occurs to wake the ADE7566 /ADE7569 from PSM2, a pending external interrupt is generated. When the EX0 or EX1 bits in the Interrupt Enable SFR (IE, 0xA8) are set to enable external interrupts, the program counter is loaded with the IE0 or IE1 interrupt vector. The IE0 and IE1 interrupt flags in the TCON register are not affected by events that occur when the 8052 MCU core is shut down during PSM2. See the Power Supply Monitor Interrupt (PSM) section. The RTC, temperature ADC, and I2C/SPI interrupts are latched such that pending interrupts cannot be cleared without entering their respective interrupt service routines. Clearing the RTC midnight flags and alarm flags does not clear a pending RTC
interrupt. Similarly, clearing the I2C/SPI status bits in the SPI Interrupt Status Register SFR (SPISTAT, 0xEA) does not cancel a pending I2C/SPI interrupt. These interrupts remain pending until the RTC or I2C/SPI interrupt vectors are enabled. Their respective interrupt service routines are entered shortly thereafter. Figure 75 shows how the interrupts are cleared when the interrupt service routines are entered. Some interrupts with multiple interrupt sources are not automatically cleared; specifically the PSM, ADE, UART, and Timer 2 interrupt vectors. Note that the INT0 and INT1 interrupts are only cleared if the external interrupt is configured to be triggered by a falling edge by setting IT0 in the Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, 0x88). If INT0 or INT1 is configured to interrupt on a low level, the interrupt service routine is reentered until the respective pin goes high.
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Preliminary Technical Data
IE/IEIP2 REGISTERS PSM IPSMF IPSME FPSM (IPSMF.6) IP/IEIP2 REGISTERS LOW
ADE7566/ADE7569
PRIORITY LEVEL HIGH HIGHEST
RTC
MIDNIGHT ALARM
IN OUT LATCH RESET
ADE
MIRQSTH MIRQENH
MIRQSTM MIRQENM
MIRQSTL MIRQENL
MIRQSTL.7
WATCHDOG
WATCHDOG TIMEOUT WDIR
TEMP ADC
TEMPADC INTERRUPT
IN OUT LATCH RESET
EXTERNAL INTERRUPT 0
INT0
IT0 0 1 IT0
PSM2 IE0
TIMER 0
TF0
INTERRUPT POLLING SEQUENCE
EXTERNAL INTERRUPT 1
IT1 INT1 0 1 IT1
PSM2 IE1
TF1 TIMER 1
SPI INTERRUPT CFG.5 I2C/SPI
1 0
I2C INTERRUPT
IN OUT LATCH RESET
UART
RI TI
TIMER 2
TF2 EXF2
Figure 75. Interrupt System Functional Block Diagram
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06353-064
INDIVIDUAL INTERRUPT ENABLES GLOBAL INTERRUPT ENABLE (EA)
LEGEND AUTOMATIC CLEAR SIGNAL
ADE7566/ADE7569
INTERRUPT VECTORS
When an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. When the interrupt service routine is complete, the program counter is popped off the stack by a RETI instruction. This allows program execution to resume from where it was interrupted. The interrupt vector addresses are shown in Table 70.
Table 70. Interrupt Vector Addresses
Source IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 ITEMP (Temperature ADC) ISPI/I2CI IPSM (Power Supply) IADE (Energy Measurement DSP) IRTC (RTC Interval Timer) WDT (Watchdog Timer) Vector Address 0x0003 0x000B 0x0013 0x001B 0x0023 0x002B 0x0033 0x003B 0x0043 0x004B 0x0053 0x005B
Preliminary Technical Data
CONTEXT SAVING
When the 8052 vectors to an interrupt, only the program counter is saved on the stack. Therefore, the interrupt service routine must be written to ensure that registers used in the main program are restored to their pre-interrupt state. Common registers that can be modified in the ISR are the accumulator register and the PSW register. Any general-purpose registers that are used as scratchpads in the ISR should also be restored before exiting the interrupt. The following example 8051 code shows how to restore some commonly used registers:
GeneralISR: ; save the current Accumulator value PUSH ACC ; save the current status and register bank selection PUSH PSW
; service interrupt … ; restore the status and register bank selection POP POP RETI PSW ACC ; restore the accumulator
INTERRUPT LATENCY
The 8051 architecture requires that at least one instruction execute between interrupts. To ensure this, the 8051 MCU core hardware prevents the program counter from jumping to an ISR immediately after completing a RETI instruction or an access of the IP and IE registers. The shortest interrupt latency is 3.25 instruction cycles, 800 ns with a clock of 4.096 MHz. The longest interrupt latency for a high priority interrupt results when a pending interrupt is generated during a low priority interrupt RETI, followed by a multiply instruction. This results in a maximum interrupt latency of 16.25 instruction cycles, 4 μs with a clock of 4.096 MHz.
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Preliminary Technical Data WATCHDOG TIMER
The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADE7566/ADE7569 enter an erroneous state, possibly due to a programming error or electrical noise. The watchdog is enabled by default with a timeout of 2 sec and creates a system reset if not cleared within 2 sec. The watchdog function can be disabled by clearing the watchdog enable bit (WDE) in the Watchdog Timer SFR (WDCON, 0xC0). The watchdog circuit generates a system reset or interrupt (WDS) if the user program fails to set the WDE bit within a predetermined amount of time (set by the PRE[3:0] bits). The watchdog timer is clocked from the 32.768 kHz external crystal connected between the CLKIN and CLKOUT pins.
ADE7566/ADE7569
The WDCON SFR can be written only by user software if the double write sequence described in Table 71 is initiated on every write access to the WDCON SFR. To prevent any code from inadvertently disabling the watchdog, a watchdog protection can be activated. This watchdog protection locks in the watchdog enable and event settings so they cannot be changed by user code. The protection is activated by clearing a watchdog protection bit in the flash memory. The watchdog protection bit is the most significant bit at Address 0x3FFA of the flash memory. When this bit is cleared, the WDIR bit is forced to 0, and the WDE bit is forced to 1. Note that the sequence for configuring the flash protection bits must be followed to modify the watchdog protection bit at Address 0x3FFA (see the Protecting the Flash section).
Table 71. Watchdog Timer SFR (WDCON, 0xC0)
Bit No. 7 to 4 Address 0xC7 to 0xC4 Mnemonic PRE[3:0] Default 7 Description Watchdog Prescaler. In normal mode, the 16-bit watchdog timer is clocked by the input clock (32.768 kHz). The PREx bits set which of the upper bits of the counter are used as the watchdog output following:
t WATCHDOG = 2 PRE ×
29 CLKIN
3
0xC3
WDIR
0
2
0xC2
WDS
0
1
0xC1
WDE
1
0
0xC0
WDWR
0
PRE[3:0] Result (Watchdog timeout) 0000 15.6 ms 0001 31.2 ms 0010 62.5 ms 0011 125 ms 0100 250 ms 0101 500 ms 0110 1 sec 0111 2 sec 1000 0, Automatic reset 1001 0, Serial download reset 1010 to 1111 Not a valid selection Watchdog Interrupt Response Bit. When cleared, the watchdog generates a system reset when the watchdog time out period has expired. When set, the watchdog generates a interrupt when the watchdog time out period has expired. Watchdog Status Bit. This bit is set to indicate that a watchdog timeout has occurred. It is cleared by writing a 0 or by an external hardware reset. A watchdog reset will not clear WDS; therefore, it can be used to distinguish between a watchdog reset and a hardware reset from the RESET pin. Watchdog Enable Bit. When set, this bit enables the watchdog and clears its counter. The watchdog counter is subsequently cleared again whenever WDE is set. If the watchdog is not cleared within its selected timeout period, it generates a system reset or watchdog interrupt, depending on the WDIR bit. Watchdog Write Enable Bit. See the Writing to the Watchdog Timer SFR (WDCON, 0xC0) section.
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ADE7566/ADE7569
Writing to the Watchdog Timer SFR (WDCON, 0xC0)
Preliminary Technical Data
Writing data to the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the following instruction must be a write instruction to the WDCON SFR.
Disable Watch dog CLR EA SETB WDWR CLR WDE SETB EA
This sequence is necessary so that the WDCON SFR is protected from code execution upsets that might unintentionally modify this SFR. Interrupts should be disabled during this operation due to the consecutive instruction cycles.
Table 72. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA)
Bit No. 7 Mnemonic WDPROT_PROTKY7 Default 1 Description This bit holds the protection for the Watchdog timer and the 7th bit of the flash protection key. When this bit is cleared, the watchdog enable and event, selected by WDE and WDIR cannot be changed by user code. The watchdog configuration is then fixed to WDIR=0 and WDE=1. The watchdog timeout in PRE[3:0] can still be modified by user code. The value of this bit is also used to set the Flash protection key. If this bit is cleared to protect the watchdog, then the default value for the Flash protection key is 0x7F instead of 0xFF (see the Protecting the Flash section for more information on how to clear this bit). These bits hold the flash protection key. The content of this Flash address is compared to the Flash Protection Key SFR (PROTKY, 0xBB) when the protection is being set or changed. If the two values match, the new protection is written to the Flash addresses 0x3FFF to 0x3FFB. see the Protecting the Flash section for more information on how to configure these bits.
7 to 0
PROTKY[7:0]
0xFF
Watchdog Timer Interrupt
If the watchdog timer is not cleared within the watchdog timeout period, a system reset occurs unless the watchdog timer interrupt is enabled. The watchdog timer interrupt enable bit (WDIR) is located in the Watchdog Timer SFR (WDCON, 0xC0). Enabling the WDIR bit allows the program to examine the stack or other variables that may have led the program to execute inappropriate code. The watchdog timer interrupt also allows the watchdog to be used as a long interval timer.
Note that WDIR is automatically configured as a high priority interrupt. This interrupt cannot be disabled by the EA bit in the IE register. Even if all of the other interrupts are disabled, the watchdog is kept active to watch over the program.
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Preliminary Technical Data LCD DRIVER
Using shared pins, the LCD module is capable of directly driving an LCD panel of 17 × 4 segments without comprising any ADE7566/ADE7569 functions. It is capable of driving LCDs with 2×, 3×, and 4× multiplexing. The LCD waveform voltages generated through internal charge pump circuitry support up to 5 V LCDs. An external resistor ladder for LCD waveform voltage generation is also supported. Each ADE7566/ADE7569 has an embedded LCD control circuit, driver, and power supply circuit. The LCD module is functional in all operating modes (see the Operating Modes section).
ADE7566/ADE7569
LCD REGISTERS
There are six LCD control registers that configure the driver for the specific type of LCD in the end system and set up the user display preferences. The LCD Configuration SFR (LCDCON, 0x95), LCD Configuration X SFR (LCDCONX, 0x9C), and LCD Configuration Y SFR (LCDCONY, 0xB1) contain general LCD driver configuration information including the LCD enable and reset, as well as the method of LCD voltage generation and multiplex level. The LCD Clock SFR (LCDCLK, 0x96) configures timing settings for LCD frame rate and blink rate. LCD pins are configured for LCD functionality in the LCD Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR (LCDSEGE2, 0xED).
Table 73. LCD Driver SFRs
SFR Address 0x95 0x96 0x97 0x9C 0xAC R/W R/W R/W R/W R/W R/W Name LCDCON LCDCLK LCDSEGE LCDCONX LCDPTR Description LCD Configuration SFR (see Table 74). LCD Clock (see Table 78). LCD Segment Enable (see Table 81). LCD Configuration X (see Table 75).
LCD Pointer (see
Table 82). LCD Data (see Table 83 LCD Configuration Y (see Table 77). LCD Segment Enable 2 (see Table 84).
0xAE 0xB1 0xED
R/W R/W R/W
LCDDAT LCDCONY LCDSEGE2
Table 74. LCD Configuration SFR (LCDCON, 0x95)
Bit No. 7 6 5 4 Mnemonic LCDEN LCDRST BLINKEN LCDPSM2 Value 0 0 0 0 Description LCD Enable. If this bit is set, the LCD driver is enabled. LCD Data Registers Reset. If this bit is set, the LCD data registers are reset to zero. Blink Mode Enable Bit. If this bit is set, blink mode is enabled. The blink mode is configured by the BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96). Force LCD off when in PSM2 (Sleep Mode). LCDPSM2 Result 0 The LCD is disabled or enabled in PSM2 by LCDEN bit. 1 The LCD is disabled in PSM2 regardless of LCDEN setting. LCD Clock Selection. CLKSEL Result 0 fLCDCLK = 2048 Hz 1 fLCDCLK = 128 Hz Bias Mode. BIAS Result 0 1/2 1 1/3 LCD Multiplex Level. LMUX[1:0] Result 00 Reserved. 01 2× Multiplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as FP28. 10 3× Mulitplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as COM2. 11 4× Multiplexing. FP27/COM3 is used as COM3. FP28/COM2 is used as COM2.
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3
CLKSEL
0
2
BIAS
0
1 to 0
LMUX[1:0]
0
ADE7566/ADE7569
Table 75. LCD Configuration X SFR (LCDCONX, 0x9C)
Bit No. 7 6 Mnemonic Reserved EXTRES Default 0 0
Preliminary Technical Data
Description Reserved. External Resistor Ladder Selection Bit. EXTRES Result 0 External resistor ladder is disabled. Charge pump is enabled. 1 External resistor ladder is enabled. Charge pump is disabled. Bias Level Selection Bits. See Table 76.
5 to 0
BIASLVL[5:0]
0
Table 76. LCD Bias Voltage When Contrast Control Is Enabled
BIASLVL[5] 0 1 VA ( V) VB V B = VA V B = VA 1/2 Bias VC V C = 2 x VA V C = 2 x VA VB V B = 2 x VA V B = 2 x VA 1/3 Bias VC V C = 3 x VA V C = 3 x VA
VREF ×
BLVL[4:0 ] 31
⎛ BLVL[4:0 ] ⎞ VREF × ⎜1 + ⎟ 31 ⎠ ⎝
Table 77. LCD Configuration Y SFR (LCDCONY, 0xB1)
Bit No. 7 6 5 to 2 1 0 Mnemonic Reserved INV_LVL Reserved UPDATEOVER REFRESH Default 0 0 0 0 0 Description This bit should be kept cleared for proper operation. Frame Inversion Mode Enable Bit. If this bit is set, frames are inverted every other frame. If this bit is cleared, frames are not inverted. These bits should be kept cleared for proper operation. Update Finished Flag Bit. This bit is updated by LCD driver. When set, this bit indicates that the LCD memory has been updated and a new frame has begun. Refresh LCD Data Memory Bit. This bit should be set by user. When set, the LCD driver does not use the data in the LCD data registers to update display. The LCD data registers can be updated by the 8052. When cleared, the LCD driver uses the data in the LCD data registers to update display at the next frame.
Table 78. LCD Clock SFR (LCDCLK, 0x96)
Bit No. 7 to 6 Mnemonic BLKMOD[1:0] Default 0 Description Blink Mode Clock Source Configuration Bits. BLKMOD[1:0] Result 00 The blink rate is controlled by software. The display is off. 01 The blink rate is controlled by software. The display is on. 10 The blink rate is 2 Hz 11 The blink rate is set by BLKFREQ[1:0] Blink Rate Configuration Bits. These bits control the LCD blink rate if BLKMOD[1:0] = 11 BLKFREQ[1:0] Result (Blink Rate) 00 1 Hz 01 1/2 Hz 10 1/3 Hz 11 1/4 Hz LCD Frame Rate Selection Bits. See Table 79 and Table 80.
5 to 4
BLKFREQ[1:0]
0
3 to 0
FD[3:0]
0
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Preliminary Technical Data
Table 79. LCD Frame Rate Selection for fLCDCLK = 2048 Hz (LCDCON[3]=0)
FD3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
1
ADE7566/ADE7569
3× Multiplexing fLCD (Hz) Frame Rate (Hz) 341.3 170.71 341.3 113.81 256 85.3 204.8 68.3 170.7 56.9 146.3 48.8 128 42.7 113.8 37.9 102.4 34.1 93.1 31 85.3 28.4 78.8 26.3 73.1 24.4 68.3 22.8 64 21.3 32 10.7 4× Multiplexing fLCD (Hz) Frame Rate (Hz) 512 1281 341.3 85.3 256 64 204.8 51.2 170.7 42.7 146.3 36.6 128 32 113.8 28.5 102.4 25.6 93.1 23.25 85.3 21.35 78.8 19.7 73.1 18.3 68.3 17.05 64 16 32 8
FD2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
FD1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
FD0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
2× Multiplexing fLCD (Hz) Frame Rate (Hz) 256 128 1 170.7 85.3 128 64 102.4 51.2 85.3 42.7 73.1 36.6 64 32 56.9 28.5 51.2 25.6 46.5 23.25 42.7 21.35 39.4 19.7 36.6 18.3 34.1 17.05 32 16 16 8
Not within the range of typical LCD frame rates.
Table 80. LCD Frame Rate Selection for fLCDCLK = 128 Hz (LCDCON[3]=1)
FD3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 FD2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 FD1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 FD0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 2× Multiplexing fLCD (Hz) Frame Rate (Hz) 32 16 1 21.3 10.6 16 8 16 8 16 8 16 8 16 8 16 8 16 8 16 8 16 8 16 8 16 8 16 8 128 64 64 32 3× Multiplexing fLCD (Hz) Frame Rate (Hz) 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 128 42.7 64 21.3 4× Multiplexing fLCD (Hz) Frame Rate (Hz) 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 128 32 64 16
Table 81. LCD Segment Enable SFR (LCDSEGE, 0x97)
Bit No. 7 6 5 4 3 2 1 to 0 Mnemonic FP25EN FP24EN FP23EN FP22EN FP21EN FP20EN Reserved Default 0 0 0 0 0 0 0 Description FP25 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. FP24 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. FP23 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. FP22 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. FP21 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. FP20 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. These bits should be left at 0 for proper operation
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ADE7566/ADE7569
Table 82. LCD Pointer SFR (LCDPTR, 0xAC)
Bit No. 7 6 5 to 0 Mnemonic W/R RESERVED ADDRESS Default 0 0 0
Preliminary Technical Data
Description Read or Write LCD Bit. If this bit is set (1), the data in LCDDAT is written to the address indicated by the LCDPTR[5:0] bits. Reserved. LCD Memory Address (see Table 85).
Table 83. LCD Data SFR (LCDDAT, 0xAE)
Bit No. 7 to 0 Mnemonic LCDDATA Default 0 Description Data to be written into or read out of the LCD Memory SFRs.
Table 84. LCD Segment Enable 2 SFR (LCDSEGE2, 0xED)
Bit No. 7 to 4 3 2 1 0
1
Mnemonic RESERVED FP19EN FP18EN FP17EN FP16EN
Default 0 0 0 0 0
Description Reserved. FP19 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. FP18 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. FP17 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function. FP16 Function Select Bit. 0 = General-Purpose I/O, 1 = LCD function.
Not within the range of typical LCD frame rates.
LCD SETUP
The LCD Configuration SFR (LCDCON, 0x95) configures the LCD module to drive the type of LCD in the user end system. The BIAS and LMUX[1:0] bits in this SFR should be set according to the LCD specifications. The COM2/FP28 and COM3/FP27 pins default to LCD segment lines. Selecting the 3× multiplex level in the LCD Configuration SFR (LCDCON, 0x95) by setting LMUX[1:0] to 2d changes the FP28 pin functionality to COM2. The 4× multiplex level selection, LMUX[1:0] = 3d, changes the FP28 pin functionality to COM2 and the FP27 pin functionality to COM3. LCD segments FP0 to FP15 and FP26 are enabled by default. Additional pins are selected for LCD functionality in the LCD Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR (LCDSEGE2, 0xED) where there are individual enable bits for segment pins FP16 to FP25. The LCD pins do not have to be enabled sequentially. For example, if the alternate function of FP23, the Timer 2 input, is required, any of the other shared pins, FP16 to FP25, can be enabled instead. The Display Element Control section contains details about setting up the LCD data memory to turn individual LCD segments on and off. Setting the LCDRST bit in the LCD Configuration SFR (LCDCON, 0x95) resets the LCD data memory to its default (0). A power-on reset also clears the LCD data memory.
LCD TIMING AND WAVEFORMS
An LCD segment acts like a capacitor that is charged and discharged at a certain rate. This rate, the refresh rate, determines the visual characteristics of the LCD. A slow refresh rate results in the LCD blinking on and off in between refreshes. A fast refresh rate presents a screen that appears to be continuously lit up. In addition, a faster refresh rate consumes more power. The frame rate, or refresh rate, for the LCD module is derived from the LCD clock, fLCDCLK. The LCD clock is selected as 2048 Hz or 128 Hz by the CLKSEL bit in the LCD Configuration SFR (LCDCON, 0x95). The minimum refresh rate needed for the LCD to appear solid (without blinking) is independent of the multiplex level. The LCD waveform frequency, fLCD, is the frequency at which the LCD switches which common line is active. Thus, the LCD waveform frequency depends heavily on the multiplex level. The frame rate and LCD waveform frequency are set by fLCDCLK, the multiplex level, and the FD[3:0] frame rate selection bits in the LCD Clock SFR (LCDCLK, 0x96). The LCD module provides 16 different frame rates for fLCDCLK = 2048 Hz, ranging from 8 Hz to 128 Hz for an LCD with 4× multiplexing. Fewer options are available with fLCDCLK = 128 Hz, ranging from 8 Hz to 32 Hz for a 4× multiplexed LCD. The 128 Hz clock is beneficial for battery operation because it consumes less power than the 2048 Hz clock. The frame rate is set by the FD[3:0] bits in the LCD Clock SFR (LCDCLK, 0x96); see Table 79 and Table 80. The LCD waveform is inverted at twice the LCD waveform frequency, fLCD. This way, each frame has an average DC offset of zero. ADC offset degrades the lifetime and performance of the LCD.
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Preliminary Technical Data
BLINK MODE
Blink mode is enabled by setting the BLINKEN bit in the LCD Configuration SFR (LCDCON, 0x95). This mode is used to alternate between the LCD on state and LCD off state so that the LCD screen appears to blink. There are two blinking modes: a software controlled blink mode and an automatic blink mode.
ADE7566/ADE7569
selects the LCD data byte to be accessed and initiates a read or write operation (see Table 82).
Writing to LCD Data Registers
To update the LCD data memory, first set the LSB of the LCD Configuration Y SFR (LCDCONY, 0xB1) to freeze the data being displayed on the LCD while updating it. Then, move the data to the LCD Data SFR (LCDDAT, 0xAE) prior to accessing the LCD Pointer SFR (LCDPTR, 0xAC). When the MSB of the LCD Pointer SFR (LCDPTR, 0xAC) is set, the content of the LCD Data SFR (LCDDAT, 0xAE) is transferred to the internal LCD data memory designated by the address in the LCD Pointer SFR (LCDPTR, 0xAC). Clear the LSB of the LCD Configuration Y SFR (LCDCONY, 0xB1) when all of the data memory has been updated to allow the use of the new LCD setup for display. To update the segments attached to the FP10 and FP11 pins, use the following sample 8052 code:
ORL LCDCONY,#01h the data MOV MOV ANL LCDDATA,#FFh LCDPTR,#80h OR 05h LCDCONY,#0FEh ;update finished ;start updating
Software Controlled Blink Mode
The LCD blink rate can be controlled by user code with the BLKMOD[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96) by toggling the bits to turn the display on and off at a rate determined by the MCU code.
Automatic Blink Mode
There are five blink rates available if the RTC peripheral is enabled by setting the RTCEN bit in the RTC Configuration SFR (TIMECON, 0xA1). These blink rates are selected by the BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96); see Table 78.
DISPLAY ELEMENT CONTROL
A bank of 15 bytes of data memory located in the LCD module controls the on or off state of each LCD segment. The LCD data memory is stored in Address 0 through Address 14 in the LCD module. Each byte configures the on and off states of two segment lines. The LSBs store the state of the even numbered segment lines, and the MSBs store the state of the odd numbered segment lines. For example, LCD Data Address 0 refers to segment lines one and zero (see Table 85). Note that the LCD data memory is maintained in PSM2 operating mode. The LCD data memory is accessed indirectly through the LCD Pointer SFR (LCDPTR, 0xAC)and LCD Data SFR (LCDDAT, 0xAE). Moving a value to the LCD Pointer SFR (LCDPTR, 0xAC)
Reading LCD Data Registers
When the MSB of the LCD Pointer SFR (LCDPTR, 0xAC) is cleared, the content of the LCD data memory address designated by LCDPTR is transferred to the LCD Data SFR (LCDDAT, 0xAE). Sample 8052 code to read the contents of LCD Data Memory Address 0x07, which holds the on and off state of the segments attached to FP14 and FP15, is shown below.
MOV MOV LCDPTR,#NOT 80h AND 07h R1, LCDDATA
Table 85. LCD Data Memory Accessed Indirectly Through LCD Pointer SFR (LCDPTR, 0xAC) and LCD Data SFR (LCDDAT, 0xAE) 1, 2
LCD Memory Address 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
1 2
COM3 FP27 FP25 FP23 FP21 FP19 FP17 FP15 FP13 FP11 FP9 FP7 FP5 FP3 FP1
COM2 FP27 FP25 FP23 FP21 FP19 FP17 FP15 FP13 FP11 FP9 FP7 FP5 FP3 FP1
COM1 FP27 FP25 FP23 FP21 FP19 FP17 FP15 FP13 FP11 FP9 FP7 FP5 FP3 FP1
COM0 FP27 FP25 FP23 FP21 FP19 FP17 FP15 FP13 FP11 FP9 FP7 FP5 FP3 FP1
COM3 FP28 FP26 FP24 FP22 FP20 FP18 FP16 FP14 FP12 FP10 FP8 FP6 FP4 FP2 FP0
COM2 FP28 FP26 FP24 FP22 FP20 FP18 FP16 FP14 FP12 FP10 FP8 FP6 FP4 FP2 FP0
COM1 FP28 FP26 FP24 FP22 FP20 FP18 FP16 FP14 FP12 FP10 FP8 FP6 FP4 FP2 FP0
COM0 FP28 FP26 FP24 FP22 FP20 FP18 FP16 FP14 FP12 FP10 FP8 FP6 FP4 FP2 FP0
COM# designates the common lines. FP# designates the segment lines. Rev. PrA | Page 91 of 136
ADE7566/ADE7569
VOLTAGE GENERATION
The ADE7566/ADE7569 provide two ways to generate the LCD waveform voltage levels. The on-chip charge pump option can generate 5 V. This makes it possible to use 5 V LCDs with the 3.3 V ADE7566/ADE7569. There is also an option to use an external resistor ladder with a 3.3 V LCD. The EXTRES bit in the LCD Configuration X SFR (LCDCONX, 0x9C) selects the resistor ladder or charge pump option. When selecting how to generate the LCD waveform voltages, the following should be considered:
• •
Preliminary Technical Data
cleared by default for charge pump voltage generation, but can be set to enable an external resistor ladder.
Charge Pump
Voltage generation through the charge pump requires external capacitors to store charge. The external connections to LCDVA, LCDVB, and LCDVC, as well as LCDVP1 and LCDVP2, are shown in Figure 76.
LCDVC CHARGE PUMP AND LCD WAVEFORM CIRCUITRY LCDVB LCDVA LCDVP1 LCDVP2 100nF 470nF
06353-065
06353-066
470nF 470nF
Lifetime performance power consumption Contrast control
Lifetime Performance Power Consumption
In most LCDs, a high amount of current is required when the LCD waveforms change state. The external resistor ladder option draws a constant amount of current, whereas the charge pump circuitry allows dynamic current consumption. If the LCD module is used with the internal charge pump option when the display is disabled, the voltage generation is disabled, so that no power is consumed by the LCD function. This feature results in significant power savings if the display is turned off during battery operation.
Figure 76. External Circuitry for Charge Pump Option
External Resistor Ladder
To enable the external resistor ladder option, set the EXTRES bit in the LCD Configuration X SFR (LCDCONX, 0x9C). When EXTRES = 1, the LCD waveform voltages are supplied by the external resistor ladder. Because the LCD voltages are not being generated on-chip, the LCD bias compensation implemented to maintain contrast over temperature and supply is not possible. The external circuitry needed for the resistor ladder option is shown in Figure 77. The resistors required should be in the range of 10 kΩ to 100 kΩ and based on the current required by the LCD being used.
LCDVC LCD WAVEFORM CIRCUITRY LCDVB LCDVA LCDVP1 LCDVP2
Contrast Control
The electrical characteristics of the liquid in the LCD change over temperature. This requires adjustments in the LCD waveform voltages to ensure a readable display. An added benefit of the internal charge pump voltage generation is a configurable bias voltage that can be compensated over temperature and supply to maintain contrast on the LCD. These compensations can be performed based on the ADE7566/ADE7569 temperature and supply voltage measurements (see the Temperature, Battery, and Supply Voltage Measurements section). This dynamic contrast control is not easily implemented with external resistor ladder voltage generation. The LCD bias voltage sets the contrast of the display when the charge pump provides the LCD waveform voltages. The ADE7566/ ADE7569 provide 64 bias levels selected by the BIASLVL bits in the LCD Configuration X SFR (LCDCONX, 0x9C). The voltage level on LCDVA, LCDVB and LCDVC depend on the internal voltage reference value (VREF), BIASLVL[5:0] selection, and the biasing selected as described in Table 76.
Figure 77. External Circuitry for External Resistor Ladder Option
LCD FUNCTION IN PSM2
The LCDPSM2 and LCDEN bits in the LCD Configuration SFR (LCDCON, 0x95) control LCD functionality in the PSM2 operating mode (see Table 86).
Table 86.
LCDPSM2 0 0 1 LCDEN 0 1 X Result The display is off in PSM2. The display is on in PSM2. The display is off in PSM2.
Lifetime Performance
DC offset on a segment degrades its performance over time. The voltages generated through the internal charge pump switch faster than those generated by the external resistor ladder, reducing the likelihood of a dc voltage being applied to a segment and increasing the lifetime of the LCD.
Note that the LCD configuration and data memory is retained when the display is turned off.
Example LCD Setup
An example to set up the LCD peripheral for a specific LCD is described in this section with the following parameters:
• • •
LCD EXTERNAL CIRCUITRY
The voltage generation selection is made by bit EXTRES in the LCD Configuration X SFR (LCDCONX, 0x9C). This bit is
Type of LCD: 5 V, 4× multiplexed with 1/3 bias, 96 segment Voltage generation: internal charge pump Refresh rate: 64 Hz
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Preliminary Technical Data
A 96 segment LCD with 4× multiplexing requires 96/4 = 24 segment lines. Sixteen pins, FP0 to FP15, are automatically dedicated for use as LCD segments. Eight more pins must be chosen for the LCD function. Because the LCD has 4× multiplexing, all four common lines are used. As a result, COM2/FP28 and COM3/FP27 cannot be utilized as segment lines. Based on the alternate functions of the pins used for FP16 through FP25, FP16 to F23 are chosen for the seven remaining segment lines. The LCD is setup with the following 8052 code:
; setup LCD pins to have LCD functionality MOV MOV LCDSEG, # FP20EN+FP21EN+FP22EN+FP23EN LCDSEGX, #FP16EN+FP17EN+FP18EN+FP19EN
ADE7566/ADE7569
These pins are enabled for LCD functionality in the LCD Segment Enable SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). To determine contrast setting for this 5 V LCD, Table 76 shows the BIASLVL[5:0] setting that corresponds to a VC of 5 V in 1/3 bias mode. The nominal bias level setting for this LCD is BIASLVL[5:0] = [111111].
; setup LCDCON for fLCDCLK=2048Hz, 1/3 bias and 4x multiplexing MOV MOV MOV LCDCON, #BIAS+LMUX1+LMUX0 LCDCONX, #BIASLVL5+BIASLVL4+BIASLVL3+ BIASLVL2+BIASLVL1+BIASLVL0 LCDCLK, #FD3+FD2+FD1+FD0 ; setup LCDCONX for charge pump and BIASLVL[1110111] ; set up refresh rate for 64Hz with fLCDCLK=2048Hz ; set up LCD data registers with data to be displayed using ; LCDPTR and LCDDATA registers ; turn all segments on FP25 ON and FP26 OFF ORL MOV MOV ANL ORL LCDCONY,#01h ; start data memory refresh LCDDAT, #F0H LCDPTR, #80h OR 0DH LCDCONY,#0FEh ; end of data memory refresh LCDCON,#LCDEN ; enable LCD
To setup the same 3.3 V LCD for use with an external resistor ladder:
; setup LCD pins to have LCD functionality MOV MOV LCDSEG, #FP20EN+FP21EN+FP22EN+FP23EN LCDSEGX, #FP16EN+FP17EN+FP18EN+FP19EN
; setup LCDCON for fLCDCLK=2048Hz, 1/3 bias and 4x multiplexing MOV MOV MOV LCDCON, #BIAS+LMUX1+LMUX0 LCDCONX, #EXTRES LCDCLK, #FD3+FD2+FD1+FD0 ; setup LCDCONX for external resistor ladder ; set up refresh rate for 64Hz with fLCDCLK=2048Hz ; set up LCD data registers with data to be displayed using ; LCDPTR and LCDDATA registers ; turn all segments on FP25 ON and FP26 OFF ORL MOV MOV ANL ORL LCDCONY,#01h ; start data memory refresh LCDDAT, #F0H LCDPTR, #80h OR 0DH LCDCONY,#0FEh ; end of data memory refresh LCDCON,#LCDEN ; enable LCD
Rev. PrA | Page 93 of 136
ADE7566/ADE7569 FLASH MEMORY
OVERVIEW
Flash memory is a type of nonvolatile memory that is in-circuit programmable. The default state of a byte of flash memory is 0xFF (erased). When a byte of flash memory is programmed, the required bits change from 1 to 0. The flash memory must be erased to turn the 0s back to 1s. However, a byte of flash memory cannot be erased individually. The entire segment, or page, of flash memory that contains the byte must be erased. The ADE7566/ADE7569 provide 16 kB of flash program/ information memory. This memory is segmented into 32 pages of 512 bytes each. Therefore, to reprogram 1 byte of flash memory, the 511 bytes in that page must be erased. The flash memory can be erased by page or all at once in a mass erase. There is a command to verify that a flash write operation has completed successfully. The ADE7566/ADE7569 flash memory controller also offers configurable flash memory protection. The 16 kB of flash memory are provided on-chip to facilitate code execution without any external discrete ROM device requirements. The program memory can be programmed incircuit, using the serial download mode provided or using conventional third party memory programmers.
Preliminary Technical Data
In reliability qualification, every byte in both the program and data Flash/EE memory is cycled from 0x00 to 0xFF until a first fail is recorded, signifying the endurance limit of the on-chip Flash/EE memory. As indicated in the Specifications section, the ADE7566/ADE7569 flash memory endurance qualification has been carried out in accordance with JEDEC Retention Lifetime Specification (A117) over the industrial temperature range of −40°C, +25°C, and +85°C. The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with a minimum endurance figure of 20,000 cycles of operation at 25°C. Retention is the ability of the flash memory to retain its programmed data over time. Again, the part have been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 55°C). As part of this qualification procedure, the flash memory is cycled to its specified endurance limit before data retention is characterized. This means that the flash memory is guaranteed to retain its data for its full specified retention lifetime every time the flash memory is reprogrammed. It should also be noted that retention lifetime, based on an activation energy of 0.6 eV, derates with TJ as shown in Figure 78.
300
Flash/EE Memory Reliability
The flash memory arrays on the ADE7566/ADE7569 are fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. 1. 2. 3. 4. Initial page erase sequence. Read/verify sequence. Byte program sequence. Second read/verify sequence.
250
RETENTION (Years)
200
150
ANALOG DEVICES SPECIFICATION 100 YEARS MIN. AT TJ = 55°C
100
50
50
60 70 90 80 TJ JUNCTION TEMPERATURE (°C)
100
110
Figure 78. Flash/EE Memory Data Retention
Rev. PrA | Page 94 of 136
06353-067
0 40
Preliminary Technical Data
FLASH MEMORY ORGANIZATION
The 16 kB of flash memory provided by the ADE7566/ADE7569 are segmented into 32 pages of 512 bytes each. It is up to the user to decide which flash memory to allocate for data memory. It is recommended that each page be dedicated solely to program memory or data memory. Doing so prevents the program counter from being loaded with data memory instead of an opcode from the program memory. It also prevents program memory used to update a byte of data memory from being erased.
0x3FFF 0x3E00 0x3DFF 0x3C00 0x3BFF 0x3A00 0x39FF 0x3800 0x37FF 0x3600 0x35FF 0x3400 0x33FF 0x3200 0x31FF 0x3000 0x2FFF 0x2E00 0x2DFF 0x2C00 0x2BFF 0x2A00 0x29FF 0x2800 0x27FF 0x2600 0x25FF 0x2400 0x23FF 0x2200 0x21FF 0x2000 PAGE 31 PAGE 30 PAGE 29 PAGE 28 PAGE 27 PAGE 26 PAGE 25 PAGE 24 PAGE 23 PAGE 22 PAGE 21 PAGE 20 PAGE 19 PAGE 18 PAGE 17 PAGE 16 READ PROTECT BIT 4 READ PROTECT BIT 5 READ PROTECT BIT 6 READ PROTECT BIT 7 0x1FFF 0x1E00 0x1DFF 0x1C00 0x1BFF 0x1A00 0x19FF 0x1800 0x17FF 0x1600 0x15FF 0x1400 0x13FF 0x1200 0x11FF 0x1000 0x0FFF 0x0E00 0x0DFF 0x0C00 0x0BFF 0x0A00 0x09FF 0x0800 0x07FF 0x0600 0x05FF 0x0400 0x03FF 0x0200 0x01FF 0x0000 PAGE 15 PAGE 14 PAGE 13 PAGE 12 PAGE 11 PAGE 10 PAGE 9 PAGE 8 PAGE 7 PAGE 6 PAGE 5 PAGE 4 PAGE 3 PAGE 2 PAGE 1 PAGE 0
06353-068
ADE7566/ADE7569
Therefore, Page 0 through Page 30 are for general program and data memory use. It is recommended that Page 31 be used for constants or code that do not need to be updated. Note that the last 6 bytes of Page 31 are reserved for protecting the flash memory.
USING THE FLASH MEMORY
The 16 kB of flash memory are configured as 32 pages, each of 512 bytes. As with the other ADE7566/ADE7569 peripherals, the interface to this memory space is via a group of registers mapped in the SFR space (see Table 87). A data register, EDATA, holds the byte of data to be accessed. The byte of flash memory is addressed via the EADRH and EADRL registers. Finally, ECON is an 8-bit control register that can be written to with one of seven flash memory access commands to trigger various read, write, erase, and verify functions.
Table 87. The Flash SFRs
READ PROTECT BIT 3
READ PROTECT BIT 2
SFR ECON FLSHKY PROTKY EDATA PROTB0 PROTB1 PROTR
Address 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC6 0xC7
Default 0x00 0xFF 0xFF 0x00 0xFF 0xFF 0xFF 0x00 0x00
Bit Addressable No No No No No No No No No
READ PROTECT BIT 1
READ PROTECT BIT 0
EADRL EADRH
Description Flash Control. Flash Key. Flash Protection Key. Flash Data. Flash W/E Protection 0. Flash W/E Protection 1. Flash Read Protection. Flash Low Address. Flash High Address.
CONTAINS PROTECTION SETTINGS.
Figure 79. Flash Memory Organization
Figure 80 demonstrates the steps required for access to the flash memory.
ECON COMMAND ADDRESS EADRH EADRL FLASH PROTECTION KEY FLSHKY ADDRESS DECODER PROTECTION DECODER ACCESS ALLOWED? TRUE: ACCESS ALLOWED ECON = 0
06353-069
The flash memory can be protected from read or write/erase (W/E) access. The protection is implemented in part of the last page of the flash memory, Page 31. Four of the bytes from this page are used to set up write/erase protection for each page. Another byte is used for configuring read protection of the flash memory. The read protection is selected for groups of four pages. Finally, one byte is used to store the key required for modifying the protection scheme. The last page of flash memory must be write/erase protected for any flash protection to be active. The implication of write/erase protecting the last page is that the content of the 506 bytes in this page that are available to the user must not change. Thus, if code protection is enabled, it is recommended to use this last page for program memory only (if the firmware does not need to be updated in the field). If the firmware must be protected and can be updated at a future date, the last page should be used only for constants utilized by the program code that do not need to be read during emulation or debug.
FLSHKY = 0 × 3B?
FALSE: ACCESS DENIED ECON = 1
Figure 80. Flash Memory Read/Write/Erase Protection Block Diagram
ECON—Flash/EE Memory Control SFR
Programming flash memory is done through the Flash Control SFR (ECON, 0xB9). This SFR allows the user to read, write, erase, or verify the 16 kB of flash memory. As a method of security, a key must be written to the FLSHKY register to initiate any user access to the flash memory. Upon completion of the flash memory operation, the FLSHKY register is reset so that it must be written to prior to another flash memory operation. Requiring the key to be set before an access to the flash memory decreases the likelihood of user code or data being overwritten by a program inappropriately modified during its execution.
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ADE7566/ADE7569
The program counter (PC) is held on the instruction where the ECON register is written to until the flash memory controller is done performing the requested operation. Then, the PC increments to continue with the next instruction.
Preliminary Technical Data
Any interrupt requests that occur while the flash controller is performing an operation are not handled until the flash operation is complete. All peripherals, such as timers and counters, continue to operate as configured throughout the flash memory access.
Table 88. Flash Control SFR (ECON, 0xB9)
Bit No. 7 to 0 Mnemonic ECON Value 1 2 3 4 5 8 Description Write Byte. The value in EDATA is written to the flash memory at the page address given by EADRH and EADRL. Note that the byte being addressed must be pre-erased. Erase Page. A 512-byte page of flash memory address is erased. The page is selected by the address in EADRH/EADRL. Any address in the page can be written to EADRH/EADRL to select it for erasure. Erase All. All 16 kB of the flash memory are erased. Note that this command is used during serial and parallel download modes but should not be executed by user code. Read Byte. The byte in the flash memory addressed by EADRH/EADRL is read into EDATA. Erase Page and Write Byte. The page that holds the byte addressed by EADRH/EADRL is erased. Data in EDATA is then written to the byte of flash memory addressed by EADRH/EADRL. Protect Code (see the Protecting the Flash section).
Table 89. Flash Key SFR (FLSHKY, 0xBA)
Bit No. 7 to 0 Mnemonic FLSHKY Default 0xFF Description The content of this SFR is compared to the flash key, 0x3B. If the two values match, the next ECON operation is allowed (see the Protecting the Flash section).
Table 90. Flash Protection Key SFR (PROTKY, 0xBB)
Bit No. 7 to 0 Mnemonic PROTKY Default 0xFF Description The content of this SFR is compared to the flash memory location at address 0x3FFA. If the two values match, the update of the write/erase and read protection set up is allowed (see the Protecting the Flash section). If the protection key in the flash is 0xFF, the PROTKY SFR value is not used for comparison. This SFR is also used to write the protection key in the flash. This is done by writing the desired value in PROTKY and by writing 0x08 in the ECON SFR. This operation can only be done once.
Table 91. Flash Data SFR (EDATA, 0xBC)
Bit No. 7 to 0 Mnemonic EDATA Default 0 Description Flash Pointer Data.
Table 92. Flash Write/Erase Protection 0 SFR (PROTB0, 0xBD)
Bit No. 7 to 0 Mnemonic PROTB0 Default 0xFF Description This SFR is used to write the write/erase protection bits for Page 0 to Page 7 of the flash memory (see the Protecting the Flash section). Clearing the bits enables the protection. PROTB0.7 PROTB0.6 PROTB0.5 PROTB0.4 PROTB0.3 PROTB0.2 PROTB0.1 PROTB0.0 Page 7 Page 6 Page 5 Page 4 Page 3 Page 2 Page 1 Page 0
Table 93. Flash Write/Erase Protection 1 SFR (PROTB1, 0xBE)
Bit No. 7 to 0 Mnemonic PROTB1 Default 0xFF Description This SFR is used to write the write/erase protection bits for Page 8 to Page15 of the flash memory (see the Protecting the Flash section). Clearing the bits enables the protection. PROTB1.7 PROTB1.6 PROTB1.5 PROTB1.4 PROTB1.3 PROTB1.2 PROTB1.1 PROTB1.0 Page 15 Page 14 Page 13 Page 12 Page 11 Page 10 Page 9 Page 8
Rev. PrA | Page 96 of 136
Preliminary Technical Data
Table 94. Flash Read Protection SFR (PROTR, 0xBF)
Bit No. 7 to 0 Mnemonic PROTR Default 0xFF
ADE7566/ADE7569
Description This SFR is used to write the read protection bits for Page 0 to Page 31 of the flash memory (see the Protecting the Flash section). Clearing the bits enables the protection. PROTR.7 PROTR.6 PROTR.5 PROTR.4 PROTR.3 PROTR.2 PROTR.1 Page 28 to Page 24 to Page 20 to Page 16 to Page 12 to Page 8 to Page 4 to Page 31 Page 27 Page 23 Page 19 Page 15 Page 11 Page 7
PROTR.0 Page 0 to Page 3
Table 95. Flash Low Byte Address SFR (EADRL, 0xC6)
Bit No. 7 to 0 Mnemonic EADRL Default 0 Description Flash Pointer Low Byte Address. This SFR is also used to write the write/erase protection bits for Page 16 to Page 23 of the flash memory (see the Protecting the Flash section). Clearing the bits enables the protection. EADRL.7 EADRL.6 EADRL.5 EADRL.4 EADRL.3 EADRL.2 EADRL.1 EADRL.0 Page 23 Page 22 Page 21 Page 20 Page 19 Page 18 Page 17 Page 16
Table 96. Flash High Byte Address SFR (EADRH, 0xC7)
Bit No. 7 to 0 Mnemonic EADRH Default 0 Description Flash Pointer High Byte Address. This SFR is also used to write the write/erase protection bits for Page 24 to Page 31 of the flash memory (see the Protecting the Flash section). Clearing the bits enables the protection. EADRH.7 EADRH.6 EADRH.5 EADRH.4 EADRH.3 EADRH.2 EADRH.1 EADRH.0 Page 31 Page 30 Page 29 Page 28 Page 27 Page 26 Page 25 Page 24
Flash Functions
Sample 8051 code is provided in this section to demonstrate how to use the flash functions. For these examples, the byte of flash memory 0x3C00 is accessed.
Erase All
Erase all of the 16 kB flash memory.
MOV FLSHKY, #3Bh key. MOV ECON, #03H ; Write Flash security ; Erase All
Write Byte
Write 0xF3 into flash memory byte 0x3C00.
MOV EDATA, #F3h MOV EADRH, #3Ch MOV EADRL, #00h MOV FLSHKY, #3Bh key. MOV ECON, #01H ; Write Flash security ; Write Byte ; Data to be written ; Setup byte address
Read Byte
Read flash memory byte 0x3C00.
MOV EADRH, #3Ch MOV EADRL, #00h MOV FLSHKY, #3Bh key. MOV ECON, #04H ; Write Flash security ; Read Byte ; Setup byte address
Erase Page
Erase the page containing flash memory byte 0x3C00.
MOV EADRH, #3Ch byte address MOV EADRL, #00h MOV FLSHKY, #3Bh key. MOV ECON, #02H ; Write Flash security ; Erase Page ; Select page through
; Data is ready in EDATA register
Erase Page and Write Byte
Erase the page containing flash memory byte 0x3C00 and then write 0xF3 to that address. Note that the other 511 bytes in this page are erased.
MOV EDATA, #F3h MOV EADRH, #3Ch MOV EADRL, #00h MOV FLSHKY, #3Bh key. MOV ECON, #05H write byte
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; Data to be written ; Setup byte address ; Write Flash security ; Erase page and then
ADE7566/ADE7569
PROTECTING THE FLASH
Two forms of protection are offered for this flash memory: read protection and write/erase protection. The read protection ensures that any pages that are read protected are not able to be read by the end user. The write protection ensures that the flash memory cannot be erased or written over. This protects the end system from tampering and can prevent the code from being overwritten in the event of a unexpected disruption of the normal execution of the program. Write/erase protection is individually selectable for all of the 32 pages. Read protection is selected in groups of 4 pages (see Figure 79 for the groupings). The protection bits are stored in the last flash memory locations, Address 0x3FFA through Address 0x3FFF (see Figure 81); 4 bytes are reserved for write/erase protection, 1 byte is for read protection, and another byte sets the protection security key. The user must enable read and write/erase protection for the last page for the entire protection scheme to work. Note that the read protection does not prevent MOVC commands to be executed within the code. There is an additional layer of protection offered by a protection security key. The user can set up this security key so that the protection scheme cannot be changed without this key. Once the protection key has been configured, it cannot be modified. 1.
Preliminary Technical Data
The sequence for writing the protection bits is as follows: Set up the EADRH, EADRL, PROTB1, and PROTB0 registers with the write/erase protection bits. When erased, the protection bits default to 1 (like any other bit of flash memory). The default protection setting is for no protection. To enable protection, write a 0 to the bits corresponding to the pages that should be protected. Set up the PROTR register with the read protection bits. Note that every read protection bit protects four pages. To enable the read protection bit, write a 0 to the bits that should be read protected. To enable the protection key, write to the PROTKY register. If enabled, the protection key is required to modify the protection scheme. The protection key, Flash Memory Address 0x3FFA, defaults to 0xFF; if the PROTKY register is not written to, it remains 0xFF. If the protection key is written to, the PROTKY register must be written with this value every time the protection functionality is accessed. Note that once the protection key is configured, it cannot be modified. Also note that the most significant bit of Address 0x3FFA is used to enable a lock mechanism for the watchdog settings (see the Watchdog Timer section for more information). Run the protection command by writing 0x0 to the ECON register. Reset the chip to activate the new protection.
2.
3.
4. 5.
Enabling Flash Protection by Code
The protection bytes in the flash memory can be programmed using flash controller command and programming ECON to 0x08. In this case, the EADRH, EADRL, PROTB1, and PROTB0 bytes are used to store the data to be written to the 32 bits of write protection. Note that the EADRH and EADRL registers are not used as data pointers here, but to store write protection data.
EADRH 0x3FFF EADRL 0x3FFE PROTB1 0x3FFD PROTB0 0x3FFC PROTR PROTKY WP 31 WP 23 WP 15 WP 7 WP 30 WP 22 WP 14 WP 6 WP 29 WP 21 WP 13 WP 5 WP 28 WP 20 WP 12 WP 4 WP 27 WP 19 WP 11 WP 3 WP 26 WP 18 WP 10 WP 2 WP 25 WP 17 WP 9 WP 1 RP 7–4 WP 24 WP 16 WP 8 WP 0 RP 3–0
To enable read and write/erase protection for the last page only, use the following 8051 code. Writing the flash protection command to the ECON register initiates programming the protection bits in the flash. ; enable write/erase protection on the last page only
MOV EADRH, #07FH MOV EADRL, #0FFH MOV PROTB1, #FFH MOV PROTB0, #FFH
; enable read protection on the last four pages only
MOV PROTR, #07FH
RP RP RP RP RP RP 0x3FFB 31–28 27–24 23–20 19–16 15–12 11–8 WDOG 0x3FFA LOCK 0x3FF9
; set up a protection key of 0A3H. This command can be ; omitted to use the default protection key of 0xFF
MOV PROTKY, #0A3H
PROTECTION KEY
; write the flash key to the FLSHKY register to enable flash
06353-070
; access. The flash access key is not configurable.
MOV FLSHKY, #3BH
0x3E00
Figure 81. Flash Protection in Page 31
; write flash protection command to the ECON register
MOV ECON, #08H
Rev. PrA | Page 98 of 136
Preliminary Technical Data
Enabling Flash Protection by Emulator Commands
Another way to set the flash protection bytes is to use some reserved emulator commands available only in download mode. These commands write directly to the SFRs and can be used to duplicate the operation mentioned in the Enabling Flash Protection by Code section. Once these flash bytes are written, the part can exit emulation mode by a reset and the protections are effective. This method can be used in production and implemented after downloading the program. The commands used for this operation are an extension of the commands listed in the Application Note uC004: Understanding the Serial Download Protocol.
• •
ADE7566/ADE7569
Protection bits can be modified from a 1 to a 0, even after the last page has been protected. In this way, more protection can be added but none can be removed. The protection scheme is intended to protect the end system. Protection should be disabled while developing and emulating code.
Flash Memory Timing
Typical program and erase times for the flash memory are shown in Table 97.
Table 97.
Command Write Byte Erase Page Erase All Read Byte Erase Page and Write Byte Verify Byte Bytes Affected 1 byte 512 bytes 16 kB 1 bytes 512 bytes 1 byte Flash Memory Timing 30 μs 20 ms 200 ms 100 ns 21 ms 100 ns
Command with ASCII code I or 0x49 write the data into R0. Command with ASCII code F or 0x46 write R0 into the SFR address defined in the data of this command.
By omitting the protocol defined in the uC004: Understanding the Serial Download Protocol application note, the sequence to load protections are similar to the sequence presented in the Enabling Flash Protection by Code section, except that two emulator commands are necessary to replace one assembly command. For example, to write the protection value in EADRH, the two following commands need to be executed:
• •
Command I with data = value of protection byte 0x3FFF. Command F with data = 0xC7.
Following this protocol, the protection can be written to the flash using the same sequence as mentioned in the Enabling Flash Protection by Code section. When the part is reset, the protection is effective.
Note that the core microcontroller operation is idled until the requested flash memory operation is complete. In practice, this means that even though the flash operation is typically initiated with a two-machine-cycle MOV instruction to write to the Flash Control SFR (ECON, 0xB9), the next instruction is not executed until the Flash/EE operation is complete. This means that the core cannot respond to interrupt requests until the Flash/EE operation is complete, although the core peripheral functions, such as counters and timers, continue to count as configured throughout this period.
IN-CIRCUIT PROGRAMMING
Serial Downloading
The ADE7566/ADE7569 facilitate code download via the standard UART serial port. The parts enter serial download mode after a reset or a power cycle if the SDEN pin is pulled low through an external 1 kΩ resistor. When in serial download mode, the hidden embedded download kernel executes. This allows the user to download code to the full 16 kB of flash memory while the device is in-circuit in its target application hardware. Protection configured in the last page of the ADE7566/ADE7569 affects whether flash memory can be accessed in serial download mode. Read protected pages cannot be read. Write/erase protected pages cannot be written or erased. The configuration bits cannot be programmed in serial download mode.
Notes on Flash Protection
The flash protection scheme is disabled by default so that none of the pages of the flash are protected from reading or writing/ erasing. The last page must be read and write/erase protected for the protection scheme to work. To activate the protection settings, the ADE7566/ADE7569 must be reset after configuring the protection. After configuring protection on the last page and resetting the part, protections that have been enabled can only be removed by mass erasing the flash memory. The protection bits are read and erase protected by enabling read and write/erase protection on the last page, but the protection bits are never truly write protected.
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ADE7566/ADE7569 TIMERS
Each ADE7566/ADE7569 has three 16-bit timer/counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware is included on-chip to relieve the processor core of overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: THx and TLx (x = 0, 1, or 2). All three can be configured to operate either as timers or as event counters. When functioning as a timer, the TLx register is incremented every machine cycle. Thus, users can think of it as counting machine cycles. Because a machine cycle on a single-cycle core consists of one core clock period, the maximum count rate is the core clock frequency.
Table 98. Timer SFRs
SFR TCON TMOD TL0 TL1 TH0 TH1 T2CON RCAP2L RCAP2H TL2 TH2 Address 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0xC8 0xCA 0xCB 0xCC 0xCD Bit Addressable Yes No No No No No Yes No No No No
Preliminary Technical Data
When functioning as a counter, the TLx register is incremented by a 1-to-0 transition at its corresponding external input pin: T0, T1, or T2. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. Because it takes two machine cycles (two core clock periods) to recognize a 1-to-0 transition, the maximum count rate is half the core clock frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle. User configuration and control of all timer operating modes is achieved via the SFRs in Table 98.
Description Timer0 and Timer1 Control Register (see Table 100). Timer0 and Timer1 Mode Register (see Table 99). Timer0 LSB (see Table 103). Timer1 LSB (see Table 105). Timer0 MSB (see Table 102). Timer1 MSB (see Table 104). Timer2 Control Register (see Table 101). Timer2 Reload/Capture LSB (see Table 109). Timer2 Reload/Capture MSB (see Table 108). Timer2 LSB (see Table 107). Timer2 MSB (see Table 106).
TIMER SFR REGISTERS
Table 99. Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89)
Bit No. 7 6 5 to 4 Mnemonic Gate1 C/T1 T1/M1, T1/M0 Default 0 0 00 Description Timer 1 Gating Control. Set by software to enable Timer/Counter 1 only when the INT1 pin is high and the TR1 control is set. Cleared by software to enable Timer 1 whenever the TR1control bit is set. Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin). Cleared by software to select the timer operation (input from internal system clock). Timer 1 Mode Select Bits. T1/M[1:0] Result 00 TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler. 01 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler. 10 8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each time it overflows. 11 Timer/Counter 1 Stopped. Timer 0 Gating Control. Set by software to enable Timer/Counter 0 only when the INT0 pin is high and the TR0 control bit is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set. Timer 0 Timer or Counter Select Bit. Set by software to the select counter operation (input from T0 pin). Cleared by software to the select timer operation (input from internal system clock). Timer 0 Mode Select Bits. T0/M[1:0] Result 00 TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler. 01 16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler. 10 8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time it overflows. 11 TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
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3 2 1 to 0
Gate0 C/T0 T0/M1, T0/M0
0 0 00
Preliminary Technical Data
Table 100. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, 0x88)
Bit No. 7 6 5 4 3 Address 0x8F 0x8E 0x8D 0x8C 0x8B Mnemonic TF1 TR1 TF0 TR0 IE1 1 Default 0 0 0 0 0
ADE7566/ADE7569
Description Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the program counter (PC) vectors to the interrupt service routine. Timer 1 Run Control Bit. Set by the user to turn on Timer/Counter 1. Cleared by the user to turn off Timer/Counter 1. Timer 0 Overflow Flag. Set by hardware on a Timer/Counter 0 overflow. Cleared by hardware when the PC vectors to the interrupt service routine. Timer 0 Run Control Bit. Set by the user to turn on Timer/Counter 0. Cleared by the user to turn off Timer/Counter 0. External Interrupt 1 (INT1) Flag. Set by hardware by a falling edge or by a zero level applied to the external interrupt pin, INT1, depending on the state of Bit IT1. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag rather than the on-chip hardware. External Interrupt 1 (IE1) Trigger Type. Set by software to specify edge-sensitive detection, that is, 1-to-0 transition. Cleared by software to specify level-sensitive detection, that is, zero level. External Interrupt 0 (INT0) Flag. Set by hardware by a falling edge or by a zero level being applied to the external interrupt pin, INT0, depending on the state of Bit IT0. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag rather than the on-chip hardware. External Interrupt 0 (IE0) Trigger Type. Set by software to specify edge-sensitive detection, that is, 1-to-0 transition. Cleared by software to specify level-sensitive detection, that is, zero level.
2 1
0x8A 0x89
IT11 IE01
0 0
0
1
0x88
IT01
0
These bits are not used to control Timer/Counter 0 and Timer/Counter 1, but are instead used to control and monitor the external INT0 and INT1 interrupt pins.
Table 101. Timer/Counter 2 Control SFR (T2CON, 0xC8)
Bit No. 7 6 5 Address 0xCF 0xCE 0xCD Mnemonic TF2 EXF2 RCLK Default 0 0 0 Description Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when either RCLK = 1 or TCLK = 1. Cleared by user software. Timer 2 External Flag. Set by hardware when either a capture or reload is caused by a negative transition on T2EX pin and EXEN2 = 1. Cleared by user software. Receive Clock Enable Bit. Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user to enable Timer 1 overflow to be used for the receive clock. Transmit Clock Enable Bit. Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user to enable Timer 1 overflow to be used for the transmit clock. Timer 2 External Enable Flag. Set by the user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. Cleared by the user for Timer 2 to ignore events at T2EX. Timer 2 Start/Stop Control Bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2. Timer 2 Timer or Counter Function Select Bit. Set by the user to select the counter function (input from external T2 pin). Cleared by the user to select the timer function (input from onchip core clock). Timer 2 Capture/Reload Select Bit. Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1. Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow.
4
0xCC
TCLK
0
3
0xCB
EXEN2
0
2 1
0xCA 0xC9
TR2 C/T2
0 0
0
0xC8
CAP2
0
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ADE7566/ADE7569
Table 102. Timer 0 High Byte SFR (TH0, 0x8C)
Bit No. 7 to 0 Mnemonic TH0 Default 0 Description Timer 0 Data High Byte.
Preliminary Technical Data
Timer/Counter 0 and Timer/Counter 1 Operating Modes
This section describes the operating modes for Timer/Counter 0 and Timer/Counter 1. Unless otherwise noted, these modes of operation are the same for both Timer 0 and Timer 1.
Table 103. Timer 0 Low Byte SFR (TL0, 0x8A)
Bit No. 7 to 0 Mnemonic TL0 Default 0 Description Timer 0 Data High Byte.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter. Figure 82 shows Mode 0 operation. Note that the divide-by-12 prescaler is not present on the single-cycle core.
fCORE
C/T0 = 0
Table 104. Timer 1 High Byte SFR (TH1, 0x8D)
Bit No. 7 to 0 Mnemonic TH1 Default 0 Description Timer 1 Data High Byte.
Table 105. Timer 1 Low Byte SFR (TL1, 0x8B)
Bit No. 7 to 0 Mnemonic TL1 Default 0 Description Timer 1 Data High Byte.
C/T0 = 1 P0.6/T0
TL0 TH0 (5 BITS) (8 BITS)
INTERRUPT TF0
TR0
CONTROL
Table 106. Timer 2 High Byte SFR (TH2, 0xCD)
GATE
INT0
Table 107. Timer 2 Low Byte SFR (TL2, 0xCC)
Bit No. 7 to 0 Mnemonic TL2 Default 0 Description Timer 2 Data High Byte.
Figure 82. Timer/Counter 0, Mode 0
Table 108. Timer 2 Reload/Capture High Byte SFR (RACP2H, 0xCB)
Bit No. 7 to 0 Mnemonic TH2 Default 0 Description Timer 2 Reload/ Capture High Byte.
Table 109. Timer 2 Reload/Capture Low Byte SFR (RACP2L, 0xCA)
Bit No. 7 to 0 Mnemonic TL2 Default 0 Description Timer 2 Reload/ Capture Low Byte.
In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer overflow flag, TF0. TF0 can then be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1. Setting Gate0 = 1 allows the timer to be controlled by external input INT0 to facilitate pulse-width measurements. TR0 is a control bit in the Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, 0x88); the Gate bit is in Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89). The 13-bit register consists of all 8 bits of Timer 0 High Byte SFR (TH0, 0x8C) and the lower 5 bits of Timer 0 Low Byte SFR (TL0, 0x8A). The upper 3 bits of Timer 0 Low Byte SFR (TL0, 0x8A) are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers.
TIMER 0 AND TIMER 1
Timer/Counter 0 and Timer/Counter 1 Data Registers
Each timer consists of two 8-bit registers. They are Timer 0 High Byte SFR (TH0, 0x8C), Timer 0 Low Byte SFR (TL0, 0x8A), Timer 1 High Byte SFR (TH1, 0x8D) and Timer 1 Low Byte SFR (TL1, 0x8B) These can be used as independent registers or combined into a single 16-bit register, depending on the timer mode configuration (see Table 102 to Table 105).
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0 except that the Mode 1 timer register runs with all 16 bits. Mode 1 is shown in Figure 83.
fCORE
C/T0 = 0
TL0 TH0 (8 BITS) (8 BITS)
C/T0 = 1
INTERRUPT TF0
P0.6/T0 TR0
CONTROL
GATE INT 0
Figure 83. Timer/Counter 0, Mode 1
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06353-072
06353-071
Bit No. 7 to 0
Mnemonic TH2
Default 0
Description Timer 2 Data High Byte.
Preliminary Technical Data
Mode 2 (8-Bit Timer/Counter with Autoreload)
Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload as shown in Figure 84. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged.
fCORE
C/T = 0
ADE7566/ADE7569
TIMER 2
Timer/Counter 2 Data Registers
Timer/Counter 2 also has two pairs of 8-bit data registers associated with it: Timer 2 High Byte SFR (TH2, 0xCD), Timer 2 Low Byte SFR (TL2, 0xCC), Timer 2 Reload/Capture High Byte SFR (RACP2H, 0xCB), and Timer 2 Reload/Capture Low Byte SFR (RACP2L, 0xCA). These are used as both timer data registers and as timer capture/reload registers (see Table 106 to Table 109).
TL0 (8 BITS)
C/T = 1
INTERRUPT TF0
P0.6/T0
CONTROL
TR0 RELOAD TH0 (8 BITS)
Timer/Counter 2 Operating Modes
The following sections describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the Timer/Counter 2 Control SFR (T2CON, 0xC8), as shown in Table 101 and Table 110.
Table 110. T2CON Operating Modes
RCLK (or) TCLK 0 0 1 X CAP2 0 1 X X TR2 1 1 1 0 Mode 16-Bit Autoreload 16-Bit Capture Baud Rate Off
GATE INT 0
Figure 84. Timer/Counter 0, Mode 2
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. This configuration is shown in Figure 85. TL0 uses the Timer 0 control bits, C/T, Gate0 (see Table 99), TR0, TF0 (see Table 100), and INT0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Therefore, TH0 controls the Timer 1 interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or it can be used by the serial interface as a baud rate generator. In fact, Timer1 can be used in any application not requiring an interrupt from Timer 1 itself.
fCORE
C/T = 0 TL0 (8 BITS) C/T = 1 TF0 CORE CLK/12 INTERRUPT
06353-073
16-Bit Autoreload Mode
Autoreload mode has two options that are selected by Bit EXEN2 in Timer/Counter 2 Control SFR (T2CON, 0xC8). If EXEN2 = 0 when Timer 2 rolls over, it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16-bit value in registers Timer 2 Reload/Capture High Byte SFR (RACP2H, 0xCB) and Timer 2 Reload/Capture Low Byte SFR (RACP2L, 0xCA), which are preset by software. If EXEN2 = 1, Timer 2 performs the same events as when EXEN2 = 0, but adds a 1-to-0 transition at external input T2EX, which triggers the 16-bit reload and sets EXF2. Autoreload mode is shown in Figure 86.
16-Bit Capture Mode
Capture mode has two options that are selected by Bit EXEN2 in Timer/Counter 2 Control SFR (T2CON, 0xC8). If EXEN2 = 0, Timer 2 is a 16-bit timer or counter that, upon overflowing, sets Bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same events as when EXEN2 = 0, but adds a l-to-0 transition on external input T2E, which causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into the RCAP2L and RCAP2H registers, respectively. In addition, the transition at T2EX causes Bit EXF2 in T2CON to be set, and EXF2, like TF2, can generate an interrupt. Capture mode is shown in Figure 87. The baud rate generator mode is selected by RCLK = 1 and/or TCLK = 1. In either case, if Timer 2 is used to generate the baud rate, the TF2 interrupt flag does not occur. Therefore, Timer 2 interrupts do not occur and do not have to be disabled. In this mode, the EXF2 flag can, however, still cause interrupts that can be used as a third external interrupt. Baud rate generation is described as part of the UART serial port operation in UART Serial Interface section.
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P0.6/T0
CONTROL TR0
GATE INT0
TR1
Figure 85. Timer/Counter 0, Mode 3
06353-074
fCORE/12
TH0 (8 BITS)
INTERRUPT TF1
ADE7566/ADE7569
fCORE
C/ T2 = 0
Preliminary Technical Data
TL2 (8 BITS) TH2 (8 BITS)
P1.4/T2
C/ T2 = 1
CONTROL TR2 RELOAD TRANSITION DETECTOR RCAP2L RCAP2H TF2 TIMER INTERRUPT EXF2
P1.3/ T2EX
EXEN2
Figure 86. Timer/Counter 2, 16-Bit Autoreload Mode
fCORE
C/ T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2
P1.4/T2
C/ T2 = 1
CONTROL TR2 CAPTURE
TRANSITION DETECTOR RCAP2L RCAP2H
TIMER INTERRUPT
P1.3/ T2EX CONTROL EXEN2
EXF2
Figure 87. Timer/Counter 2, 16-Bit Capture Mode
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06353-076
06353-075
CONTROL
Preliminary Technical Data PLL
The ADE7566/ADE7569 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power savings when maximum core performance is not required. The default core clock is the PLL clock divided by 4 or 1.024 MHz. The ADE energy measurement clock is derived from the PLL clock and is maintained at 4.096 MHz/5 MHz, 819.2 kHz across all CD settings.
ADE7566/ADE7569
The PLL is controlled by the CD[2:0] bits in the Power Control SFR (POWCON, 0xC5). To protect erroneous changes to the Power Control SFR (POWCON, 0xC5), a key is required to modify the register. First, the Key SFR (KYREG, 0xC1) is written with the key, 0xA7, and then a new value is written to the Power Control SFR (POWCON, 0xC5). If the PLL loses lock, the MCU is reset and the PLL_FLT bit is set in the Peripheral Configuration SFR (PERIPH, 0xF4). Set the PLLACK bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the PLL fault, clearing the PLL_FLT bit.
PLL SFR REGISTER LIST
Table 111. Power Control SFR (POWCON, 0xC5)
Bit No. 7 6 5 4 3 2 to 0 Mnemonic Reserved METER_OFF Reserved COREOFF Reserved CD[2:0] Default 0 0 0 0 010 Description Reserved. Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering functions are not needed in PSM0 Reserved. Set this bit to shut down the core if in the PSM1 operating mode. Reserved. Controls the core clock frequency (fCORE). fCORE = 4.096 MHz/2CD CD[2:0] Result (fCORE in MHz) 000 4.096 001 2.048 010 1.024 011 0.512 100 0.256 101 0.128 110 0.064 111 0.032
Table 112. Key SFR (KYREG, 0xC1)
Bit No. 7 to 0 Mnemonic KYREG Default 0 Description Write 0xA7 to the KYREG SFR before writing to the POWCON SFR to unlock it. Write 0xEA to the KYREG SFR before writing to the HTHSEC, SEC, MIN, or HOUR timekeeping registers to unlock it.
Table 113. Peripheral Configuration SFR (PERIPH, 0xF4)
Bit No. 7 6 5 4 3 2 1 to 0 Mnemonic RXFLAG VSWSOURCE VDD_OK PLL_FLT Reserved EXTREFEN RXPROG[1:0] Default 0 1 0 0 0 00 Description If set, indicates that a Rx edge event triggered wake-up from PSM2. Indicates the power supply that is connected internally to VSW. If set, VSW = VDD. If cleared, VSW = VBAT. If set, indicates that VDD power supply is ok for operation. If set, indicates that PLL is not locked. Reserved. Set this bit if an external reference is connected to the REFIN pin. Controls the function of the P1.0/RxD pin. RXPROG [1:0] Result 00 GPIO 01 Rx with wake-up disabled 11 Rx with wake-up enabled
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ADE7566/ADE7569
Table 114. Start ADC Measurement SFR (ADCGO, 0xD8)
Bit No. 7 6 to 3 2 1 0 Address 0xDF 0xDE to 0xDB 0xDA 0xD9 0xD8 Mnemonic PLL_FTL_ACK Reserved VDCIN_ADC_GO TEMP_ADC_GO BATT_ADC_GO Default 0 0 0 0 0
Preliminary Technical Data
Description Set this bit to clear the PLL fault bit, PLL_FLT in the PERIPH register. A PLL fault is generated if a reset was caused because the PLL lost lock. Reserved. Set this bit to initiate an external voltage measurement. This bit is cleared when the measurement request is received by the ADC. Set this bit to initiate a temperature measurement. This bit is cleared when the measurement request is received by the ADC. Set this bit to initiate a battery measurement. This bit is cleared when the measurement request is received by the ADC.
Rev. PrA | Page 106 of 136
Preliminary Technical Data REAL TIME CLOCK
The ADE7566/ADE7569 have an embedded real time clock (RTC) as shown in Figure 88. The external 32.768 kHz crystal is used as the clock source for the RTC. Calibration is provided to compensate the nominal crystal frequency and for variations in the external crystal frequency over temperature. By default, the RTC is maintained active in all power-saving modes. The RTC counters retain their values through watchdog resets and external resets. They are only reset during a power-on reset.
32.768kHz CRYSTAL RTCCOMP
ADE7566/ADE7569
TEMPCAL
CALIBRATION CALIBRATED 32.768kHz RTCEN
ITS1
ITS0
8-BIT PRESCALER
HUNDREDTHS COUNTER HTHSEC INTERVAL TIMEBASE SELECTION MUX ITEN
SECOND COUNTER SEC
MINUTE COUNTER MIN
HOUR COUNTER HOUR
MIDNIGHT EVENT
8-BIT INTERVAL COUNTER EQUAL? INTVAL SFR
Figure 88. RTC Implementation
RTC SFR REGISTER LIST
Table 115. Real Time Clock SFR
SFR TIMECON HTHSEC SEC MIN HOUR INTVAL RTCCOMP TEMPCAL Address 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xF6 0xF7 Bit Addressable No No No No No No No No Description RTC Configuration (see Table 116). Hundredths of a Second Counter (see Table 117). Seconds Counter (see Table 118). Minutes Counter (see Table 119). Hours Counter (see Table 120). Alarm Interval (see Table 121). RTC Nominal Compensation (see Table 122). RTC Temperature Compensation (see Table 123).
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06353-077
ALARM EVENT
ADE7566/ADE7569
Table 116. RTC Configuration SFR (TIMECON, 0xA1)
Bit No. 7 Mnemonic MIDNIGHT Default 0
Preliminary Technical Data
Description Midnight Flag. This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to indicate that the midnight event has been serviced. In twenty-four hour mode, the midnight flag is raised once a day at midnight. Twenty-Four Hour Mode. This bit is retained during a watchdog reset or an external reset. It is reset after a power on reset (POR). TFH Result 0 256-Hour Mode. The HOUR register rolls over from 255 to 0. 1 24-Hour Mode. The HOUR register rolls over from 23 to 0. Interval Timer Time-Base Selection. ITS[1:0] Result (Time base) 00 1/128 sec. 01 Second. 10 Minute. 11 Hour. Interval Timer 1 Time Alarm. SIT Result 0 The ALARM flag is set after INTVAL counts and then another interval count starts. 1 The ALARM flag is set after one time interval. Interval Timer Alarm Flag. This bit is set when the configured time interval has elapsed. It can be cleared by the user to indicate that the alarm event has been serviced. This bit cannot be set to 1 by user code. Interval Timer Enable. ITEN Result 0 The interval timer is disabled. The 8-bit interval timer counter is reset. 1 Set this bit to enable the interval timer. The RTCEN bit must also be set to enable the interval timer. RTC Enable. Also Temperature, Battery and Supply ADC Background Strobe Enable. Note that the RTC is always enabled.
6
TFH
0
5 to 4
ITS[1:0]
0
3
SIT
0
2 1
ALARM ITEN
0 0
0
RTCEN
1
Table 117. Hundredths of a Second Counter SFR (HTHSEC, 0xA2)
Bit No. 7 to 0 Mnemonic HTHSEC Default 0 Description This counter updates every 1/128 sec, referenced from the calibrated 32 kHz clock. It overflows from 127 to 00, incrementing the seconds counter (SEC). This register is retained during a watchdog reset or an external reset. It is reset after a POR.
Table 118. Seconds Counter SFR (SEC, 0xA3)
Bit No. 7 to 0 Mnemonic SEC Default 0 Description This counter updates every second, referenced from the calibrated 32 kHz clock. It overflows from 59 to 00, incrementing the minutes counter (MIN). This register is retained during a watchdog reset or an external reset. It is reset after a POR.
Table 119. Minutes Counter SFR (MIN, 0xA4)
Bit No. 7 to 0 Mnemonic MIN Default 0 Description This counter updates every minute, referenced from the calibrated 32 kHz clock. It overflows from 59 to 00, incrementing the hours counter, HOUR. This register is retained during a watchdog reset or an external reset. It is reset after a POR.
Table 120. Hours Counter SFR (HOUR, 0xA5)
Bit No. 7 to 0 Mnemonic HOUR Default 0 Description This counter updates every hour, referenced from the calibrated 32 kHz clock. If the TFH bit in the RTC Configuration SFR (TIMECON, 0xA1) is set, the HOUR SFR overflows from 23 to 00, setting the MIDNIGHT bit and creating a pending RTC interrupt. If the TFH bit is cleared, the HOUR SFR overflows from 255 to 00, setting the MIDNIGHT bit and creating a pending RTC interrupt. This register is retained during a watchdog reset or an external reset. It is reset after a POR.
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Preliminary Technical Data
Table 121. Alarm Interval SFR (INTVAL, 0xA6)
Bit No. 7 to 0 Mnemonic INTVAL Default 0
ADE7566/ADE7569
Description The interval timer counts according to the time base established in the ITS[1:0] bits of the RTC Configuration SFR (TIMECON, 0xA1). Once the number of counts is equal to INTVAL, the ALARM flag is set and a pending RTC interrupt is created. Note that the interval counter is 8-bits. Therefore, it could count up to 255 sec, for example.
Table 122. RTC Nominal Compensation SFR (RTCCOMP, 0xF6)
Bit No. 7 to 0 Mnemonic RTCCOMP Default 0 Description The RTCCOMP SFR holds the nominal RTC compensation value at 25°C. This register is retained during a watchdog reset or an external reset. It is reset after a POR.
Table 123. RTC Temperature Compensation SFR (TEMPCAL, 0xF7)
Bit No. 7 to 0 Mnemonic TEMPCAL Default 0 Description The TEMPCAL SFR is adjusted based on the temperature read in the TEMPADC to calibrate the RTC over temperature. This allows the external crystal shift to be compensated over temperature. This register is retained during a watchdog reset or an external reset. It is reset after a POR.
Table 124. Interrupt Pins Configuration SFR (INTPR, 0xFF)
Bit No. 7 6 to 5 Mnemonic RTCCAL FSEL[1:0] Default 0 Description Controls the RTC calibration output. When set, the RTC calibration frequency selected by FSEL[1:0] is output on the P0.2/CF1/RTCCAL pin. Sets RTC calibration output frequency and calibration window. FSEL[1:0] Result (Calibration window, frequency) 0 0 30.5 sec, 1 Hz 0 1 30.5 sec, 512 Hz 1 0 0.244 sec, 500 Hz 1 1 0.244 sec, 16.384 kHz Controls the function of INT1. INT1PRG[2:0] x 0 x 0 0 1 1 1 0 INT0PRG 0 INT0PRG 0 1 0 1 x x Result GPIO BCTRL INT1 input disabled INT1 input enabled Result INT0 input disabled INT0 input enabled
4 3 to 1
Reserved INT1PRG[2:0]
000
Controls the function of INT0.
Writing to the Interrupt Pins Configuration SFR (INTPR, 0xFF)
To protect the RTC from runaway code, a key must be written to the KYREG register to obtain write access to the Interrupt Pins Configuration SFR (INTPR, 0xFF). The KYREG should be set to 0xEA to unlock this SFR and resets to zero after a timekeeping register is written to. The RTC registers can be written using the following 8052 assembly code:
MOV MOV KYREG, #0EAh INTPR, #080h
Table 125. Key SFR (KYREG, 0xC1)
Bit No. 7 to 0 Mnemonic KYREG Default 0 Description Write 0xA7 to the this SFR before writing to the POWCON SFR, which unlocks KYREG. Write 0xEA to the this SFR before writing to the HTHSEC, SEC, MIN, or HOUR timekeeping registers to unlock KYREG.
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ADE7566/ADE7569
READ AND WRITE OPERATIONS
Writing to the RTC Registers
The RTC circuitry runs off a 32.768 kHz clock. The timekeeping registers, Hundredths of a Second Counter SFR (HTHSEC, 0xA2), Seconds Counter SFR (SEC, 0xA3), Minutes Counter SFR (MIN, 0xA4), and Hours Counter SFR (HOUR, 0xA5) are updated with a 32.768 kHz clock. However, the RTC Configuration SFR (TIMECON, 0xA1) and Alarm Interval SFR (INTVAL, 0xA6) are updated with a 128 Hz clock. It takes up to two 128 Hz clock cycles from when the MCU writes to the RTC Configuration SFR (TIMECON, 0xA1) or Alarm Interval SFR (INTVAL, 0xA6) until it is successfully updated in the RTC. To protect the RTC timekeeping registers from runaway code, a key must be written to the Key SFR (KYREG, 0xC1) to obtain write access to the HTHSEC, SEC, MIN and HOUR SFRs. The Key SFR (KYREG, 0xC1) should be set to 0xEA to unlock the timekeeping registers and resets to 0 after a timekeeping register is written to. The RTC registers can be written using the following 8052 assembly code:
MOV RTCKey, #0EAh CALL … UpdateRTC: MOV KYREG, RTCKey MOV SEC, #30 MOV KYREG, RTCKey MOV MIN, #05 MOV KYREG, RTCKey MOV HOUR, #04 RET UpdateRTC
Preliminary Technical Data
RTC MODES
The RTC can be configured in a 24-hour mode or a 256-hour mode. A midnight event is generated when the RTC hour counter rolls over from 23 to 0 or 255 to 0, depending on whether the TFH bit is set in the RTC Configuration SFR (TIMECON, 0xA1). The midnight event sets the MIDNIGHT flag in the RTC Configuration SFR (TIMECON, 0xA1) and a pending RTC interrupt is created. The RTC midnight event wakes the 8052 MCU core if the MCU is asleep in PSM2 when the midnight event occurs. In the 24-hour mode, the midnight event is generated once a day at midnight. The 24-hour mode is useful for updating a software calendar to keep track of the current day. The 256-hour mode results in power savings during extended operation in PSM2 because the MCU core wakes up less frequently.
RTC INTERRUPTS
The RTC midnight interrupt and alarm interrupt are enabled by setting the ETI bit in the Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9). When a midnight or alarm event occurs, a pending RTC interrupt is generated. If the RTC interrupt is enabled, the program vectors to the RTC interrupt address and the pending interrupt is cleared. If the RTC interrupt is disabled, the RTC interrupt remains pending until the RTC interrupt is enabled. The program then vectors to the RTC interrupt address. The MIDNIGHT flag and ALARM flag are set when the midnight event and alarm event occur, respectively. The user should manage these flags to keep track of which event caused an RTC interrupt by servicing the event and clearing the appropriate flag in the RTC interrupt servicing routine. Note that if the ADE7566/ADE7569 are awakened by an RTC event, either by the MIDNIGHT event or ALARM event, the pending RTC interrupt must be serviced before the device can go back to sleep again. The ADE7566/ADE7569 will keep waking up until this interrupt has been serviced.
Reading the RTC Counter SFRs
The RTC cannot be stopped to read the current time because stopping the RTC would introduce an error in its timekeeping. So the RTC is read on the fly. Therefore, the counter registers must be checked for overflow. This can be accomplished through the following 8052 assembly code:
ReadAgain: MOV R0, HTHSEC MOV R1, SEC MOV R2, MIN MOV R3, HOUR MOV A, CJNE Bank 0 HTHSEC A, 00h, ReadAgain ; 00h is R0 in ; using Bank 0
Interval Timer Alarm
The RTC can be used as an interval timer. When the interval timer is enabled by setting the ITEN bit in the RTC Configuration SFR (TIMECON, 0xA1), the interval timer clock source selected by the ITS1 and ITS0 bits is passed through an 8-bit counter. This counter increments on every interval timer clock pulse until it is equal to the value in the Alarm Interval SFR (INTVAL, 0xA6). Then, an alarm event is generated, setting the ALARM flag and creating a pending RTC interrupt. If the SIT bit in the RTC Configuration SFR (TIMECON, 0xA1) is cleared, the 8-bit counter is also cleared and starts counting again. If the SIT bit is set, the 8-bit counter is held in reset after the alarm occurs.
Rev. PrA | Page 110 of 136
Preliminary Technical Data
Take care when changing the interval timer time base. The recommended procedure is as follows: 1. If the Alarm Interval SFR (INTVAL, 0xA6) is going to be modified, write to this register first. Then, wait for one 128 Hz clock cycle to synchronize with the RTC, 64,000 cycles at a 4.096 MHz instruction cycle clock. Disable the interval timer by clearing the ITEN bit in the RTC Configuration SFR (TIMECON, 0xA1). Then, wait for one 128 Hz clock cycle to synchronize with the RTC, 64,000 cycles at a 4.096 MHz instruction cycle clock. Read the RTC Configuration SFR (TIMECON, 0xA1) to ensure that the ITEN bit is clear. If it is not, wait for another 128 Hz clock cycle. Set the time-base bits (ITS[1:0]) in the RTC Configuration SFR (TIMECON, 0xA1) to configure the interval. Wait for a 128 Hz clock cycle for this change to take effect.
ADE7566/ADE7569
with FSEL[1:0] = 00 and 512 Hz with FSEL[1:0] = 01 in the Interrupt Pins Configuration SFR (INTPR, 0xFF). A shorter window of 0.244 sec is offered for fast calibration during PSM0 or PSM1. Two output frequencies are offered for this RTC calibration output mode: 500 Hz with FSEL[1:0] = 10 and 16.384 kHz with FSEL[1:0] = 11 in the Interrupt Pins Configuration SFR (INTPR, 0xFF). Note that for the 0.244 sec calibration window, the RTC is clocked 125 times faster than in normal mode, resulting in timekeeping registers that represent seconds/125, minutes/125 and hours/125 instead of seconds, minutes, and hours. Therefore, this mode should be used for calibration only.
Table 126. RTC Calibration Options
Option Normal Mode 0 Normal Mode 1 Calibration Mode 0 Calibration Mode 1 FSEL[1:0] 00 01 10 11 Calibration Window (sec) 30.5 30.5 0.244 0.244 fRTCCAL (Hz) 1 512 500 16,384
2.
3.
4.
The RTC alarm event wakes the 8052 MCU core if the MCU is in PSM2 when the alarm event occurs.
RTC CALIBRATION
The RTC provides registers to calibrate the nominal external crystal frequency and its variation over temperature. A frequency error up to ±248 ppm can be calibrated out by the RTC circuitry, which adds or subtracts pulses from the external crystal signal. The nominal crystal frequency should be calibrated with the RTC nominal compensation register so that the clock going into the RTC is precisely 32.768 kHz at 25°C. The RTC Temperature Compensation SFR (TEMPCAL, 0xF7) is used to compensate for the external crystal drift over temperature by adding or subtracting additional pulses based on temperature. The LSB of each RTC compensation register represents a ±2 ppm frequency error. The RTC compensation circuitry adds the RTC Temperature Compensation SFR (TEMPCAL, 0xF7) and the RTC Nominal Compensation SFR (RTCCOMP, 0xF6) to determine how much compensation is required. Note that the sum of these two registers is limited to ±248 ppm.
When no RTC compensation is applied, that is, when RTC Nominal Compensation SFR (RTCCOMP, 0xF6) and RTC Temperature Compensation SFR (TEMPCAL, 0xF7) are equal to 0, the nominal compensation required to account for the error in the external crystal can be determined. In this case, it is not necessary to wait for an entire calibration window to determine the error in the pulse output. Calculating at the error in frequency between two consecutive pulses on the P0.2/CF1/RTCCAL pin is enough. The value to write to the RTC Nominal Compensation SFR (RTCCOMP, 0xF6) is calculated from the % error or seconds per day error on the frequency output. Each LSB of the RTC Nominal Compensation SFR (RTCCOMP, 0xF6) represents 2 ppm of correction where 1 sec/day error is equal to 11.57 ppm.
RTCCOMP = 5000 × (% Error ) RTCCOMP =
Calibration Flow
A RTC calibration pulse output is provided on the P0.2/CF1/ RTCCAL pin. Enable the RTC output by setting the RTCCAL bit in the Interrupt Pins Configuration SFR (INTPR, 0xFF). The RTC calibration is accurate to within ±2 ppm over a 30.5 sec window in all operational modes: PSM0, PSM1, and PSM2. Two output frequencies are offered for the normal RTC mode: 1 Hz
1 × (sec/day Error ) 2 × 11.57
During calibration, user software writes the RTC with the current time. Refer to the Read and Write Operations section for more information on how to read and write the RTC timekeeping registers.
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ADE7566/ADE7569 UART SERIAL INTERFACE
The ADE7566/ADE7569 UART can be configured in one of four modes.
• • • •
Preliminary Technical Data
pins, while the firmware interface is through the SFRs presented in Table 127. Both the serial port receive and transmit registers are accessed through the Serial Port Buffer SFR (SBUF, 0x99). Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. An enhanced UART mode is offered by using the UART timer and by providing enhanced frame error, break error, and overwrite error detection. This mode is enabled by setting the EXTEN bit in the Configuration SFR (CFG, 0xAF) (see the UART Additional Features section). The Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E) and UART Timer Fractional Divider SFR (SBAUDF, 0x9D) are used to configure UART timer and to indicate the enhanced UART errors.
Shift register with baud rate fixed at fCORE/12 8-bit UART with variable baud rate 9-bit UART with baud rate fixed at fCORE/64 or fCORE/32 9-bit UART with variable baud rate
Variable baud rates are defined by using an internal timer to generate any rate between 300 baud/sec and 115,200 baud/sec. The UART serial interface provided in the ADE7566/ADE7569 is a full-duplex serial interface. It is also receive buffered by storing the first received byte in a receive buffer until the reception of the second byte is complete. The physical interface to the UART is provided via the RxD (P1.0) and TxD (P1.1)
UART SFR REGISTERS
Table 127. Serial Port SFRs
SFR SCON SBUF SBAUDT SBAUDF Address 0x98 0x99 0x9E 0x9D Bit Addressable Yes No No No Description Serial Communications Control Register (see Table 128). Serial Port Buffer (see Table 129). Enhanced Error Checking (see Table 130). Enhanced Fractional Divider (see Table 131).
Table 128. Serial Communications Control Register Bit Description SFR (SCON, 0x98)
Bit No. 7 to 6 Address 0x9F, 0x9E Mnemonic SM0, SM1 Default 00 Description UART Serial Mode Select Bits. These bits select the serial port operating mode. SM[0:1] Result (Selected Operating Mode) 00 Mode 0, shift register, fixed baud rate (fCORE/12). 01 Mode 1, 8-bit UART, variable baud rate. 10 Mode 2, 9-bit UART, fixed baud rate (fCORE/32) or (fCORE/16). 11 Mode 3, 9-bit UART, variable baud rate. Multiprocessor Communication Enable Bit. Enables multiprocessor communication in Mode 2 and Mode 3, and framing error detection in Mode 1. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is cleared, RI is set as soon as the byte of data is received. In Modes 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI is set as soon as the byte of data is received. Serial Port Receive Enable Bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. Serial Port Transmit (Bit 9). The data loaded into TB8 is the ninth data bit transmitted in Mode 2 and Mode 3. Serial Port Receiver Bit 9. The ninth data bit received in Mode 2 and Mode 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8. Serial Port Transmit Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0 or at the beginning of the stop bit in Mode 1, Mode 2, and Mode 3. TI must be cleared by user software. Serial Port Receive Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Mode 1, Mode 2, and Mode 3. RI must be cleared by user software.
5
0x9D
SM2
0
4 3 2 1
0x9C 0x9B 0x9A 0x99
REN TB8 RB8 TI
0 0 0 0
0
0x98
RI
0
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Preliminary Technical Data
Table 129. Serial Port Buffer SFR (SBUF, 0x99)
Bit No. 7 to 0 Mnemonic SBUF Default 0 Description Serial Port Data Buffer.
ADE7566/ADE7569
Table 130. Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E)
Bit No. 7 Mnemonic OWE Default 0 Description Overwrite Error. This bit is set when new data is received and RI = 1. It indicates that SBUF was not read before the next character was transferred in, causing the prior SBUF data to be lost. Write a 0 to this bit to clear it. Frame Error. This bit is set when the received frame did not have a valid stop bit. This bit is read only and updated every time a frame is received. Break Error. This bit is set whenever the receive data line (Rx) is low for longer than a full transmission frame, which is the time required for a start bit, 8 data bits, a parity bit, and half a stop bit. This bit is updated every time a frame is received. Extended divider ratio for baud rate setting as shown in Table 132. Binary Divider. DIV[2:0] Result 000 Divide by 1 (see Table 132). 001 Divide by 2 (see Table 132). 010 Divide by 4 (see Table 132). 011 Divide by 8 (see Table 132). 100 Divide by 16 (see Table 132). 101 Divide by 32 (see Table 132). 110 Divide by 64 (see Table 132). 111 Divide by 128 (see Table 132).
6 5
FE BE
0 0
4, 3 2, 1, 0
SBTH1, SBTH0 DIV2, DIV1, DIV0
0 0
Table 131. UART Timer Fractional Divider SFR (SBAUDF, 0x9D)
Bit No. 7 Mnemonic UARTBAUDEN Default 0 Description UART Baud Rate Enable. Set to enable UART timer to generate the baud rate. When set, PCON.7 (SMOD), T2CON.4 (TCLK), and T2CON.5 (RCLK) are ignored. Cleared to let the baud rate be generated as per a standard 8052. Not Implemented, Write Don’t Care. UART Timer Fractional Divider Bit 5. UART Timer Fractional Divider Bit 4. UART Timer Fractional Divider Bit 3. UART Timer Fractional Divider Bit 2. UART Timer Fractional Divider Bit 1. UART Timer Fractional Divider Bit 0.
6 5 4 3 2 1 0
– SBAUDF.5 SBAUDF.4 SBAUDF.3 SBAUDF.2 SBAUDF.1 SBAUDF.0
0 0 0 0 0 0
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ADE7566/ADE7569
Table 132. Common Baud Rates Using UART Timer with a 4.096 MHz PLL Clock
Ideal Baud 115200 115200 57600 57600 38400 38400 38400 19200 19200 19200 19200 9600 9600 9600 9600 9600 4800 4800 4800 4800 4800 4800 2400 2400 2400 2400 2400 2400 2400 300 300 300 300 300 300 300 300 CD 0 1 0 1 0 1 2 0 1 2 3 0 1 2 3 4 0 1 2 3 4 5 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 SBTH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 DIV 1 0 2 1 2 1 0 3 2 1 0 4 3 2 1 0 5 4 3 2 1 0 6 5 4 3 2 1 0 7 7 7 6 5 4 3 2 SBAUDT 0x01 0x00 0x02 0x01 0x02 0x01 0x00 0x03 0x02 0x01 0x00 0x04 0x03 0x02 0x01 0x00 0x05 0x04 0x03 0x02 0x01 0x00 0x06 0x05 0x04 0x03 0x02 0x01 0x00 0x17 0x0F 0x07 0x06 0x05 0x04 0x03 0x02
Preliminary Technical Data
SBAUDF 0x87 0x87 0x87 0x87 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB % Error +0.16 +0.16 +0.16 +0.16 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31 −0.31
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Preliminary Technical Data
UART OPERATION MODES
Mode 0 (Shift Register with Baud Rate Fixed at fCORE/12)
Mode 0 is selected when the SM0 and SM1 bits in the Serial Communications Control Register Bit Description SFR (SCON, 0x98) are cleared. In this shift register mode, serial data enters and exits through RxD. TxD outputs the shift clock. The baud rate is fixed at fCORE/12. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to the Serial Port Buffer SFR (SBUF, 0x99). The data is shifted out of the RxD line. The 8 bits are transmitted with the least significant bit (LSB) first. Reception is initiated when the receive enable bit (REN) is 1 and the receive interrupt bit (RI) is 0. When RI is cleared, the data is clocked into the RxD line, and the clock pulses are output from the TxD line as shown in Figure 89.
RxD (DATA OUT) TxD (SHIFT CLOCK) DATA BIT 0 DATA BIT 1 DATA BIT 6 DATA BIT 7
06353-078
ADE7566/ADE7569
All of the following conditions must be met at the time the final shift pulse is generated to receive a character:
•
•
If the extended UART is disabled (EXTEN = 0 in the CFG SFR), RI must be 0 to receive a character. This ensures that the data in the SBUF SFR is not overwritten if the last received character has not been read. If frame error checking is enabled by setting SM2, the received stop bit must be set to receive a character. This ensures that every character received comes from a valid frame, with both a start bit and a stop bit.
If any of these conditions are not met, the received frame is irretrievably lost, and the receive interrupt flag (RI) is not set. If the received frame has met the previous criteria, the following events occur:
• • •
The 8 bits in the receive shift register are latched into the SBUF SFR. The ninth bit (stop bit) is clocked into RB8 in the SCON SFR. The receiver interrupt flag (RI) is set.
Figure 89. 8-Bit Shift Register Mode
Mode 2 (9-Bit UART with Baud Fixed at fCORE/64 or fCORE/32)
Mode 2 is selected by setting SM0 and clearing SM1. In this mode, the UART operates in 9-bit mode with a fixed baud rate. The baud rate is fixed at fCORE/64 by default, although setting the SMOD bit in the Program Control SFR (PCON, 0x87) doubles the frequency to fCORE/32. Eleven bits are transmitted or received: a start bit (0), 8 data bits, a programmable ninth bit, and a stop bit (1). The ninth bit is most often used as a parity bit or as part of a multiprocessor communication protocol, although it can be used for anything, including a ninth data bit, if required. To use the ninth data bit as part of a communication protocol for a multiprocessor network such as RS-485, the ninth bit is set to indicate that the frame contains the address of the device that the master would like to communicate with. The devices on the network are always listening for a packet with the ninth bit set and are configured such that if the ninth bit is cleared, the frame is not valid, and a receive interrupt is not generated. If the ninth bit is set, all devices on the network receive the address and obtain a receive character interrupt. The devices examine the address and if it matches one of the device’s preprogrammed address, that device configures itself to listen to all incoming frames, even those with the ninth bit cleared. Because the master has initiated communication with that device, all the following packets with the ninth bit cleared are intended specifically for that addressed device until another packet with the ninth bit set is received. If the address does not match, the device continues to listen for address packets.
Mode 1 (8-Bit UART, Variable Baud Rate)
Mode 1 is selected by clearing SM0 and setting SM1. Each data byte (LSB first) is preceded by a start bit (0) and followed by a stop bit (1). Therefore, each frame consists of 10 bits transmitted on TxD or received on RxD. The baud rate is set by a timer overflow rate. Timer 1 or Timer 2 can be used to generate baud rates, or both timers can be used simultaneously where one generates the transmit rate and the other generates the receive rate. There is also a dedicated timer for baud rate generation, the UART timer, which has a fractional divisor to precisely generate any baud rate (see the UART Timer Generated Baud Rates section). Transmission is initiated by a write to the Serial Port Buffer SFR (SBUF, 0x99) Next, a stop bit (1) is loaded into the ninth bit position of the transmit shift register. The data is output bit-bybit until the stop bit appears on TxD and the transmit interrupt flag (TI) is automatically set as shown in Figure 90.
START BIT TxD TI (SCON.1) SET INTERRUPT (FOR EXAMPLE, READY FOR MORE DATA)
06353-079
STOP BIT D0 D1 D2 D3 D4 D5 D6 D7
Figure 90. 8-Bit Variable Baud Rate
Reception is initiated when a 1-to-0 transition is detected on RxD. Assuming that a valid start bit is detected, character reception continues. The 8 data bits are clocked into the serial port shift register.
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ADE7566/ADE7569
To transmit, the 8 data bits must be written into the Serial Port Buffer SFR (SBUF, 0x99). The ninth bit must be written to TB8 in the Serial Communications Control Register Bit Description SFR (SCON, 0x98). When transmission is initiated, the 8 data bits from SBUF are loaded into the transmit shift register (LSB first). The ninth data bit, held in TB8, is loaded into the ninth bit position of the transmit shift register. The transmission starts at the next valid baud rate clock. The transmit interrupt flag (TI) is set as soon as the transmission completes, when the stop bit appears on TxD. All of the following conditions must be met at the time the final shift pulse is generated to receive a character:
•
Preliminary Technical Data
UART BAUD RATE GENERATION
Mode 0 Baud Rate Generation
The baud rate in Mode 0 is fixed.
⎛f ⎞ Mode 0 Baud Rate = ⎜ core ⎟ ⎝ 12 ⎠
Mode 2 Baud Rate Generation
The baud rate in Mode 2 depends on the value of the PCON.7 (SMOD) bit in the Program Control SFR (PCON, 0x87). If SMOD = 0, the baud rate is 1/32 of the core clock. If SMOD = 1, the baud rate is 1/16 of the core clock. Mode 2 Baud Rate =
2 SMOD × fCORE 32
•
If the extended UART is disabled (EXTEN = 0 in the CFG SFR), RI must be 0 to receive a character. This ensures that the data in SBUF is not overwritten if the last received character has not been read. If multiprocessor communication is enabled by setting SM2, the received ninth bit must be set to receive a character. This ensures that only frames with the ninth bit set, frames that contain addresses, generate a receive interrupt.
Mode 1 and Mode 3 Baud Rate Generation
The baud rates in Mode 1 and Mode 3 are determined by the overflow rate of the timer generating the baud rate, that is, either Timer 1, Timer 2, or the dedicated baud rate generator, UART timer, which has an integer and fractional divisor.
Timer 1 Generated Baud Rates
When Timer 1 is used as the baud rate generator, the baud rates in Mode 1 and Mode 3 are determined by the Timer 1 overflow rate. The value of SMOD is as follows: Mode 1 and Mode 3 Baud Rate =
2 SMOD × Timer 1 Overflow Rate 32
If any of these conditions are not met, the received frame is irretrievably lost, and the receive interrupt flag (RI) is not set. Reception for Mode 2 is similar to that of Mode 1. The 8 data bytes are input at RxD (LSB first) and loaded onto the receive shift register. If the received frame has met the previous criteria, the following events occur:
• • •
The 8 bits in the receive shift register are latched into the SBUF SFR. The ninth data bit is latched into RB8 in the SCON SFR. The receiver interrupt flag (RI) is set.
Mode 3 (9-Bit UART with Variable Baud Rate)
Mode 3 is selected by setting both SM0 and SM1. In this mode, the 8051 UART serial port operates in 9-bit mode with a variable baud rate. The baud rate is set by a timer overflow rate. Timer 1 or Timer 2 can be used to generate baud rates, or both timers can be used simultaneously where one generates the transmit rate and the other generates the receive rate. There is also a dedicated timer for baud rate generation, the UART timer, which has a fractional divisor to precisely generate any baud rate (see the UART Timer Generated Baud Rates section). The operation of the 9-bit UART is the same as for Mode 2, but the baud rate can be varied. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 when RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1.
The Timer 1 interrupt should be disabled in this application. The timer itself can be configured for either timer or counter operation, and in any of its three running modes. In the most typical application, it is configured for timer operation in autoreload mode (high nibble of TMOD = 0010 binary). In that case, the baud rate is given by the following formula: f core 2 SMOD Mode 1 and Mode 3 Baud Rate = × 32 (256 − TH1)
Timer 2 Generated Baud Rates
Baud rates can also be generated by using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted or received. Because Timer 2 has a 16-bit autoreload mode, a wider range of baud rates is possible. Mode 1 and Mode 3 Baud Rate = 1 × Timer 2 Overflow Rate 16
Therefore, when Timer 2 is used to generate baud rates, the timer increments every two clock cycles rather than every core machine cycle as before. It increments six times faster than Timer 1, and, therefore, baud rates six times faster are possible. Because Timer 2 has 16-bit autoreload capability, very low baud rates are still possible.
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Preliminary Technical Data
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in Timer/Counter 2 Control SFR (T2CON, 0xC8). The baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode as shown in Figure 92. In this case, the baud rate is given by the following formula: Mode 1 and Mode 3 Baud Rate =
f CORE
fCORE
FRACTIONAL ÷(1 + SBAUDF/64) DIVIDER
ADE7566/ADE7569
TIMER 1/TIMER 2 Tx CLOCK TIMER 1/TIMER 2 Rx CLOCK 1 ÷2DIV + SBTH Rx CLOCK UARTBAUDEN Tx CLOCK
06353-081
0
÷32
1 UART TIMER Rx/Tx CLOCK
0
(16 × [65536 − (RCAP 2H : RCAP 2L )])
UART Timer Generated Baud Rates
The high integer dividers in a UART block mean that high speed baud rates are not always possible. In addition, generating baud rates requires the exclusive use of a timer, rendering it unusable for other applications when the UART is required. To address this problem, each ADE7566/ADE7569 has a dedicated baud rate timer (UART timer) specifically for generating highly accurate baud rates. The UART timer can be used instead of Timer 1 or Timer 2 for generating very accurate high speed UART baud rates, including 115,200 bps. This timer also allows a much wider range of baud rates to be obtained. In fact, every desired bit rate from 12 bps to 393,216 bps can be generated to within an error of ±0.8%. The UART timer also frees up the other three timers, allowing them to be used for different applications. A block diagram of the UART timer is shown in Figure 91.
Figure 91. UART Timer, UART Baud Rate
Two SFRs, Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E) and UART Timer Fractional Divider SFR (SBAUDF, 0x9D), are used to control the UART timer. SBAUDT is the baud rate control SFR; it sets up the integer divider (DIV) and the extended divider (SBTH) for the UART timer. The appropriate value to write to the DIV[2:0] and SBTH[1:0] bits can be calculated using the following formula where fCORE is defined in the POWCON SFR (see Table 23). Note that the DIV value must be rounded down to the nearest integer.
⎛ ⎞ f CORE ⎟ log⎜ ⎜ 16 × Baud Rate ⎟ ⎝ ⎠ DIV + SBTH = log(2)
TIMER 1 OVERFLOW
2 0 1 SMOD TL2 (8 BITS) T2 PIN C/ T2 = 1 1 TR2 NOTE: AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT RELOAD 16 RCAP2L RCAP2H 0 TCLK Tx CLOCK TH2 (8 BITS) TIMER 2 OVERFLOW 1 0 RCLK 16 Rx CLOCK
fCORE
CONTROL C/ T2 = 0
T2EX PIN CONTROL EXEN2
EXF 2
TIMER 2 INTERRUPT
TRANSITION DETECTOR
Figure 92. Timer 2, UART Baud Rates
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06353-080
ADE7566/ADE7569
SBAUDF is the fractional divider ratio required to achieve the required baud rate. The appropriate value for SBAUDF can be calculated with the following formula:
⎛ ⎞ f CORE SBAUDF = 64 × ⎜ − 1⎟ ⎜ 16 × 2 DIV + SBTH × Baud Rate ⎟ ⎝ ⎠
Rx START D0
Preliminary Technical Data
D1 D2 D3 D4 D5 D6 D7 STOP
RI
06353-082
FE EXTEN = 1
Figure 93. UART Timing in Mode 1
Note that SBAUDF should be rounded to the nearest integer. Once the values for DIV and SBAUDF are calculated, the actual baud rate can be calculated with the following formula:
RX
START
D0
D1
D2
D3
D4
D5
D6
D7
D8
STOP
16 × 2 DIV + SBTH
SBAUDF ⎞ × ⎛1 + ⎜ ⎟ 64 ⎝ ⎠
FE EXTEN = 1
Figure 94. UART Timing in Mode 2 and Mode 3
For example, to obtain a baud rate of 9600 bps while operating at a core clock frequency of 4.096 MHz with the PLL CD bits equal to 0,
4,096,000 ⎞ log⎛ ⎟ ⎜ ⎝ 16 × 9600 ⎠ = 4.74 = 4 DIV + SBTH = log(2)
Note that the DIV result is rounded down.
4,096,000 SBAUDF = 64 × ⎛ − 1⎞ = 42.67 = 0 x 2 B ⎜ ⎟ ⎝ 16 × 2 3 × 9600 ⎠
The 8052 standard UART does not provide break error detection. However, for an 8-bit UART, a break error can be detected when the received character is 0, a NUL character, and when there is no stop bit because the RB8 bit is low. Break error detection is not possible for a 9-bit 8052 UART because the stop bit is not recorded. The ADE7566/ADE7569 enhanced break error detection is available through the BE bit in the SBAUDT SFR. The 8052 standard UART prevents overwrite errors by not allowing a character to be received when the RI, receive interrupt flag, is set. However, it does not indicate if a character has been lost because the RI bit is set when the frame is received. The enhanced UART overwrite error detection provides this information. When the enhanced 8052 UART is enabled, a frame is received regardless of the state of the RI flag. If RI = 1 when a new byte is received, the byte in SCON is overwritten, and the overwrite error flag is set. The overwrite error flag is cleared when SBUF is read. The extended UART is enabled by setting the EXTEN bit in the Configuration SFR (CFG, 0xAF).
Thus, the actual baud rate is 9570 bps, resulting in a 0.31% error.
UART ADDITIONAL FEATURES
Enhanced Error Checking
The extended UART provides frame error, break error, and overwrite error detection. Framing errors occur when a stop bit is not present at the end of the frame. A missing stop bit implies that the data in the frame may not have been received properly. Break error detection indicates if the Rx line has been low for longer than a 9-bit frame. It indicates that the data just received, a 0 or NUL character, is not valid because the master has disconnected. Overwrite error detection indicates when the received data has not been read fast enough and, as result, a byte of data has been lost. The 8052 standard UART offers frame-error checking for an 8-bit UART through the SM2 and RB8 bits. Setting the SM2 bit prevents frames without a stop bit from being received. The stop bit is latched into the RB8 bit in the Serial Communications Control Register Bit Description SFR (SCON, 0x98). This bit can be examined to determine if a valid frame was received. The 8052 does not, however, provide frame error checking for a 9-bit UART. This enhanced error checking functionality is available through the frame error bit, FE in the Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E). The FE bit is set on framing errors for both 8-bit and 9-bit UARTs.
UART TxD Signal Modulation
There is an internal 38 kHz signal that can be OR’ed with the UART transmit signal for use in remote control applications (see the 38 kHz Modulation section). One of the events that can wake the MCU from sleep mode is activity on the Rx pin (see the 3.3 V Peripherals and Wake-Up Events section).
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Actual Baud Rate =
f CORE
RI
Preliminary Technical Data SERIAL PERIPHERAL INTERFACE (SPI)
The ADE7566/ADE7569 integrate a complete hardware serial peripheral interface on-chip. The SPI is full duplex so that 8 bits of data are synchronously transmitted and simultaneously received. This SPI implementation is double buffered, allowing users to read the last byte of received data while a new byte is shifted in. The next byte to be transmitted can be loaded while the current byte is shifted out. The SPI port can be configured for master or slave operation. The physical interface to the SPI is via MISO (P0.5), MOSI (P0.4), SCLK (P0.6), and SS (P0.7) pins, while the firmware interface is
ADE7566/ADE7569
via the SPI Configuration Register SFR (SPIMOD1, 0xE8), the SPI Configuration Register SFR (SPIMOD2, 0xE9), the SPI Interrupt Status Register SFR (SPISTAT, 0xEA), the SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A), and the SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B). Note that the SPI pins are shared with the I2C pins. Therefore, the user can enable only one interface at a time. The SCPS bit in the Configuration SFR (CFG, 0xAF) selects which peripheral is active.
SPI SFR REGISTER LIST
Table 133. SPI SFR Register List
SFR Address 0x9A 0x9B 0xE8 0xE9 0xEA Name SPI2CTx SPI2CRx SPIMOD1 SPIMOD2 SPISTAT R/W W R R/W R/W R/W Length 8 8 8 8 8 Default 0 0x10 0 0 Description SPI/I2C Data Out Register (see Table 134). SPI/I2C Data in Register (see Table 135). SPI Configuration Register (see Table 136). SPI Configuration Register. (see Table 137). SPI/I2C Interrupt Status Register (see Table 138).
Table 134. SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A)
Bit No. 7 to 0 Mnemonic SPI2CTx Default 0 Description SPI or I2C Transmit Buffer. When SPI2CTx SFR is written, its content is transferred to the transmit FIFO input. When a write is requested, the FIFO output is sent on the SPI or I2C bus.
Table 135. SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B)
Bit No. 7 to 0 Mnemonic SPI2CRx Default 0 Description SPI or I2C Receive Buffer. When SPI2CRx SFR is read, one byte from the receive FIFO output is transferred to SPI2CRx SFR. A new data byte from the SPI or I2C bus is written to the FIFO input.
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Table 136. SPI Configuration Register SFR (SPIMOD1, 0xE8)
Bit No. 7 to 5 5 Address 0xEF to 0xEE 0xED Mnemonic Reserved INTMOD Default 0 0
Preliminary Technical Data
Description Reserved. SPI Interrupt Mode. INTMOD Result 0 SPI interrupt set when SPI Rx buffer is full. 1 SPI interrupt set when SPI Tx buffer is empty. Master Mode, SS Output Control (see Figure 95). Result The SS is held low while this bit is cleared. This allows manual chip select control using the SS pin. 1 Single Byte Read or Write. The SS goes low during a single byte transmission and then returns high. Continuous Transfer. The SS goes low during the duration of the multibyte continuous transfer and then returns high. Slave Mode, SS Input Enable. When this bit is set to Logic 1, the SS pin is defined as the slave select input pin for the SPI slave interface. Receive Buffer Overflow Write Enable. RxOFW Result 0 If the SPI2CRx SFR has not been read when a new data byte is received, the new byte is discarded. 1 If the SPI2CRx SFR has not been read when a new data byte is received, the new byte overwrites the old data. Master Mode, SPI SCLK Frequency. SPIR[1:0] Result 00 fCORE/8 = 512 kHz (if fCORE = 4.096 MHz) 01 fCORE/16 = 256 kHz (if fCORE = 4.096 MHz) 10 fCORE/32 = 128 kHz (if fCORE = 4.096 MHz) 11 fCORE/64 = 64 kHz (if fCORE = 4.096 MHz) AUTO_SS 0
4
0xEC
AUTO_SS
1
3
0xEB
SS_EN
0
2
0xEA
RxOFW
0
1 to 0
0xE9 to 0xE8
SPIR[1:0]
0
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Preliminary Technical Data
Table 137. SPI Configuration Register SFR (SPIMOD2, 0xE9)
Bit No. 7 Mnemonic SPICONT Default 0
ADE7566/ADE7569
Description Master Mode, SPI Continuous Transfer Mode Enable Bit. SPICONT Result 0 The SPI interface stops after one byte is transferred and SS is deasserted. A new data transfer can be initiated after a stalled period. 1 The SPI interface continues to transfer data until no valid data is available in the SPI2CTx SFR. SS remains asserted until the SPI2CTx SFR and the transmit shift register is empty. SPI Interface Enable Bit. SPIEN Result 0 The SPI interface is disabled. 1 The SPI interface is enabled. SPI Open Drain Output Configuration Bit. SPIODO Result 0 Internal pull-up resistors are connected to the SPI outputs. 1 The SPI outputs are open-drain and need external pull-up resistors. SPI Master Mode Enable Bit. SPIMS_b Result 0 The SPI interface is defined as a slave. 1 The SPI interface is defined as a master. SPI Clock Polarity Configuration Bit (see Figure 97). SPICPOL Result 0 The default state of SCLK is low, and the first SCLK edge is rising. Depending on SPICPHA bit, the SPI data output changes state on the falling or rising edge of SCLK while the SPI data input is sampled on the rising or falling edge of SCLK. 1 The default state of SCLK is high, and the first SCLK edge is falling. Depending on SPICPHA bit, the SPI data output changes state on the rising or falling edge of SCLK while the SPI data input is sampled on the falling or rising edge of SCLK. SPI Clock Phase Configuration Bit (see Figure 97). SPICPHA Result 0 The SPI data output changes state when SS goes low at the second edge of SCLK and then every two subsequent edges while the SPI data input is sampled at the first SCLK edge and then every two subsequent edges. 1 The SPI data output changes state at the first edge of SCLK and then every two subsequent edges while the SPI data input is sampled at the second SCLK edge and then every two subsequent edges. Master Mode, LSB First Configuration Bit. SPILSBF Result 0 The MSB of the SPI outputs is transmitted first. 1 The LSB of the SPI outputs is transmitted first. Transfer and Interrupt Mode of the SPI Interface. TIMODE Result 0 Transfer is initiated when data is read from the SPI2CRx SFR, and an interrupt is generated when there is new data in the SPI2CRx SFR. 1 Transfer is initiated when data is written to the SPI2CTx SFR, and an interrupt is generated when the SPI2CTx SFR is empty.
6
SPIEN
0
5
SPIODO
0
4
SPIMS_b
0
3
SPICPOL
0
2
SPICPHA
0
1
SPILSBF
0
0
TIMODE
0
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ADE7566/ADE7569
Table 138. SPI Interrupt Status Register SFR (SPISTAT, 0xEA)
Bit No. 7 Mnemonic BUSY Default 0
Preliminary Technical Data
Description SPI Peripheral Busy Flag. BUSY Result 0 The SPI peripheral is idle. 1 The SPI peripheral is busy transferring data in slave or master mode. SPI Multi-Master Error Flag. MMERR Result 0 A multiple master error has not occurred. 1 If the SS_EN bit is set, enabling the slave select input and asserting the SS while the SPI peripheral is transferring data as a master, this flag is raised to indicate the error. Write a 0 to this bit to clear it. SPI Receive Overflow Error Flag. Reading the SPI2CRx SFR clears this bit. SPIRxOF TIMODE Result 0 X The SPI2CRx register contains valid data 1 1 This bit is set if the SPI2CRx register is not read before the end of the next byte transfer. If the RxOFW bit is set and this condition occurs, SPI2CRx is overwritten. SPI Receive Mode Interrupt Flag. Reading the SPI2CRx SFR clears this bit. SPIRxIRQ TIMODE Result 0 X The SPI2CRx register does not contain new data. 1 0 This bit is set when the SPI2CRx register contains new data. If the SPI/I2C interrupt is enabled, an interrupt is generated when this bit is set. If the SPI2CRx register is not read before the end of the current byte transfer, the transfer stop and the SS is deasserted. 1 1 The SPI2CRx register contains new data. Status Bit for SPI Rx Buffer. When set, the Rx FIFO is full. A read of the SPI2CRx clears this flag Status Bit for SPI Tx Buffer. When set, the Tx FIFO is underflowing and data can be written into SPI2CTx. Write a 0 to this bit to clear it. SPI Transmit Mode Interrupt Flag. Writing new data to the SPI2CTx SFR clears this bit. SPITxIRQ TIMODE Result 0 X The SPI2CTx register is full. 1 0 The SPI2CTx register is empty. 1 1 This bit is set when the SPI2CTx register is empty. If the SPI/I2C interrupt is enabled, an interrupt is generated when this bit is set. If new data is not written into the SPI2CTx SFR before the end of the current byte transfer, the transfer stops, and the SS is deasserted. Write a 0 to this bit to clear it. Status Bit for SPI Tx Buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it.
6
MMERR
0
5
SPIRxOF
0
4
SPIRxIRQ
0
3 2 1
SPIRxBF SPITxUF SPITxIRQ
0 0 0
0
SPITxBF
0
SPI PINS
MISO (Master in, Slave out Data I/O Pin)
The MISO pin is configured as an input line in master mode and as an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte-wide (8-bit) serial data, MSB first.
SCLK (Serial Clock I/O Pin)
The master serial clock (SCLK) is used to synchronize the data being transmitted and received through the MOSI and MISO data lines. The SCLK pin is configured as an output in master mode and as an input in slave mode. In master mode, the bit rate, polarity, and phase of the clock are controlled by the SPI Configuration Register SFR (SPIMOD1, 0xE8) and SPI Configuration Register SFR (SPIMOD2, 0xE9). In slave mode, the SPI Configuration Register SFR (SPIMOD2, 0xE9) must be configured with the phase and polarity of the expected input clock. In both master and slave modes, the data is transmitted on one edge of the SCLK signal and sampled on the other. It is important, therefore, that the SPICPHA and SPICPOL bits are configured the same for the master and slave devices.
MOSI (Master out, Slave in Pin)
The MOSI pin is configured as an output line in master mode and as an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in).The data is transferred as byte-wide (8-bit) serial data, MSB first.
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Preliminary Technical Data
SS (Slave Select Pin)
In SPI slave mode, a transfer is initiated by the assertion of SS low. The SPI port then transmits and receives 8-bit data until the data is concluded by the deassertion of SS. In slave mode, SS is always an input. In SPI master mode, the SS can be used to control data transfer to a slave device. In the automatic slave select control mode, the SS is asserted low to select the slave device and then raised to deselect the slave device after the transfer is complete. Automatic slave select control is enabled by setting the AUTO_SS bit in the SPI Configuration Register SFR (SPIMOD1, 0xE8). In a multimaster system, the SS can be configured as an input so that the SPI peripheral can operate as a slave in some situations and as a master in others. In this case, the slave selects for the slaves controlled by this SPI peripheral should be generated with general I/O pins.
AUTO_SS = 1 SPICONT = 0 SS SCLK
ADE7566/ADE7569
AUTO_SS = 1 SPICONT = 1
DIN
DIN1
DIN2
DOUT
DOUT1
DOUT2
SS SCLK
DIN
DIN1
DIN2
SPI MASTER OPERATING MODES
The double buffered receive and transmit registers can be used to maximize the throughput of the SPI peripheral by continuously streaming out data in master mode. The continuous transmit mode is designed to use the full capacity of the SPI. In this mode, the master transmits and receives data until the SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A) is empty at the start of a byte transfer. Continuous mode is enabled by setting the SPICONT bit in the SPI Configuration Register SFR (SPIMOD2, 0xE9).The SPI peripheral also offers a single byte read and a single byte write function. In master mode, the type of transfer is handled automatically, depending on the configuration of the TIMODE and SPICONT bits in the SPI Configuration Register SFR (SPIMOD2, 0xE9). Table 139 shows the sequence of events that should be performed for each master operating mode. Based on the SS configuration, some of these events take place automatically. Figure 95 shows the SPI output for certain automatic chip select and continuous mode selections. Note that if the continuous mode is not used, a short delay is inserted between transfers.
Table 139. Procedures for Using SPI as a Master
Mode Single Byte Write SPIMOD2[7] = SPICONT Bit 0
DOUT
DOUT1
DOUT2
SS SCLK
AUTO_SS = 0 SPICONT = 0 (MANUAL SS CONTROL)
DIN
DIN1
DIN2
DOUT
DOUT1
DOUT2
Figure 95. Automatic Chip Select and Continuous Mode Output
Note that reading the content of the SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B) should be done using a 2-cycle instruction set such as MOV A or SPI2CRX. Using a 3-cycle instruction such as MOV 0x3D or SPI2CRX will not transfer the right information into the target register.
Continuous
1
Description of Operation Step 1. Write to SPI2CTx SFR. Step 2. SS is asserted low and a write routine is initiated. Step 3. SPITxIRQ interrupt flag is set when SPI2CTx register is empty. Step 4. SS is deasserted high. Step 5. Write to SPI2CTx SFR to clear SPITxIRQ interrupt flag. Step 1. Write to SPI2CTx SFR. Step 2. SS is asserted low and write routine is initiated. Step 3. Wait for SPITxIRQ interrupt flag to write to SPI2CTx SFR. Transfer continues until the SPI2CTx register and transmit shift registers are empty. Step 4. SPITxIRQ interrupt flag is set when SPI2CTx register is empty. Step 5. SS is deasserted high. Step 6. Write to SPI2CTx SFR to clear SPITxIRQ interrupt flag.
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06353-084
ADE7566/ADE7569
SPI INTERRUPT AND STATUS FLAGS
The SPI interface has several status flags that indicate the status of the double buffered receive and transmit registers. Figure 96 shows when the status and interrupt flags are raised. The transmit interrupt occurs when the transmit shift register is loaded with the data in the SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A) register. If the SPI master is in transmit operating mode, and the SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A) register has not been written with new data by the beginning of the next byte transfer, the transmit operation stops. When a new byte of data is received in the SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B) register, the SPI receive interrupt
SCLK (SPICPOL = 1) SCLK (SPICPOL=0)
Preliminary Technical Data
flag is raised. If the data in the SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B) register is not read before new data is ready to be loaded into the SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B), an overflow condition has occurred. This overflow condition, indicated by the SPIRxOF flag, forces the new data to be discarded or overwritten if the RxOFW bit is set.
SPITx SPITxIRQ = 1 TRANSMIT SHIFT REGISTER SPIRx SPIRxIRQ = 1 RECEIVE SHIFT REGISTER
SPITx (EMPTY) STOPS TRANSFER IF TIMODE = 1 TRANSMIT SHIFT REGISTER
SPIRx (FULL)
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SPIRxOF = 1
RECEIVE SHIFT REGISTER
Figure 96. SPI Receive and Transmit Interrupt and Status Flags
SS_b
MISO
? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MOSI SPICPHA = 1 SPIRx AND SPITx FLAGS WITH INTMOD = 1 SPIRx AND SPITx FLAGS WITH INTMOD = 0
? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MISO
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
?
MOSI SPICPHA = 0 SPIRx AND SPITx FLAGS WITH INTMOD = 1
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
?
Figure 97. SPI Timing Configurations
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SPIRx AND SPITx FLAGS WITH INTMOD = 0
Preliminary Technical Data I2C COMPATIBLE INTERFACE
The ADE7566/ADE7569 support a fully licensed I2C interface. The I2C interface is implemented as a full hardware master. SDATA is the data I/O pin, and SCLK is the serial clock. These two pins are shared with the MOSI and SCLK pins of the on-chip SPI interface. Therefore, the user can enable only one interface or the other on these pins at any given time. The SCPS bit in the Configuration SFR (CFG, 0xAF) selects which peripheral is active. The two pins used for data transfer, SDATA and SCLK, are configured in a wire-AND format that allows arbitration in a multimaster system. The transfer sequence of a I C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the address of the slave device and the direction of the data transfer in the initial address transfer. If the slave acknowledges, the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle.
2
ADE7566/ADE7569
The bit rate is defined in the I2CMOD SFR as follows: f SCLK = f CORE 16 × 2 I 2CR[1:0]
SLAVE ADDRESSES
The I2C Slave Address SFR (I2CADR, 0xE9) contains the slave device ID. The LSB of this register contains a read/write request. A write to this SFR starts the I2C communication.
I2C SFR REGISTER LIST
The I2C peripheral interface consists of five SFRs: • • • • • I2CMOD SPI2CSTAT I2CADR SPI2CTx SPI2CRx
SERIAL CLOCK GENERATION
The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (256 kHz) or standard mode (32 kHz).
Because the SPI and I2C serial interfaces share the same pins, they also share the same SFRs, such as the SPI2CTx and SPIXCRx SFRs. In addition, the I2CMOD, I2CADR, SPI2CSTAT, and SPI2CTx SFRs are shared with the SPIMOD1, SPIMOD2, and SPISTAT SFRs, respectively.
Table 140. I2C SFR Register List
SFR Address 0x9A 0x9B 0xE8 0xE9 0xEA Name SPI2CTx SPI2CRx I2CMOD I2CADR SPI2CSTAT R/W W R R/W R/W R/W Length 8 8 8 8 8 Default 0 0 0 0 Description SPI/I2C Data out Register (see Table 134). SPI/I2C Data in Register (see Table 135). I2C Configuration Register (see Table 141). I2C Configuration Register (see Table 142). SPI/I2C Interrupt Status Register (see Table 143).
Table 141. I2C Mode Register SFR (I2CMOD, 0xE8)
Bit No. 7 6 to 5 Address 0xEF 0xEE to 0xED Mnemonic I2CEN I2CR[1:0] Default 0 0 Description I2C Enable Bit. When this bit is set to Logic 1, the I2C interface is enabled. A write to the I2CADR SFR starts a communication. I2C SCLK Frequency. I2CR[1:0] Result 00 fCORE/16 = 256 kHz if fCORE = 4.096 MHz 01 fCORE/32 = 128 kHz if fCORE = 4.096 MHz 10 fCORE/64 = 64 Hz if fCORE = 4.096 MHz 11 fCORE/128= 32 kHz if fCORE = 4.096 MHz Configures the length of the I2C received FIFO buffer. The I2C peripheral stops when I2CRCT, Bit[4:0] + 1 byte have been read or if an error has occurred.
4 to 0
0xEC to 0xE8
I2CRCT[4:0]
0
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ADE7566/ADE7569
Table 142. I2C Slave Address SFR (I2CADR, 0xE9)
Bit No. 7 to 1 0 Mnemonic I2CSLVADR I2CR_W Default 0 0
Preliminary Technical Data
Description Address of the I2C Slave Being Addressed. Writing to this register starts the I2C transmission (read or write). Command Bit for Read or Write. When this bit is set to Logic 1, a read command is transmitted on the I2C bus. Data from slave in the SPI2CRx SFR is expected after command byte. When this bit is set to Logic 0, a write command is transmitted on the I2C bus. Data to slave is expected in the SPI2CTx SFR.
Table 143. I2C Interrupt Status Register SFR (SPI2CSTAT, 0xEA)
Bit No. 7 6 Mnemonic I2CBUSY I2CNOACK Default 0 0 Description This bit is set to Logic 1 when the I2C interface is used. When set, the Tx FIFO is emptied I2C No Acknowledgement Transmit Interrupt. This bit is set to Logic 1 when the slave device does not send an acknowledgement. The I2C communication is stopped after this event. Write a 0 to this bit to clear it. I2C Receive Interrupt. This bit is set to Logic 1 when the receive FIFO is not empty. Write a 0 to this bit to clear it. I2C Transmit Interrupt. This bit is set to Logic 1 when the transmit FIFO is empty. Write a 0 to this bit to clear it. Status Bits for 3- or 4-Bytes Deep I2C FIFO. The FIFO monitored in these 2 bits is the one currently used in I2C communication (receive or transmit) because only one FIFO is active at a time. I2CFIFOSTAT[1:0] Result 00 FIFO empty 01 Reserved 10 FIFO half full 11 FIFO full Set when trying to write and read at the same time. Write a 0 to this bit to clear it. Set when write was attempted when I2C transmit FIFO was full. Write a 0 to this bit to clear it.
5 4 3 to 2
I2CRxIRQ I2CTxIRQ I2CFIFOSTAT[1:0]
0 0 0
1 0
I2CACC_ERR I2CTxWR_ERR
0 0
READ AND WRITE OPERATIONS
Figure 98 and Figure 99 depict I2C read and write operations, respectively. Note that the LSB of the I2CADR register is used to select whether a read or write operation is performed on the slave device. During the read operation, the master acknowledges are generated automatically by the I2C peripheral. The master generated NACK before the end of a read operation is also automatically generated after the I2CRCT, Bits[4:0] bits have been read from the slave. If the I2CADR register is updated during a transmission, instead of generating a stop at the end of the read or write operation, the master generates a start condition and continues with the next communication.
Reading the SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B)
Reading the SPI2CRx SFR should be done with a 2-cycle instruction, such as
Mov a, spi2crx or Mov R0, spi2crx.
A 3-cycle instruction such as
Mov 3dh, spi2crx
will not transfer the right data into RAM Address 0x3d.
1 SCLK 9 1 9 1 9
SDATA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK BY SLAVE
D7
D6
D5
D4
D3
D2
D1
D0 ACK BY MASTER
D7
D6
D5
D4
D3
D2
D1
D0
06353-087
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 DATA BYTE 1 FROM MASTER
FRAME N + 1 DATA BYTE N FROM SLAVE
NACK BY STOP BY MASTER MASTER
Figure 98. I2C Read Operation
1 SCLK 9 1 9
SDATA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK BY SLAVE
D7
D6
D5
D4
D3
D2
D1
D0
06353-088
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 DATA BYTE 1 FROM MASTER
ACK BY SLAVE
STOP BY MASTER
Figure 99. I2C Write Operation
Rev. PrA | Page 126 of 136
Preliminary Technical Data
I2C RECEIVE AND TRANSMIT FIFOS
The I2C peripheral has a 4 byte receive FIFO and a 4 byte transmit FIFO. The buffers reduce the overhead associated with using the I2C peripheral. Figure 100 shows the operation of the I2C receive and transmit FIFOs. The Tx FIFO can be loaded with four bytes to be transmitted to the slave at the beginning of a write operation. When the transmit FIFO is empty, the I2C transmit interrupt flag is set, and the PC vectors to the I2C interrupt vector if this interrupt is enabled. If a new byte is not loaded into the Tx FIFO before it is needed in the transmit shift register, the communication stops. An error, such as not receiving an acknowledge, also causes the communication to terminate. In case of an error during a write operation, the Tx FIFO is flushed. The Rx FIFO allows four bytes to be read in from the slave before the MCU has to read the data. A receive interrupt can
ADE7566/ADE7569
be generated after each byte is received or when the Rx FIFO is full. If the peripheral is reading from a slave address, the communication stops once the number of received bytes equals the number set in the I2CRCT, Bits[4:0]. An error, such as not receiving an acknowledge, also causes the communication to terminate.
CODE TO FILL Tx FIFO: MOV MOV MOV MOV I2CTx, I2CTx, I2CTx, I2CTx, TxDATA1 TxDATA2 TxDATA3 TxDATA4 I2CTx CODE TO READ Rx FIFO: MOV A, MOV A, MOV A, MOV A, I2CRx; I2CRx; I2CRx; I2CRx; RESULT: A = RxDATA1 RESULT: A = RxDATA2 RESULT: A = RxDATA3 RESULT: A = RxDATA4 I2CRx
TxDATA4 4 BYTE FIFO TxDATA3 TxDATA2 TxDATA1 4 BYTE FIFO
RxDATA1 RxDATA2 RxDATA3 RxDATA4
06353-089
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
Figure 100. I2C FIFO Operation
Rev. PrA | Page 127 of 136
ADE7566/ADE7569 DUAL DATA POINTERS
Each ADE7566/ADE7569 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the Data Pointer Control SFR SFR (DPCON, 0xA7). DPCON features automatic hardware post-increment and postdecrement, as well as an automatic data pointer toggle. Note that this section of the data sheet is the only place where the main and shadow data pointers are distinguished. Whenever the data pointer (DPTR) is mentioned elsewhere in the data sheet, active DPTR is implied. In addition, only the MOVC/MOVX @DPTR instructions automatically post-increment and post-decrement the DPTR. Other MOVC/MOVX instructions, such as MOVC PC or MOVC @Ri, do not cause the DPTR to automatically postincrement and post-decrement. To illustrate the operation of DPCON, the following code copies 256 bytes of code memory at Address 0xD000 into XRAM, starting from Address 0x0000:
MOV DPTR,#0
Preliminary Technical Data
;Main DPTR = 0 ;Select shadow DPTR
MOV DPCON,#55H
;DPTR1 increment mode ;DPTR0 increment mode ;DPTR auto toggling ON MOV DPTR,#0D000H ;DPTR = D000H MOVELOOP: CLR A MOVC A,@A+DPTR ;Post Inc DPTR ;Swap to Main DPTR(Data) MOVX @DPTR,A XRAM ;Increment main DPTR ;Swap Shadow DPTR(Code) MOV A, DPL JNZ MOVELOOP ;Put ACC in ;Get data
Table 144. Data Pointer Control SFR SFR (DPCON, 0xA7)
Bit No. 7 6 5, 4 Mnemonic – DPT DP1m1, DP1m0 Default 0 0 0 Description Not Implemented, Write Don’t Care. Data Pointer Automatic Toggle Enable. Cleared by the user to disable auto swapping of the DPTR. Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction. Shadow Data Pointer Mode. These bits enable extra modes of the shadow data pointer operation, allowing more compact and more efficient code size and execution. DP1m1 DP1m0 Result (Behavior of the Shadow Data Pointer) 0 0 8052 behavior. 0 1 DPTR is post-incremented after a MOVX or a MOVC instruction. 1 0 DPTR is post-decremented after a MOVX or MOVC instruction. 1 1 DPTR LSB is toggled after a MOVX or MOVC instruction. This instruction can be useful for moving 8-bit blocks to/from 16-bit devices. Main Data Pointer Mode. These bits enable extra modes of the main data pointer operation, allowing more compact and more efficient code size and execution. DP0m1 DP0m0 Result (Behavior of the Main Data Pointer) 0 0 8052 behavior. 0 1 DPTR is post-incremented after a MOVX or a MOVC instruction. 1 0 DPTR is post-decremented after a MOVX or MOVC instruction. 1 1 DPTR LSB is toggled after a MOVX or MOVC instruction. This instruction is useful for moving 8-bit blocks to/from 16-bit devices. Not Implemented, Write Don’t Care. Data Pointer Select. Cleared by the user to select the main data pointer, meaning that the contents of this 16-bit register are placed into the DPL SFR and DPH SFR. Set by the user to select the shadow data pointer, meaning that the contents of a separate 16-bit register appear in the DPL SRF and DPH SFR.
3, 2
DP0m1, DP0m0
0
1 0
– DPSEL
0 0
Rev. PrA | Page 128 of 136
Preliminary Technical Data I/O PORTS
PARALLEL I/O
The ADE7566/ADE7569 use three input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some are capable of driving an LCD or performing alternate functions for the peripherals available onchip. In general, when a peripheral is enabled, the pins associated with it cannot be used as a general-purpose I/O. The I/O port can be configured through the SFRs in Table 145.
Table 145. I/O Port SFRs
SFR P0 P1 P2 EPCFG PINMAP0 PINMAP1 PINMAP2 Address 0x80 0x90 0xA0 0x9F 0xB2 0xB3 0xB4 Bit Addressable Yes Yes Yes No No No No Description Port 0 Register. Port 1 Register. Port 2 Register. Extended Port Configuration. Port 0 Weak Pull-Up Enable. Port 1 Weak Pull-Up Enable. Port 2 Weak Pull-Up Enable.
ADE7566/ADE7569
Weak Internal Pull-Ups Enabled
A pin with weak internal pull-up enabled is used as an input by writing a 1 to the pin. The pin is pulled high by the internal pullups, and the pin is read using the circuitry shown in Figure 101. If the pin is driven low externally, it sources current because of the internal pull-ups. A pin with internal pull-up enabled is used as an output by writing a 1 or a 0 to the pin to control the level of the output. If a 0 is written to the pin, it drives a logic low output voltage (VOL) and is capable of sinking TBD mA.
Open Drain (Weak Internal Pull-Ups Disabled)
When the weak internal pull-up on a pin is disabled, the pin becomes open-drain. Use this open-drain pin as a high impedance input by writing a 1 to the pin. The pin is read using the circuitry shown in Figure 101. The open drain option is preferable for inputs because it draws less current than the internal pull-ups that were enabled. To use an open-drain pin as a general-purpose output, an external pull-up resistor is required. Open drain outputs are convenient for changing the voltage to a logic high. The ADE7566/ADE7569 are 3.3 V devices, so an external resistor pulled up to 5 V may ease interfacing to a 5 V IC, although most 5 V ICs are tolerant of 3.3 V inputs. Pins with 0s written to them drive a logic low output voltage (VOL) and are capable of sinking 1.6 mA.
The three bidirectional I/O ports have internal pull-ups that can be enabled or disabled individually for each pin. The internal pull-ups are enabled by default. Disabling an internal pull-up causes a pin to become open-drain. Weak internal pull-ups are configured through the PINMAPx SFRs. Figure 101 shows a typical bit latch and I/O buffer for an I/O pin. The bit latch (one bit in the each port’s SFR) is represented as a Type D flip-flop, which clocks in a value from the internal bus in response to a write-to-latch signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a read-latch signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU. Some instructions that read a port activate the read latch signal, and others activate the read pin signal. See the Read-Modify-Write Instructions section for details.
DVDD
38 kHz Modulation
Every ADE7566/ADE7569 provides a 38 kHz modulation signal. The 38 kHz modulation is accomplished by internally XOR’ing the level written to the I/O pin with a 38 kHz square wave. Then, when a 0 is written to the I/O pin, it is modulated as shown in Figure 102.
LEVEL WRITTEN TO MOD38 38kHz MODULATION SIGNAL OUTPUT AT MOD38 PIN
06353-091
Figure 102. 38 kHz Modulation
READ LATCH INTERNAL BUS WRITE TO LATCH
ALTERNATE OUTPUT FUNCTION
INTERNAL PULL-UP CLOSED: PINMAPx.x = 0 OPEN: PINMAPx.x = 1 Px.x PIN
D
Q
Uses for this 38 kHz modulation include IR modulation of a UART transmit signal or a low power signal to drive an LED. The modulation can be enabled or disabled with the MOD38EN bit in the CFG SFR. The 38 kHz modulation is available on 8 pins, selected by the MOD38[7:0] bits in the Extended Port Configuration SFR (EPCFG, 0x9F).
CL Q LATCH
Figure 101. Port 0 Bit Latch and I/O Buffer
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READ PIN
ALTERNATE INPUT FUNCTION
ADE7566/ADE7569
I/O SFR REGISTER LIST
Table 146. Extended Port Configuration SFR (EPCFG, 0x9F)
Bit No. 7 6 5 4 3 2 1 0 Mnemonic MOD38_FP21 MOD38_FP22 MOD38_FP23 MOD38_TxD MOD38_CF1 MOD38_SSb MOD38_MISO MOD38_CF2 Default 0 0 0 0 0 0 0 0
Preliminary Technical Data
Description Enable 38 kHz modulation on P1.6/FP21 pin. Enable 38 kHz modulation on P1.5/FP22 pin. Enable 38 kHz modulation on P1.4/T2/FP23 pin. Enable 38 kHz modulation on P1.1/TxD pin. Enable 38 kHz modulation on P0.2/CF1 pin. Enable 38 kHz modulation on P0.7/SS/T1pin. Enable 38 kHz modulation on P0.5/MISO pin. Enable 38 kHz modulation on P0.3/CF2 pin.
Table 147. Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2)
Bit No. 7 6 5 4 3 2 1 0 Mnemonic PINMAP0.7 PINMAP0.6 PINMAP0.5 PINMAP0.4 PINMAP0.3 PINMAP0.2 PINMAP0.1 PINMAP0.0 Default 0 0 0 0 0 0 0 0 Description The weak pull-up on P0.7 is disabled when this bit is set. The weak pull-up on P0.6 is disabled when this bit is set. The weak pull-up on P0.5 is disabled when this bit is set. The weak pull-up on P0.4 is disabled when this bit is set. The weak pull-up on P0.3 is disabled when this bit is set. The weak pull-up on P0.2 is disabled when this bit is set. The weak pull-up on P0.1 is disabled when this bit is set. The weak pull-up on P0.0 is disabled when this bit is set.
Table 148. Port 1 Weak Pull-Up Enable SFR (PINMAP1, 0xB3)
Bit No. 7 6 5 4 3 2 1 0 Mnemonic PINMAP1.7 PINMAP1.6 PINMAP1.5 PINMAP1.4 PINMAP1.3 PINMAP1.2 PINMAP1.1 PINMAP1.0 Default 0 0 0 0 0 0 0 0 Description The weak pull-up on P1.7 is disabled when this bit is set. The weak pull-up on P1.6 is disabled when this bit is set. The weak pull-up on P1.5 is disabled when this bit is set. The weak pull-up on P1.4 is disabled when this bit is set. The weak pull-up on P1.3 is disabled when this bit is set. The weak pull-up on P1.2 is disabled when this bit is set. The weak pull-up on P1.1 is disabled when this bit is set. The weak pull-up on P1.0 is disabled when this bit is set.
Table 149. Port 2 Weak Pull-Up Enable SFR (PINMAP2, 0xB4)
Bit No. 7 to 6 5 4 3 2 1 0 Mnemonic Reserved PINMAP2.5 Reserved PINMAP2.3 PINMAP2.2 PINMAP2.1 PINMAP2.0 Default 0 0 0 0 0 0 0 Description Reserved. Should be left cleared. The weak pull-up on RESET is disabled when this bit is set. The weak pull-up on EA is disabled when this bit is set. Reserved. Should be left cleared. The weak pull-up on P2.2 is disabled when this bit is set. The weak pull-up on P2.1 is disabled when this bit is set. The weak pull-up on P2.0 is disabled when this bit is set.
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Preliminary Technical Data
Table 150. Port 0 SFR (P0, 0x80)
Bit No. 7 6 5 4 3 2 1 0
1
ADE7566/ADE7569
Description 1 This bit reflects the state of P0.7/SS/T1 pin. It can be written or read. This bit reflects the state of P0.6/SCLK/T0 pin. It can be written or read. This bit reflects the state of P0.5/MISO pin. It can be written or read. This bit reflects the state of P0.4/MOSI/SDATA pin. It can be written or read. This bit reflects the state of P0.3/CF2 pin. It can be written or read. This bit reflects the state of P0.2/CF1 pin. It can be written or read. This bit reflects the state of P0.1/FP19 pin. It can be written or read. This bit reflects the state of BCTRL/INT1/P0.0 pin. It can be written or read.
Address 0x87 0x86 0x85 0x84 0x83 0x82 0x81 0x80
Mnemonic T1 T0
CF2 CF1 INT1
Default 1 1 1 1 1 1 1 1
When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.
Table 151. Port 1 SFR (P1, 0x90)
Bit No. 7 6 5 4 3 2 1 0
1
Address 0x97 0x96 0x95 0x94 0x93 0x92 0x91 0x90
Mnemonic
T2 T2EX TxD RxD
Default 1 1 1 1 1 1 1 1
Description 1 This bit reflects the state of P1.7/FP20 pin. It can be written or read. This bit reflects the state of P1.6/FP2 pin. It can be written or read. This bit reflects the state of P1.5/FP22 pin. It can be written or read. This bit reflects the state of P1.4/T2/FP23 pin. It can be written or read. This bit reflects the state of P1.3/T2EX/FP24 pin. It can be written or read. This bit reflects the state of P1.2/FP25 pin. It can be written or read. This bit reflects the state of P1.1/TxD pin. It can be written or read. This bit reflects the state of P1.0/RxD pin. It can be written or read.
When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.
Table 152. Port 2 SFR (P2, 0xA0)
Bit No. 7 to 2 1 0
1
Address 0x97 to 0x92 0x91 0x90
Mnemonic P2.1 P2.0
Default 0x3F 1 1
Description 1 These bits are unused and should be left set. This bit reflects the state of P2.1/FP17 pin. It can be written or read. This bit reflects the state of P2.0/FP18 pin. It can be written or read.
When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.
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ADE7566/ADE7569
Table 153. Port 0 Alternate Functions
Pin No. P0.0 Alternate Function BCTRL External Battery Control Input INT1 External Interrupt INT1 Wake-up from PSM2 Operating Mode P0.1 P0.2 P0.3 P0.4 FP19 LCD Segment Pin CF1 ADE Calibration Frequency Output CF2 ADE Calibration Frequency Output MOSI SPI Data Line SDATA I2C Data Line P0.5 P0.6 MISO SPI Data Line SCLK Serial Clock for I2C or SPI T0 Timer0 Input P0.7 SS SPI Slave Select Input for SPI in Slave Mode SS SPI Slave Select Output for SPI in Master Mode T1 Timer 1 Input
Preliminary Technical Data
Alternate Function Enable Set INT1PROG[2:0] = X01 in the Interrupt Pins Configuration SFR (INTPR, 0xFF). Set EX1 in the Interrupt Enable SFR (IE, 0xA8). Set INT1PROG[2:0] = 11X in the Interrupt Pins Configuration SFR (INTPR, 0xFF). Set FP19EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). Clear the DISCF1 bit in the ADE energy measurement internal MODE1 Register (0x0B). Clear the DISCF2 bit in the ADE energy measurement internal MODE1 Register (0x0B). Set the SCPS bit in the Configuration SFR (CFG, 0xAF) and set the SPIEN bit in the SPI Configuration Register SFR (SPIMOD2, 0xE9). Clear the SCPS bit in the Configuration SFR (CFG, 0xAF) and set the I2CEN bit in the I2C Mode Register SFR (I2CMOD, 0xE8). Set the SCPS bit in the Configuration SFR (CFG, 0xAF) and set the SPIEN bit in the SPI Configuration Register SFR (SPIMOD2, 0xE9). Set the I2CEN bit in the I2C Mode Register SFR (I2CMOD, 0xE8) or the SPIEN bit in the SPI Configuration Register SFR (SPIMOD2, 0xE9) to enable the I2C or SPI interface. Set the C/T0 bit in the Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89) to enable T0 as an external event counter. Set the SS_EN bit in the SPI Configuration Register SFR (SPIMOD1, 0xE8). Set the SPIMS_b bit in the SPI Configuration Register SFR (SPIMOD2, 0xE9). Set the C/T1 bit in the Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89) to enable T1 as an external event counter.
Table 154. Port 1 Alternate Functions
Pin No. P1.0 Alternate Function RxD Receiver Data Input for UART Rx Edge Wake-up from PSM2 Operating Mode TxD Transmitter Data Output for UART FP25 LCD Segment Pin FP24 LCD Segment Pin T2EX Timer 2 Control Input FP23 LCD Segment Pin T2 Timer 2 Input FP22 LCD Segment Pin FP21 LCD Segment Pin FP20 LCD Segment Pin Alternate Function Enable Set the REN bit in the Serial Communications Control Register Bit Description SFR (SCON, 0x98). Set RXPROG[1:0]=11 in the Peripheral Configuration SFR (PERIPH, 0xF4). This pin becomes TxD as soon as data is written into SBUF. Set FP25EN in the LCD Segment Enable SFR (LCDSEGE, 0x97). Set FP24EN in the LCD Segment Enable SFR (LCDSEGE, 0x97). Set EXEN2 in the Timer/Counter 2 Control SFR (T2CON, 0xC8). Set FP23EN in the LCD Segment Enable SFR (LCDSEGE, 0x97). Set the C/T2 bit in the Timer/Counter 2 Control SFR (T2CON, 0xC8) to enable T2 as an external event counter. Set FP22EN in the LCD Segment Enable SFR (LCDSEGE, 0x97). Set FP21EN in the LCD Segment Enable SFR (LCDSEGE, 0x97). Set FP20EN in the LCD Segment Enable SFR (LCDSEGE, 0x97).
P1.1 P1.2 P1.3 P1.4
P1.5 P1.6 P1.7
Table 155. Port 2 Alternate Functions
Pin No. P2.0 P2.1 P2.2 P2.3 Alternate Function FP18 LCD Segment Pin FP17 LCD Segment Pin FP16 LCD Segment Pin SDEN serial download pin sampled on reset. P2.3 is an output only. Alternate Function Enable Set FP18EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). Set FP17EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). Set FP16EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). Enabled by default.
Rev. PrA | Page 132 of 136
Preliminary Technical Data
PORT 0
Port 0 is controlled directly through the bit-addressable Port 0 SFR (P0, 0x80). The weak internal pull-ups for Port 0 are configured through the Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP0.x. Port 0 pins also have various secondary functions as described in Table 153. The alternate functions of Port 0 pins can be activated only if the corresponding bit latch in the Port 0 SFR contains a 1. Otherwise, the port pin remains at 0.
ADE7566/ADE7569
Port 1 pins also have various secondary functions as described in Table 154. The alternate functions of Port 1 pins can be activated only if the corresponding bit latch in the Port 1 SFR contains a 1. Otherwise, the port pin remains at 0.
PORT 2
Port 2 is a 4-bit bidirectional port controlled directly through the bit-addressable Port 2 SFR (P2, 0xA0). Note that P2.3 can be used as an output only. The weak internal pull-ups for Port 2 are configured through the Port 2 Weak Pull-Up Enable SFR (PINMAP2, 0xB4); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP2.x. Port 2 pins also have various secondary functions as described in Table 155. The alternate functions of Port 2 pins can be activated only if the corresponding bit latch in the Port 2 SFR contains a 1. Otherwise, the port pin remains at 0.
PORT 1
Port 1 is an 8-bit bidirectional port controlled directly through the bit-addressable Port 1 SFR (P1, 0x90). The weak internal pull-ups for Port 1 are configured through the Port 1 Weak Pull-Up Enable SFR (PINMAP1, 0xB3); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP1.x.
Rev. PrA | Page 133 of 136
ADE7566/ADE7569 DETERMINING THE VERSION OF THE ADE7566/ADE7569
Each ADE7566/ADE7569 holds in its internal flash registers a value that defines its version. This value helps to determine if users have the latest version of the part. The ADE7566/ADE756 version corresponding to this datasheet is ADE7566/ADE7569V3.4.
Preliminary Technical Data
To access this value, the following procedure should be followed: 1. 2. 3. 4. 5. Launch HyperTerminal with a 9600 baud rate. Put the part in serial download mode. Hold the SDEN button. Press and release the RESET button. The following string should appear on the HyperTerminal screen: ADE7566/ADE7569V3.4.
Rev. PrA | Page 134 of 136
Preliminary Technical Data OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
1 PIN 1
ADE7566/ADE7569
12.20 12.00 SQ 11.80
64 49 48
TOP VIEW
(PINS DOWN)
10.20 10.00 SQ 9.80
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 7° 3.5° 0°
16 17 32
33
0.08 COPLANARITY
VIEW A
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 103. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters
9.00 BSC SQ
0.60 MAX 0.60 MAX
49 48
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
6.35 6.20 SQ 6.05
0.50 0.40 0.30
33 32
17 16
1.00 0.85 0.80
12° MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF
7.50 REF
SEATING PLANE
051706-A
063006-B
ROTATED 90° CCW
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 104. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters
Rev. PrA | Page 135 of 136
ADE7566/ADE7569
ORDERING GUIDE
Model 1 ADE7566ACPZF8 2 ADE7566ACPZF8-RL2 ADE7566ACPZF162 ADE7566ACPZF16-RL12 ADE7566ASTZF82 ADE7566ASTZF8-RL2 ADE7566ASTZF162 ADE7566ASTZF16-RL2 ADE7569ACPZF162 ADE7569ACPZF16-RL2 ADE7569ASTZF162 ADE7569ASTZF16-RL2 EVAL- ADE7566F16EB EVAL- ADE7569F16EB
1 2
Preliminary Technical Data
VAR No No No No No No No No Yes Yes Yes Yes Flash (kB) 8 8 16 16 8 8 16 16 16 16 16 16 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead LFCSP 64-Lead LFCSP in Reel 64-Lead LFCSP 64-Lead LFCSP in Reel 64-Lead LQFP 64-Lead LQFP in Reel 64-Lead LQFP 64-Lead LQFP in Reel 64-Lead LFCSP 64-Lead LFCSP in Reel 64-Lead LQFP 64-Lead LQFP in Reel ADE7566 Evaluation Board ADE7569 Evaluation Board Package Option CP-64-4 CP-64-4 CP-64-4 CP-64-4 ST-64-2 ST-64-2 ST-64-2 ST-64-2 CP-64-4 CP-64-4 ST-64-2 ST-64-2
Antitaper No No No No No No No No No No No No
All models have W + VA + rms, 5 V LCD, and RTC. Z = RoHS Compliant Part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06353-0-8/07(PrA)
Rev. PrA | Page 136 of 136
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