ADE7758ARWZRL

Poly Phase Multifunction Energy Metering IC with Per Phase Information ADE7758 Data Sheet FEATURES Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time Reference 2.4 V (drift 30 ppm/°C typical) with external overdrive capability Single 5 V supply, low power (70 mW typical) Highly accurate; supports IEC 60687, IEC 61036, IEC 61268, IEC 62053-21, IEC 62053-22, and IEC 62053-23 Compatible with 3-phase/3-wire, 3-phase/4-wire, and other 3-phase services Less than 0.1% active energy error over a dynamic range of 1000 to 1 at 25°C Supplies active/reactive/apparent energy, voltage rms, current rms, and sampled waveform data Two pulse outputs, one for active power and the other selectable between reactive and apparent power with programmable frequency Digital power, phase, and rms offset calibration On-chip, user-programmable thresholds for line voltage SAG and overvoltage detections An on-chip, digital integrator enables direct interface-tocurrent sensors with di/dt output A PGA in the current channel allows direct interface to current transformers An SPI®-compatible serial interface with IRQ GENERAL DESCRIPTION The ADE7758 is a high accuracy, 3-phase electrical energy measurement IC with a serial interface and two pulse outputs. The ADE7758 incorporates second-order Σ-Δ ADCs, a digital integrator, reference circuitry, a temperature sensor, and all the signal processing required to perform active, reactive, and apparent energy measurement and rms calculations. The ADE7758 is suitable to measure active, reactive, and apparent energy in various 3-phase configurations, such as WYE or DELTA services, with both three and four wires. The ADE7758 provides system calibration features for each phase, that is, rms offset correction, phase calibration, and power calibration. The APCF logic output gives active power information, and the VARCF logic output provides instantaneous reactive or apparent power information. FUNCTIONAL BLOCK DIAGRAM 4 12 PGA1 + IAN 6 – VAP AVRMSGAIN[11:0] 7 PGA1 + IBN 8 – VBP 15 ICP ICN VCP VN 9 10 14 13 dt HPF ADC REACTIVE OR APPARENT POWER INTEGRATOR DFC ADC ADC PGA2 + – ADC ÷ 17 VARCF 1 APCF 3 DVDD 2 DGND 19 CLKIN 20 CLKOUT LPF2 VARCFDEN[ 11:0] AVARG[11:0] Φ PHASE B AND PHASE C DATA AWATTOS[11:0] ACTIVE/REACTIVE/AP PARENT ENERGIES AND VOLTAGE/CURRENT RMS CALCUL ATION FOR PHASE B (SEE PHASE A FOR DETAILED SIGNAL PATH) AWG[11:0] ACTIVE POWER APCFNUM[11:0] % VADIV[7:0] % VARDIV[7:0] DFC % WDIV[7:0] – VARCFNUM[ 11:0] AIRMSOS[11:0] LPF2 ADC – 90° PHASE SHIFTING FILTER π 2 AVAROS[11:0] APHCAL[6:0] PGA2 + PGA1 + AVRMSOS[11:0] X2 ADC – IBP AVAG[11:0] LPF PGA2 + 16 ADE7758 4kΩ 2.4V REF 5 11 | X| POWER SUPPLY MONITOR IAP AGND ACTIVE/REACTIVE/AP PARENT ENERGIES AND VOLTAGE/CURRENT RMS CALCUL ATION FOR PHASE C (SEE PHASE A FOR DETAILED SIGNAL PATH) ÷ APCFDEN[ 11:0] ADE7758 REGISTERS AND SERIAL INTERFACE 22 24 23 21 18 DIN DOUT SCLK CS IRQ 04443-001 REFIN/OUT AVDD Figure 1. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved. ADE7758 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Temperature Measurement ....................................................... 27  General Description ......................................................................... 1  Root Mean Square Measurement............................................. 28  Functional Block Diagram .............................................................. 1  Active Power Calculation .......................................................... 30  General Description ......................................................................... 4  Reactive Power Calculation ...................................................... 35  Specifications..................................................................................... 5  Apparent Power Calculation..................................................... 39  Timing Characteristics ................................................................ 6  Energy Registers Scaling ........................................................... 41  Timing Diagrams.............................................................................. 7  Waveform Sampling Mode ....................................................... 41  Absolute Maximum Ratings............................................................ 8  Calibration................................................................................... 42  ESD Caution.................................................................................. 8  Checksum Register..................................................................... 55  Pin Configuration and Function Descriptions............................. 9  Interrupts..................................................................................... 55  Terminology .................................................................................... 11  Using the Interrupts with an MCU.......................................... 56  Typical Performance Characteristics ........................................... 12  Interrupt Timing ........................................................................ 56  Test Circuits..................................................................................... 17  Serial Interface ............................................................................ 56  Theory of Operation ...................................................................... 18  Serial Write Operation............................................................... 57  Antialiasing Filter ....................................................................... 18  Serial Read Operation................................................................ 59  Analog Inputs.............................................................................. 18  Accessing the On-Chip Registers............................................. 59  Current Channel ADC............................................................... 19  Registers........................................................................................... 60  di/dt Current Sensor and Digital Integrator............................... 20  Communications Register......................................................... 60  Peak Current Detection ............................................................. 21  Operational Mode Register (0x13) .......................................... 64  Overcurrent Detection Interrupt ............................................. 21  Measurement Mode Register (0x14) ....................................... 64  Voltage Channel ADC ............................................................... 22  Waveform Mode Register (0x15) ............................................. 65  Zero-Crossing Detection........................................................... 23  Computational Mode Register (0x16)..................................... 66  Phase Compensation.................................................................. 23  Line Cycle Accumulation Mode Register (0x17) ................... 67  Period Measurement .................................................................. 25  Interrupt Mask Register (0x18) ................................................ 68  Line Voltage SAG Detection ..................................................... 25  Interrupt Status Register (0x19)/Reset Interrupt Status Register (0x1A)........................................................................... 69  SAG Level Set.............................................................................. 26  Peak Voltage Detection.............................................................. 26  Phase Sequence Detection......................................................... 26  Outline Dimensions ....................................................................... 70  Ordering Guide .......................................................................... 70  Power-Supply Monitor............................................................... 27  Reference Circuit ........................................................................ 27  Revision History 10/11—Rev. D to Rev. E Changes to Figure 1.......................................................................... 1 Changes to Figure 41...................................................................... 19 Changes to Figure 60...................................................................... 27 Added Figure 61; Renumbered Sequentially .............................. 27 Changes to Phase Sequence Detection Section .......................... 27 Changes to Power-Supply Monitor Section ................................ 27 Changes to Figure 62...................................................................... 28 Changes to Figure 67...................................................................... 32 Changes to Figure 68...................................................................... 32 Changes to Equation 25................................................................. 34 Changes to Figure 69...................................................................... 34 Changes to Table 17 ....................................................................... 62 Change to Table 18 ......................................................................... 64 Changes to Table 24 ....................................................................... 69 Changes to Ordering Guide .......................................................... 70 10/08—Rev. C to Rev. D Changes to Figure 1...........................................................................1 Changes to Phase Sequence Detection Section and Figure 60. 27 Rev. E | Page 2 of 72 Data Sheet ADE7758 Changes to Current RMS Calculation Section............................28 Changes to Voltage Channel RMS Calculation Section and Figure 63 ...........................................................................................29 Changes to Table 17 ........................................................................60 Changes to Ordering Guide...........................................................70 7/06—Rev. B to Rev. C Updated Format.................................................................. Universal Changes to Figure 1...........................................................................1 Changes to Table 2 ............................................................................6 Changes to Table 4 ............................................................................9 Changes to Figure 34 and Figure 35 .............................................17 Changes to Current Waveform Gain Registers Section and Current Channel Sampling Section ..............................................19 Changes to Voltage Channel Sampling Section ..........................22 Changes to Zero-Crossing Timeout Section ...............................23 Changes to Figure 60 ......................................................................27 Changes to Current RMS Calculation Section............................28 Changes to Current RMS Offset Compensation Section and Voltage Channel RMS Calculation Section .................................29 Added Table 7 and Table 9; Renumbered Sequentially..............29 Changes to Figure 65 ......................................................................30 Changes to Active Power Offset Calibration Section.................31 Changes to Reactive Power Frequency Output Section.............38 Changes to Apparent Power Frequency Output Section and Waveform Sampling Mode Section ..............................................41 Changes to Gain Calibration Using Line Accumulation Section ....................................................................49 Changes to Example: Power Offset Calibration Using Line Accumulation Section ....................................................................53 Changes to Calibration of IRMS and VRMS Offset Section.....54 Changes to Table 18 ........................................................................64 Changes to Table 20 ........................................................................65 11/05—Rev. A to Rev. B Changes to Table 1 ............................................................................5 Changes to Figure 23 Caption .......................................................14 Changes to Current Waveform Gain Registers Section .............19 Changes to di/dt Current Sensor and Digital Integrator Section............................................................................20 Changes to Phase Compensation Section....................................23 Changes to Figure 57 ......................................................................25 Changes to Figure 60 ......................................................................27 Changes to Temperature Measurement Section and Root Mean Square Measurement Section ............................28 Inserted Table 6................................................................................28 Changes to Current RMS Offset Compensation Section ..........29 Inserted Table 7................................................................................29 Added Equation 17 .........................................................................31 Changes to Energy Accumulation Mode Section.......................33 Changes to the Reactive Power Calculation Section..................35 Added Equation 32...........................................................................36 Changes to Energy Accumulation Mode Section.......................38 Changes to the Reactive Power Frequency Output Section ......38 Changes to the Apparent Energy Calculation Section...............40 Changes to the Calibration Section ..............................................42 Changes to Figure 76 through Figure 84............................... 43–54 Changes to Table 15 ........................................................................59 Changes to Table 16 ........................................................................63 Changes to Ordering Guide...........................................................69 9/04—Rev. 0 to Rev. A Changed Hexadecimal Notation...................................... Universal Changes to Features List...................................................................1 Changes to Specifications Table ......................................................5 Change to Figure 25........................................................................16 Additions to the Analog Inputs Section.......................................19 Added Figures 36 and 37; Renumbered Subsequent Figures....19 Changes to Period Measurement Section ....................................26 Change to Peak Voltage Detection Section .................................26 Added Figure 60 ..............................................................................27 Change to the Current RMS Offset Compensation Section .....29 Edits to Active Power Frequency Output Section ......................33 Added Figure 68; Renumbered Subsequent Figures ..................33 Changes to Reactive Power Frequency Output Section.............37 Added Figure 73; Renumbered Subsequent Figures ..................38 Change to Gain Calibration Using Pulse Output Example .......44 Changes to Equation 37 .................................................................45 Changes to Example—Phase Calibration of Phase A Using Pulse Output.........................................................................45 Changes to Equations 56 and 57 ...................................................53 Addition to the ADE7758 Interrupts Section .............................54 Changes to Example-Calibration of RMS Offsets ......................54 Addition to Table 20 .......................................................................66 1/04—Revision 0: Initial Version Rev. E | Page 3 of 72 ADE7758 Data Sheet GENERAL DESCRIPTION The ADE7758 has a waveform sample register that allows access to the ADC outputs. The part also incorporates a detection circuit for short duration low or high voltage variations. The voltage threshold levels and the duration (number of half-line cycles) of the variation are user programmable. A zero-crossing detection is synchronized with the zero-crossing point of the line voltage of any of the three phases. This information can be used to measure the period of any one of the three voltage inputs. The zero-crossing detection is used inside the chip for the line cycle energy accumulation mode. This mode permits faster and more accurate calibration by synchronizing the energy accumulation with an integer number of line cycles. Data is read from the ADE7758 via the SPI serial interface. The interrupt request output (IRQ) is an open-drain, active low logic output. The IRQ output goes active low when one or more interrupt events have occurred in the ADE7758. A status register indicates the nature of the interrupt. The ADE7758 is available in a 24-lead SOIC package. Rev. E | Page 4 of 72 Data Sheet ADE7758 SPECIFICATIONS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = −40°C to +85°C. Table 1. Parameter 1, 2 ACCURACY Active Energy Measurement Error (per Phase) Phase Error Between Channels PF = 0.8 Capacitive PF = 0.5 Inductive AC Power Supply Rejection Output Frequency Variation DC Power Supply Rejection Output Frequency Variation Active Energy Measurement Bandwidth IRMS Measurement Error IRMS Measurement Bandwidth VRMS Measurement Error VRMS Measurement Bandwidth ANALOG INPUTS Maximum Signal Levels Input Impedance (DC) ADC Offset Error 3 Gain Error3 WAVEFORM SAMPLING Current Channels Signal-to-Noise Plus Distortion Bandwidth (−3 dB) Voltage Channels Signal-to-Noise Plus Distortion Bandwidth (−3 dB) REFERENCE INPUT REFIN/OUT Input Voltage Range Input Capacitance ON-CHIP REFERENCE Reference Error Current Source Output Impedance Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS DIN, SCLK, CLKIN, and CS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN Specification Unit Test Conditions/Comments 0.1 % typ Over a dynamic range of 1000 to 1 ±0.05 ±0.05 °max °max 0.01 % typ 0.01 14 0.5 14 0.5 260 % typ kHz % typ kHz % typ Hz ±500 380 ±30 ±6 mV max kΩ min mV max % typ 62 14 dB typ kHz 62 260 dB typ Hz 2.6 2.2 10 V max V min pF max Line frequency = 45 Hz to 65 Hz, HPF on Phase lead 37° Phase lag 60° AVDD = DVDD = 5 V + 175 mV rms/120 Hz V1P = V2P = V3P = 100 mV rms AVDD = DVDD = 5 V ± 250 mV dc V1P = V2P = V3P = 100 mV rms Over a dynamic range of 500:1 Over a dynamic range of 20:1 See the Analog Inputs section Differential input Uncalibrated error, see the Terminology section External 2.5 V reference Sampling CLKIN/128, 10 MHz/128 = 78.1 kSPS See the Current Channel ADC section See the Voltage Channel ADC section 2.4 V + 8% 2.4 V − 8% Nominal 2.4 V at REFIN/OUT pin ±200 6 4 30 mV max μA max kΩ min ppm/°C typ 15 5 MHz max MHz min 2.4 0.8 ±3 10 V min V max μA max pF max All specifications CLKIN of 10 MHz Rev. E | Page 5 of 72 DVDD = 5 V ± 5% DVDD = 5 V ± 5% Typical 10 nA, VIN = 0 V to DVDD ADE7758 Data Sheet Parameter 1, 2 LOGIC OUTPUTS IRQ, DOUT, and CLKOUT Output High Voltage, VOH Output Low Voltage, VOL APCF and VARCF Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY AVDD DVDD AIDD DIDD Specification Unit 4 0.4 V min V max 4 1 V min V max 4.75 5.25 4.75 5.25 8 13 V min V max V min V max mA max mA max Test Conditions/Comments DVDD = 5 V ± 5% IRQ is open-drain, 10 kΩ pull-up resistor ISOURCE = 5 mA ISINK = 1 mA ISOURCE = 8 mA ISINK = 5 mA For specified performance 5 V − 5% 5 V + 5% 5 V − 5% 5 V + 5% Typically 5 mA Typically 9 mA 1 See the Typical Performance Characteristics. See the Terminology section for a definition of the parameters. 3 See the Analog Inputs section. 2 TIMING CHARACTERISTICS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = −40°C to +85°C. Table 2. Parameter 1, 2 WRITE TIMING t1 t2 t3 t4 t5 t6 t7 t8 READ TIMING t9 3 t10 t11 4 t12 5 t135 Specification Unit Test Conditions/Comments 50 50 50 10 5 1200 400 100 ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) CS falling edge to first SCLK falling edge SCLK logic high pulse width SCLK logic low pulse width Valid data setup time before falling edge of SCLK Data hold time after SCLK falling edge Minimum time between the end of data byte transfers Minimum time between byte transfers during a serial write CS hold time after SCLK falling edge 4 μs (min) 50 30 100 10 100 10 ns (min) ns (min) ns (max) ns (min) ns (max) ns (min) Minimum time between read command (that is, a write to communication register) and data read Minimum time between data byte transfers during a multibyte read Data access time after SCLK rising edge following a write to the communications register Bus relinquish time after falling edge of SCLK Bus relinquish time after rising edge of CS 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. See the timing diagrams in Figure 3 and Figure 4 and the Serial Interface section. 3 Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min. 4 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. 5 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted here is the true bus relinquish time of the part and is independent of the bus loading. 2 Rev. E | Page 6 of 72 Data Sheet ADE7758 TIMING DIAGRAMS 200µA 2.1V CL 50pF 1.6mA IOH 04443-002 TO OUTPUT PIN IOL Figure 2. Load Circuit for Timing Specifications t8 CS t6 t3 SCLK t4 t2 A6 1 DIN A5 t7 t7 A4 t5 A3 A2 A1 DB7 A0 MOST SIGNIFICANT BYTE COMMAND BYTE DB0 DB7 DB0 LEAST SIGNIFICANT BYTE 04443-003 t1 Figure 3. Serial Write Timing CS t1 t13 t9 SCLK 0 A6 A5 A4 A3 A2 A1 A0 t12 t11 DOUT DB7 COMMAND BYTE DB0 MOST SIGNIFICANT BYTE Figure 4. Serial Read Timing Rev. E | Page 7 of 72 DB7 DB0 LEAST SIGNIFICANT BYTE 04443-004 DIN t10 ADE7758 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to AGND DVDD to DGND DVDD to AVDD Analog Input Voltage to AGND, IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP, VCP, VN Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Industrial Range Storage Temperature Range Junction Temperature 24-Lead SOIC, Power Dissipation θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating –0.3 V to +7 V –0.3 V to +7 V –0.3 V to +0.3 V –6 V to +6 V ESD CAUTION –0.3 V to AVDD + 0.3 V –0.3 V to DVDD + 0.3 V –0.3 V to DVDD + 0.3 V –40°C to +85°C –65°C to +150°C 150°C 88 mW 53°C/W 215°C 220°C Rev. E | Page 8 of 72 Data Sheet ADE7758 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS APCF 1 24 DOUT DGND 2 23 SCLK DVDD 3 22 DIN AVDD 4 21 CS IAP 5 ADE7758 CLKOUT TOP VIEW 19 CLKIN (Not to Scale) IBP 7 18 IRQ 20 IBN 8 17 VARCF ICP 9 16 VAP ICN 10 15 VBP AGND 11 14 VCP REFIN/OUT 12 13 VN 04443-005 IAN 6 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic APCF 2 DGND 3 DVDD 4 AVDD 5, 6, 7, 8, 9, 10 IAP, IAN, IBP, IBN, ICP, ICN 11 AGND 12 REFIN/OUT 13, 14, 15, 16 VN, VCP, VBP, VAP Description Active Power Calibration Frequency (APCF) Logic Output. It provides active power information. This output is used for operational and calibration purposes. The full-scale output frequency can be scaled by writing to the APCFNUM and APCFDEN registers (see the Active Power Frequency Output section). This provides the ground reference for the digital circuitry in the ADE7758, that is, the multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7758 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. However, high bus capacitance on the DOUT pin can result in noisy digital current that could affect performance. Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7758. The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7758. The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. The Typical Performance Characteristics show the power supply rejection performance. This pin should be decoupled to AGND with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. Analog Inputs for Current Channel. This channel is used with the current transducer and is referenced in this document as the current channel. These inputs are fully differential voltage inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the gain selections of the internal PGA (see the Analog Inputs section). All inputs have internal ESD protection circuitry. In addition, an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage. This pin provides the ground reference for the analog circuitry in the ADE7758, that is, ADCs, temperature sensor, and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, for example, antialiasing filters, current, and voltage transducers. To keep ground noise around the ADE7758 to a minimum, the quiet ground plane should be connected to the digital ground plane at only one point. It is acceptable to place the entire device on the analog ground plane. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source can also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic capacitor. Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is referenced as the voltage channels in this document. These inputs are single-ended voltage inputs with the maximum signal level of ±0.5 V with respect to VN for specified operation. These inputs are voltage inputs with maximum input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the gain selections of the internal PGA (see the Analog Inputs section). All inputs have internal ESD protection circuitry, and in addition, an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage. Rev. E | Page 9 of 72 ADE7758 Pin No. 17 Mnemonic VARCF 18 IRQ 19 CLKIN 20 CLKOUT 21 CS 22 DIN 23 SCLK 24 DOUT Data Sheet Description Reactive Power Calibration Frequency Logic Output. It gives reactive power or apparent power information depending on the setting of the VACF bit of the WAVMODE register. This output is used for operational and calibration purposes. The full-scale output frequency can be scaled by writing to the VARCFNUM and VARCFDEN registers (see the Reactive Power Frequency Output section). Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include: an active energy register at half level, an apparent energy register at half level, and waveform sampling up to 26 kSPS (see the Interrupts section). Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7758. The clock frequency for specified operation is 10 MHz. Ceramic load capacitors of a few tens of picofarad should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for the load capacitance requirements A crystal can be connected across this pin and CLKIN as previously described to provide a clock source for the ADE7758. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. Chip Select. Part of the 4-wire serial interface. This active low logic input allows the ADE7758 to share the serial bus with several other devices (see the Serial Interface section). Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK (see the Serial Interface section). Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this clock (see the Serial Interface section). The SCLK has a Schmidt-trigger input for use with a clock source that has a slow edge transition time, for example, opto-isolator outputs. Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output is normally in a high impedance state, unless it is driving data onto the serial data bus (see the Serial Interface section). Rev. E | Page 10 of 72 Data Sheet ADE7758 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7758 is defined by Measuremen t Error = Energy Registered by ADE7758 – True Energy True Energy × 100% (1) Phase Error Between Channels The high-pass filter (HPF) and digital integrator introduce a slight phase mismatch between the current and the voltage channel. The all-digital design ensures that the phase matching between the current channels and voltage channels in all three phases is within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2° over a range of 40 Hz to 1 kHz. This internal phase mismatch can be combined with the external phase error (from current sensor or component tolerance) and calibrated with the phase calibration registers. Power Supply Rejection (PSR) This quantifies the ADE7758 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when an ac signal (175 mV rms/100 Hz) is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading—see the Measurement Error definition. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when the power supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading. ADC Offset Error This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND that the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection (see the Typical Performance Characteristics section). However, when HPFs are switched on, the offset is removed from the current channels and the power calculation is not affected by this offset. Gain Error The gain error in the ADCs of the ADE7758 is defined as the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC section and the Voltage Channel ADC section). The difference is expressed as a percentage of the ideal code. Gain Error Match The gain error match is defined as the gain error (minus the offset) obtained when switching between a gain of 1, 2, or 4. It is expressed as a percentage of the output ADC code obtained under a gain of 1. Rev. E | Page 11 of 72 ADE7758 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.20 PF = 1 0.4 0.15 0.3 PERCENT ERROR (%) PERCENT ERROR (%) 0.10 0.2 0.1 +25°C 0 –40°C –0.1 –0.2 PF = +0.5, –40°C 0.05 PF = –0.5, +25°C 0 –0.05 PF = +0.5, +85°C PF = +0.5, +25°C –0.10 –0.4 –0.5 0.01 –0.15 04443-006 +85°C 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 04443-009 –0.3 –0.20 0.01 100 Figure 6. Active Energy Error as a Percentage of Reading (Gain = +1) over Temperature with Internal Reference and Integrator Off 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 9. Active Energy Error as a Percentage of Reading (Gain = +1) over Temperature with External Reference and Integrator Off 0.3 0.6 0.5 PF = +0.5, +25°C PF = +1, +25°C 0 –0.1 PF = –0.5, +25°C PF = +0.5, +85°C –0.2 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 0.2 0.1 0 PF = 0.5 –0.1 –0.2 PF = +0.5, –40°C –0.3 0.01 PF = 1 0.3 04443-010 0.1 PERCENT ERROR (%) WITH RESPECT TO 55Hz 0.4 04443-007 PERCENT ERROR (%) 0.2 –0.3 –0.4 45 100 Figure 7. Active Energy Error as a Percentage of Reading (Gain = +1) over Power Factor with Internal Reference and Integrator Off 47 49 51 53 55 57 59 LINE FREQUENCY (Hz) 61 63 65 Figure 10. Active Energy Error as a Percentage of Reading (Gain = +1) over Frequency with Internal Reference and Integrator Off 0.3 0.10 PF = 1 PF = 1 0.08 0.2 PERCENT ERROR (%) WITH RESPECT TO 5V; 3A GAIN = +4 0 –0.1 GAIN = +1 GAIN = +2 VDD = 5.25V 0.02 0 –0.02 VDD = 5V –0.04 VDD = 4.75V 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) –0.08 –0.10 0.01 100 Figure 8. Active Energy Error as a Percentage of Reading over Gain with Internal Reference and Integrator Off 04443-011 –0.3 0.01 0.04 –0.06 –0.2 04443-008 PERCENT ERROR (%) 0.06 0.1 0.1 1 10 100 PERCENT FULL-SCALE CURRENT (%) Figure 11. Active Energy Error as a Percentage of Reading (Gain = +1) over Power Supply with Internal Reference and Integrator Off Rev. E | Page 12 of 72 Data Sheet ADE7758 0.3 0.25 PF = 1 0.20 0.2 0.15 PERCENT ERROR (%) ALL PHASES 0.05 0 –0.05 PHASE B –0.10 PHASE C –0.15 PF = 0, +85°C 0 –0.1 PF = 0, +25°C PF = 0, –40°C 04443-012 –0.2 –0.20 –0.25 0.01 0.1 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 04443-015 PERCENT ERROR (%) PHASE A 0.10 –0.3 0.01 100 Figure 12. APCF Error as a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) Figure 15. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Temperature with External Reference and Integrator Off 0.4 0.3 PF = +0.866, –40°C 0.3 0.2 PF = –0.866, +25°C PERCENT ERROR (%) 0.1 PF = 0, +25°C 0 PF = 0, –40°C –0.1 –0.2 0 PF = +0.866, +85°C PF = +0.866, +25°C –0.2 04443-013 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) –0.3 0.01 100 Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Temperature with Internal Reference and Integrator Off 0.8 0.6 0.6 PERCENT ERROR (%) WITH RESPECT TO 55Hz 0.4 PF = 0, +25°C PF = –0.866, +25°C 0 –0.2 PF = +0.866, –40°C PF = +0.866, +25°C –0.4 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 16. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Power Factor with External Reference and Integrator Off 0.8 0.2 PF = 0, +25°C –0.1 PF = 0, +85°C –0.3 PERCENT ERROR (%) 0.1 04443-016 PERCENT ERROR (%) 0.2 –0.4 0.01 100 0.4 PF = 0 0.2 0 –0.2 PF = 0.866 –0.4 PF = +0.866, +85°C 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) –0.8 45 100 Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Power Factor with Internal Reference and Integrator Off 04443-017 –0.8 0.01 –0.6 04443-014 –0.6 47 49 51 53 55 57 59 LINE FREQUENCY (Hz) 61 63 65 Figure 17. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Frequency with Internal Reference and Integrator Off Rev. E | Page 13 of 72 ADE7758 Data Sheet 0.10 0.3 0.08 0.2 5.25V 0.04 PERCENT ERROR (%) 5V 0.02 0 –0.02 –0.04 0 +25°C –0.1 4.75V –0.06 +85°C –0.10 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) –0.3 0.01 100 Figure 18. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Supply with Internal Reference and Integrator Off 04443-021 04443-018 –0.2 –0.08 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 21. Active Energy Error as a Percentage of Reading (Gain = +4) over Temperature with Internal Reference and Integrator On 0.3 0.5 PF = 0 0.2 0.4 0.3 GAIN = +2 GAIN = +4 PERCENT ERROR (%) PERCENT ERROR (%) –40°C 0.1 0.1 0 GAIN = +1 –0.1 0.2 0.1 0 –0.1 04443-019 –0.3 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) PF = +1, +25°C –0.2 –0.3 –0.2 PF = +0.5, –40°C PF = +0.5, +25°C PF = –0.5, +25°C PF = +0.5, +85°C 04443-022 PERCENT ERROR (%) WITH RESPECT TO 5V; 3A 0.06 –0.4 –0.5 0.01 100 Figure 19. Reactive Energy Error as a Percentage of Reading over Gain with Internal Reference and Integrator Off 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 22. Active Energy Error as a Percentage of Reading (Gain = +4) over Power Factor with Internal Reference and Integrator On 0.8 0.4 PF = 1 0.6 0.3 PF = –0.866, –40°C PERCENT ERROR (%) PHASE C 0 –0.1 –0.2 PHASE B PHASE A 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) PF = 0, +25°C 0 –0.2 PF = +0.866, +25°C PF = –0.866, +25°C –0.4 –0.3 –0.4 0.01 0.2 –0.6 –0.8 0.01 100 Figure 20. VARCF Error as a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off PF = –0.866, +85°C 04443-023 0.1 0.4 ALL PHASES 04443-020 PERCENT ERROR (%) 0.2 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 23. Reactive Energy Error as a Percentage of Reading (Gain = +4) over Power Factor with Internal Reference and Integrator On Rev. E | Page 14 of 72 Data Sheet ADE7758 0.4 0.8 PF = 0 0.6 0.3 0.4 0.1 0 +25°C –0.1 –0.2 –0.3 0 –0.2 04443-024 +85°C –0.5 0.01 –0.6 PF = 1 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) –1.0 –1.2 0.01 100 Figure 24. Reactive Energy Error as a Percentage of Reading (Gain = +4) over Temperature with Internal Reference and Integrator On 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 27. IRMS Error as a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off 0.5 0.8 0.4 0.6 0.3 0.4 PERCENT ERROR (%) 0.2 0.1 PF = 0.5 –0.1 –0.2 PF = 1 51 53 55 57 59 LINE FREQUENCY (Hz) 61 63 PF = +1 –0.2 –0.4 –0.8 04443-025 –0.4 49 PF = –0.5 0 –0.6 –0.3 47 0.2 –1.0 0.1 65 Figure 25. Active Energy Error as a Percentage of Reading (Gain = +4) over Frequency with Internal Reference and Integrator On 04443-028 0 –0.5 45 PF = 0.5 –0.4 –0.8 –0.4 PERCENT ERROR (%) 0.2 04443-027 –40°C PERCENT ERROR (%) PERCENT ERROR (%) 0.2 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 28. IRMS Error as a Percentage of Reading (Gain = +4) with Internal Reference and Integrator On 1.2 0.4 1.0 0.3 0.8 0.4 PERCENT ERROR (%) PERCENT ERROR (%) 0.2 0.6 PF = 0 0.2 0 PF = 0.866 –0.2 0.1 0 –0.1 –0.2 –0.4 47 49 51 53 55 57 59 LINE FREQUENCY (Hz) 61 63 –0.4 65 Figure 26. Reactive Energy Error as a Percentage of Reading (Gain = +4) over Frequency with Internal Reference and Integrator On Rev. E | Page 15 of 72 04443-029 –0.8 45 –0.3 04443-026 –0.6 1 10 VOLTAGE (V) 100 Figure 29. VRMS Error as a Percentage of Reading (Gain = +1) with Internal Reference ADE7758 Data Sheet 1.5 21 MEAN: 6.5149 SD: 2.816 18 1.0 15 0.5 +25°C HITS 0 12 9 –0.5 6 +85°C –1.0 04443-030 3 –1.5 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 0 100 Figure 30. Apparent Energy Error as a Percentage of Reading (Gain = +1) over Temperature with Internal Reference and Integrator Off 04443-032 PERCENT ERROR (%) –40°C –2 0 2 4 6 8 CH 1 PhB OFFSET (mV) 10 12 Figure 32. Phase B Channel 1 Offset Distribution 12 MEAN: 5.55393 SD: 3.2985 MEAN: 6.69333 SD: 2.70443 18 10 15 8 HITS 6 9 4 6 0 –4 –2 0 2 4 6 8 CH 1 PhA OFFSET (mV) 10 0 12 04443-033 2 3 04443-031 HITS 12 2 4 6 8 10 CH 1 PhC OFFSET (mV) 12 14 Figure 33. Phase C Channel 1 Offset Distribution Figure 31. Phase A Channel 1 Offset Distribution Rev. E | Page 16 of 72 Data Sheet ADE7758 TEST CIRCUITS VDD CURRENT 10µF TRANSFORMER I 100nF 4 RB 3 17 AVDD DVDD VARCF APCF 1 5 IAP 1kΩ 825Ω PS2501-1 1 4 2 3 33nF 1kΩ 6 TO FREQ. COUNTER ADE7758 IAN 22pF 33nF CLKOUT 20 7 IBP SAME AS IAP, IAN 10MHz 8 IBN CLKIN 19 9 ICP DOUT 24 10 ICN SCLK 23 16 VAP SAME AS VAP 15 VBP SAME AS VAP 14 VCP 22pF SAME AS IAP, IAN 1MΩ 220V 1kΩ CT TURN RATIO 1800:1 CHANNEL 2 GAIN = +1 IRQ 18 REFIN/OUT 12 VN 13 1kΩ 100nF AGND DGND 11 10µF 2 33nF RB 10Ω 5Ω 2.5Ω 1.25Ω 04443-034 CHANNEL 1 GAIN 1 2 4 8 TO SPI BUS CS 21 DIN 22 33nF Figure 34. Test Circuit for Integrator Off VDD di/dt SENSOR I 100nF 10µF 4 1kΩ 1kΩ 33nF 33nF 1kΩ 1kΩ 33nF 33nF 3 17 AVDD DVDD VARCF APCF 1 5 IAP 6 825Ω PS2501-1 4 2 3 TO FREQ. COUNTER ADE7758 IAN 1 22pF CLKOUT 20 7 IBP SAME AS IAP, IAN 10MHz 8 IBN CLKIN 19 9 ICP DOUT 24 10 ICN SCLK 23 16 VAP SAME AS VAP 15 VBP SAME AS VAP 14 VCP 22pF 1MΩ 220V 1kΩ CS 21 CHANNEL 1 GAIN = +8 CHANNEL 2 GAIN = +1 1kΩ TO SPI BUS DIN 22 33nF IRQ 18 REFIN/OUT 12 VN 13 AGND DGND 11 100nF 10µF 2 33nF Figure 35. Test Circuit for Integrator On Rev. E | Page 17 of 72 04443-035 SAME AS IAP, IAN ADE7758 Data Sheet THEORY OF OPERATION V2 This filter prevents aliasing, which is an artifact of all sampled systems. Input signals with frequency components higher than half the ADC sampling rate distort the sampled signal at a frequency below half the sampling rate. This happens with all ADCs, regardless of the architecture. The combination of the high sampling rate ∑-Δ ADC used in the ADE7758 with the relatively low bandwidth of the energy meter allows a very simple lowpass filter (LPF) to be used as an antialiasing filter. A simple RC filter (single pole) with a corner frequency of 10 kHz produces an attenuation of approximately 40 dB at 833 kHz. This is usually sufficient to eliminate the effects of aliasing. ANALOG INPUTS The ADE7758 has six analog inputs divided into two channels: current and voltage. The current channel consists of three pairs of fully differential voltage inputs: IAP and IAN, IBP and IBN, and ICP and ICN. These fully differential voltage input pairs have a maximum differential signal of ±0.5 V. The current channel has a programmable gain amplifier (PGA) with possible gain selection of 1, 2, or 4. In addition to the PGA, the current channels also have a full-scale input range selection for the ADC. The ADC analog input range selection is also made using the gain register (see Figure 38). As mentioned previously, the maximum differential input voltage is ±0.5 V. However, by using Bit 3 and Bit 4 in the gain register, the maximum ADC input voltage can be set to ±0.5 V, ±0.25 V, or ±0.125 V on the current channels. This is achieved by adjusting the ADC reference (see the Reference Circuit section). +500mV VAP, VBP, OR VCP SINGLE-ENDED INPUT ±500mV MAX PEAK VCM COMMON-MODE ±25mV MAX Figure 37. Maximum Signal Levels, Voltage Channels, Gain = 1 The gain selections are made by writing to the gain register. Bit 0 to Bit 1 select the gain for the PGA in the fully differential current channel. The gain selection for the PGA in the singleended voltage channel is made via Bit 5 to Bit 6. Figure 38 shows how a gain selection for the current channel is made using the gain register. GAIN (K) SELECTION IAP, IBP, ICP VIN Figure 39 shows how the gain settings in PGA 1 (current channel) and PGA 2 (voltage channel) are selected by various bits in the gain register. GAIN REGISTER1 CURRENT AND VOLTAGE CHANNEL PGA CONTROL V1 IAN, IBN, OR ICN –500mV INTEGRATOR ENABLE 0 = DISABLE 1 = ENABLE PGA 2 GAIN SELECT 00 = ×1 01 = ×2 10 = ×4 Figure 36. Maximum Signal Levels, Current Channels, Gain = 1 The voltage channel has three single-ended voltage inputs: VAP, VBP, and VCP. These single-ended voltage inputs have a maximum input voltage of ±0.5 V with respect to VN. Both the current and voltage channel have a PGA with possible gain selections of 1, 2, or 4. The same gain is applied to all the inputs of each channel. Figure 37 shows the maximum signal levels on the voltage channel inputs. The maximum common-mode signal is ±25 mV, as shown in Figure 36. 1REGISTER 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 RESERVED ADDRESS: 0x23 PGA 1 GAIN SELECT 00 = ×1 01 = ×2 10 = ×4 CURRENT INPUT FULL-SCALE SELECT 00 = 0.5V 01 = 0.25V 10 = 0.125V CONTENTS SHOW POWER-ON DEFAULTS Figure 39. Analog Gain Register Bit 7 of the gain register is used to enable the digital integrator in the current signal path. Setting this bit activates the digital integrator (see the DI/DT Current Sensor and Digital Integrator section). Rev. E | Page 18 of 72 04443-039 IAP, IBP, OR ICP V2 04443-038 Figure 38. PGA in Current Channel 04443-036 VCM K × VIN IAN, IBN, ICN V1 + V2 COMMON-MODE ±25mV MAX VCM AGND –500mV +500mV DIFFERENTIAL INPUT V1 + V2 = 500mV MAX PEAK VN GAIN[7:0] Figure 36 shows the maximum signal levels on the current channel inputs. The maximum common-mode signal is ±25 mV, as shown in Figure 37. VCM V2 04443-037 ANTIALIASING FILTER Data Sheet ADE7758 When in waveform sample mode, one of four output sample rates can be chosen by using Bit 5 and Bit 6 of the WAVMODE register (DTRT[1:0]). The output sample rate can be 26.04 kSPS, 13.02 kSPS, 6.51 kSPS, or 3.25 kSPS. By setting the WFSM bit in the interrupt mask register to Logic 1, the interrupt request output IRQ goes active low when a sample is available. The timing is shown in Figure 40. The 24-bit waveform samples are transferred from the ADE7758 one byte (8-bits) at a time, with the most significant byte shifted out first. CURRENT CHANNEL ADC Figure 41 shows the ADC and signal processing path for the input IA of the current channels (same for IB and IC). In waveform sampling mode, the ADC outputs are signed twos complement 24-bit data-words at a maximum of 26.0 kSPS (thousand samples per second). With the specified full-scale analog input signal of ±0.5 V, the ADC produces its maximum output code value (see Figure 41). This diagram shows a fullscale voltage signal being applied to the differential inputs IAP and IAN. The ADC output swings between 0xD7AE14 (−2,642,412) and 0x2851EC (+2,642,412). IRQ SCLK DIN The waveform samples of the current channel can be routed to the WFORM register at fixed sampling rates by setting the WAVSEL[2:0] bit in the WAVMODE register to 000 (binary) (see Table 20). The phase in which the samples are routed is set by setting the PHSEL[1:0] bits in the WAVMODE register. Energy calculation remains uninterrupted during waveform sampling. DOUT Figure 40. Current Channel Waveform Sampling The interrupt request output IRQ stays low until the interrupt routine reads the reset status register (see the Interrupts section). REFERENCE PGA1 VIN GAIN[7] GAIN[1:0] ×1, ×2, ×4 DIGITAL INTEGRATOR 1 ADC SGN CURRENT CHANNE L DATA–24 BITS GAIN[4:3] 2.42V, 1.21V, 0.6V IAP READ FROM WAVEFORM 0x12 0 04443-040 Current Channel Sampling HPF CURRENT RMS (IRMS) CALCULATION WAVEFORM SAMPLE REGISTER ACTIVE AND REACTIVE POWER CALCULATION IAN 50Hz CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE AFTER INTEGRATOR (50Hz AND AIGAIN[11:0] = 0x000) 0x34D1B8 CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE 0x2851EC 0V 0x000000 ANALOG INPUT RANGE 0x000000 0xCB2E48 60Hz CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE AFTER INTEGRATOR (60Hz AND AIGAIN[11:0] = 0x000) 0x2BE893 0xD7AE14 ADC OUTPUT WORD RANGE 1WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED. Figure 41. Current Channel Signal Path Rev. E | Page 19 of 72 0x000000 0xD4176D 04443-041 VIN 0.5V/GAIN 0.25V/GAIN 0.125V/GAIN ADE7758 Data Sheet 80 DI/DT CURRENT SENSOR AND DIGITAL INTEGRATOR 81 82 The di/dt sensor detects changes in the magnetic field caused by the ac current. Figure 42 shows the principle of a di/dt current sensor. PHASE (Degrees) 83 MAGNETIC FIELD CREATED BY CURRENT (DIRECTLY PROPORTIONAL TO CURRENT) 84 85 86 87 88 04443-044 89 90 91 10 04443-042 + EMF (ELECTROMOTIVE FORCE) – INDUCED BY CHANGES IN MAGNETIC FLUX DENSITY (di/dt) 100 1k FREQUENCY (Hz) 10k Figure 44. Combined Phase Response of the Digital Integrator and Phase Compensator Figure 42. Principle of a di/dt Current Sensor The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. The changes in the magnetic flux density passing through a conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal that is proportional to the di/dt of the current. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current carrying conductor and the di/dt sensor. 5 MAGNITUDE (dB) 4 The current signal needs to be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form. The ADE7758 has a builtin digital integrator to recover the current signal from the di/dt sensor. The digital integrator on Channel 1 is disabled by default when the ADE7758 is powered up. Setting the MSB of the GAIN[7:0] register turns on the integrator. Figure 43 to Figure 46 show the magnitude and phase response of the digital integrator. 3 2 1 –1 40 04443-045 0 45 50 55 60 FREQUENCY (Hz) 65 70 Figure 45. Combined Gain Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz) 20 89.80 10 89.85 PHASE (Degrees) –10 –20 –30 89.90 89.95 90.00 –40 100 1k FREQUENCY (Hz) 90.10 40 10k Figure 43. Combined Gain Response of the Digital Integrator and Phase Compensator 04443-046 –50 10 90.05 04443-043 GAIN (dB) 0 45 50 55 60 FREQUENCY (Hz) 65 Figure 46. Combined Phase Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz) Rev. E | Page 20 of 72 70 Data Sheet ADE7758 Note that the integrator has a −20 dB/dec attenuation and approximately −90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. However, the di/dt sensor has a 20 dB/dec gain associated with it and generates significant high frequency noise. A more effective antialiasing filter is needed to avoid noise due to aliasing (see the Theory of Operation section). When the digital integrator is switched off, the ADE7758 can be used directly with a conventional current sensor, such as a current transformer (CT) or a low resistance current shunt. Note that the number of half-line cycles is based on counting the zero crossing of the voltage channel. The ZXSEL[2:0] bits in the LCYCMODE register determine which voltage channels are used for the zero-crossing detection. The same signal is also used for line cycle energy accumulation mode if activated (see the Line Cycle Accumulation Mode Register (0X17) section). OVERCURRENT DETECTION INTERRUPT Figure 48 illustrates the behavior of the overcurrent detection. CURRENT PEAK WAVEFORM BEING MONITORED (SELECTED BY PKIRQSEL[2:0] IN MMODE REGISTER) PEAK CURRENT DETECTION IPINTLVL[7:0] The ADE7758 can be programmed to record the peak of the current waveform and produce an interrupt if the current exceeds a preset limit. Peak Current Detection Using the PEAK Register The peak absolute value of the current waveform within a fixed number of half-line cycles is stored in the IPEAK register. Figure 47 illustrates the timing behavior of the peak current detection. PKI INTERRUPT FLAG (BIT 15 OF STATUS REGISTER) L2 READ RSTATUS REGISTER 04443-048 PKI RESET LOW WHEN RSTATUS REGISTER IS READ L1 Figure 48. ADE7758 Overcurrent Detection CURRENT WAVEFORM (PHASE SELECTED BY PEAKSEL[2:0] IN MMODE REGISTER) CONTENT OF IPEAK[7:0] 00 L1 L2 04443-047 NO. OF HALF LINE CYCLES SPECIFIED BY LINECYC[15:0] REGISTER L1 Figure 47. Peak Current Detection Using the IPEAK Register Note that the content of the IPEAK register is equivalent to Bit 14 to Bit 21 of the current waveform sample. At full-scale analog input, the current waveform sample is 0x2851EC. The IPEAK at full-scale input is therefore expected to be 0xA1. Note that the content of the IPINTLVL[7:0] register is equivalent to Bit 14 to Bit 21 of the current waveform sample. Therefore, setting this register to 0xA1 represents putting peak detection at full-scale analog input. Figure 48 shows a current exceeding a threshold. The overcurrent event is recorded by setting the PKI flag (Bit 15) in the interrupt status register. If the PKI enable bit is set to Logic 1 in the interrupt mask register, the IRQ logic output goes active low (see the Interrupts section). Similar to peak level detection, multiple phases can be activated for peak detection. If any of the active phases produce waveform samples above the threshold, the PKI flag in the interrupt status register is set. The phase of which overcurrent is monitored is set by the PKIRQSEL[2:0] bits in the MMODE register (see Table 19). In addition, multiple phases can be activated for the peak detection simultaneously by setting more than one of the PEAKSEL[2:4] bits in the MMODE register to logic high. These bits select the phase for both voltage and current peak measurements. Note that if more than one bit is set, the VPEAK and IPEAK registers can hold values from two different phases, that is, the voltage and current peak are independently processed (see the Peak Current Detection section). Rev. E | Page 21 of 72 ADE7758 Data Sheet PHASE CALIBRATION VAP VA TO ACTIVE AND REACTIVE ENERGY CALCULATION Φ GAIN[6:5] ×1, ×2, ×4 + PGA – PHCAL[6:0] TO VOLTAGE RMS CALCULATION AND WAVEFORM SAMPLING ADC LPF1 VN f3dB = 260Hz 50Hz LPF OUTPUT WORD RANGE 0x2797 VA 0V ANALOG INPUT RANGE 0.5V GAIN 0x0 0x2852 0xD869 0x0 60Hz 0xD7AE LPF OUTPUT WORD RANGE 0x2748 04443-049 0x0 0xD8B8 Figure 49. ADC and Signal Processing in Voltage Channel 0 VOLTAGE CHANNEL ADC Voltage Channel Sampling The waveform samples on the voltage channels can also be routed to the WFORM register. However, before passing to the WFORM register, the ADC outputs pass through a single-pole, low-pass filter (LPF1) with a cutoff frequency at 260 Hz. Figure 50 shows the magnitude and phase response of LPF1. This filter attenuates the signal slightly. For example, if the line frequency is 60 Hz, the signal at the output of LPF1 is attenuated by 3.575%. The waveform samples are 16-bit, twos complement data ranging between 0x2748 (+10,056d) and 0xD8B8 (−10,056d). The data is sign extended to 24-bit in the WFORM register. H(f )= 1 ⎛ 60 Hz ⎞ ⎟ 1+ ⎜ ⎜ 260 Hz ⎟ ⎝ ⎠ 2 = 0.974 = −0.225 dB (3) –20 (60Hz; –13°) –40 –20 –60 –30 –80 10 100 FREQUENCY (Hz) –40 1k GAIN (dB) –10 04443-050 For active and reactive energy measurements, the output of the ADC passes to the multipliers directly and is not filtered. This solution avoids the much larger multibit multiplier and does not affect the accuracy of the measurement. An HPF is not implemented on the voltage channel to remove the dc offset because the HPF on the current channel alone should be sufficient to eliminate error due to ADC offsets in the power calculation. However, ADC offset in the voltage channels produces large errors in the voltage rms calculation and affects the accuracy of the apparent energy calculation. (60Hz; –0.2dB) PHASE (Degrees) Figure 49 shows the ADC and signal processing chain for the input VA in the voltage channel. The VB and VC channels have similar processing chains. 0 Figure 50. Magnitude and Phase Response of LPF1 Note that LPF1 does not affect the active and reactive energy calculation because it is only used in the waveform sampling signal path. However, waveform samples are used for the voltage rms calculation and the subsequent apparent energy accumulation. The WAVSEL[2:0] bits in the WAVMODE register should be set to 001 (binary) to start the voltage waveform sampling. The PHSEL[1:0] bits control the phase from which the samples are routed. In waveform sampling mode, one of four output sample rates can be chosen by changing Bit 5 and Bit 6 of the WAVMODE register (see Table 20). The available output sample rates are 26.0 kSPS, 13.5 kSPS, 6.5 kSPS, or 3.3 kSPS. By setting the WFSM bit in the interrupt mask register to Logic 1, the interrupt request output IRQ goes active low when a sample is available. The 24bit waveform samples are transferred from the ADE7758 one byte (8 bits) at a time, with the most significant byte shifted out first. The sign of the register is extended in the upper 8 bits. The timing is the same as for the current channels, as seen in Figure 40. Rev. E | Page 22 of 72 Data Sheet ADE7758 every time a zero crossing is detected on its associated input. The default value of ZXTOUT is 0xFFFF. If the internal register decrements to 0 before a zero crossing at the corresponding input is detected, it indicates an absence of a zero crossing in the time determined by the ZXTOUT[15:0]. The ZXTOx detection bit of the corresponding phase in the interrupt status register is then switched on (Bit 6 to Bit 8). An active low on the IRQ output also appears if the ZXTOx mask bit for the corresponding phase in the interrupt mask register is set to Logic 1. Figure 52 shows the mechanism of the zero-crossing timeout detection when the Line Voltage A stays at a fixed dc level for more than 384/CLKIN × ZXTOUT[15:0] seconds. ZERO-CROSSING DETECTION The ADE7758 has zero-crossing detection circuits for each of the voltage channels (VAN, VBN, and VCN). Figure 51 shows how the zero-cross signal is generated from the output of the ADC of the voltage channel. GAIN[6:5] ×1, ×2, ×4 VAN, VBN, VCN PGA REFERENCE ZEROCROSSING DETECTOR ADC LPF1 f–3dB = 260Hz 24.8° @ 60Hz 1.0 0.908 ANALOG VOLTAGE WAVEFORM (VAN, VBN, OR VCN) 16-BIT INTERNAL REGISTER VALUE LPF1 OUTPUT ZXTOUT[15:0] IRQ 04443-051 VOLTAGE CHANNEL A READ RSTATUS The zero-crossing interrupt is generated from the output of LPF1. LPF1 has a single pole at 260 Hz (CLKIN = 10 MHz). As a result, there is a phase lag between the analog input signal of the voltage channel and the output of LPF1. The phase response of this filter is shown in the Voltage Channel Sampling section. The phase lag response of LPF1 results in a time delay of approximately 1.1 ms (at 60 Hz) between the zero crossing on the voltage inputs and the resulting zero-crossing signal. Note that the zero-crossing signal is used for the line cycle accumulation mode, zero-crossing interrupt, and line period/frequency measurement. When one phase crosses from negative to positive, the corresponding flag in the interrupt status register (Bit 9 to Bit 11) is set to Logic 1. An active low in the IRQ output also appears if the corresponding ZX bit in the interrupt mask register is set to Logic 1. Note that only zero crossing from negative to positive generates an interrupt. The flag in the interrupt status register is reset to 0 when the interrupt status register with reset (RSTATUS) is read. Each phase has its own interrupt flag and mask bit in the interrupt register. Zero-Crossing Timeout Each zero-crossing detection has an associated internal timeout register (not accessible to the user). This unsigned, 16-bit register is decreased by 1 every 384/CLKIN seconds. The registers are reset to a common user-programmed value, that is, the zero-crossing timeout register (ZXTOUT[15:0], Address 0x1B), READ RSTATUS 04443-052 ZXTOA DETECTION BIT Figure 51. Zero-Crossing Detection on Voltage Channels Figure 52. Zero-Crossing Timeout Detection PHASE COMPENSATION When the HPF in the current channel is disabled, the phase error between the current channel (IA, IB, or IC) and the corresponding voltage channel (VA, VB, or VC) is negligible. When the HPF is enabled, the current channels have phase response (see Figure 53 through Figure 55). The phase response is almost 0 from 45 Hz to 1 kHz. The frequency band is sufficient for the requirements of typical energy measurement applications. However, despite being internally phase compensated, the ADE7758 must work with transducers that may have inherent phase errors. For example, a current transformer (CT) with a phase error of 0.1° to 0.3° is not uncommon. These phase errors can vary from part to part, and they must be corrected to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7758 provides a means of digitally calibrating these small phase errors. The ADE7758 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for the small phase errors. The phase calibration registers (APHCAL, BPHCAL, and CPHCAL) are twos complement, 7-bit sign-extended registers that can vary the time advance in the voltage channel signal path from +153.6 μs to −75.6 μs (CLKIN = 10 MHz), Rev. E | Page 23 of 72 ADE7758 Data Sheet 0.20 0.15 PHASE (Degrees) Figure 56 illustrates how the phase compensation is used to remove a 0.1° phase lead in IA of the current channel from the external current transducer. To cancel the lead (0.1°) in the current channel of Phase A, a phase lead must be introduced into the corresponding voltage channel. The resolution of the phase adjustment allows the introduction of a phase lead of 0.104°. The phase lead is achieved by introducing a time advance into VA. A time advance of 4.8 μs is made by writing −2 (0x7E) to the time delay block (APHCAL[6:0]), thus reducing the amount of time delay by 4.8 μs or equivalently, 360° × 4.8 μs × 60 Hz = 0.104° at 60 Hz. 80 60 0 –0.10 40 45 50 55 60 FREQUENCY (Hz) 65 70 Figure 54. Phase Response of the HPF and Phase Compensation (40 Hz to 70 Hz) 0.10 0.08 50 0.06 0.04 0.02 0 40 04443-055 PHASE (Degrees) 70 0.05 –0.05 PHASE (Degrees) 90 0.10 04443-054 respectively. Negative values written to the PHCAL registers represent a time advance, and positive values represent a time delay. One LSB is equivalent to 1.2 μs of time delay or 2.4 μs of time advance with a CLKIN of 10 MHz. With a line frequency of 60 Hz, this gives a phase resolution of 0.026° (360° × 1.2 μs × 60 Hz) at the fundamental in the positive direction (delay) and 0.052° in the negative direction (advance). This corresponds to a total correction range of −3.32° to +1.63° at 60 Hz. –0.02 30 44 20 0 0 100 200 300 400 500 600 FREQUENCY (Hz) 700 800 900 48 50 52 FREQUENCY (Hz) 54 56 Figure 55. Phase Response of HPF and Phase Compensation (44 Hz to 56 Hz) 04443-053 10 46 1k Figure 53. Phase Response of the HPF and Phase Compensation (10 Hz to 1 kHz) Rev. E | Page 24 of 72 Data Sheet ADE7758 IAP PGA1 IA ADC IAN ACTIVE AND REACTIVE ENERGY CALCULATION RANGE OF PHASE CALIBRATION VAP PGA2 VA DIGITAL INTEGRATOR HPF ADC +1.36°, –2.76° @ 50Hz; 0.022°, 0.043° +1.63°, –3.31° @ 60Hz; 0.026°, 0.052° VN 6 0 1 1 1 1 1 0 0 VA 0.1° VA IA APHCAL[6:0] –153.6µs TO +75.6µs VA ADVANCED BY 4.8µs (+0.104 ° @ 60Hz) 0x7E 60Hz 60Hz 04443-056 IA Figure 56. Phase Calibration on Voltage Channels The ADE7758 provides the period or frequency measurement of the line voltage. The period is measured on the phase specified by Bit 0 to Bit 1 of the MMODE register. The period register is an unsigned 12-bit FREQ register and is updated every four periods of the selected phase. If the SAG enable bit is set to Logic 1 for this phase (Bit 1 to Bit 3 in the interrupt mask register), the IRQ logic output goes active low (see the Interrupts section). The phases are compared to the same parameters defined in the SAGLVL and SAGCYC registers. VAP, VBP, OR VCP FULL-SCALE Bit 7 of the LCYCMODE selects whether the period register displays the frequency or the period. Setting this bit causes the register to display the period. The default setting is logic low, which causes the register to display the frequency. When set to measure the period, the resolution of this register is 96/CLKIN per LSB (9.6 μs/LSB when CLKIN is 10 MHz), which represents 0.06% when the line frequency is 60 Hz. At 60 Hz, the value of the period register is 1737d. At 50 Hz, the value of the period register is 2084d. When set to measure frequency, the value of the period register is approximately 960d at 60 Hz and 800d at 50 Hz. This is equivalent to 0.0625 Hz/LSB. SAGLVL[7:0] SAGCYC[7:0] = 0x06 6 HALF CYCLES SAG INTERRUPT FLAG (BIT 3 TO BIT 5 OF STATUS REGISTER) SAG EVENT RESET LOW WHEN VOLTAGE CHANNEL EXCEEDS SAGLVL[7:0] LINE VOLTAGE SAG DETECTION The ADE7758 can be programmed to detect when the absolute value of the line voltage of any phase drops below a certain peak value for a number of half cycles. Each phase of the voltage channel is controlled simultaneously. This condition is illustrated in Figure 57. Figure 57 shows a line voltage fall below a threshold, which is set in the SAG level register (SAGLVL[7:0]), for nine half cycles. Because the SAG cycle register indicates a six half-cycle threshold (SAGCYC[7:0] = 0x06), the SAG event is recorded at the end of the sixth half cycle by setting the SAG flag of the corresponding phase in the interrupt status register (Bit 1 to Bit 3 in the interrupt status register). READ RSTATUS REGISTER 04443-057 PERIOD MEASUREMENT Figure 57. ADE7758 SAG Detection Figure 57 shows a line voltage fall below a threshold, which is set in the SAG level register (SAGLVL[7:0]), for nine half cycles. Because the SAG cycle register indicates a six half-cycle threshold (SAGCYC[7:0] = 0x06), the SAG event is recorded at the end of the sixth half cycle by setting the SAG flag of the corresponding phase in the interrupt status register (Bit 1 to Bit 3 in the interrupt status register). If the SAG enable bit is set to Logic 1 for this phase (Bit 1 to Bit 3 in the interrupt mask register), the IRQ logic output goes active low (see the Interrupts section). The phases are compared to the same parameters defined in the SAGLVL and SAGCYC registers. Rev. E | Page 25 of 72 ADE7758 Data Sheet SAG LEVEL SET The contents of the single-byte SAG level register, SAGLVL[0:7], are compared to the absolute value of Bit 6 to Bit 13 from the voltage waveform samples. For example, the nominal maximum code of the voltage channel waveform samples with a full-scale signal input at 60 Hz is 0x2748 (see the Voltage Channel Sampling section). Bit 13 to Bit 6 are 0x9D. Therefore, writing 0x9D to the SAG level register puts the SAG detection level at full scale and sets the SAG detection to its most sensitive value. The detection is made when the content of the SAGLVL[7:0] register is greater than the incoming sample. Writing 0x00 puts the SAG detection level at 0. The detection of a decrease of an input voltage is disabled in this case. Note that if more than one bit is set, the VPEAK and IPEAK registers can hold values from two different phases, that is, the voltage and current peak are independently processed (see the Peak Current Detection section). Note that the number of half-line cycles is based on counting the zero crossing of the voltage channel. The ZXSEL[2:0] bits in the LCYCMODE register determine which voltage channels are used for the zero-crossing detection (see Table 22). The same signal is also used for line cycle energy accumulation mode if activated. Overvoltage Detection Interrupt Figure 59 illustrates the behavior of the overvoltage detection. VOLTAGE PEAK WAVEFORM BEING MONITORED (SELECTED BY PKIRQSEL[5:7] IN MMODE REGISTER) PEAK VOLTAGE DETECTION The ADE7758 can record the peak of the voltage waveform and produce an interrupt if the current exceeds a preset limit. VPINTLVL[7:0] Peak Voltage Detection Using the VPEAK Register The peak absolute value of the voltage waveform within a fixed number of half-line cycles is stored in the VPEAK register. Figure 58 illustrates the timing behavior of the peak voltage detection. L2 PKV INTERRUPT FLAG (BIT 14 OF STATUS REGISTER) L1 READ RSTATUS REGISTER VOLTAGE WAVEFORM (PHASE SELECTED BY PEAKSEL[2:4] IN MMODE REGISTER) Figure 59. ADE7758 Overvoltage Detection 00 L1 L2 04443-058 NO. OF HALF LINE CYCLES SPECIFIED BY LINECYC[15:0] REGISTER CONTENT OF VPEAK[7:0] 04443-059 PKV RESET LOW WHEN RSTATUS REGISTER IS READ L1 Figure 58. Peak Voltage Detection Using the VPEAK Register Note that the content of the VPEAK register is equivalent to Bit 6 to Bit 13 of the 16-bit voltage waveform sample. At fullscale analog input, the voltage waveform sample at 60 Hz is 0x2748. The VPEAK at full-scale input is, therefore, expected to be 0x9D. In addition, multiple phases can be activated for the peak detection simultaneously by setting multiple bits among the PEAKSEL[2:4] bits in the MMODE register. These bits select the phase for both voltage and current peak measurements. Note that the content of the VPINTLVL[7:0] register is equivalent to Bit 6 to Bit 13 of the 16-bit voltage waveform samples; therefore, setting this register to 0x9D represents putting the peak detection at full-scale analog input. Figure 59 shows a voltage exceeding a threshold. By setting the PKV flag (Bit 14) in the interrupt status register, the overvoltage event is recorded. If the PKV enable bit is set to Logic 1 in the interrupt mask register, the IRQ logic output goes active low (see the Interrupts section). Multiple phases can be activated for peak detection. If any of the active phases produce waveform samples above the threshold, the PKV flag in the interrupt status register is set. The phase in which overvoltage is monitored is set by the PKIRQSEL[5:7] bits in the MMODE register (see Table 19). PHASE SEQUENCE DETECTION The ADE7758 has an on-chip phase sequence error detection interrupt. This detection works on phase voltages and considers all associated zero crossings. The regular succession of these zero crossings events is a negative to positive transition on Phase A, followed by a positive to negative transition on Phase C, followed by a negative to positive transition on Phase B, and so on. Rev. E | Page 26 of 72 Data Sheet ADE7758 On the ADE7758, if the regular succession of the zero crossings presented above happens, the SEQERR bit (Bit 19) in the STATUS register is set (Figure 60). If SEQERR is set in the mask register, the IRQ logic output goes active low (see the Interrupts section). monitor threshold. The power supply and decoupling for the part should be designed such that the ripple at AVDD does not exceed 5 V ± 5% as specified for normal operation. AVDD 5V 4V 0V To have the ADE7758 trigger SEQERR status bit when the zero crossing regular succession does not occur, the analog inputs for Phase C and Phase B should be swapped. In this case, the Phase B voltage input should be wired to the VCP pin, and the Phase C voltage input should be wired to the VBP pin. B = –120° A = 0° C B A C B A C B A C SEQERR BIT OF STATUS REGISTER IS SET 04443-060 A Figure 60. Regular Phase Sequence Sets SEQERR Bit to 1 C = –120° A = 0° B = +120° A B C A B C A B C A SEQERR BIT OF STATUS REGISTER IS NOT SET B 04443-160 VOLTAGE WAVEFORMS ZERO CROSSINGS INACTIVE ACTIVE INACTIVE Figure 62. On-Chip, Power-Supply Monitoring REFERENCE CIRCUIT The nominal reference voltage at the REFIN/OUT pin is 2.42 V. This is the reference voltage used for the ADCs in the ADE7758. However, the current channels have three input range selections (full scale is selectable among 0.5 V, 0.25 V, and 0.125 V). This is achieved by dividing the reference internally by 1, ½, and ¼. The reference value is used for the ADC in the current channels. Note that the full-scale selection is only available for the current inputs. C = +120° VOLTAGE WAVEFORMS ZERO CROSSINGS ADE7758 INTERNAL CALCULATIONS TIME 04443-061 If the regular zero crossing succession does not occur, that is when a negative to positive transition on Phase A followed by a positive to negative transition on Phase B, followed by a negative to positive transition on Phase C, and so on, the SEQERR bit (Bit 19) in the STATUS register is cleared to 0. Figure 61. Erroneous Phase Sequence Clears SEQERR Bit to 0 The REFIN/OUT pin can be overdriven by an external source, for example, an external 2.5 V reference. Note that the nominal reference value supplied to the ADC is now 2.5 V and not 2.42 V. This has the effect of increasing the nominal analog input signal range by 2.5/2.42 × 100% = 3% or from 0.5 V to 0.5165 V. The voltage of the ADE7758 reference drifts slightly with temperature; see the Specifications section for the temperature coefficient specification (in ppm/°C). The value of the temperature drift varies from part to part. Because the reference is used for all ADCs, any ×% drift in the reference results in a 2×% deviation of the meter accuracy. The reference drift resulting from temperature changes is usually very small and typically much smaller than the drift of other components on a meter. Alternatively, the meter can be calibrated at multiple temperatures. POWER-SUPPLY MONITOR TEMPERATURE MEASUREMENT The ADE7758 also contains an on-chip power-supply monitor. The analog supply (AVDD) is monitored continuously by the ADE7758. If the supply is less than 4 V ± 5%, the ADE7758 goes into an inactive state, that is, no energy is accumulated when the supply voltage is below 4 V. This is useful to ensure correct device operation at power-up and during power-down. The power-supply monitor has built-in hysteresis and filtering. This gives a high degree of immunity to false triggering due to noisy supplies. When AVDD returns above 4 V ± 5%, the ADE7758 waits 18 μs for the voltage to achieve the recommended voltage range, 5 V ± 5% and then becomes ready to function. Figure 62 shows the behavior of the ADE7758 when the voltage of AVDD falls below the power-supply The ADE7758 also includes an on-chip temperature sensor. A temperature measurement is made every 4/CLKIN seconds. The output from the temperature sensing circuit is connected to an ADC for digitizing. The resultant code is processed and placed in the temperature register (TEMP[7:0]). This register can be read by the user and has an address of 0x11 (see the Serial Interface section). The contents of the temperature register are signed (twos complement) with a resolution of 3°C/LSB. The offset of this register may vary significantly from part to part. To calibrate this register, the nominal value should be measured, and the equation should be adjusted accordingly. Rev. E | Page 27 of 72 ADE7758 Data Sheet Current RMS Calculation (4) For example, if the temperature register produces a code of 0x46 at ambient temperature (25°C), and the temperature register currently reads 0x50, then the temperature is 55°C : Temp (°C) = [(0x50 – 0x46) × 3°C/LSB] + 25°C = 55°C Depending on the nominal value of the register, some finite temperature can cause the register to roll over. This should be compensated for in the system master (MCU). The ADE7758 temperature register varies with power supply. It is recommended to use the temperature register only in applications with a fixed, stable power supply. Typical error with respect to power supply variation is show in Table 5. 4.5 V 219 +2.34 4.75 V 216 +0.93 5V 214 0 5.25 V 211 −1.40 5.5 V 208 −2.80 ROOT MEAN SQUARE MEASUREMENT Root mean square (rms) is a fundamental measurement of the magnitude of an ac signal. Its definition can be both practical and mathematical. Defined practically, the rms value assigned to an ac signal is the amount of dc required to produce an equivalent amount of power in the load. Mathematically, the rms value of a continuous signal f(t) is defined as FRMS = 1 T ∫0 T f 2 (t )dt (5) For time sampling signals, rms calculation involves squaring the signal, taking the average, and obtaining the square root. FRMS = 1 N AIRMSOS[11:0] SGN 224 223 222 216 215 214 0x2851EC 0x1D3781 0x0 0x00 0xD7AE14 LPF3 Table 5. Temperature Register Error with Power Supply Variation Register Value % Error Figure 63 shows the detail of the signal processing chain for the rms calculation on one of the phases of the current channel. The current channel rms value is processed from the samples used in the current channel waveform sampling mode. The current rms values are stored in 24-bit registers (AIRMS, BIRMS, and CIRMS). One LSB of the current rms register is equivalent to one LSB of the current waveform sample. The update rate of the current rms measurement is CLKIN/12. CURRENT SIGNAL FROM HPF OR INTEGRATOR (IF ENABLED) X2 + + AIRMS[23:0] Figure 63. Current RMS Signal Processing With the specified full-scale analog input signal of 0.5 V, the ADC produces an output code that is approximately ±2,642,412d (see the Current Channel ADC section). The equivalent rms value of a full-scale sinusoidal signal at 60 Hz is 1,914,753 (0x1D3781). The accuracy of the current rms is typically 0.5% error from the full-scale input down to 1/500 of the full-scale input. Additionally, this measurement has a bandwidth of 14 kHz. It is recommended to read the rms registers synchronous to the voltage zero crossings to ensure stability. The IRQ can be used to indicate when a zero crossing has occurred (see the Interrupts section). Table 6 shows the settling time for the IRMS measurement, which is the time it takes for the rms register to reflect the value at the input to the current channel. N ∑ f 2[n] n=1 (6) The method used to calculate the rms value in the ADE7758 is to low-pass filter the square of the input signal (LPF3) and take the square root of the result (see Figure 63). i(t) = √2 × IRMS × sin(ωt) (7) i2(t) = IRMS2 − IRMS2 × cos(ωt) (8) 04443-062 Temp (°C) = [(TEMP[7:0] − Offset) × 3°C/LSB] + Ambient(°C) Table 6. Settling Time for IRMS Measurement Integrator Off Integrator On then The rms calculation is simultaneously processed on the six analog input channels. Each result is available in separate registers. While the ADE7758 measures nonsinusoidal signals, it should be noted that the voltage rms measurement, and therefore the apparent energy, are bandlimited to 260 Hz. The current rms as well as the active power have a bandwidth of 14 kHz. Rev. E | Page 28 of 72 63% 80 ms 40 ms 100% 960 ms 1.68 sec Data Sheet ADE7758 VRMSOS[11:0] Current RMS Offset Compensation IRMS  IRMS0 2  16384  IRMSOS Table 7. Approximate IRMS Register Values Integrator Off (d) 1,921,472 1,914,752 Integrator On (d) 2,489,581 2,067,210 28 27 26 + + |X| VAN LPF1 AVRMS[23:0] LPF3 50Hz VOLTAGE SIGNAL–V(t) 0.5 GAIN 50Hz 0x193504 LPF OUTPUT WORD RANGE 0x2797 60Hz 0x0 0xD869 0x0 0x1902BD 60Hz LPF OUTPUT WORD RANGE 0x0 0x2748 0x0 0xD8B8 (9) where IRMS0 is the rms measurement without offset correction. Frequency (Hz) 50 60 AVRMSGAIN[11:0] 04443-063 The ADE7758 incorporates a current rms offset compensation register for each phase (AIRMSOS, BIRMSOS, and CIRMSOS). These are 12-bit signed registers that can be used to remove offsets in the current rms calculations. An offset can exist in the rms calculation due to input noises that are integrated in the dc component of I2(t). Assuming that the maximum value from the current rms calculation is 1,914,753d with full-scale ac inputs (60 Hz), one LSB of the current rms offset represents 0.94% of the measurement error at 60 dB down from full scale. The IRMS measurement is undefined at zero input. Calibration of the offset should be done at low current and values at zero input should be ignored. For details on how to calibrate the current rms measurement, see the Calibration section. SGN 216 215 214 Figure 64. Voltage RMS Signal Processing Table 8 shows the settling time for the VRMS measurement, which is the time it takes for the rms register to reflect the value at the input to the voltage channel. Table 8. Settling Time for VRMS Measurement 63% 100 ms 100% 960 ms Voltage Channel RMS Calculation Voltage RMS Offset Compensation Figure 64 shows the details of the signal path for the rms estimation on Phase A of the voltage channel. This voltage rms estimation is done in the ADE7758 using the mean absolute value calculation, as shown in Figure 64.The voltage channel rms value is processed from the waveform samples after the low-pass filter LPF1. The output of the voltage channel ADC can be scaled by ±50% by changing VRMSGAIN[11:0] registers to perform an overall rms voltage calibration. The VRMSGAIN registers scale the rms calculations as well as the apparent energy calculation because apparent power is the product of the voltage and current rms values. The voltage rms values are stored in 24-bit registers (AVRMS, BVRMS, and CVRMS). One LSB of a voltage waveform sample is approximately equivalent to 256 LSBs of the voltage rms register. The update rate of the voltage rms measurement is CLKIN/12. The ADE7758 incorporates a voltage rms offset compensation for each phase (AVRMSOS, BVRMSOS, and CVRMSOS). These are 12-bit signed registers that can be used to remove offsets in the voltage rms calculations. An offset can exist in the rms calculation due to input noises and offsets in the input samples. It should be noted that the offset calibration does not allow the contents of the VRMS registers to be maintained at 0 when no voltage is applied. This is caused by noise in the voltage rms calculation, which limits the usable range between full scale and 1/50th of full scale. One LSB of the voltage rms offset is equivalent to 64 LSBs of the voltage rms register. With the specified full-scale ac analog input signal of 0.5 V, the LPF1 produces an output code that is approximately 63% of its full-scale value, that is, ±9,372d, at 60 Hz (see the Voltage Channel ADC section). The equivalent rms value of a full-scale ac signal is approximately 1,639,101 (0x1902BD) in the VRMS register. The accuracy of the VRMS measurement is typically 0.5% error from the full-scale input down to 1/20 of the full-scale input. Additionally, this measurement has a bandwidth of 260 Hz. It is recommended to read the rms registers synchronous to the voltage zero crossings to ensure stability. The IRQ can be used to indicate when a zero crossing has occurred (see the Interrupts section). Assuming that the maximum value from the voltage rms calculation is 1,639,101d with full-scale ac inputs, then 1 LSB of the voltage rms offset represents 0.042% of the measurement error at 1/10 of full scale. VRMS = VRMS0 + VRMSOS × 64 (10) where VRMS0 is the rms measurement without the offset correction. Table 9. Approximate VRMS Register Values Frequency (Hz) 50 60 Rev. E | Page 29 of 72 Value (d) 1,678,210 1,665,118 ADE7758 Data Sheet Voltage RMS Gain Adjust The ADC gain in each phase of the voltage channel can be adjusted for the rms calculation by using the voltage rms gain registers (AVRMSGAIN, BVRMSGAIN, and CVRMSGAIN). The gain of the voltage waveforms before LPF1 is adjusted by writing twos complement, 12-bit words to the voltage rms gain registers. Equation 11 shows how the gain adjustment is related to the contents of the voltage gain register. Content of VRMS Register  VRMSGAIN  (11) Nominal RMS Values Without Gain  1   212   The instantaneous power signal p(t) is generated by multiplying the current and voltage signals in each phase. The dc component of the instantaneous power signal in each phase (A, B, and C) is then extracted by LPF2 (the low-pass filter) to obtain the average active power information on each phase. Figure 65 shows this process. The active power of each phase accumulates in the corresponding 16-bit watt-hour register (AWATTHR, BWATTHR, or CWATTHR). The input to each active energy register can be changed depending on the accumulation mode setting (see Table 22). INSTANTANEOUS POWER SIGNAL p(t) = VRMS × IRMS – VRMS × IRMS × cos(2ωt) 0x19999A ACTIVE REAL POWER SIGNAL = VRMS × IRMS For example, when 0x7FF is written to the voltage gain register, the RMS value is scaled up by 50%. 0x7FF = 2047d 2047/212 = 0.5 VRMS × IRMS 0xCCCCD Similarly, when 0x800, which equals –2047d (signed twos complement), is written the ADC output is scaled by –50%. 0x00000 ACTIVE POWER CALCULATION v(t) = √2 × VRMS × sin(ωt) (12) i(t) = √2 × IRMS × sin(ωt) (13) where VRMS = rms voltage and IRMS = rms current. p(t) = v(t) × i(t) VOLTAGE v(t) = 2 × VRMS × sin(ωt) Figure 65. Active Power Calculation Because LPF2 does not have an ideal brick wall frequency response (see Figure 66), the active power signal has some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the active power signal is integrated over time to calculate the energy. 0 (14) –4 The average power over an integral number of line cycles (n) is given by the expression in Equation 15. 1 nT  p t dt  VRMS  IRMS nT 0 –8 (15) where: GAIN (dB) p –12 –16 t is the line cycle period. P is referred to as the active or real power. Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 14, that is, VRMS × IRMS. This is the relationship used to calculate the active power in the ADE7758 for each phase. –20 04443-065 p(t) = IRMS × VRMS − IRMS × VRMS × cos(2ωt) CURRENT i(t) = 2 × IRMS × sin(ωt) 04443-064 Electrical power is defined as the rate of energy flow from source to load. It is given by the product of the voltage and current waveforms. The resulting waveform is called the instantaneous power signal and it is equal to the rate of energy flow at every instant of time. The unit of power is the watt or joules/sec. Equation 14 gives an expression for the instantaneous power signal in an ac system. –24 1 3 8 10 30 FREQUENCY (Hz) Figure 66. Frequency Response of the LPF Used to Filter Instantaneous Power in Each Phase Rev. E | Page 30 of 72 100 Data Sheet ADE7758 Active Power Gain Calibration Note that the average active power result from the LPF output in each phase can be scaled by ±50% by writing to the phase’s watt gain register (AWG, BWG, or CWG). The watt gain registers are twos complement, signed registers and have a resolution of 0.024%/LSB. Equation 16 describes mathematically the function of the watt gain registers. Average Power Data = ⎛ Watt Gain Register ⎞ LPF 2 Output × ⎜1 + ⎟ 212 ⎠ ⎝ (16) The output is scaled by −50% by writing 0x800 to the watt gain registers and increased by +50% by writing 0x7FF to them. These registers can be used to calibrate the active power (or energy) calculation in the ADE7758 for each phase. The REVPAP bit (Bit 17) in the interrupt status register is set if the average power from any one of the phases changes sign. The phases monitored are selected by TERMSEL bits in the COMPMODE register (see Table 21). The TERMSEL bits are also used to select which phases are included in the APCF and VARCF pulse outputs. If the REVPAP bit is set in the mask register, the IRQ logic output goes active low (see the Interrupts section). Note that this bit is set whenever there are sign changes, that is, the REVPAP bit is set for both a positive-tonegative change and a negative-to-positive change of the sign bit. The response time of this bit is approximately 176 ms for a full-scale signal, which has an average value of 0xCCCCD at the low pass filter output. For smaller inputs, the time is longer. ⎡ ⎤ 225 4 Response Time ≅ 160 ms + ⎢ (17) ⎥× ⎢⎣ Average Value ⎥⎦ CLKIN Active Power Offset Calibration The ADE7758 also incorporates a watt offset register on each phase (AWATTOS, BWATTOS, and CWATTOS). These are signed twos complement, 12-bit registers that are used to remove offsets in the active power calculations. An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the chip itself. The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed. One LSB in the active power offset register is equivalent to 1/16 LSB in the active power multiplier output. At full-scale input, if the output from the multiplier is 0xCCCCD (838,861d), then 1 LSB in the LPF2 output is equivalent to 0.0075% of measurement error at 60 dB down from full scale on the current channel. At −60 dB down on full scale (the input signal level is 1/1000 of full-scale signal inputs), the average word value from LPF2 is 838.861 (838,861/1000). One LSB is equivalent to 1/838.861/16 × 100% = 0.0075% of the measured value. The active power offset register has a correction resolution equal to 0.0075% at −60 dB. The APCFNUM [15:13] indicate reverse power on each of the individual phases. Bit 15 is set if the sign of the power on Phase A is negative, Bit 14 for Phase B, and Bit 13 for Phase C. No-Load Threshold The ADE7758 has an internal no-load threshold on each phase. The no-load threshold can be activated by setting the NOLOAD bit (Bit 7) of the COMPMODE register. If the active power falls below 0.005% of full-scale input, the energy is not accumulated in that phase. As stated, the average multiplier output with fullscale input is 0xCCCCD. Therefore, if the average multiplier output falls below 0x2A, the power is not accumulated to avoid creep in the meter. The no-load threshold is implemented only on the active energy accumulation. The reactive and apparent energies do not have the no-load threshold option. Active Energy Calculation As previously stated, power is defined as the rate of energy flow. This relationship can be expressed mathematically as Sign of Active Power Calculation Power = Note that the average active power is a signed calculation. If the phase difference between the current and voltage waveform is more than 90°, the average power becomes negative. Negative power indicates that energy is being placed back on the grid. The ADE7758 has a sign detection circuitry for active power calculation. dEnergy dt (18) Conversely, Energy is given as the integral of power. Rev. E | Page 31 of 72 Energy = ∫ p (t )dt (19) ADE7758 Data Sheet AWATTOS[11:0] HPF DIGITAL INTEGRATOR I SIGN 26 MULTIPLIER 20 + + 0 40 + % 0x2851EC 0 + 0x00 WDIV[7:0] 0xD7AE14 AVERAGE POWER SIGNAL–P Φ V AWATTHR[15:0] AWG[11:0] LPF2 CURRENT SIGNAL–i(t) 15 2–1 2–2 2–3 2–4 T TOTAL ACTIVE POWER IS ACCUMULATED (INTEGRATED) IN THE ACTIVE ENERGY REGISTER PHCAL[6:0] 0xCCCCD 000x 04443-066 VOLTAGE SIGNAL–v(t) 0x2852 0x00000 TIME (nT) 0xD7AE Figure 67. ADE7758 Active Energy Accumulation ⎧∞ ⎫ Energy = ∫ p (t )dt = Lim ⎨ ∑ p (nT ) × T ⎬ T →0 ⎩n = 0 ⎭ (20) where: n is the discrete time sample number. T is the sample period. Figure 67 shows a signal path of this energy accumulation. The average active power signal is continuously added to the internal active energy register. This addition is a signed operation. Negative energy is subtracted from the active energy register. Note the values shown in Figure 67 are the nominal full-scale values, that is, the voltage and current inputs at the corresponding phase are at their full-scale input level. The average active power is divided by the content of the watt divider register before it is added to the corresponding watt-hr accumulation registers. When the value in the WDIV[7:0] register is 0 or 1, active power is accumulated without division. WDIV is an 8-bit unsigned register that is useful to lengthen the time it takes before the watt-hr accumulation registers overflow. This is the time it takes before overflow can be scaled by writing to the WDIV register and therefore can be increased by a maximum factor of 255. Note that the active energy register content can roll over to fullscale negative (0x8000) and continue increasing in value when the active power is positive (see Figure 67). Conversely, if the active power is negative, the energy register would under flow to full-scale positive (0x7FFF) and continue decreasing in value. By setting the AEHF bit (Bit 0) of the interrupt mask register, the ADE7758 can be configured to issue an interrupt (IRQ) when Bit 14 of any one of the three watt-hr accumulation registers has changed, indicating that the accumulation register is half full (positive or negative). Setting the RSTREAD bit (Bit 6) of the LCYMODE register enables a read-with-reset for the watt-hr accumulation registers, that is, the registers are reset to 0 after a read operation. WATT GAIN = 0x7FF CONTENTS OF WATT-HR ACCUMULATION REGISTER Figure 68 shows the energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three displayed curves show the minimum time it takes for the watt-hr accumulation register to overflow when the watt gain register of the corresponding phase equals to 0x7FF, 0x000, and 0x800. The watt gain registers are used to carry out a power calibration in the ADE7758. As shown, the fastest integration time occurs when the watt gain registers are set to maximum full scale, that is, 0x7FF. Rev. E | Page 32 of 72 WATT GAIN = 0x000 WATT GAIN = 0x800 0x7FFF 0x3FFF 0x0000 0.34 0.68 1.02 1.36 1.70 2.04 0xC000 0x8000 TIME (Sec) Figure 68. Energy Register Roll-Over Time for Full-Scale Power (Minimum and Maximum Power Gain) 04443-067 The ADE7758 achieves the integration of the active power signal by continuously accumulating the active power signal in the internal 41-bit energy registers. The watt-hr registers (AWATTHR, BWATTHR, and CWATTHR) represent the upper 16 bits of these internal registers. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 20 expresses the relationship. Data Sheet ADE7758 The discrete time sample period (T) for the accumulation register is 0.4 μs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the watt gain registers set to 0x000, the average word value from each LPF2 is 0xCCCCD (see Figure 65 and Figure 67). The maximum value that can be stored in the watthr accumulation register before it overflows is 215 − 1 or 0x7FFF. Because the average word value is added to the internal register, which can store 240 − 1 or 0xFF, FFFF, FFFF before it overflows, the integration time under these conditions with WDIV = 0 is calculated as Time = 0xFF, FFFF, FFFF 0xCCCCD × 0.4 μs = 0.524 sec (21) When WDIV is set to a value different from 0, the time before overflow is scaled accordingly as shown in Equation 22. Time = Time (WDIV = 0) × WDIV[7:0] (22) Energy Accumulation Mode The active power accumulated in each watt-hr accumulation register (AWATTHR, BWATTHR, or CWATTHR) depends on the configuration of the CONSEL bits in the COMPMODE register (Bit 0 and Bit 1). The different configurations are described in Table 10. Table 10. Inputs to Watt-Hr Accumulation Registers CONSEL[1, 0] 00 01 10 11 AWATTHR VA × IA VA × (IA – IB) VA × (IA – IB) Reserved BWATTHR VB × IB 0 0 Reserved CWATTHR VC × IC VC × (IC – IB) VC × IC Reserved Depending on the poly phase meter service, the appropriate formula should be chosen to calculate the active energy. The American ANSI C12.10 Standard defines the different configurations of the meter. Table 11. Meter Form Configuration CONSEL (d) 0 1 2 0 APCFNUM[11:0] INPUT TO AWATTHR REGISTER INPUT TO BWATTHR REGISTER INPUT TO CWATTHR REGISTER + + + DFC ÷ ÷4 APCFDEN[11:0] APCF Figure 69. Active Power Frequency Output A digital-to-frequency converter (DFC) is used to generate the APCF pulse output from the total active power. The TERMSEL bits (Bit 2 to Bit 4) of the COMPMODE register can be used to select which phases to include in the total power calculation. Setting Bit 2, Bit 3, and Bit 4 includes the input to the AWATTHR, BWATTHR, and CWATTHR registers in the total active power calculation. The total active power is signed addition. However, setting the ABS bit (Bit 5) in the COMPMODE register enables the absolute-only mode; that is, only the absolute value of the active power is considered. The output from the DFC is divided down by a pair of frequency division registers before being sent to the APCF pulse output. Namely, APCFDEN/APCFNUM pulses are needed at the DFC output before the APCF pin outputs a pulse. Under steady load conditions, the output frequency is directly proportional to the total active power. The pulse width of APCF is 64/CLKIN if APCFNUM and APCFDEN are both equal. If APCFDEN is greater than APCFNUM, the pulse width depends on APCFDEN. The pulse width in this case is T × (APCFDEN/2), where T is the period of the APCF pulse and APCFDEN/2 is rounded to the nearest whole number. An exception to this is when the period is greater than 180 ms. In this case, the pulse width is fixed at 90 ms. The maximum output frequency (APCFNUM = 0x00 and APCFDEN = 0x00) with full-scale ac signals on one phase is approximately 16 kHz. Table 11 describes which mode should be chosen in these different configurations. ANSI Meter Form 5S/13S 3-Wire Delta 6S/14S 4-Wire Wye 8S/15S 4-Wire Delta 9S/16S 4-Wire Wye simple, single-wire, optically isolated interface to external calibration equipment. Figure 69 illustrates the energy-tofrequency conversion in the ADE7758. 04443-068 Integration Time Under Steady Load TERMSEL (d) 3, 5, or 6 7 7 7 Active Power Frequency Output Pin 1 (APCF) of the ADE7758 provides frequency output for the total active power. After initial calibration during manufacturing, the manufacturer or end customer often verifies the energy meter calibration. One convenient way to verify the meter calibration is for the manufacturer to provide an output frequency that is proportional to the energy or active power under steady load conditions. This output frequency can provide a The ADE7758 incorporates two registers to set the frequency of APCF (APCFNUM[11:0] and APCFDEN[11:0]). These are unsigned 12-bit registers that can be used to adjust the frequency of APCF by 1/212 to 1 with a step of 1/212. For example, if the output frequency is 1.562 kHz while the contents of APCFDEN are 0 (0x000), then the output frequency can be set to 6.103 Hz by writing 0xFF to the APCFDEN register. If 0 were written to any of the frequency division registers, the divider would use 1 in the frequency division. In addition, the ratio APCFNUM/APCFDEN should be set not greater than 1 to ensure proper operation. In other words, the APCF output frequency cannot be higher than the frequency on the DFC output. The output frequency has a slight ripple at a frequency equal to 2× the line frequency. This is due to imperfect filtering of the instantaneous power signal to generate the active power signal Rev. E | Page 33 of 72 ADE7758 Data Sheet (see the Active Power Calculation section). Equation 14 gives an expression for the instantaneous power signal. This is filtered by LPF2, which has a magnitude response given by Equation 23. 1 2 1+ f Vlt (23) 82 The active power signal (output of the LPF2) can be rewritten as ⎡ ⎤ ⎢ VRMS × IRMS ⎥ p(t ) = VRMS × IRMS − ⎢ ⎥ × cos(4 πf1t ) ⎢ (2 f1 )2 2 ⎥ 1 + ⎢⎣ 8 ⎥⎦ VI – 4π × f1 1 + (24) 2f1 2 × cos(4π × f1 × t) 8 04443-069 H( f ) = E(t) t Figure 70. Output Frequency Ripple where f1 is the line frequency, for example, 60 Hz. Line Cycle Active Energy Accumulation Mode From Equation 24, E(t) equals The ADE7758 is designed with a special energy accumulation mode that simplifies the calibration process. By using the onchip, zero-crossing detection, the ADE7758 updates the watt-hr accumulation registers after an integer number of zero crossings (see Figure 71). The line-active energy accumulation mode for watt-hr accumulation is activated by setting the LWATT bit (Bit 0) of the LCYCMODE register. The total energy accumulated over an integer number of half-line cycles is written to the watt-hr accumulation registers after the LINECYC number of zero crossings is detected. When using the line cycle accumulation mode, the RSTREAD bit (Bit 6) of the LCYCMODE register should be set to Logic 0. ⎡ ⎢ VRMS × IRMS VRMS × IRMS × t – ⎢ ⎢ 2 ⎢ 4πf1 1 + (2 f1 ) 2 8 ⎣⎢ ⎤ ⎥ ⎥ × cos(4πf t ) (25) 1 ⎥ ⎥ ⎦⎥ From Equation 25, it can be seen that there is a small ripple in the energy calculation due to the sin(2ωt) component (see Figure 70). The ripple gets larger with larger loads. Choosing a lower output frequency for APCF during calibration by using a large APCFDEN value and keeping APCFNUM relatively small can significantly reduce the ripple. Averaging the output frequency over a longer period achieves the same results. WATTOS[11:0] ACTIVE POWER + WG[11:0] WDIV[7:0] + % 40 + 0 + ZXSEL01 15 ZERO-CROSSING DETECTION (PHASE A) 0 WATTHR[15:0] ZXSEL11 ZERO-CROSSING DETECTION (PHASE B) ACCUMULATE ACTIVE POWER FOR LINECYC NUMBER OF ZERO-CROSSINGS; WATT-HR ACCUMULATION REGISTERS ARE UPDATED ONCE EVERY LINECYC NUMBER OF ZERO-CROSSINGS CALIBRATION CONTROL ZXSEL21 1ZXSEL[0:2] ARE LINECYC[15:0] 04443-070 ZERO-CROSSING DETECTION (PHASE C) BITS 3 TO 5 IN THE LCYCMODE REGISTER Figure 71. ADE7758 Line Cycle Active Energy Accumulation Mode Rev. E | Page 34 of 72 Data Sheet ADE7758 The number of zero crossings is specified by the LINECYC register. LINECYC is an unsigned 16-bit register. The ADE7758 can accumulate active power for up to 65535 combined zero crossings. Note that the internal zero-crossing counter is always active. By setting the LWATT bit, the first energy accumulation result is, therefore, incorrect. Writing to the LINECYC register when the LWATT bit is set resets the zero-crossing counter, thus ensuring that the first energy accumulation result is accurate. At the end of an energy calibration cycle, the LENERGY bit (Bit 12) in the STATUS register is set. If the corresponding mask bit in the interrupt mask register is enabled, the IRQ output also goes active low; thus, the IRQ can also be used to signal the end of a calibration. Because active power is integrated on an integer number of halfline cycles in this mode, the sinusoidal component is reduced to 0, eliminating any ripple in the energy calculation. Therefore, total energy accumulated using the line-cycle accumulation mode is E(t) = VRMS × IRMS × t (26) where t is the accumulation time. Note that line cycle active energy accumulation uses the same signal path as the active energy accumulation. The LSB size of these two methods is equivalent. Using the line cycle accumulation to calculate the kWh/LSB constant results in a value that can be applied to the WATTHR registers when the line accumulation mode is not selected (see the Calibration section). Then the instantaneous reactive power q(t) can be expressed as q(t ) = v (t ) × i ′(t ) π π q(t ) = VI cos⎛⎜ – θ – ⎞⎟ – VI cos⎛⎜ 2ωt – θ – ⎞⎟ 2⎠ 2⎠ ⎝ ⎝ where i ′(t ) is the current waveform phase shifted by 90°. Note that q(t) can be rewritten as q(t ) = VI sin(θ) + VI sin(2ωt – θ) Q= 1 nT ∫ q(t )dt = V × I × sin(θ) nT 0 T is the period of the line cycle. Q is referred to as the average reactive power. The instantaneous reactive power signal q(t) is generated by multiplying the voltage signals and the 90° phase-shifted current in each phase. The dc component of the instantaneous reactive power signal in each phase (A, B, and C) is then extracted by a low-pass filter to obtain the average reactive power information on each phase. This process is illustrated in Figure 72. The reactive power of each phase is accumulated in the corresponding 16-bit VARhour register (AVARHR, BVARHR, or CVARHR). The input to each reactive energy register can be changed depending on the accumulation mode setting (see Table 21). The frequency response of the LPF in the reactive power signal path is identical to that of the LPF2 used in the average active power calculation (see Figure 66). INSTANTANEOUS REACTIVE POWER SIGNAL q(t) = VRMS × IRMS × sin(φ) + VRMS × IRMS × sin(2ωt + θ) AVERAGE REACTIVE POWER SIGNAL = VRMS × IRMS × sin(θ) VRMS × IRMS × sin(φ) 0x00000 π i′(t ) = 2 I sin⎛⎜ ωt + ⎞⎟ 2⎠ ⎝ where: θ VOLTAGE v(t) = 2 × VRMS × sin(ωt – θ) (27) i(t ) = 2 I sin(ωt ) (28) (31) where: Equation 30 gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by +90°. v(t ) = 2 V sin(ωt – θ) (30) The average reactive power over an integral number of line cycles (n) is given by the expression in Equation 31. REACTIVE POWER CALCULATION A load that contains a reactive element (inductor or capacitor) produces a phase difference between the applied ac voltage and the resulting current. The power associated with reactive elements is called reactive power, and its unit is VAR. Reactive power is defined as the product of the voltage and current waveforms when one of these signals is phase shifted by 90°. (29) CURRENT i(t) = 2 × IRMS × sin(ωt) Figure 72. Reactive Power Calculation The low-pass filter is nonideal, so the reactive power signal has some ripple. This ripple is sinusoidal and has a frequency equal to 2× the line frequency. Because the ripple is sinusoidal in nature, it is removed when the reactive power signal is integrated over time to calculate the reactive energy. Rev. E | Page 35 of 72 04443-071 Phase A, Phase B, and Phase C zero crossings are, respectively, included when counting the number of half-line cycles by setting ZXSEL[0:2] bits (Bit 3 to Bit 5) in the LCYCMODE register. Any combination of the zero crossings from all three phases can be used for counting the zero crossing. Only one phase should be selected at a time for inclusion in the zero crossings count during calibration (see the Calibration section). v = rms voltage. i = rms current. θ = total phase shift caused by the reactive elements in the load. ADE7758 Data Sheet The phase-shift filter has –90° phase shift when the integrator is enabled and +90° phase shift when the integrator is disabled. In addition, the filter has a nonunity magnitude response. Because the phase-shift filter has a large attenuation at high frequency, the reactive power is primarily for the calculation at line frequency. The effect of harmonics is largely ignored in the reactive power calculation. Note that because of the magnitude characteristic of the phase shifting filter, the LSB weight of the reactive power calculation is slightly different from that of the active power calculation (see the Energy Registers Scaling section). The ADE7758 uses the line frequency of the phase selected in the FREQSEL[1:0] bits of the MMODE[1:0] to compensate for attenuation of the reactive energy phase shift filter over frequency (see the Period Measurement section). Reactive Power Gain Calibration The average reactive power from the LPF output in each phase can be scaled by ±50% by writing to the phase’s VAR gain register (AVARG, BVARG, or CVARG). The VAR gain registers are twos complement, signed registers and have a resolution of 0.024%/LSB. The function of the VAR gain registers is expressed by Average Reactive Power = ⎛ VAR Gain Register ⎞ LPF 2 Output × ⎜1 + ⎟ 212 ⎝ ⎠ bits in the COMPMODE register (see Table 21). If the REVPRP bit is set in the mask register, the IRQ logic output goes active low (see the Interrupts section). Note that this bit is set whenever there is a sign change; that is, the bit is set for either a positiveto-negative change or a negative-to-positive change of the sign bit. The response time of this bit is approximately 176 ms for a full-scale signal, which has an average value of 0xCCCCD at the low-pass filter output. For smaller inputs, the time is longer. ⎡ ⎤ 2 25 4 ResponseTime ≅ 160 ms + ⎢ ⎥× AverageVal ue CLKIN ⎣ ⎦ (33) Table 12. Sign of Reactive Power Calculation Φ1 Between 0 to +90 Between −90 to 0 Between 0 to +90 Between −90 to 0 1 Integrator Off Off On On Sign of Reactive Power Positive Negative Positive Negative Φ is defined as the phase angle of the voltage signal minus the current signal; that is, Φ is positive if the load is inductive and negative if the load is capacitive. Reactive Energy Calculation (32) The output is scaled by –50% by writing 0x800 to the VAR gain registers and increased by +50% by writing 0x7FF to them. These registers can be used to calibrate the reactive power (or energy) calculation in the ADE7758 for each phase. Reactive Power Offset Calibration The ADE7758 incorporates a VAR offset register on each phase (AVAROS, BVAROS, and CVAROS). These are signed twos complement, 12-bit registers that are used to remove offsets in the reactive power calculations. An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the chip itself. The offset calibration allows the contents of the reactive power register to be maintained at 0 when no reactive power is being consumed. The offset registers’ resolution is the same as the active power offset registers (see the Apparent Power Offset Calibration section). Sign of Reactive Power Calculation Note that the average reactive power is a signed calculation. As stated previously, the phase shift filter has –90° phase shift when the integrator is enabled and +90° phase shift when the integrator is disabled. Table 12 summarizes the relationship between the phase difference between the voltage and the current and the sign of the resulting VAR calculation. The ADE7758 has a sign detection circuit for the reactive power calculation. The REVPRP bit (Bit 18) in the interrupt status register is set if the average reactive power from any one of the phases changes. The phases monitored are selected by TERMSEL Reactive energy is defined as the integral of reactive power. Reactive Energy = ∫ q(t )dt (34) Similar to active power, the ADE7758 achieves the integration of the reactive power signal by continuously accumulating the reactive power signal in the internal 41-bit accumulation registers. The VAR-hr registers (AVARHR, BVARHR, and CVARHR) represent the upper 16 bits of these internal registers. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 35 expresses the relationship ⎧∞ ⎫ Reactive Energy = ∫ q(t )dt = Lim ⎨ ∑ q(nT ) × T ⎬ T →0 ⎩n =0 ⎭ (35) where: n is the discrete time sample number. T is the sample period. Figure 73 shows the signal path of the reactive energy accumulation. The average reactive power signal is continuously added to the internal reactive energy register. This addition is a signed operation. Negative energy is subtracted from the reactive energy register. The average reactive power is divided by the content of the VAR divider register before it is added to the corresponding VAR-hr accumulation registers. When the value in the VARDIV[7:0] register is 0 or 1, the reactive power is accumulated without any division. VARDIV is an 8-bit unsigned register that is useful to lengthen the time it takes before the VAR-hr accumulation registers overflow. Rev. E | Page 36 of 72 Data Sheet ADE7758 Similar to reactive power, the fastest integration time occurs when the VAR gain registers are set to maximum full scale, that is, 0x7FF. The time it takes before overflow can be scaled by writing to the VARDIV register; and, therefore, it can be increased by a maximum factor of 255. By setting the REHF bit (Bit 1) of the interrupt mask register, the ADE7758 can be configured to issue an interrupt (IRQ) when Bit 14 of any one of the three VAR-hr accumulation registers has changed, indicating that the accumulation register is half full (positive or negative). When overflow occurs, the VAR-hr accumulation registers content can rollover to full-scale negative (0x8000) and continue increasing in value when the reactive power is positive. Conversely, if the reactive power is negative, the VAR-hr accumulation registers content can roll over to full-scale positive (0x7FFF) and continue decreasing in value. Setting the RSTREAD bit (Bit 6) of the LCYMODE register enables a read-with-reset for the VAR-hr accumulation registers; that is, the registers are reset to 0 after a read operation. VAROS[11:0] HPF 90° PHASE SHIFTING FILTER π 2 I CURRENT SIGNAL–i(t) 0x2851EC 0x00 SIGN 26 MULTIPLIER 20 15 2–1 2–2 2–3 2–4 0 VARG[11:0] LPF2 + + % 40 + 0 + VARDIV[7:0] 0xD7AE14 Φ V VARHR[15:0] TOTAL REACTIVE POWER IS ACCUMULATED (INTEGRATED) IN THE VAR-HR ACCUMULATION REGISTERS PHCAL[6:0] VOLTAGE SIGNAL–v(t) 0x2852 04443-072 0x00 0xD7AE Figure 73. ADE7758 Reactive Energy Accumulation Rev. E | Page 37 of 72 ADE7758 Data Sheet The discrete time sample period (T) for the accumulation register is 0.4 μs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs, a 90° phase difference between the voltage and the current signal (the largest possible reactive power), and the VAR gain registers set to 0x000, the average word value from each LPF2 is 0xCCCCD. The maximum value that can be stored in the reactive energy register before it overflows is 215 − 1 or 0x7FFF. Because the average word value is added to the internal register, which can store 240 − 1 or 0xFF, FFFF, FFFF before it overflows, the integration time under these conditions with VARDIV = 0 is calculated as 0xFF, FFFF, FFFF Time = × 0.4 μs = 0.5243 sec 0xCCCCD (36) When VARDIV is set to a value different from 0, the time before overflow are scaled accordingly as shown in Equation 37. Time = Time(VARDIV = 0) × VARDIV (37) Energy Accumulation Mode The reactive power accumulated in each VAR-hr accumulation register (AVARHR, BVARHR, or CVARHR) depends on the configuration of the CONSEL bits in the COMPMODE register (Bit 0 and Bit 1). The different configurations are described in Table 13. Note that IA’/IB’/IC’ are the current phase-shifted current waveform. Table 13. Inputs to VAR-Hr Accumulation Registers CONSEL[1, 0] 00 01 10 11 AVARHR VA × IA’ VA (IA’ – IB’) VA (IA’ – IB’) Reserved BVARHR VB × IB 0 0 Reserved CVARHR VC × IC’ VC (IC’ – IB’) VC × IC’ Reserved Reactive Power Frequency Output Pin 17 (VARCF) of the ADE7758 provides frequency output for the total reactive power. Similar to APCF, this pin provides an output frequency that is directly proportional to the total reactive power. The pulse width of VARPCF is 64/CLKIN if VARCFNUM and VARCFDEN are both equal. If VARCFDEN is greater than VARCFNUM, the pulse width depends on VARCFDEN. The pulse width in this case is T × (VARCFDEN/2), where T is the period of the VARCF pulse and VARCFDEN/2 is rounded to the nearest whole number. An exception to this is when the period is greater than 180 ms. In this case, the pulse width is fixed at 90 ms. A digital-to-frequency converter (DFC) is used to generate the VARCF pulse output from the total reactive power. The TERMSEL bits (Bit 2 to Bit 4) of the COMPMODE register can be used to select which phases to include in the total reactive power calculation. Setting Bit 2, Bit 3, and Bit 4 includes the input to the AVARHR, BVARHR, and CVARHR registers in the total reactive power calculation. The total reactive power is signed addition. However, setting the SAVAR bit (Bit 6) in the COMPMODE register enables absolute value calculation. If the active power of that phase is positive, no change is made to the sign of the reactive power. However, if the sign of the active power is negative in that phase, the sign of its reactive power is inverted before summing and creating VARCF pulses. This mode should be used in conjunction with the absolute value mode for active power (Bit 5 in the COMPMODE register) for APCF pulses. The effects of setting the ABS and SAVAR bits of the COMPMODE register are as follows when ABS = 1 and SAVAR = 1: If watt > 0, APCF = Watts, VARCF = +VAR. If watt < 0, APCF = |Watts|, VARCF = −VAR. INPUT TO AVARHR REGISTER INPUT TO BVARHR REGISTER + + + VARCFNUM[11:0] INPUT TO CVARHR REGISTER 0 DFC 1 INPUT TO AVAHR REGISTER INPUT TO BVAHR REGISTER INPUT TO CVAHR REGISTER + + + ÷ ÷4 VARCF VARCFDEN[11:0] VACF BIT (BIT 7) OF WAVMODE REGISTER 04443-073 Integration Time Under Steady Load Figure 74. Reactive Power Frequency Output The output from the DFC is divided down by a pair of frequency division registers before sending to the VARCF pulse output. Namely, VARCFDEN/VARCFNUM pulses are needed at the DFC output before the VARCF pin outputs a pulse. Under steady load conditions, the output frequency is directly proportional to the total reactive power. Figure 74 illustrates the energy-to-frequency conversion in the ADE7758. Note that the input to the DFC can be selected between the total reactive power and total apparent power. Therefore, the VARCF pin can output frequency that is proportional to the total reactive power or total apparent power. The selection is made by setting the VACF bit (Bit 7) in the WAVMODE register. Setting this bit switches the input to the total apparent power. The default value of this bit is logic low. Therefore, the default output from the VARCF pin is the total reactive power. All other operations of this frequency output are similar to that of the active power frequency output (see the Active Power Frequency Output section). Line Cycle Reactive Energy Accumulation Mode The line cycle reactive energy accumulation mode is activated by setting the LVAR bit (Bit 1) in the LCYCMODE register. The total reactive energy accumulated over an integer number of zero crossings is written to the VAR-hr accumulation registers after the LINECYC number of zero crossings is detected. The operation of this mode is similar to watt-hr accumulation (see the Line Cycle Active Energy Accumulation Mode section). Rev. E | Page 38 of 72 Data Sheet ADE7758 When using the line cycle accumulation mode, the RSTREAD bit (Bit 6) of the LCYCMODE register should be set to Logic 0. APPARENT POWER CALCULATION Apparent power is defined as the amplitude of the vector sum of the active and reactive powers. Figure 75 shows what is typically referred to as the power triangle. APPARENT POWER For a pure sinusoidal system, the two approaches should yield the same result. The apparent energy calculation in the ADE7758 uses the arithmetical approach. However, the line cycle energy accumulation mode in the ADE7758 enables energy accumulation between active and reactive energies over a synchronous period, thus the vectorial method can be easily implemented in the external MCU (see the Line Cycle Active Energy Accumulation Mode section). REACTIVE POWER Note that apparent power is always positive regardless of the direction of the active or reactive energy flows. The rms value of the current and voltage in each phase is multiplied to produce the apparent power of the corresponding phase. The output from the multiplier is then low-pass filtered to obtain the average apparent power. The frequency response of the LPF in the apparent power signal path is identical to that of the LPF2 used in the average active power calculation (see Figure 66). 04443-074 Apparent Power Gain Calibration θ ACTIVE POWER Figure 75. Power Triangle There are two ways to calculate apparent power: the arithmetical approach or the vectorial method. The arithmetical approach uses the product of the voltage rms value and current rms value to calculate apparent power. Equation 38 describes the arithmetical approach mathematically. S = VRMS × IRMS The vectorial method uses the square root of the sum of the active and reactive power, after the two are individually squared. Equation 39 shows the calculation used in the vectorial approach. where: S is the apparent power. P is the active power. Q is the reactive power. Average Apparent Power = VAGAIN Register ⎞ ⎛ LPF 2 Output × ⎜1 + ⎟ 212 ⎝ ⎠ (38) where S is the apparent power, and VRMS and IRMS are the rms voltage and current, respectively. S = P2 + Q2 Note that the average active power result from the LPF output in each phase can be scaled by ±50% by writing to the phase’s VAGAIN register (AVAG, BVAG, or CVAG). The VAGAIN registers are twos complement, signed registers and have a resolution of 0.024%/LSB. The function of the VAGAIN registers is expressed mathematically as (39) (40) The output is scaled by –50% by writing 0x800 to the VAR gain registers and increased by +50% by writing 0x7FF to them. These registers can be used to calibrate the apparent power (or energy) calculation in the ADE7758 for each phase. Apparent Power Offset Calibration Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value (see the Current RMS Calculation section and the Voltage Channel RMS Calculation section). The voltage and current rms values are then multiplied together in the apparent power signal processing. As no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. The offset compensation of the apparent power measurement in each phase should be done by calibrating each individual rms measurement (see the Calibration section). Rev. E | Page 39 of 72 ADE7758 Data Sheet Apparent Energy Calculation Similar to active or reactive power accumulation, the fastest integration time occurs when the VAGAIN registers are set to maximum full scale, that is, 0x7FF. When overflow occurs, the content of the VA-hr accumulation registers can roll over to 0 and continue increasing in value. Apparent energy is defined as the integral of apparent power. Apparent Energy = ∫ S(t)dt (41) Similar to active and reactive energy, the ADE7758 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in the internal 41-bit, unsigned accumulation registers. The VA-hr registers (AVAHR, BVAHR, and CVAHR) represent the upper 16 bits of these internal registers. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 42 expresses the relationship ⎧ ∞ ⎫ Apparent Energy = ∫ S(t ) dt = Lim ⎨ ∑ S (nT ) × T ⎬ T→0 ⎩ n =0 ⎭ By setting the VAEHF bit (Bit 2) of the mask register, the ADE7758 can be configured to issue an interrupt (IRQ) when the MSB of any one of the three VA-hr accumulation registers has changed, indicating that the accumulation register is half full. Setting the RSTREAD bit (Bit 6) of the LCYMODE register enables a read-with-reset for the VA-hr accumulation registers; that is, the registers are reset to 0 after a read operation. (42) Integration Time Under Steady Load The discrete time sample period (T) for the accumulation register is 0.4 μs (4/CLKIN). With full-scale, 60 Hz sinusoidal signals on the analog inputs and the VAGAIN registers set to 0x000, the average word value from each LPF2 is 0xB9954. The maximum value that can be stored in the apparent energy register before it overflows is 216 − 1 or 0xFFFF. As the average word value is first added to the internal register, which can store 241 − 1 or 0x1FF, FFFF, FFFF before it overflows, the integration time under these conditions with VADIV = 0 is calculated as where: n is the discrete time sample number. T is the sample period. Figure 76 shows the signal path of the apparent energy accumulation. The apparent power signal is continuously added to the internal apparent energy register. The average apparent power is divided by the content of the VA divider register before it is added to the corresponding VA-hr accumulation register. When the value in the VADIV[7:0] register is 0 or 1, apparent power is accumulated without any division. VADIV is an 8-bit unsigned register that is useful to lengthen the time it takes before the VA-hr accumulation registers overflow. Time = 0x1FF, FFFF, FFFF 0xB9954 × 0.4 μs = 1.157 sec When VADIV is set to a value different from 0, the time before overflow is scaled accordingly, as shown in Equation 44. Time = Time(VADIV = 0) × VADIV 15 IRMS MULTIPLIER CURRENT RMS SIGNAL 0x1C82B 0x00 (43) VARHR[15:0] (44) 0 VAG[11:0] LPF2 % 40 + 0 + VADIV[7:0] VRMS APPARENT POWER IS ACCUMULATED (INTEGRATED) IN THE VA-HR ACCUMULATION REGISTERS VOLTAGE RMS SIGNAL 0x17F263 50Hz 0x0 0x174BAC 04443-075 60Hz 0x0 Figure 76. ADE7758 Apparent Energy Accumulation Rev. E | Page 40 of 72 Data Sheet ADE7758 Table 14. Inputs to VA-Hr Accumulation Registers CONSEL[1, 0] 00 01 10 11 1 AVAHR1 AVRMS × AIRMS AVRMS × AIRMS AVRMS × AIRMS Reserved BVAHR BVRMS × BIRMS AVRMS + CVRMS/2 × BIRMS BVRMS × BIRMS Reserved CVAHR CVRMS × CIRMS CVRMS × CIRMS CVRMS × CIRMS Reserved AVRMS/BVRMS/CVRMS are the rms voltage waveform, and AIRMS/BIRMS/CIRMS are the rms values of the current waveform. Energy Accumulation Mode The apparent power accumulated in each VA-hr accumulation register (AVAHR, BVAHR, or CVAHR) depends on the configuration of the CONSEL bits in the COMPMODE register (Bit 0 and Bit 1). The different configurations are described in Table 14. The contents of the VA-hr accumulation registers are affected by both the registers for rms voltage gain (VRMSGAIN), as well as the VAGAIN register of the corresponding phase. Apparent Power Frequency Output Pin 17 (VARCF) of the ADE7758 provides frequency output for the total apparent power. By setting the VACF bit (Bit 7) of the WAVMODE register, this pin provides an output frequency that is directly proportional to the total apparent power. A digital-to-frequency converter (DFC) is used to generate the pulse output from the total apparent power. The TERMSEL bits (Bit 2 to Bit 4) of the COMPMODE register can be used to select which phases to include in the total power calculation. Setting Bit 2, Bit 3, and Bit 4 includes the input to the AVAHR, BVAHR, and CVAHR registers in the total apparent power calculation. A pair of frequency divider registers, namely VARCFDEN and VARCFNUM, can be used to scale the output frequency of this pin. Note that either VAR or apparent power can be selected at one time for this frequency output (see the Reactive Power Frequency Output section). Line Cycle Apparent Energy Accumulation Mode The line cycle apparent energy accumulation mode is activated by setting the LVA bit (Bit 2) in the LCYCMODE register. The total apparent energy accumulated over an integer number of zero crossings is written to the VA-hr accumulation registers after the LINECYC number of zero crossings is detected. The operation of this mode is similar to watt-hr accumulation (see the Line Cycle Active Energy Accumulation Mode section). When using the line cycle accumulation mode, the RSTREAD bit (Bit 6) of the LCYCMODE register should be set to Logic 0. Note that this mode is especially useful when the user chooses to perform the apparent energy calculation using the vectorial method. By setting LWATT and LVAR bits (Bit 0 and Bit 1) of the LCYCMODE register, the active and reactive energies are accumulated over the same period. Therefore, the MCU can perform the squaring of the two terms and then take the square root of their sum to determine the apparent energy over the same period. ENERGY REGISTERS SCALING The ADE7758 provides measurements of active, reactive, and apparent energies that use separate signal paths and filtering for calculation. The differences in the datapaths can result in small differences in LSB weight between the active, reactive, and apparent energy registers. These measurements are internally compensated so that the scaling is nearly one to one. The relationship between the registers is shown in Table 15. Table 15. Energy Registers Scaling 60 Hz Integrator Off VAR VA Integrator On VAR VA Frequency 50 Hz 1.004 × WATT 1.00058 × WATT 1.0054 × WATT 1.0085 × WATT 1.0059 × WATT 1.00058 × WATT 1.0064 × WATT 1.00845 × WATT WAVEFORM SAMPLING MODE The waveform samples of the current and voltage waveform, as well as the active, reactive, and apparent power multiplier outputs, can all be routed to the WAVEFORM register by setting the WAVSEL[2:0] bits (Bit 2 to Bit 4) in the WAVMODE register. The phase in which the samples are routed is set by setting the PHSEL[1:0] bits (Bit 0 and Bit 1) in the WAVMODE register. All energy calculation remains uninterrupted during waveform sampling. Four output sample rates can be chosen by using Bit 5 and Bit 6 of the WAVMODE register (DTRT[1:0]). The output sample rate can be 26.04 kSPS, 13.02 kSPS, 6.51 kSPS, or 3.25 kSPS (see Table 20). By setting the WFSM bit in the interrupt mask register to Logic 1, the interrupt request output IRQ goes active low when a sample is available. The 24-bit waveform samples are transferred from the ADE7758 one byte (8 bits) at a time, with the most significant byte shifted out first. The interrupt request output IRQ stays low until the interrupt routine reads the reset status register (see the Interrupts section). Rev. E | Page 41 of 72 ADE7758 Data Sheet CALIBRATION Calibration Using Pulse Output A reference meter or an accurate source is required to calibrate the ADE7758 energy meter. When using a reference meter, the ADE7758 calibration output frequencies APCF and VARCF are adjusted to match the frequency output of the reference meter under the same load conditions. Each phase must be calibrated separately in this case. When using an accurate source for calibration, one can take advantage of the line cycle accumulation mode and calibrate the three phases simultaneously. The ADE7758 provides a pulsed output proportional to the active power accumulated by all three phases, called APCF. Additionally, the VARCF output is proportional to either the reactive energy or apparent energy accumulated by all three phases. The following section describes how to calibrate the gain, offset, and phase angle using the pulsed output information. The equations are based on the pulse output from the ADE7758 (APCF or VARCF) and the pulse output of the reference meter or CFEXPECTED. There are two objectives in calibrating the meter: to establish the correct impulses/kW-hr constant on the pulse output and to obtain a constant that relates the LSBs in the energy and rms registers to Watt/VA/VAR hours, amps, or volts. Additionally, calibration compensates for part-to-part variation in the meter design as well as phase shifts and offsets due to the current sensor and/or input networks. Figure 77 shows a flowchart of how to calibrate the ADE7758 using the pulse output. Because the pulse outputs are proportional to the total energy in all three phases, each phase must be calibrated individually. Writing to the registers is fast to reconfigure the part for calibrating a different phase; therefore, Figure 77 shows a method that calibrates all phases at a given test condition before changing the test condition. Rev. E | Page 42 of 72 Data Sheet ADE7758 CALIBRATE IRMS OFFSET START CALIBRATE VRMS OFFSET YES ALL PHASES VA AND WATT GAIN CAL? MUST BE DONE BEFORE VA GAIN CALIBRATION NO SET UP PULSE OUTPUT FOR A, B, OR C YES ALL PHASES GAIN CAL VAR? NO SET UP FOR PHASE A, B, OR C YES ALL PHASES PHASE ERROR CAL? NO CALIBRATE WATT AND VA GAIN @ ITEST, PF = 1 WATT AND VA CAN BE CALIBRATED SIMULTANEOUSLY @ PF = 1 BECAUSE THEY HAVE SEPARATE PULSE OUTPUTS CALIBRATE VAR GAIN @ ITEST, PF = 0, INDUCTIVE SET UP PULSE OUTPUT FOR A, B, OR C YES ALL PHASES VAR OFFSET CAL? CALIBRATE PHASE @ ITEST, PF = 0.5, INDUCTIVE NO SET UP PULSE OUTPUT FOR A, B, OR C YES ALL PHASES WATT OFFSET CAL? NO SET UP PULSE OUTPUT FOR A, B, OR C CALIBRATE VAR OFFSET @ IMIN, PF = 0, INDUCTIVE END 04443-076 CALIBRATE WATT OFFSET @ IMIN, PF = 1 Figure 77. Calibration Using Pulse Output Gain Calibration Using Pulse Output Gain calibration is used for meter-to-meter gain adjustment, APCF or VARCF output rate calibration, and determining the Wh/LSB, VARh/LSB, and VAh/LSB constant. The registers used for watt gain calibration are APCFNUM (0x45), APCFDEN (0x46), and xWG (0x2A to 0x2C). Equation 50 through Equation 52 show how these registers affect the Wh/LSB constant and the APCF pulses. For calibrating VAR gain, the registers in Equation 50 through Equation 52 should be replaced by VARCFNUM (0x47), VARCFDEN (0x48), and xVARG (0x2D to 0x2F). For VAGAIN, they should be replaced by VARCFNUM (0x47), VARCFDEN (0x48), and xVAG (0x30 to 0x32). Figure 78 shows the steps for gain calibration of watts, VA, or VAR using the pulse outputs. Rev. E | Page 43 of 72 ADE7758 Data Sheet STEP 1 ENABLE APCF AND VARCF PULSE OUTPUTS START STEP 1A SELECT VA FOR VARCF OUTPUT STEP 2 CLEAR GAIN REGISTERS: xWG, xVAG, xVARG ALL PHASES VA AND WATT GAIN CAL? YES NO STEP 3 SELECT VAR FOR VARCF OUTPUT YES SET UP PULSE OUTPUT FOR PHASE A, B, OR C ALL PHASES VAR GAIN CALIBRATED? NO NO STEP 3 STEP 4 SET UP PULSE OUTPUT FOR PHASE A, B, OR C END CFNUM/VARCFNUM SET TO CALCULATE VALUES? SET CFNUM/VARCFNUM AND CFDEN/VARCFDEN TO CALCULATED VALUES YES STEP 5 SET UP SYSTEM FOR ITEST , VNOM PF = 1 STEP 6 SELECT PHASE A, B, OR C FOR LINE PERIOD MEASUREMENT MEASURE % ERROR FOR APCF AND VARCF STEP 7 NO VARCFNUM/ VARCFDEN SET TO CALCULATED VALUES? STEP 4 CALCULATE AND WRITE TO xWG, xVAG YES STEP 5 SET UP SYSTEM FOR ITEST , VNOM PF = 0, INDUCTIVE SET VARCFNUM/VARCFDEN TO CALCULATED VALUES CALCULATE Wh/LSB AND VAh/LSB CONSTANTS STEP 6 MEASURE % ERROR FOR VARCF STEP 7 CALCULATE VARh/LSB CONSTANT 04443-077 CALCULATE AND WRITE TO xVARG Figure 78. Gain Calibration Using Pulse Output Step 1: Enable the pulse output by setting Bit 2 of the OPMODE register (0x13) to Logic 0. This bit enables both the APCF and VARCF pulses. Step 1a: VAR and VA share the VARCF pulse output. WAVMODE[7], Address (0x15), should be set to choose between VAR or VA pulses on the output. Setting the bit to Logic 1 selects VA. The default is Logic 0 or VARCF pulse output. the COMPMODE register (0x16). Setting Bit 2 to Logic 1 and Bit 3 and Bit 4 to Logic 0 allows only Phase A to be included in the pulse outputs. Select Phase A, Phase B, or Phase C for a line period measurement with the FREQSEL[1:0] bits in the MMODE register (0x14). For example, clearing Bit 1 and Bit 0 selects Phase A for line period measurement. Step 2: Ensure the xWG/xVARG/xVAG are zero. Step 3: Disable the Phase B and Phase C contribution to the APCF and VARCF pulses. This is done by the TERMSEL[2:4] bits of Rev. E | Page 44 of 72 Data Sheet ADE7758 Step 4: Set APCFNUM (0x45) and APCFDEN (0x46) to the calculated value to perform a coarse adjustment on the imp/kWh ratio. For VAR/VA calibration, set VARCFNUM (0x47) and VARCFDEN (0x48) to the calculated value. where CFREF = APCFEXPECTED = the pulse output of the reference meter. The pulse output frequency with one phase at full-scale inputs is approximately 16 kHz. A sample set of meters could be tested to find a more exact value of the pulse output at full scale in the user application. Step 7: Calculate xWG adjustment. One LSB change in xWG (12 bits) changes the WATTHR register by 0.0244% and therefore APCF by 0.0244%. The same relationship holds true for VARCF. APCFEXPECTED = APCFNOMINAL × To calculate the values for APCFNUM/APCFDEN and VARCFNUM/VARCFDEN, use the following formulas: APCFNOMINAL = 16 kHz × APCFEXPECTED = VNOM VFULLSCALE MC × I TEST × VNOM 1000 × 3600 × I TEST I FULLSCALE × cos(θ) ⎛ APCFNOMINAL ⎞ APCFDEN = INT ⎜ ⎟ ⎝ APCFEXPECTED ⎠ xWG = – (45) (46) VARCFEXPECTED = MC × I TEST × VNOM 1000 × 3600 × sin(θ) Example: Watt Gain Calibration of Phase A Using Pulse Output For this example, ITEST = 10 A, VNOM = 220 V, VFULLSCALE = 500 V, IFULLSCALE = 130 A, MC = 3200 impulses/kWh, Power Factor = 1, and Frequency = 50 Hz. Clear APCFNUM (0x45) and write the calculated value to APCFDEN (0x46) to perform a coarse adjustment on the imp/kWh ratio, using Equation 45 through Equation 47. (48) APCFEXPECTED = Because the APCFDEN and VARCFDEN values can be calculated from the meter design, these values can be written to the part automatically during production calibration. Step 6: Measure the percent error in the pulse output, APCF and/or VARCF, from the reference meter: APCF – CFREF % Error = × 100% CFREF (52) Return to Step 2 to calibrate Phase B and Phase C gain. APCFNOMINAL = 16 kHz × Step 5: Set the test system for ITEST, VNOM, and the unity power factor. For VAR calibration, the power factor should be set to 0 inductive in this step. For watt and VA, the unity power factor should be used. VAGAIN can be calibrated at the same time as WGAIN because VAGAIN can be calibrated at the unity power factor, and both pulse outputs can be measured simultaneously. However, when calibrating VAGAIN at the same time as WGAIN, the rms offsets should be calibrated first (see the Calibration of IRMS and VRMS Offset section). (51) Wh 1 = LSB 4 × MC × APCFDEN × 1 1000 APCFNUM WDIV where: The equations for calculating the VARCFNUM and VARCFDEN during VAR calibration are similar: %Error 0.0244% When APCF is calibrated, the xWATTHR registers have the same Wh/LSB from meter to meter if the meter constant and the APCFNUM/APCFDEN ratio remain the same. The Wh/LSB constant is (47) MC is the meter constant. ITEST is the test current. VNOM is the nominal voltage at which the meter is tested. VFULLSCALE and IFULLSCALE are the values of current and voltage, which correspond to the full-scale ADC inputs of the ADE7758. θ is the angle between the current and the voltage channel. APCFEXPECTED is equivalent to the reference meter output under the test conditions. APCFNUM is written to 0 or 1. APCFNUM[11 : 0] ⎛ xWG[11 : 0] ⎞ (50) × ⎜1 + ⎟ APCFDEN[11 : 0] ⎝ 212 ⎠ 220 10 × = 0.542 kHz 500 130 3200 × 10 × 220 1000 × 3600 × cos(0 ) = 1.9556 Hz ⎛ 542 Hz ⎞ ⎟ = 277 APCFDEN = INT ⎜ ⎜ 1.9556 Hz ⎟ ⎝ ⎠ With Phase A contributing to CF, at ITEST, VNOM, and the unity power factor, the example ADE7758 meter shows 2.058 Hz on the pulse output. This is equivalent to a 5.26% error from the reference meter value using Equation 49. %Error = 2.058 Hz – 1.9556 Hz 1.9556 Hz × 100% = 5.26% The AWG value is calculated to be −216 d using Equation 51, which means the value 0xF28 should be written to AWG. AWG = – (49) Rev. E | Page 45 of 72 5.26% = − 215.5 = −216 = 0xF 28 0.0244% ADE7758 Data Sheet Step 5: Calculate xPHCAL. PHASE CALIBRATION USING PULSE OUTPUT The ADE7758 includes a phase calibration register on each phase to compensate for small phase errors. Large phase errors should be compensated by adjusting the antialiasing filters. The ADE7758 phase calibration is a time delay with different weights in the positive and negative direction (see the Phase Compensation section). Because a current transformer is a source of phase error, a fixed nominal value can be decided on to load into the xPHCAL registers at power-up. During calibration, this value can be adjusted for CT-to-CT error. Figure 79 shows the steps involved in calibrating the phase using the pulse output. START YES ALL PHASES PHASE ERROR CALIBRATED? xPHCAL  Phase Error  where PHCAL_LSB_Weight is 1.2 μs if the %Error is negative or 2.4 μs if the %Error is positive (see the Phase Compensation section). If it is not known, the line period is available in the ADE7758 frequency register, FREQ (0x10). To configure line period measurement, select the phase for period measurement in the MMODE[1:0] and set LCYCMODE[7]. Equation 55 shows how to determine the value that needs to be written to xPHCAL using the period register measurement. xPHCAL  NO Phase Error  STEP 1 SET UP PULSE OUTPUT FOR PHASE A, B, OR C AND ENABLE CF OUTPUTS END PHCAL _ LSB _ Weight  FREQ[11 : 0] 360 (55) For this example, ITEST = 10 A, VNOM = 220 V, VFULLSCALE = 500 V, IFULLSCALE = 130 A, MC = 3200 impulses/kWh, power factor = 0.5 inductive, and frequency = 50 Hz. With Phase A contributing to CF, at ITEST, VNOM, and 0.5 inductive power factor, the example ADE7758 meter shows 0.9668 Hz on the pulse output. This is equivalent to −1.122% error from the reference meter value using Equation 49. STEP 3 MEASURE % ERROR IN APCF CONFIGURE FREQ[11:0] FOR A LINE PERIOD MEASUREMENT 9.6 s Example: Phase Calibration of Phase A Using Pulse Output STEP 2 SET UP SYSTEM FOR ITEST , VNOM, PF = 0.5, INDUCTIVE STEP 4 SELECT PHASE FOR LINE PERIOD MEASUREMENT 1 1 1 (54)   PHCAL _ LSB _ Weight Line Period(s) 360 The Phase Error in degrees using Equation 53 is 0.3713°. CALCULATE PHASE ERROR (DEGREES)  – 1.122%  Phase Error   – Arcsin   0.3713  100%  3  NO PERIOD OF SYSTEM KNOWN? YES STEP 5 CALCULATE AND WRITE TO xPHCAL 04443-078 MEASURE PERIOD USING FREQ[11:0] REGISTER If at 50 Hz the FREQ register = 2083d, the value that should be written to APHCAL is 17d, or 0x11 using Equation 55. Note that a PHCAL_LSB_Weight of 1.2 μs is used because the %Error is negative. APHCAL  0.3713  Figure 79. Phase Calibration Using Pulse Output Step 1: Step 1 and Step 3 from the gain calibration should be repeated to configure the ADE7758 pulse output. Ensure the xPHCAL registers are zero. Step 2: Set the test system for ITEST, VNOM, and 0.5 power factor inductive. Step 3: Measure the percent error in the pulse output, APCF, from the reference meter using Equation 49. Step 4: Calculate the Phase Error in degrees by  %Error  Phase Error   – Arcsin   100%  3  (53) 9.6 μs 2083   17.19  17  0 x11 360 1.2 μs Power Offset Calibration Using Pulse Output Power offset calibration should be used for outstanding performance over a wide dynamic range (1000:1). Calibration of the power offset is done at or close to the minimum current where the desired accuracy is required. The ADE7758 has power offset registers for watts and VAR (xWATTOS and xVAROS). Offsets in the VA measurement are compensated by adjusting the rms offset registers (see the Calibration of IRMS and VRMS Offset section). Figure 80 shows the steps to calibrate the power offsets using the pulse outputs. Rev. E | Page 46 of 72 Data Sheet ADE7758 STEP 1 ENABLE CF OUTPUTS START STEP 2 CLEAR OFFSET REGISTERS xWATTOS, xVAROS YES ALL PHASES WATT OFFSET CALIBRATED? NO STEP 3 SET UP APCF PULSE OUTPUT FOR PHASE A, B, OR C YES ALL PHASES VAR OFFSET CALIBRATED? STEP 4 SET UP SYSTEM FOR IMIN, VNOM, PF = 1 NO STEP 3 END SET UP VARCF PULSE OUTPUT FOR PHASE A, B, OR C STEP 5 SELECT PHASE FOR LINE PERIOD MEASUREMENT STEP 6 MEASURE % ERROR FOR APCF CALCULATE AND WRITE TO xWATTOS CONFIGURE FREQ[11:0] FOR A LINE PERIOD MEASUREMENT STEP 7. REPEAT STEP 3 TO STEP 6 FOR xVAROS STEP 4 SET UP SYSTEM FOR IMIN, VNOM, PF = 0, INDUCTIVE STEP 5 MEASURE % ERROR FOR VARCF MEASURE PERIOD USING FREQ[11:0] REGISTER STEP 6 04443-079 CALCULATE AND WRITE TO xVAROS Figure 80. Offset Calibration Using Pulse Output Step 4: Set the test system for IMIN, VNOM, and unity power factor. For Step 6, set the test system for IMIN, VNOM, and zero-power factor inductive. Step 1: Repeat Step 1 and Step 3 from the gain calibration to configure the ADE7758 pulse output. Step 2: Clear the xWATTOS and xVAROS registers. Step3: Disable the Phase B and Phase C contribution to the APCF and VARCF pulses. This is done by the TERMSEL[2:4] bits of the COMPMODE register (0x16). Setting Bit 2 to Logic 1 and Bit 3 and Bit 4 to Logic 0 allows only Phase A to be included in the pulse outputs. Select Phase A, Phase B, or Phase C for a line period measurement with the FREQSEL[1:0] bits in the MMODE register (0x14). For example, clearing Bit 1 and Bit 0 selects Phase A for line period measurement. Step 5: Measure the percent error in the pulse output, APCF or VARCF, from the reference meter using Equation 49. Step 6: Calculate xWATTOS using Equation 56 (for xVAROS use Equation 57). Rev. E | Page 47 of 72 xWATTOS = 4 APCFDEN (56) ⎛ %APCFERROR ⎞ 2 –⎜ × APCFEXPECTED ⎟ × × 100% ⎝ ⎠ Q APCFNUM ADE7758 Data Sheet xVAROS = For AWATTOS, 4 Q= (57) For AVAROS, Q= where Q is defined in Equation 58 and Equation 59. For xWATTOS, Q= CLKIN 1 1 × 25 × 4 2 4 1 202 1 CLKIN × 24 × × 4 2 ⎛ FREQ[11 : 0] ⎞ 4 ⎜ ⎟ 4 ⎝ ⎠ 10 E 6 1 202 1 × 24 × × = 0.01444 2083 4 4 2 4 Calibration Using Line Accumulation (58) For xVAROS, Q= 10E6 1 1 × 25 × = 0.01863 4 2 4 (59) where the FREQ (0x10) register is configured for line period measurements. Step 7: Repeat Step 3 to Step 6 for xVAROS calibration. Line cycle accumulation mode configures the nine energy registers such that the amount of energy accumulated over an integer number of half line cycles appears in the registers after the LENERGY interrupt. The benefit of using this mode is that the sinusoidal component of the active energy is eliminated. Figure 81 shows a flowchart of how to calibrate the ADE7758 using the line accumulation mode. Calibration of all phases and energies can be done simultaneously using this mode to save time during calibration. Example: Offset Calibration of Phase A Using Pulse Output For this example, IMIN = 50 mA, VNOM = 220 V, VFULLSCALE = 500 V, IFULLSCALE = 130 A, MC = 3200 impulses/kWh, Power Factor = 1, Frequency = 50 Hz, and CLKIN = 10 MHz. START CAL IRMS OFFSET CAL VRMS OFFSET With IMIN, VNOM, and unity power factor, the example ADE7758 meter shows 0.009789 Hz on the APCF pulse output. When the power factor is changed to 0.5 inductive, the VARCF output is 0.009769 Hz. This is equivalent to 0.1198% for the watt measurement and −0.0860% for the VAR measurement. Using Equation 56 through Equation 59, the values 0xFFD and 0x3 should be written to AWATTOS (0x39) and AVAROS (0x3C), respectively. AWATTOS = 0.1198% 24 277 × 0.009778 ⎞⎟ × – ⎛⎜ × = –2.8 = – 3 = 0xFFD 1 ⎝ 100% ⎠ 0.01863 – 0.0860% 24 277 AVAROS = –⎛⎜ × 0.009778 ⎞⎟ × × = 2.6 = 3 ⎝ 100% ⎠ 0.01444 1 CAL WATT AND VA GAIN ALL PHASES @ PF = 1 CAL VAR GAIN ALL PHASES @ PF = 0, INDUCTIVE CALIBRATE PHASE ALL PHASES @ PF = 0.5, INDUCTIVE CALIBRATE ALL PHASES WATT OFFSET @ IMIN AND PF = 1 CALIBRATE ALL PHASES VAR OFFSETS @ IMIN AND PF = 0, INDUCTIVE END 04443-080 ⎛ %VARCFERROR ⎞ 2 –⎜ × VARCFEXPECTED ⎟ × × 100% ⎝ ⎠ Q VARCFDEN VARCFNUM Figure 81. Calibration Using Line Accumulation Rev. E | Page 48 of 72 Data Sheet ADE7758 Gain Calibration Using Line Accumulation Step 2: Select Phase A, Phase B, or Phase C for a line period measurement with the FREQSEL[1:0] bits in the MMODE register (0x14). For example, clearing Bit 1 and Bit 0 selects Phase A for line period measurement. Gain calibration is used for meter-to-meter gain adjustment, APCF or VARCF output rate calibration, and determining the Wh/LSB, VARh/LSB, and VAh/LSB constant. Step 3: Set up ADE7758 for line accumulation by writing 0xBF to LCYCMODE. This enables the line accumulation mode on the xWATTHR, xVARHR, and xVAHR (0x01 to 0x09) registers by setting the LWATT, LVAR, and LVA bits, LCYCMODE[0:2] (0x17), to Logic 1. It also sets the ZXSEL bits, LCYCMODE[3:5], to Logic 1 to enable the zero-crossing detection on all phases for line accumulation. Additionally, the FREQSEL bit, LCYCMODE[7], is set so that FREQ (0x10) stores the line period. When using the line accumulation mode, the RSTREAD bit of LCYCMODE should be set to 0 to disable the read with reset mode. Select the phase for line period measurement in MMODE[1:0]. Step 0: Before performing the gain calibration, the APCFNUM/ APCFDEN (0x45/0x46) and VARCFNUM/ VARCFDEN (0x47/0x48) values can be set to achieve the correct impulses/kWh, impulses/kVAh, or impulses/kVARh using the same method outlined in Step 4 in the Gain Calibration Using Pulse Output section. The calibration of xWG/xVARG/xVAG (0x2A through 0x32) is done with the line accumulation mode. Figure 82 shows the steps involved in calibrating the gain registers using the line accumulation mode. Step 1: Clear xWG, xVARG, and xVAG. Step 4: Set the number of half-line cycles for line accumulation by writing to LINECYC (0x1C). STEP 0 SET APCFNUM/APCFDEN AND VARCFNUM/VARCFDEN STEP 3 SET LYCMODE REGISTER STEP 1 CLEAR xWG/xVAR/xVAG STEP 4 SET ACCUMULATION TIME (LINECYC) STEP 2 SELECT PHASE FOR LINE PERIOD MEASUREMENT STEP 5 SET MASK FOR LENERGY INTERRUPT CONFIGURE FREQ[11:0] FOR A LINE PERIOD MEASUREMENT STEP 6 STEP 11 SET UP SYSTEM FOR ITEST , VNOM, PF = 1 CALIBRATE WATT AND VA @ PF = 1 SET UP TEST SYSTEM FOR ITEST , VNOM, PF = 0, INDUCTIVE STEP 12 FREQUENCY KNOWN? YES STEP 8 RESET STATUS REGISTER STEP 9 STEP 7 READ FREQ[11:0] REGISTER RESET STATUS REGISTER STEP 13 READ ALL xVARHR AFTER LENERGY INTERRUPT READ ALL xWATTHR AND xVAHR AFTER LENERGY INTERRUPT CALCULATE xVARG STEP 9A STEP 15 CALCULATE xWG STEP 9B CALCULATE xVAG STEP 10 WRITE TO xWG AND xVAG Figure 82. Gain Calibration Using Line Accumulation Rev. E | Page 49 of 72 STEP 14 WRITE TO xVARG STEP 16 CALCULATE Wh/LSB, VAh/LSB, VARh/LSB END 04443-081 NO ADE7758 Data Sheet Step 5: Set the LENERGY bit, MASK[12] (0x18), to Logic 1 to enable the interrupt signaling the end of the line cycle accumulation. Step 9b: Calculate the values to be written to the xVAG registers according to the following equation: VAHR EXPECTED = Step 6: Set the test system for ITEST, VNOM, and unity power factor (calibrate watt and VA simultaneously and first). 4 × MC × I TEST × VNOM × AccumTime 1000 × 3600 Step 7: Read the FREQ (0x10) register if the line frequency is unknown. ⎛ VAHR EXPECTED ⎞ − 1⎟⎟ × 212 xVAG = ⎜⎜ VAHR MEASURED ⎝ ⎠ Step 9: Read all six xWATTHR (0x01 to 0x03) and xVAHR (0x07 to 0x09) energy registers after the LENERGY interrupt and store the values. Step 10: Write to xWG and xVAG. Step 9a: Calculate the values to be written to xWG registers according to the following equations: Step 12: Repeat Step 7. × Step 11: Set the test system for ITEST, VNOM, and zero power factor inductive to calibrate VAR gain. Step 13: Read the xVARHR (0x04 to 0x06) after the LENERGY interrupt and store the values. WATTHREXPECTED = 1000 × 3600 (60) Step 14: Calculate the values to be written to the xVARG registers (to adjust VARCF to the expected value). VARHREXPECTED = APCFDEN 1 × APCFNUM WDIV 4 × MC × ITEST × VNOM × sin(θ ) × AccumTime where AccumTime is LINECYC[15:0] 2 × Line Frequency × No. of Phases Selected 1 VARCFDEN × VARCFNUM VADIV (64) Step 8: Reset the interrupt status register by reading RSTATUS (0x1A). 4 × MC × ITEST × VNOM × cos(θ ) × AccumTime × 1000 × 3600 (61) × (65) VARCFDEN 1 × VARCFNUM VARDIV ⎛ VARHREXPECTED ⎞ − 1⎟⎟ × 212 xVARG = ⎜⎜ ⎝ VARHR MEASURED ⎠ where: MC is the meter constant. θ is the angle between the current and voltage. Step 15: Write to xVARG. Line Frequency is known or calculated from the FREQ[11:0] register. With the FREQ[11:0] register configured for line period measurements, the line frequency is calculated with Equation 62. Step 16: Calculate the Wh/LSB, VARh/LSB, and VAh/LSB constants. 1 Line Frequency = FREQ[11 : 0]× 9.6 ×10-6 (62) No. of Phases Selected is the number of ZXSEL bits set to Logic 1 in LCYCMODE (0x17). Then, xWG is calculated as ⎛ WATTHR EXPECTED ⎞ − 1 ⎟⎟ × 212 xWG = ⎜⎜ WATTHR MEASURED ⎝ ⎠ (63) Wh ITEST × VNOM × cos(θ ) × AccumTime = LSB 3600 × xWATTHR (66) VAh I TEST × VNOM × AccumTime = LSB 3600 × xVAHR (67) VARh ITEST × VNOM × sin(θ ) × AccumTime = LSB 3600 × xVARHR (68) Example: Watt Gain Calibration Using Line Accumulation This example shows only Phase A watt calibration. The steps outlined in the Gain Calibration Using Line Accumulation section show how to calibrate watt, VA, and VAR. All three phases can be calibrated simultaneously because there are nine energy registers. For this example, ITEST = 10 A, VNOM = 220 V, Power Factor = 1, Frequency = 50 Hz, LINECYC (0x1C) is set to 0x800, and MC = 3200 imp/kWhr. Rev. E | Page 50 of 72 Data Sheet ADE7758 STEP 1 To set APCFNUM (0x45) and APCFDEN (0x46) to the calculated value to perform a coarse adjustment on the imp/kW-hr ratio, use Equation 45 to Equation 47. APCFNOMINAL = 16 kH z × APCFEXPECTED = SET LCYCMODE, LINECYC AND MASK REGISTERS STEP 2 220 10 × = 0.5415 kHz 500 130 3200 × 10 × 220 1000 × 3600 SET UP SYSTEM FOR ITEST , VNOM, PF = 0.5, INDUCTIVE × cos(θ) = 1.956 Hz STEP 3 RESET STATUS REGISTER ⎛ 541.5 Hz ⎞ ⎟ = 277 APCFDEN = INT⎜ ⎜ 1.956 Hz ⎟ ⎝ ⎠ STEP 4 READ ALL xWATTHR REGISTERS AFTER LENERGY INTERRUPT Under the test conditions above, the AWATTHR register value is 15559d after the LENERGY interrupt. Using Equation 60 and Equation 61, the value to be written to AWG is −199d, 0xF39. AccumTime = STEP 5 CALCULATE PHASE ERROR IN DEGREES FOR ALL PHASES LINECYC[15:0] 1 × No. of Phases Selected 2× FREQ[11 : 0] × 9.6 × 10 −6 STEP 6 AccumTime = 0 x 800 = 6.832128s 1 2× ×3 −6 2085 × 9.6 × 10 WATTHREXPECTED = 4 × 3200 × 10 × 220 × 1 × 6.832 1000 × 3600 × 04443-082 CALCULATE AND WRITE TO ALL xPHCAL REGISTERS Figure 83. Phase Calibration Using Line Accumulation Step 1: If the values were changed after gain calibration, Step 1, Step 3, and Step 4 from the gain calibration should be repeated to configure the LCYCMODE and LINECYC registers. 277 × 1 = 14804 1 Step 2: Set the test system for ITEST, VNOM, and 0.5 power factor inductive. 14804 ⎞ 12 xWG = ⎛⎜ − 1⎟ × 2 = –198.87640 = –199 = 0xF39 ⎝ 15559 ⎠ Step 3: Reset the interrupt status register by reading RSTATUS (0x1A). Using Equation 66, the Wh/LSB constant is Wh 10 × 220 × 6.832 = 0.0002820 = LSB 3600 × 14804 Phase Calibration Using Line Accumulation The ADE7758 includes a phase calibration register on each phase to compensate for small phase errors. Large phase errors should be compensated by adjusting the antialiasing filters. The ADE7758 phase calibration is a time delay with different weights in the positive and negative direction (see the Phase Compensation section). Because a current transformer is a source of phase error, a fixed nominal value can be decided on to load into the xPHCAL (0x3F to 0x41) registers at power-up. During calibration, this value can be adjusted for CT-to-CT error. Figure 83 shows the steps involved in calibrating the phase using the line accumulation mode. Step 4: The xWATTHR registers should be read after the LENERGY interrupt. Measure the percent error in the energy register readings (AWATTHR, BWATTHR, and CWATTHR) compared to the energy register readings at unity power factor (after gain calibration) using Equation 69. The readings at unity power factor should have been repeated after the gain calibration and stored for use in the phase calibration routine. Error = xWATTHRPF = 5 – xWATTHRPF = 1 xWATTHRPF = 1 2 (69) 2 Step 5: Calculate the Phase Error in degrees using the equation ⎛ Error ⎞ Phase Error (°) = – Arcsin⎜ ⎟ ⎝ 3 ⎠ (70) Step 6: Calculate xPHCAL and write to the xPHCAL registers (0x3F to 0x41). xPHCAL = Phase Error × 1 1 1 (71) × × PHCAL _ LSB _ Weight Line Period(s) 360° where PHCAL_LSB_Weight is 1.2 μs if the %Error is negative or 2.4 μs if the %Error is positive (see the Phase Compensation section). Rev. E | Page 51 of 72 ADE7758 Data Sheet If it is not known, the line period is available in the ADE7758 frequency register, FREQ (0x10). To configure line period measurement, select the phase for period measurement in the MMODE[1:0] and set LCYCMODE[7]. Equation 72 shows how to determine the value that needs to be written to xPHCAL using the period register measurement. xPHCAL = Phase Error × 14804d in the AWATTHR register. This is equivalent to −1.132% error. Error = 14804 2 = −0.01132 = −1.132% 14804 2 7318 – The Phase Error in degrees using Equation 66 is 0.374°. 9.6 μs PHCAL _ LSB _ Weight × (72) FREQ[11 : 0] 360° Example: Phase Calibration Using Line Accumulation This example shows only Phase A phase calibration. All three PHCAL registers can be calibrated simultaneously using the same method. ⎛ − 0.01132 ⎞ Phase Error (°) = –Arc sin⎜ ⎟ = 0.374° 3 ⎠ ⎝ Using Equation 72, the value written to APHCAL (0x3F), if at 50 Hz, the FREQ (0x10) register = 2085d, is 17d. Note that a PHCAL_LSB_Weight of 1.2 μs is used because the %Error is negative. For this example, ITEST = 10 A, VNOM = 220 V, power factor = 0.5 inductive, and frequency = 50 Hz. Also, LINECYC = 0x800. APHCAL = 0.374° × With ITEST, VNOM, and 0.5 inductive power factor, the example ADE7758 meter shows 7318d in the AWATTHR (0x01) register. For unity power factor (after gain calibration), the meter shows STEP 1 SET MMODE, LCYCMODE, LINECYC AND MASK REGISTERS STEP 2 SET UP SYSTEM FOR IMIN, VNOM @ PF = 1 STEP 3 RESET STATUS REGISTER STEP 4 FOR STEP 8 READ ALL xVARHR AFTER LENERGY INTERRUPT READ ALL xWATTHR REGISTERS AFTER LENERGY INTERRUPT STEP 5 CALCULATE xWATTOS FOR ALL PHASES FOR STEP 8, CALCULATE xVAROS FOR ALL PHASES STEP 6 WRITE TO ALL xWATTOS REGISTERS FOR STEP 8, WRITE TO ALL xVAROS REGISTERS STEP 7 SET UP SYSTEM FOR ITEST , VNOM @ PF = 0, INDUCTIVE END Figure 84. Power Offset Calibration Using Line Accumulation Rev. E | Page 52 of 72 04443-083 STEP 8 REPEAT STEP 3 TO STEP 8 FOR xVARHR, xVAROS CALIBRATION 9.6 2085 × = 17 = 0 x11 1.2 360 Data Sheet ADE7758 Power Offset Calibration Using Line Accumulation where: Power offset calibration should be used for outstanding performance over a wide dynamic range (1000:1). Calibration of the power offset is done at or close to the minimum current. The ADE7758 has power offset registers for watts and VAR, xWATTOS (0x39 to 0x3B) and xVAROS (0x3C to 0x3E). Offsets in the VA measurement are compensated by adjusting the rms offset registers (see the Calibration of IRMS and VRMS Offset section). AccumTime is defined in Equation 61. xWATTHRITEST is the value in the energy register at ITEST. More line cycles could be required at the minimum current to minimize the effect of quantization error on the offset calibration. For example, if a current of 40 mA results in an active energy accumulation of 113 after 2000 half line cycles, one LSB variation in this reading represents an 0.8% error. This measurement does not provide enough resolution to calibrate out a