ADE7858

Poly Phase Multifunction Energy Metering IC with per Phase Active and Reactive Powers Preliminary Technical Data FEATURES Highly accurate; supports EN 50470-1, EN 50470-3, IEC 62053-21, IEC 62053-22 and IEC 62053-23 Compatible with 3-phase, 3 or 4 wire (delta or wye) and other 3-phase services Supplies total (fundamental and harmonic) active/reactive/ apparent energy on each phase and on the overall system Less than 0.1% error in active and reactive energy over a dynamic range of 1000 to 1 at 25°C Less than 0.2% error in active and reactive energy over a dynamic range of 3000 to 1 at 25°C Supports current transformer and di/dt current sensors Less than 0.1% error in voltage and current rms over a dynamic range of 1000 to 1 at 25°C Supplies sampled waveform data on all 3 phases Selectable No-load threshold level for total active, reactive and apparent powers Phase angle measurements in both current and voltage channels with max 0.3° error Wide supply voltage operation 2.4 to 3.7V Reference 1.2 V (drift 10 ppm/°C typ) with external overdrive capability Single 3.3 V supply 40-Lead Frame Chip Scale (LFCSP) Lead Free Package Operating temperature -40° to 85°C Flexible I2C, SPI®, HSDC serial interfaces ADE7858 processing required to perform total (fundamental and harmonic) active, reactive and apparent energy measurement, and rms calculations. A fixed function digital signal processor (DSP) executes this signal processing. The ADE7858 is suitable to measure active, reactive, and apparent energy in various 3-phase configurations, such as WYE or DELTA services, with both three and four wires. The ADE7858 provides system calibration features for each phase, that is, rms offset correction, phase calibration, and gain calibration. The CF1, CF2 and CF3 logic outputs provide a wide choice of power information: total active/reactive/apparent power or sum of current rms values. The ADE7858 has waveform sample registers that allow access to all ADC outputs. The device also incorporates power quality measurements such as short duration low or high voltage detections, short duration high current variations, line voltage period measurement and angles between phase voltages and currents. Two serial interfaces can be used to communicate with the ADE7858: SPI or I2C while a dedicated high speed interface, HSDC (High Speed Data Capture) port, can be used in conjunction with I2C to provide access to the ADC outputs and real time power information. The ADE7858 has also two interrupt request pins, IRQ0 and IRQ1 , to indicate that an enabled interrupt event has occurred. The ADE7858 is available in 40-lead LFCSP lead free package. GENERAL DESCRIPTION The ADE78581 is a high accuracy, 3-phase electrical energy measurement IC with serial interfaces and three flexible pulse outputs. The ADE7858 incorporates second-order Σ-Δ ADCs, a digital integrator, reference circuitry, and all the signal 1 U.S. patents pending. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADE7858 TABLE OF CONTENTS Features .............................................................................................. 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 4  Specifications..................................................................................... 5  Timing Characteristics ................................................................ 7  Absolute Maximum Ratings.......................................................... 10  ESD Caution ................................................................................ 10  Pin Configuration and Function Descriptions ........................... 11  Terminology .................................................................................... 13  Typical Performance Characteristics ........................................... 14  Test Circuit ...................................................................................... 15  Power Management ........................................................................ 16  PSM0 – Normal Power Mode ............................................... 16  PSM3 – Sleep Mode ............................................................... 16  Power Up Procedure .............................................................. 16  Hardware Reset ....................................................................... 17  Software Reset Functionality ................................................ 17  Theory of Operation ...................................................................... 19  Analog Inputs .............................................................................. 19  Analog to Digital Conversion ................................................... 19  Antialiasing Filter ................................................................... 20  ADC Transfer Function ......................................................... 20  Current Channel ADC............................................................... 20  Current Waveform Gain Registers ....................................... 20  Current Channel HPF ........................................................... 21  Current Channel Sampling ................................................... 21  di/dt Curent Sensor And Digital Integrator ............................ 22  Voltage Channel ADC ............................................................... 22  Voltage Waveform Gain Registers ........................................ 23  Voltage Channel HPF ............................................................ 23  Voltage Channel Sampling .................................................... 23  Changing Phase Voltage Data Path .......................................... 23  Power Quality Measurements ................................................... 24  Zero Crossing Detection ....................................................... 24  Zero-Crossing Timeout ......................................................... 25  Phase Sequence Detection .................................................... 25  Time Interval Between Phases.............................................. 25  Period Measurement .............................................................. 26  Phase Voltage Sag Detection ................................................. 26  Peak Detection ........................................................................ 27  Rev. PrA| Page 2 of 76 Preliminary Technical Data Overvoltage and Overcurrent Detection ............................ 28  Phase Compensation ................................................................. 29  Reference Circuit ........................................................................ 30  Digital Signal Processor............................................................. 30  Root Mean Square Measurement ............................................. 31  Current RMS Calculation ..................................................... 31  Voltage Channel RMS Calculation ...................................... 32  Voltage RMS Offset Compensation ..................................... 32  Active Power Calculation .......................................................... 33  Total Active Power Calculation ............................................ 33  Active Power Gain Calibration............................................. 34  Active Power Offset Calibration .......................................... 34  Sign of Active Power Calculation......................................... 34  Active Energy Calculation .................................................... 35  Integration Time Under Steady Load .................................. 36  Energy Accumulation Modes ............................................... 36  Line Cycle Active Energy Accumulation Mode ................. 36  Reactive Power Calculation ...................................................... 37  Reactive Power Gain Calibration ......................................... 38  Reactive Power Offset Calibration ....................................... 38  Sign of Reactive Power Calculation ..................................... 38  Reactive Energy Calculation................................................. 39  Integration Time Under Steady Load .................................. 40  Energy Accumulation Modes ............................................... 40  Line Cycle Reactive Energy Accumulation Mode ............. 40  Apparent Power Calculation ..................................................... 41  Apparent Power Gain Calibration ....................................... 41  Apparent Power Offset Calibration ..................................... 42  Apparent Power Calculation using VNOM........................ 42  Apparent Energy Calculation ............................................... 42  Integration Time Under Steady Load .................................. 43  Energy Accumulation Mode................................................. 43  Line Cycle Apparent Energy Accumulation Mode............ 43  Waveform Sampling Mode ....................................................... 43  Energy to Frequency Conversion............................................. 44  Synchronizing energy registers with CFx outputs ............ 45  CF outputs for various accumulation modes ..................... 46  Sign of sum of phase powers in CFx data path .................. 47  No-Load Condition ................................................................... 47  Preliminary Technical Data No-load detection based on total active and reactive powers.......................................................................................47  No-load detection based on apparent power ......................48  Checksum Register .....................................................................48  Interrupts......................................................................................49  Using the Interrupts with an MCU ......................................50  Serial Interfaces ...........................................................................50  Serial interface choice .............................................................50  ADE7858 I2C Compatible Interface ....................................................... 51  SPI Compatible Interface ....................................................... 52  HSDC Interface ....................................................................... 54  Registers List .................................................................................... 57  Outline Dimensions ........................................................................ 73  Ordering Guide ........................................................................... 73  Rev. PrA | Page 3 of 76 ADE7858 FUNCTIONAL BLOCK DIAGRAM RESET Preliminary Technical Data REFin/out 17 VDD 26 AGND 25 AVDD 24 DVDD 5 DGND 6 AIRMSOS LPF 4 CLKIN CLKOUT 27 POR 28 1.2V REF LDO LDO x2 LPF  AIRMS AVAGAIN 2 3 PM0 PM1 x2 AIGAIN IAP IAN 7 8 PGA1 ADC HPFDIS[23:0]  AVRMS CF1DEN Digital Integrator AVRMSOS AWATTOS LPF AWGAIN DFC  APHCAL AVGAIN HPF : CF2DEN 33 CF1 HPFDIS[23:0]  VAP 23 PGA3 ADC  HPF Phase A,B and C data AVAROS AVARGAIN CF3DEN DFC : 34 CF2 IBP IBN VBP 9 12 22 PGA1 ADC TOTAL ACTIVE/ REACTIVE/ APPARENT ENERGIES AND VOLTAGE/CURRENT RMS CALCULATION FOR PHASE B (see phase A for detailed data path) Computational Block for Total Reactive Power  DFC : 35 CF3/HSCLK PGA3 ADC 29 ICP ICN VCP VN 13 14 19 18 PGA3 ADC PGA1 ADC TOTAL ACTIVE/ REACTIVE/ APPARENT ENERGIES AND VOLTAGE/CURRENT RMS CALCULATION FOR PHASE C (see phase A for detailed data path) SPI/I2C 32 36 38 IRQ0 IRQ1 SCLK/SCL MOSI/SDA MISO/HSD Digital Signal Processor I2C 37 39 SS /HSA HSDC Figure 1. ADE7858 Functional Block Diagram Rev. PrA| Page 4 of 76 Preliminary Technical Data SPECIFICATIONS VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C. Table 1. Parameter1, 2 ACCURACY ACTIVE ENERGY MEASUREMENT Total Active Energy Measurement Error (per Phase) Phase Error Between Channels PF = 0.8 Capacitive PF = 0.5 Inductive AC Power Supply Rejection Output Frequency Variation DC Power Supply Rejection Output Frequency Variation Total Active Energy Measurement Bandwidth REACTIVE ENERGY MEASUREMENT Total Reactive Energy Measurement Error (per Phase) Phase Error Between Channels PF = 0.8 Capacitive PF = 0.5 Inductive AC Power Supply Rejection Output Frequency Variation DC Power Supply Rejection Output Frequency Variation Total Reactive Energy Measurement Bandwidth RMS MEASUREMENTS IRMS and VRMS Measurement Bandwidth IRMS and VRMS Measurement Error (PSM0 mode3) ANALOG INPUTS Maximum Signal Levels Input Impedance (DC) ADC Offset Error Gain Error WAVEFORM SAMPLING Current and Voltage Channels Signal-to-Noise Ratio Signal-to-Noise Plus Distortion Bandwidth (−3 dB) Specification Unit Test Conditions/Comments ADE7858 0.1 0.2 0.1 ±0.05 ±0.05 % typ % typ %typ °max °max Over a dynamic range of 1000 to 1, PGA=1,2,4;integrator off Over a dynamic range of 3000 to 1, PGA=1,2,4; integrator off Over a dynamic range of 500 to 1, PGA = 8, 16; integrator on Line frequency = 45 Hz to 65 Hz, HPF on Phase lead 37° Phase lag 60° TBD Conditions 0.01 0.01 2 % typ TBD Conditions % typ kHz typ 0.1 0.2 0.1 ±0.05 ±0.05 % typ % typ %typ °max °max Over a dynamic range of 1000 to 1, PGA=1,2,4;integrator off Over a dynamic range of 3000 to 1, PGA=1,2,4;integrator off Over a dynamic range of 500 to 1, PGA = 8, 16; integrator on Line frequency = 45 Hz to 65 Hz, HPF on Phase lead 37° Phase lag 60° TBD Conditions 0.01 0.01 2 % typ TBD Conditions % typ kHz typ 2 0.1 kHz typ % typ Over a dynamic range of 1000:1, PGA=1 ±500 400 ±25 ±4 mV peak, Max kΩ min mV max % typ Differential inputs: IAP-IAN, IBP-IBN, ICP-ICN Single ended inputs: VAP-VN, VBP-VN, VCP-VN Uncalibrated error, see the Terminology section External 1.2 V reference Sampling CLKIN/2048, 16.384 MHz/2048 = 8 kSPS See Waveform Sampling Mode chapter 55 62 2 dB typ dB typ kHz Rev. PrA | Page 5 of 76 ADE7858 Parameter1, 2 TIME INTERVAL BETWEEN PHASES Measurement error CF1, CF2, CF3 PULSE OUTPUTS Maximum Output Frequency Duty Cycle Active Low Pulse Width Jitter REFERENCE INPUT REFIN/OUT Input Voltage Range Input Capacitance ON-CHIP REFERENCE (PSM0 mode3) Reference Error Output Impedance Temperature Coefficient Specification 0.3 8 50 80 0.04 1.3 1.1 10 ±0.9 4 10 50 CLKIN Input Clock Frequency Crystal equivalent series resistance CLKIN input capacitance CLKOUT output capacitance LOGIC INPUTS—MOSI/SDA, SCLK/SCL, CLKIN and SS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS— IRQ0 , IRQ1 , MISO/HSDATA, HSCLK and CLKOUT Output High Voltage, VOH Output Low Voltage, VOL CF1, CF2, CF3 Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY in PSM0 mode VDD IDD POWER SUPPLY in PSM3 mode3 VDD IDD in PSM3 mode3 1 2 Preliminary Technical Data Unit deg typ KHz % Msec % typ V max V min pF max mV max kΩ min ppm/°C typ ppm/°C max All specifications CLKIN of 16.384 MHz 16.384 30 50 12 12 MHz max KΩ min KΩ max pF typ pF typ Test Conditions/Comments Line frequency = 45 Hz to 65 Hz, HPF on If CF1, CF2 or CF3 frequency >6.25Hz If CF1, CF2 or CF3 frequency