ADE9000ACPZ

Data Sheet High Performance, Multiphase Energy, and Power Quality Monitoring IC ADE9000 FEATURES 7 high performance ADCs 101 dB SNR Wide input voltage range: ±1 V, 707 mV rms FS at gain = 1 Differential inputs ±25 ppm/°C maximum channel drift (including ADC, internal VREF, PGA drift) enabling 10000:1 dynamic input range Class 0.2 metrology with standard external components Power quality measurements Enables implementation of IEC 61000-4-30 Class S VRMS ½, IRMS ½ rms voltage refreshed each half cycle 10 cycle rms/12 cycle rms Dip and swell monitors Line frequency—one per phase Zero crossing, zero-crossing timeout Phase angle measurements Supports CTs and Rogowski coil (di/dt) sensors Multiple range phase/gain compensation for CTs Digital integrator for Rogowski coils Flexible waveform buffer Able to resample waveform to ensure 128 points per line cycle for ease of external harmonic analysis GENERAL DESCRIPTION The ADE90001 is a highly accurate, fully integrated, multiphase energy and power quality monitoring device. Superior analog performance and a digital signal processing (DSP) core enable accurate energy monitoring over a wide dynamic range. An integrated high end reference ensures low drift over temperature with a combined drift of less than ±25 ppm/°C maximum for the entire channel including a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC). The ADE9000 offers complete power monitoring capability by providing total as well as fundamental measurements on rms, active, reactive, and apparent powers and energies. Advanced features such as dip and swell monitoring, frequency, phase angle, voltage total harmonic distortion (VTHD), current total harmonic distortion (ITHD), and power factor measurements enable implementation of power quality measurements. The ½ cycle rms and 10 cycle rms/12 cycle rms, calculated according to IEC 61000-4-30 Class S, provide instantaneous rms measurements for real-time monitoring. The ADE9000 offers an integrated flexible waveform buffer that stores samples at a fixed data rate of 32 kSPS or 8 kSPS, or a 1 Protected by U.S. Patents 8,350,558; 8,010,304. Other patents are pending. Rev. A Events, such as dip and swell, can trigger waveform storage Simplifies data collection for IEC 61000-4-7 harmonic analysis Advanced metrology feature set Total and fundamental active power, volt amperes reactive (VAR), volt amperes (VA), watthour, VAR hour, and VA hour Total and fundamental IRMS, VRMS Total harmonic distortion Power factor Supports active energy standards: IEC 62053-21 and IEC 62053-22; EN50470-3; OIML R46; and ANSI C12.20 Supports reactive energy standards: IEC 62053-23, IEC 62053-24 High speed communication port: 20 MHz serial port interface (SPI) Integrated temperature sensor with 12-bit successive approximation register (SAR) ADC ±3°C accuracy from −40°C to +85°C APPLICATIONS Energy and power monitoring Power quality monitoring Protective devices Machine health Smart power distribution units Polyphase energy meters sampling rate that varies based on line frequency to ensure 128 points per line cycle. Resampling simplifies fast Fourier transform (FFT) calculation of at least 50 harmonics in an external processor. The ADE9000 simplifies the implementation of energy and power quality monitoring systems by providing tight integration of acquisition and calculation engines. The integrated ADCs and DSP engine calculate various parameters and provide data through user accessible registers or indicate events through interrupt pins. With seven dedicated ADC channels, the ADE9000 can be used on a 3-phase system or up to three single-phase systems. It supports current transformers (CTs) or Rogowski coils for current measurements. A digital integrator eliminates a discrete integrator required for Rogowski coils. The ADE9000 absorbs most complexity in calculations for a power monitoring system. With a simple host microcontroller, the ADE9000 enables the design of standalone monitoring or protection systems, or low cost nodes uploading data into the cloud. Note that throughout this data sheet, multifunction pins, such as CF4/EVENT/DREADY, are referred to either by the entire pin name or by a single function of the pin, for example, EVENT, when only that function is relevant. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADE9000 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Signal-to-Noise Ratio Performance ......................................... 23 Applications ....................................................................................... 1 Test Circuit ...................................................................................... 24 General Description ......................................................................... 1 Terminology .................................................................................... 25 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 26 Typical Applications Circuit............................................................ 3 Measurements ............................................................................. 26 Specifications..................................................................................... 4 Power Quality Measurements................................................... 31 Timing Characteristics ................................................................ 8 Waveform Buffer ............................................................................ 35 Absolute Maximum Ratings ............................................................ 9 Interrupts/Events ............................................................................ 36 Thermal Resistance ...................................................................... 9 Accessing On-Chip Data ............................................................... 37 ESD Caution .................................................................................. 9 SPI Protocol Overview .............................................................. 37 Pin Configuration and Function Descriptions ........................... 10 Additional Communication Verification Registers ............... 37 Typical Performance Characteristics ........................................... 12 CRC of Configuration Registers............................................... 37 Energy Linearity over Supply and Temperature..................... 12 Configuration Lock .................................................................... 37 Energy Error over Frequency and Power Factor .................... 15 Register Map ................................................................................... 38 Energy Linearity Repeatability ................................................. 16 Register Details ............................................................................... 51 RMS Linearity over Temperature and RMS Error over Frequency .................................................................................... 17 Outline Dimensions ....................................................................... 72 Ordering Guide .......................................................................... 72 Energy and RMS Linearity with Integrator On ...................... 19 Energy and RMS Error over Frequency with Integrator On ..... 21 REVISION HISTORY 6/2017—Rev. 0 to Rev. A Changes to General Description .................................................... 1 Change to Operating Temperature Parameter, Table 3 ............... 9 Change to Temperature Section ................................................... 34 Change to Waveform Buffer Section............................................ 35 Change to Address 0x4FE, Table 6 ............................................... 47 1/2017—Revision 0: Initial Version Rev. A | Page 2 of 72 Data Sheet ADE9000 TYPICAL APPLICATIONS CIRCUIT PHASE A PHASE B PHASE C NEUTRAL ADE9000 1.25V REFERENCE IAN CLKIN DIGITAL BLOCK CLKOUT ADC PGA RESET SINC + DECIMATION VAP ANTIALIASING VAN FILTER IBP ANTIALIASING IBN FILTER VBP ANTIALIASING FILTER VBN ANTIALIASING FILTER LOAD LOAD LOAD ADC PGA ICP ICN VCP ANTIALIASING VCN FILTER ANTIALIASING FILTER ADC PGA PGA ADC PGA ADC INP INN GND ADC PGA TEMP SENSOR SAR DSP ENGINE TOTAL AND FUNDAMENTAL: (IRMS, VRMS, ACTIVE, REACTIVE, APPARENT POWER AND ENERGY) VTHD, ITHD, FREQUENCY, PHASE ANGLE, POWER FACTOR, VPEAK, IPEAK, DIP, SWELL, OVERCURRENT, FAST RMS, 10 CYCLE RMS/ 12 CYCLE RMS, PHASE SEQ ERROR. RESAMPLING ENGINE Rev. A | Page 3 of 72 IRQ0 IRQ1 CF1 DIGITAL TO FREQUENCY CONVERSION (CF) CF2 CF3/ZX CF4/EVENT/DREADY USER ACCESSIBLE REGISTERS SPI INTERFACE SS SCLK MISO MOSI WAVEFORM BUFFER (32kSPS, 8kSPS ADC SAMPLES OR RESAMPLED DATA) Figure 1. EVENT INTERRUPTS 15210-001 IAP ANTIALIASING FILTER ADE9000 Data Sheet SPECIFICATIONS VDD = 2.97 V to 3.63 V, GND = AGND = DGND = 0 V, on-chip reference, CLKIN = 24.576 MHz crystal (XTAL), TMIN to TMAX = −40°C to +85°C, TA = 25°C (typical), unless otherwise noted. Table 1. Parameter ACCURACY (MEASUREMENT ERROR PER PHASE) Total Active Energy Total Reactive Energy Total Apparent Energy Fundamental Active Energy Fundamental Reactive Energy Min Typ Max Unit Test Conditions/Comments 0.1 % 0.2 % 0.1 % 0.2 % 0.1 % 0.2 % 0.1 % 0.2 % 0.1 % 0.5 % 0.1 % 0.5 % 0.1 % 0.2 % 0.1 % 0.2 % 0.1 % 0.2 % 0.1 % 0.2 % Over a dynamic range of 5000 to 1, 10 sec accumulation Over a dynamic range of 10,000 to 1, 20 sec accumulation Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, high-pass filter (HPF) corner = 4.98 Hz Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 5000 to 1, 10 sec accumulation Over a dynamic range of 10,000 to 1, 20 sec accumulation Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 1000 to 1, 2 sec accumulation Over a dynamic range of 5000 to 1, 10 sec accumulation Over a dynamic range of 500 to 1, 1 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 5000 to 1, 2 sec accumulation Over a dynamic range of 10,000 to 1, 10 sec accumulation Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 5000 to 1, 2 sec accumulation Over a dynamic range of 10,000 to 1, 10 sec accumulation Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Rev. A | Page 4 of 72 Data Sheet Parameter Fundamental Apparent Energy ADE9000 Min Typ 0.1 Max Unit % 0.5 % 0.1 % 0.5 % 0.1 0.5 0.1 % % % 0.5 % 0.1 0.5 0.1 % % % 0.5 % 0.2 0.4 0.2 % % % 0.5 % ±0.001 0.1 % % −72 dB 1.25 % −38 dB VRMS½, IRMS½ RMS Voltage Refreshed Each Half-Cycle 1 10 Cycle/12 Cycle IRMS, VRMS1 0.25 % 0.2 % Line Period Measurement Current to Current, Voltage to Voltage, and Voltage to Current Angle Measurement 0.001 0.018 Hz Degrees IRMS, VRMS Fundamental IRMS, VRMS Active Power, VAR, VA Power Factor (PF) Error 128-Point per Line Cycle Resampled Data Rev. A | Page 5 of 72 Test Conditions/Comments Over a dynamic range of 5000 to 1, 2 sec accumulation Over a dynamic range of 10,000 to 1, 10 sec accumulation Over a dynamic range of 1000 to 1, 2 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 5000 to 1, 10 sec accumulation, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 1000 to 1 Over a dynamic range of 5000 to 1 Over a dynamic range of 500 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 1000 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 1000 to 1 Over a dynamic range of 5000 to 1 Over a dynamic range of 500 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 2000 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 1000 to 1 Over a dynamic range of, 3000 to 1 Over a dynamic range of 500 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 1000 to 1, PGA = 4, integrator on, HPF corner = 4.98 Hz Over a dynamic range of 5000 to 1 An FFT is performed to receive the magnitude response; this error is the worst case error in the magnitude caused by resampling algorithm distortion; input signal is 50 Hz fundamental and ninth harmonic both at half of full scale (FS) Amplitude of highest spur; input signal is 50 Hz fundamental and ninth harmonic both at half of FS An FFT is performed to receive the magnitude response; this error is the worst case error in the magnitude caused by resampling algorithm distortion; input signal is 50 Hz fundamental and 31st harmonic, both at half of FS Amplitude of highest spur; input signal is 50 Hz fundamental and 31st harmonic, both at half of FS Data sourced before HPF, no dc offset at inputs, over a dynamic range of 100 to 1 Data sourced before HPF, no dc offset at inputs, over a dynamic range of 100 to 1 Resolution at 50 Hz Resolution at 50 Hz ADE9000 Parameter ADC PGA Gain Settings (PGA_GAIN) Differential Input Voltage Range (VxP to VxN, IxP to IxN) Maximum Operating Voltage on Analog Input Pins (VxP, VxN, IxP, and IxN) Signal-to-Noise Ratio (SNR) 2 PGA = 1 Data Sheet Min Max Unit Test Conditions/Comments −1/Gain +1/Gain V/V V −0.6 +0.6 V PGA gain setting is referred to as PGA_GAIN 707 mV rms, when VREF = 1.25 V, this voltage corresponds to 53 million codes Voltage on the pin with respect to ground (GND = AGND = DGND = REFGND) 1, 2, or 4 PGA = 4 Total Harmonic Distortion (THD)2 PGA = 1 PGA = 4 Signal-to-Noise and Distortion Ratio (SINAD)2 PGA = 1 PGA = 4 Spurious-Free Dynamic Range (SFDR)2 PGA = 1 Output Pass Band (0.1dB) Sinc4 Outputs Sinc4 + IIR LPF Outputs Output Bandwidth (−3 dB) 2 Sinc4 Outputs Sinc4 + IIR LPF Outputs Crosstalk2 AC Power Supply Rejection Ratio (AC PSRR)2 Common-Mode Rejection Ratio (AC CMRR)2 Gain Error Gain Drift2 Offset Offset Drift2 Channel Drift (PGA, ADC, Internal Voltage Reference) Differential Input Impedance (DC) Typ 96 101 dB dB 93 96 dB dB −101 −101 −95 −95 dB dB −107 −107 −99 −99 dB dB 32 kSPS, sinc4 output, VIN = −0.5 dB from FS 8 kSPS, sinc4 + IIR LPF output, VIN = −0.5 dB from FS 32 kSPS, sinc4 output 8 kSPS, sinc4 + IIR LPF output 95 98 dB dB 93 96 dB dB 100 100 dB dB 32 kSPS, sinc4 output, VIN = −0.5 dB from FS 8 kSPS, sinc4 + IIR LPF output, VIN = −0.5 dB from FS 1.344 1.344 kHz kHz 32 kSPS, sinc4 output 8 kSPS output 7.2 3.2 −120 −120 kHz kHz dB dB 32 kSPS, sinc4 output 8 kSPS output At 50 Hz or 60 Hz, see the Terminology section At 50 Hz, see the Terminology section 115 dB At 100 Hz and 120 Hz %typ ppm/°C mV µV/°C ppm/°C See the Terminology section See the Terminology section See the Terminology section See the Terminology section PGA = 1, internal VREF ppm/°C ppm/°C kΩ kΩ kΩ PGA = 2, internal VREF PGA = 4, internal VREF PGA = 1, see the Terminology section PGA = 2 PGA = 4 ±0.3 ±3 ±0.040 0 ±7 165 80 40 32 kSPS, sinc4 output, VIN = −0.5 dB from FS 8 kSPS, sinc4 + infinite impulse response (IIR), low-pass filter (LPF) output, VIN = −0.5 dB from FS 32 kSPS, sinc4 output 8 kSPS, sinc4 + IIR LPF output ±7 ±7 185 90 45 ±1 ±3.8 ±2 ±25 ±25 ±25 Rev. A | Page 6 of 72 32 kSPS, sinc4 output, VIN = −0.5 dB from FS 8 kSPS, sinc4 + IIR LPF output, VIN = −0.5 dB from FS 32 kSPS, sinc4 output 8 kSPS, sinc4 + IIR LPF output Data Sheet Parameter INTERNAL VOLTAGE REFERENCE Voltage Reference Temperature Coefficient2 ADE9000 Min EXTERNAL VOLTAGE REFERENCE Input Voltage (REF) Input Impedance TEMPERATURE SENSOR Temperature Accuracy Typ Max Unit 1.250 ±5 ±20 V ppm/°C 1.2 or 1.25 V 7.5 kΩ ±2 ±3 °C °C °C Temperature Readout Step Size CRYSTAL OSCILLATOR Input Clock Frequency Internal Capacitance on CLKIN, CLKOUT Internal Feedback Resistance Between CLKIN and CLKOUT Transconductance (gm) EXTERNAL CLOCK INPUT Input Clock Frequency Duty Cycle2 CLKIN Logic Input Voltage High, VINH Low, VINL LOGIC INPUTS (PM0, PM1, RESET, MOSI, SCLK, and SS) Input Voltage VINH VINL Input Current, IIN Internal Capacitance, CIN LOGIC OUTPUTS MISO, IRQ0, and IRQ1 Output Voltage High, VOH Low, VOL Internal Capacitance, CIN C1, CF2, CF3, and CF4 Output Voltage VOH VOL CIN LOW DROPOUT REGULATORS (LDOs) AVDD DVDD 0.3 Test Conditions/Comments Nominal = 1.25 V ± 1 mV TA = 25°C, REF pin TA = −40°C to +85°C, tested during device characterization REFGND must be tied to GND, AGND, and DGND, a 1.25 V external reference is preferred; the FS values mentioned in this data sheet are for a voltage reference of 1.25 V −10°C to +40°C −40°C to +85°C All specifications use CLKIN = 24.576 MHz ± 30 ppm 24.33 24.576 4 2.45 5 8 24.330 45:55 24.576 50:50 24.822 MHz pF MΩ mA/V 24.822 55:45 MHz % 0.5 V V 0.8 15 10 V V µA pF 0.8 10 V V pF ISOURCE = 4 mA ISINK = 4 mA 0.8 10 V V pF ISOURCE = 7 mA ISINK = 8 mA 1.2 2.4 2.4 2.4 1.9 1.7 V V Rev. A | Page 7 of 72 ±1% 3.3 V tolerant VDD = 2.97 V to 3.63 V VDD = 2.97 V to 3.63 V VIN = 0 V ADE9000 Data Sheet Parameter POWER SUPPLY VDD Supply Current (VDD) Power Save Mode 0 (PSM0) Min Typ Max Unit Test Conditions/Comments 2.97 3.3 3.63 V Power-on reset level is 2.4 V to 2.6 V 15 14.5 90 17 16.5 300 mA mA nA Normal mode Normal mode, six ADCs enabled Idle, VDD = 3.3 V, AVDD = 0 V, DVDD = 0 V Power Save Mode 3 (PSM3) 1 2 Enables implementation of IEC 61000-4-30 Class S. Tested during device characterization. TIMING CHARACTERISTICS Table 2. Parameter SS to SCLK Edge SCLK Frequency SCLK Low Pulse Width SCLK High Pulse Width Data Output Valid After SCLK Edge Data Input Setup Time Before SCLK Edge Data Input Hold Time After SCLK Edge Data Output Fall Time Data Output Rise Time SCLK Fall Time SCLK Rise Time MISO Disable Time After SS Rising Edge SS High After SCLK Edge Symbol tSS fSCLK tSL tSH tDAV tDSU tDHD tDF tDR tSF tSR tDIS tSFS Min 10 Typ Max 20 20 20 20 10 10 10 10 10 10 100 0 SS tSS tSFS SCLK tSL tSH tDAV tSF tSR tDIS MSB MISO INTERMEDIATE BITS tDF LSB tDR INTERMEDIATE BITS LSB IN MSB IN MOSI 15210-002 tDSU tDHD Figure 2. SPI Interface Timing Digram Rev. A | Page 8 of 72 Unit ns MHz ns ns ns ns ns ns ns ns ns ns ns Data Sheet ADE9000 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Parameter VDD to GND Analog Input Voltage to GND, IAP, IAN, IBP, IBN, ICP, ICN, VAP, VAN, VBP, VBN, VCP, VCN Reference Input Voltage to REFGND Digital Input Voltage to GND Digital Output Voltage to GND Operating Temperature Industrial Range Storage Temperature Range Junction Temperature Lead Temperature (Soldering, 10 sec)1 ESD Human Body Model2 Machine Model3 Field Induced Charged Device Model (FICDM) 4 Rating −0.3 V to +3.96 V −2 V to +2 V −0.3 V to +2 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +150°C 125°C 260°C θJA and θJC are specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type CP-40-71 1 θJC 3.13 Unit °C/W The junction to air measurement uses a 2S2P JEDEC test board with 4 × 4 standard JEDEC vias. The junction to case measurement uses a 1S0P JEDEC test board with 4 × 4 standard JEDEC vias. See JEDEC standard JESD51-2. ESD CAUTION 4 kV 300 V 1.25 kV θJA 27.14 Analog Devices recommends that reflow profiles used in soldering RoHS compliant devices conform to J-STD-020D.1 from JEDEC. Refer to JEDEC for the latest revision of this standard. 2 Applicable standard: ANSI/ESDA/JEDEC JS-001-2014. 3 Applicable standard: JESD22-A115-A (ESD machine model standard of JEDEC). 4 Applicable standard: JESD22-C101F (ESD FICDM standard of JEDEC). 1 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 9 of 72 ADE9000 Data Sheet 40 39 38 37 36 35 34 33 32 31 SS MOSI MISO SCLK CF4/EVENT/DREADY CF3/ZX CF2 CF1 IRQ1 IRQ0 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADE9000 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 CLKOUT CLKIN GND VDD AGND AVDDOUT VCP VCN VBP VBN NOTES 1. IT IS RECOMMENDED TO TIE THE NC1 AND NC2 PINS TO GROUND. 2. EXPOSED PAD. CREATE A SIMILAR PAD ON THE PRINTED CIRCUIT BOARD (PCB) UNDER THE EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE PAD ON THE PCB TO CONFER MECHANICAL STRENGTH TO THE PACKAGE AND CONNECT ALL GROUNDS (GND, AGND, DGND, AND REFGND) TOGETHER AT THIS POINT. 15210-003 ICP ICN INP INN REFGND REF NC1 NC2 VAN VAP 11 12 13 14 15 16 17 18 19 20 PULL_HIGH 1 DGND 2 DVDDOUT 3 PM0 4 PM1 5 RESET 6 IAP 7 IAN 8 IBP 9 IBN 10 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 Mnemonic PULL_HIGH DGND 3 DVDDOUT 4 PM0 5 PM1 6 7, 8 RESET IAP, IAN 9, 10 IBP, IBN 11, 12 ICP, ICN 13, 14 INP, INN 15 REFGND 16 REF 17 18 NC1 NC2 Description Pull High. Tie this pin to VDD. Digital Ground. This pin provides the ground reference for the digital circuitry in the ADE9000. Because the digital return currents in the ADE9000 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point. 1.8 V Output of the Digital Low Dropout Regulator (LDO). Decouple this pin with a 0.1 µF ceramic capacitor in parallel with a 4.7 µF ceramic capacitor. Power Mode Pin 0. PM0, combined with PM1, defines the power mode. For normal operation, ground PM0 and PM1. Power Mode Pin 1. PM1 combined with PM0, defines the power mode. For normal operation, ground PM0 and PM1. Reset Input, Active Low. This pin must stay low for at least 1 µs to trigger a hardware reset. Analog Inputs, Channel IA. The IAP (positive) and IAN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. Analog Inputs, Channel IB. The IBP (positive) and IBN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. Analog Inputs, Channel IC. The ICP (positive) and ICN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. Analog Inputs, Channel IN. The INP (positive) and INN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. Ground Reference, Internal Voltage Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point. Voltage Reference. The REF pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.25 V. An external reference source of 1.2 V to 1.25 V can also be connected at this pin. In either case, decouple REF to REFGND with 0.1 µF ceramic capacitor in parallel with a 4.7 µF ceramic capacitor. After reset, the on-chip reference is enabled. To use the internal voltage reference with external circuits, a buffer is required. No Connection. It is recommended to tie this pin to ground. No Connection. It is recommended to tie this pin to ground. Rev. A | Page 10 of 72 Data Sheet Pin No. 19, 20 Mnemonic VAN, VAP 21, 22 VBN, VBP 23, 24 VCN, VCP 25 AVDDOUT 26 27 AGND VDD 28 29 GND CLKIN 30 CLKOUT 31 IRQ0 32 IRQ1 33 CF1 34 35 36 37 CF2 CF3/ZX CF4/EVENT/DREADY SCLK 38 39 40 MISO MOSI SS EPAD ADE9000 Description Analog Inputs, Channel VA. The VAP (positive) and VAN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. Analog Inputs, Channel VB. The VBP (positive) and VBN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. Analog Inputs, Channel VC. The VCP (positive) and VCN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4. 1.9 V Output of the Analog Low Dropout Regulator (LDO). Decouple AVDDOUT with a 0.1 µF ceramic capacitor in parallel with a 4.7 µF ceramic capacitor. Do not connect external active circuitry to this pin. Analog Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point. Supply Voltage. The VDD pin provides the supply voltage. Decouple VDD to GND with a ceramic 0.1 µF capacitor in parallel with a 10 µF ceramic capacitor. Supply Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point. Crystal/Clock Input. Connect a crystal across CLKIN and CLKOUT to provide a clock source. Alternatively, an external clock can be provided at this logic input. Crystal Output. Connect a crystal across CLKIN and CLKOUT to provide a clock source. When using CLKOUT to drive external circuits, connect an external buffer. Interrupt Request Output. This pin is an active low logic output. See the Interrupts/Events section for information about events that trigger interrupts. Interrupt Request Output. This pin is an active low logic output. See the Interrupts/Events section for information about events that trigger interrupts. Calibration Frequency (CF) Logic Output 1. The CF1, CF2, CF3, and CF4 outputs provide power information based on the CFxSEL bits in the CFMODE register. Use these outputs for operational and calibration purposes. Scale the full-scale output frequency by writing to the CFxDEN registers (see the Digital to Frequency Conversion—CFx Output section). CF Logic Output 2. This pin indicates CF2. CF Logic Output 3/Zero Crossing. This pin indicates CF3 or zero crossing. CF Logic Output 4/Event Pin/Data Ready. This pin indicates CF4, events, or when new data is ready. Serial Clock Input for the SPI Port. All serial data transfers synchronize to this clock (see the Accessing OnChip Data section). The SCLK pin has a Schmitt trigger input for use with a clock source that has a slow edge transition time, for example, optoisolator outputs. Data Output for the SPI Port. Data Input for the SPI Port. Slave Select for the SPI Port. Exposed Pad. Create a similar pad on the printed circuit board (PCB) under the exposed pad. Solder the exposed pad to the pad on the PCB to confer mechanical strength to the package and connect all grounds (GND, AGND, DGND, and REFGND) together at this point. Rev. A | Page 11 of 72 ADE9000 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE Total energies obtained from a sinusoidal voltage with an amplitude of 50% of full scale and a frequency of 50 Hz, a sinusoidal current with variable amplitudes from 100% of full scale down to 0.01% or 0.02% of full scale, a frequency of 50 Hz, and the integrator off. Fundamental energies obtained with a fundamental voltage component, with an amplitude of 50% of full scale in phase with a fifth harmonic, a current with a 50 Hz component that has variable amplitudes from 100% of full scale down to 0.01% of full scale, a fifth harmonic with a constant amplitude of 40% of fundamental, and the integrator off, unless otherwise noted. 0.5 0.5 TA = +85°C TA = +25°C TA = –40°C 0.1 –0.1 10 100 –0.5 0.01 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 4. Total Active Energy Error as a Percentage of Full-Scale Current over Temperature, Power Factor = 1 Figure 6. Total Apparent Energy Error as a Percentage of Full-Scale Current over Temperature, Power Factor = 1 0.5 0.5 TA = +85°C TA = +25°C TA = –40°C 0.3 2.97V 3.3V 3.63V 0.3 0.1 ERROR (%) –0.1 0.1 –0.1 –0.3 –0.3 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 –0.5 0.01 15210-102 0.10 Figure 5. Total Reactive Energy Error as a Percentage of Full-Scale Current over Temperature, Power Factor = 0 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 15210-107 ERROR (%) –0.1 15210-103 1 15210-101 0.1 PERCENTAGE OF FULL-SCALE CURRENT (%) –0.5 0.01 0.1 –0.3 –0.3 –0.5 0.01 TA = +85°C TA = +25°C TA = –40°C 0.3 ERROR (%) ERROR (%) 0.3 Figure 7. Total Active Energy Error as a Percentage of Full-Scale Current over Supply Voltage, Power Factor = 1, TA = 25°C Rev. A | Page 12 of 72 Data Sheet ADE9000 0.5 0.5 0.3 0.3 0.1 ERROR (%) –0.1 10 100 –0.5 0.01 Figure 8. Total Reactive Energy Error as a Percentage of Full-Scale Current over Supply Voltage, Power Factor = 0, TA = 25°C 2.97V 3.3V 3.63V 100 TA = +85°C TA = +25°C TA = –40°C 0.3 0.1 ERROR (%) –0.1 0.1 –0.1 –0.3 –0.3 1 10 –0.5 0.01 15210-109 0.1 100 PERCENTAGE OF FULL-SCALE CURRENT (%) 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 9. Total Apparent Energy Error as a Percentage of Full-Scale Current over Supply Voltage, Power Factor = 1, TA = 25°C 15210-143 ERROR (%) 10 0.5 0.3 Figure 12. Fundamental Apparent Energy Error as a Percentage of FullScale Current over Temperature, Power Factor = 1 0.5 0.5 TA = +85°C TA = +25°C TA = –40°C 0.3 2.97V 3.3V 3.63V 0.3 0.1 ERROR (%) ERROR (%) 1 Figure 11. Fundamental Reactive Energy Error as a Percentage of FullScale Current over Temperature, Power Factor = 0 0.5 –0.1 –0.3 0.1 –0.1 –0.3 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 –0.5 0.01 15210-141 –0.5 0.01 0.1 PERCENTAGE OF FULL-SCALE CURRENT (%) 15210-142 1 15210-108 0.1 PERCENTAGE OF FULL-SCALE CURRENT (%) –0.5 0.01 –0.1 –0.3 –0.3 –0.5 0.01 0.1 Figure 10. Fundamental Active Energy Error as a Percentage of Full-Scale Current over Temperature, Power Factor = 1 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 15210-147 ERROR (%) TA = +85°C TA = +25°C TA = –40°C 2.97V 3.3V 3.63V Figure 13. Fundamental Active Energy Error as a Percentage of Full-Scale Current over Supply Voltage, Power Factor = 1, TA = 25°C Rev. A | Page 13 of 72 ADE9000 Data Sheet 0.5 0.5 0.3 0.3 0.1 0.1 ERROR (%) –0.1 –0.1 –0.3 0.1 1 10 15210-148 –0.3 –0.5 0.01 2.97V 3.3V 3.63V 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 14. Fundamental Reactive Energy Error as a Percentage of FullScale Current over Supply Voltage, Power Factor = 0, TA = 25°C Rev. A | Page 14 of 72 –0.5 0.01 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 15210-149 ERROR (%) 2.97V 3.3V 3.63V Figure 15. Fundamental Apparent Energy Error as a Percentage of FullScale Current over Supply Voltage, Power Factor = 1, TA = 25°C Data Sheet ADE9000 ENERGY ERROR OVER FREQUENCY AND POWER FACTOR Total energies obtained from a sinusoidal voltage with an amplitude of 50% of full scale, a sinusoidal current with a constant amplitude of 10% of full scale, a variable frequency between 45 Hz and 65 Hz, and the integrator off. Fundamental energies obtained with a fundamental voltage component, with an amplitude of 50% of full scale in phase with the fifth harmonic, a current with a 50 Hz component that has constant amplitude of 10% of full scale, a fifth harmonic with a constant amplitude of 40% of fundamental, and the integrator off, unless otherwise noted. 0.10 0.10 POWER FACTOR = +1 POWER FACTOR = +0.5 POWER FACTOR = –0.5 POWER FACTOR = +1 POWER FACTOR = +0.5 POWER FACTOR = –0.5 0.05 ERROR (%) 0 –0.05 45 50 55 60 65 70 –0.10 40 LINE FREQUENCY (Hz) 45 50 55 Figure 16. Total Active Energy Error vs. Line Frequency, Power Factor = −0.5, Power Factor = +0.5, and Power Factor = +1 POWER FACTOR = 0 POWER FACTOR = +0.866 POWER FACTOR = –0.866 0.05 ERROR (%) 0 –0.05 0 –0.05 50 55 60 65 70 LINE FREQUENCY (Hz) –0.10 40 15210-114 45 Figure 17. Total Reactive Energy Error vs. Line Frequency, Power Factor = −0.866, Power Factor = 0, and Power Factor = +0.866 55 60 65 70 Figure 20. Fundamental Reactive Energy Error vs. Line Frequency, Power Factor = −0.866, Power Factor = 0, and Power Factor = +0.866 0.05 0.05 ERROR (%) 0.10 0 –0.05 45 50 55 60 65 LINE FREQUENCY (Hz) 70 15210-150 –0.05 50 LINE FREQUENCY (Hz) 0.10 0 45 15210-116 ERROR (%) 0.05 ERROR (%) 70 0.10 POWER FACTOR = 0 POWER FACTOR = +0.866 POWER FACTOR = –0.866 –0.1 40 65 Figure 19. Fundamental Active Energy Error vs. Line Frequency, Power Factor = −0.5, Power Factor = +0.5, and Power Factor = +1 0.10 –0.10 40 60 LINE FREQUENCY (Hz) 15210-115 –0.05 15210-113 –0.10 40 0 Figure 18. Total Apparent Energy Error vs. Line Frequency –0.10 40 45 50 55 60 65 70 LINE FREQUENCY (Hz) Figure 21. Fundamental Apparent Energy Error vs. Line Frequency Rev. A | Page 15 of 72 15210-117 ERROR (%) 0.05 ADE9000 Data Sheet ENERGY LINEARITY REPEATABILITY 0.5 0.5 0.3 0.3 0.1 0.1 ERROR (%) –0.1 –0.3 –0.3 0.1 1 10 –0.5 0.01 15210-123 –0.5 0.01 –0.1 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 22. Total Active Energy Error as a Percentage of Full-Scale Current, Power Factor = 1 (Standard Deviation σ = 0.02% at 0.01% of Full-Scale Current) 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) 15210-125 ERROR (%) Total energies obtained from a sinusoidal voltage with an amplitude of 50% of full scale and a frequency of 50 Hz, a sinusoidal current with variable amplitudes from 100% of full scale down to 0.01% of full scale, a frequency of 50 Hz, and the integrator off. Fundamental energies obtained with a fundamental voltage component, with an amplitude of 50% of full scale in phase with the fifth harmonic, a current with a 50 Hz component that has variable amplitudes from 100% of full scale down to 0.01% of full scale, and a fifth harmonic with a constant amplitude of 40% of fundamental, and the integrator off. Measurements at 25°C repeated 30 times, unless otherwise noted. Figure 24. Fundamental Active Energy Error as a Percentage of Full-Scale Current, Power Factor = 1 (Standard Deviation σ = 0.03% at 0.01% of Full-Scale Current) 0.5 1.0 0.3 ERROR (%) 0.1 –0.1 0 –0.5 –0.5 0.01 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 23. Total Reactive Energy Error as a Percentage of Full-Scale Current, Power Factor = 0 (Standard Deviation σ = 0.03% at 0.01% of Full-Scale Current) Rev. A | Page 16 of 72 –1.0 0.01 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 15210-126 –0.3 15210-124 ERROR (%) 0.5 Figure 25. Fundamental Reactive Energy Error as a Percentage of Full-Scale Current, Power Factor = 0 (Standard Deviation σ = 0.04% at 0.01% of Full-Scale Current) Data Sheet ADE9000 RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY RMS linearity obtained with a sinusoidal current and voltage with variable amplitudes from 100% of full scale down to 0.01% of full scale using a frequency of 50 Hz, total rms error over frequency obtained with a sinusoidal current amplitude of 10% of full scale and voltage amplitude of 50% of full scale, and the integrator off. Fundamental rms error over frequency obtained with a sinusoidal current amplitude of 10% of full scale, a voltage amplitude of 50% of full scale, a fifth harmonic with a constant amplitude of 40% of fundamental, and the integrator off, unless otherwise noted. 1.0 1.0 TA = +85°C TA = +25°C TA = –40°C TA = +85°C TA = +25°C TA = –40°C 0.5 ERROR (%) 0 –0.5 –0.5 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) –1.0 0.0001 15210-104 –1.0 0.01 0 Figure 26. Current RMS Error as a Percentage of Full-Scale Current over Temperature 0.001 0.01 1 0.1 PERCENTAGE OF FULL-SCALE CURRENT (%) 15210-144 ERROR (%) 0.5 Figure 29. Fundamental Current RMS Error as a Percentage of Full-Scale Current over Temperature 1.0 5 TA = +85°C TA = +25°C TA = –40°C TA = +85°C TA = +25°C TA = –40°C 3 ERROR (%) ERROR (%) 0.5 0 1 –1 –0.5 1 100 10 PERCENTAGE OF FULL-SCALE CURRENT (%) –5 0.01 15210-151 Figure 27. ½ Cycle Current RMS Error as a Percentage of Full-Scale Current over Temperature, Data Sourced Before High-Pass Filter and Calibrated for Offset, Register CONFIG0, Bit RMS_SRC_SEL = 1 0.1 1 10 Figure 30. ½ Cycle Current RMS Error as a Percentage of Full-Scale Current over Temperature, Data Sourced After High-Pass Filter, Register CONFIG0, Bit RMS_SRC_SEL = 0 1.0 1.0 TA = +85°C TA = +25°C TA = –40°C TA = +85°C TA = +25°C TA = –40°C 0.5 ERROR (%) ERROR (%) 0.5 0 –0.5 0 –0.5 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 –1.0 0.01 15210-152 –1.0 0.1 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 28. 10 Cycle Current RMS/12 Cycle Current Error as a Percentage of Full-Scale Current over Temperature, Data Sourced Before High-Pass Filter and Calibrated for Offset, Register CONFIG0, Bit RMS_SRC_SEL = 1 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 15210-106 –1.0 0.1 15210-105 –3 Figure 31. 10 Cycle Current RMS/12 Cycle Current Error as a Percentage of Full-Scale Current over Temperature, Data Sourced After High-Pass Filter, Register CONFIG0, Bit RMS_SRC_SEL = 0 Rev. A | Page 17 of 72 Data Sheet 0.10 0.10 0.05 0.05 ERROR (%) 0 45 50 55 60 65 70 LINE FREQUENCY (Hz) Figure 32. Current RMS Error vs. Line Frequency 50 55 60 65 70 Figure 34. ½ Cycle Current RMS Error vs. Line Frequency, Data Sourced After High-Pass Filter, Register CONFIG0, Bit RMS_SRC_SEL = 0 0.10 0.05 0.05 ERROR (%) 0.10 0 –0.05 –0.10 40 45 LINE FREQUENCY (Hz) 0 –0.05 45 50 55 60 65 70 LINE FREQUENCY (Hz) Figure 33. Fundamental Current RMS Error vs. Line Frequency –0.10 40 15210-120 ERROR (%) –0.10 40 15210-118 –0.10 40 –0.05 15210-121 –0.05 0 45 50 55 60 LINE FREQUENCY (Hz) 65 70 15210-122 ERROR (%) ADE9000 Figure 35. 10 Cycle Current RMS/12 Cycle Current Error vs. Line Frequency, Data Sourced After High-Pass Filter, Register CONFIG0, Bit RMS_SRC_SEL = 0 Rev. A | Page 18 of 72 Data Sheet ADE9000 ENERGY AND RMS LINEARITY WITH INTEGRATOR ON 0.5 0.5 0.3 0.3 0.1 0.1 ERROR (%) –0.1 –0.3 –0.3 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) –0.5 0.1 15210-127 –0.5 0.01 –0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 36. Total Active Energy Error, Gain = 4, Integrator On 15210-130 ERROR (%) The sinusoidal voltage has an amplitude of 50% of full scale and a frequency of 50 Hz, PGA_GAIN is a gain set to 4, the sinusoidal current has variable amplitudes from 100% of full scale down to 0.01% or 0.1% of full scale and a frequency of 50 Hz, full scale at gain of 4 = (full scale at gain of 1)/4, a high-pass corner frequency of 4.97 Hz, and TA = 25°C, unless otherwise noted. Figure 39. Total Current RMS Error, Gain = 4, Integrator On 1.0 0.5 0.3 0.1 ERROR (%) ERROR (%) 0.5 –0.1 0 –0.5 0.1 10 1 100 PERCENTAGE OF FULL-SCALE CURRENT (%) –1.0 0.1 15210-128 –0.5 0.01 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 37. Total Reactive Energy Error, Gain = 4, Integrator On 15210-131 –0.3 Figure 40. ½ Cycle Current RMS Error, Gain = 4, Integrator On, Data Sourced After High-Pass Filter, Register CONFIG0, Bit RMS_SRC_SEL = 0 0.5 1.0 0.3 ERROR (%) 0.1 –0.1 0 –0.5 –0.5 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 38. Total Apparent Energy Error, Gain = 4, Integrator On –1.0 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 15210-153 –0.3 15210-129 ERROR (%) 0.5 Figure 41. ½ Cycle Current RMS Error, Gain = 4, Integrator On, Data Sourced Before High-Pass Filter and Calibrated for Offset, Register CONFIG0, Bit RMS_SRC_SEL = 1 Rev. A | Page 19 of 72 Data Sheet 1.0 1.0 0.5 0.5 ERROR (%) 0 –0.5 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 15210-132 –0.5 –1.0 0.1 0 Figure 42. 10 Cycle Current RMS/12 Cycle Current Error, Gain = 4, Integrator On, Data Sourced After High-Pass Filter, Register CONFIG0, Bit RMS_SRC_SEL = 0 Rev. A | Page 20 of 72 –1.0 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 43. 10 Cycle Current RMS/12 Cycle Current RMS Error, Gain = 4, Integrator On, Data Sourced Before High-Pass Filter and Calibrated for Offset, Register CONFIG0, Bit RMS_SRC_SEL = 1 15210-154 ERROR (%) ADE9000 Data Sheet ADE9000 ENERGY AND RMS ERROR OVER FREQUENCY WITH INTEGRATOR ON The sinusoidal voltage has a constant amplitude of 50% of full scale, PGA_GAIN is a gain set to 4, the sinusoidal current has a constant amplitude of 10% of full scale, and a variable frequency between 45 Hz and 65 Hz. Fundamental quantities obtained with a fundamental voltage component in phase with a fifth harmonic, a current with a fundamental component of 10% of full scale, a fifth harmonic with an amplitude of 40% of the fundamental, a full scale at gain of 4 = (full scale at gain of 1)/4, a high-pass corner frequency of 4.97 Hz, and TA = 25°C, unless otherwise noted. 0.5 0.4 0.5 POWER FACTOR = +1 POWER FACTOR = +0.5 POWER FACTOR = –0.5 POWER FACTOR = 0 POWER FACTOR = +0.866 POWER FACTOR = –0.866 0.3 0.3 0.1 ERROR (%) ERROR (%) 0.2 0 –0.1 0.1 –0.1 –0.2 –0.3 –0.3 45 50 55 60 65 70 LINE FREQUENCY (Hz) –0.5 40 15210-133 60 65 70 0.5 POWER FACTOR = +1 POWER FACTOR = +0.5 POWER FACTOR = –0.5 0.4 0.3 0.2 0.2 0.1 0.1 ERROR (%) 0.3 0 –0.1 0 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 45 50 55 60 LINE FREQUENCY (Hz) 65 70 Figure 45. Fundamental Active Energy Error vs. Line Frequency, Gain = 4, Integrator On, Power Factor = −0.5, Power Factor = +0.5, and Power Factor = +1 POWER FACTOR = 0 POWER FACTOR = +0.866 POWER FACTOR = –0.866 –0.1 –0.2 –0.6 40 15210-136 ERROR (%) 55 Figure 46. Total Reactive Energy Error vs. Line Frequency, Gain = 4, Integrator On, Power Factor = −0.866, Power Factor = +0.8665, and Power Factor = 0 0.5 –0.6 40 50 LINE FREQUENCY (Hz) Figure 44. Total Active Energy Error vs. Line Frequency, Gain = 4, Integrator On, Power Factor = −0.5, Power Factor = +0.5, and Power Factor = +1 0.4 45 45 50 55 60 LINE FREQUENCY (Hz) 65 70 15210-137 –0.5 40 15210-134 –0.4 Figure 47. Fundamental Reactive Energy Error vs. Line Frequency, Gain = 4, Integrator On, Power Factor = −0.866, Power Factor = +0.8665, and Power Factor = 0 Rev. A | Page 21 of 72 Data Sheet 0.5 0.5 0.3 0.3 0.1 0.1 ERROR (%) –0.1 –0.3 –0.3 45 50 55 60 65 –0.5 40 15210-135 –0.5 40 –0.1 70 LINE FREQUENCY (Hz) Figure 48. Total Apparent Energy Error vs. Line Frequency, Gain = 4, Integrator On 45 50 55 60 65 70 LINE FREQUENCY (Hz) 15210-140 ERROR (%) ADE9000 Figure 51. Fundamental Current RMS Error vs. Line Frequency, Gain = 4, Integrator On 0.2 0.3 0.2 0.1 0 ERROR (%) ERROR (%) 0.1 –0.1 0 –0.2 –0.1 –0.3 45 50 55 60 65 70 LINE FREQUENCY (Hz) Figure 49. Fundamental Apparent Energy Error vs. Line Frequency, Gain = 4, Integrator On 50 55 60 65 70 Figure 52. ½ Cycle Current RMS Error, Gain = 4, Integrator On, Data Sourced After High-Pass Filter, Register CONFIG0, Bit RMS_SRC_SEL = 0 0.2 0.2 0.1 0.1 0 0 50 55 60 LINE FREQUENCY (Hz) 65 70 15210-139 45 Figure 50. Current RMS Error vs. Line Frequency, Gain = 4, Integrator On Rev. A | Page 22 of 72 –0.2 40 45 50 55 60 LINE FREQUENCY (Hz) 65 70 15210-146 –0.1 –0.1 –0.2 40 45 LINE FREQUENCY (Hz) ERROR (%) ERROR (%) –0.2 40 15210-138 –0.5 40 15210-145 –0.4 Figure 53. 10 Cycle Current RMS/12 Cycle Current Error, Gain = 4, Integrator On, Data Sourced After High-Pass Filter, Register CONFIG0, Bit RMS_SRC_SEL = 0 Data Sheet ADE9000 SIGNAL-TO-NOISE RATIO PERFORMANCE 40 30 25 20 15 10 5 0 99.5 100.0 100.5 101.0 101.5 102.0 SNR (dB) 15210-254 NUMBER OF OCCURRENCES (%) 35 Figure 54. SNR Histogram of ADC SNR for 1000 Devices Tested at TA = 25°C with PGA_GAIN = 1 and 8 kSPS Data Rate Rev. A | Page 23 of 72 ADE9000 Data Sheet TEST CIRCUIT 3.3V 10µF 1µF 1kΩ 27 3 1kΩ MISO 38 SCLK 37 3.3V 8 IAN SAME AS IAP, IAN SAME AS IAP, IAN SAME AS IAP, IAN 22nF 9 IBP CF4/EVENT/DREADY 36 CF3/ZX 35 10 IBN CF2 34 11 ICP ADE9000 12 ICN CF1 33 IRQ0 31 14 INN REF 16 4.7µF 20 VAP + 0.1µF 16pF 22 VBP 2 15 26 28 16pF 15210-054 24 VCP CLKIN 29 GND 23 VCN AGND SAME AS VAP, VAN CLKOUT 30 21 VBN REFGND SAME AS VAP, VAN DGND 22nF SAME AS CF2 IRQ1 32 13 INP 19 VAN 1kΩ 0.22µF MOSI 39 7 IAP 22nF + SS 40 6 RESET 22nF 1kΩ 5 PM1 25 VDD 10kΩ 4 PM0 0.1µF 4.7µF 0.22µF DVDDOUT 3.3V + AVDDOUT 4.7µF + Figure 55. Test Circuit Rev. A | Page 24 of 72 Data Sheet ADE9000 TERMINOLOGY Crosstalk Crosstalk is measured by grounding one channel and applying a full-scale 50 Hz or 60 Hz signal on all the other channels. The crosstalk is equal to the ratio between the grounded ADC output value and its ADC full-scale output value. The ADC outputs are acquired for 100 sec. Crosstalk is expressed in decibels. Differential Input Impedance (DC) The differential input impedance represents the impedance between the pair IxP and IxN or VxP and VxN. It varies with the PGA gain selection as indicated in Table 1. ADC Offset ADC offset is the difference between the average measured ADC output code with both inputs connected to GND and the ideal ADC output code of zero. ADC offset is expressed in mV. ADC Offset Drift over Temperature The ADC offset drift is the change in offset over temperature. It is measured at −40°C, +25°C, and +85°C. Calculate the offset drift over temperature as follows: Drift =  Offset (−40°C ) − Offset (+ 25°C )   ,   (−40°C − +25°C )  max  Offset (+ 85°C ) − Offset (+ 25°C )    (+ 85°C − +25°C )   Offset drift is expressed in µV/°C. ADC Gain Error The gain error in the ADCs represents the difference between the measured ADC output code (minus the offset) and the ideal output code when an external voltage reference of 1.2 V is used. The difference is expressed as a percentage of the ideal code. It represents the overall gain error of one channel. ADC Gain Drift over Temperature This temperature coefficient includes the temperature variation of the ADC gain while using an external voltage reference of 1.2 V. It represents the overall temperature coefficient of one current or voltage channel. With an external voltage reference of 1.2 V in use, the ADC gain is measured at −40°C, +25°C, and +85°C. Then the temperature coefficient is computed as follows: Drift =    max    Gain(−40°C ) − Gain(+ 25°C )  , Gain(+25°C) × (−40°C − +25°C )   Gain(+ 85°C ) − Gain(+ 25°C )   Gain(+25°C) × (+ 85°C − +25°C )  AC Power Supply Rejection (PSRR) AC PSRR quantifies the measurement error as a percentage of reading when the dc power supply is nominal (VNOM) and modulated with ac, and the inputs are grounded. For the ac PSRR measurement, 20 sec samples are captured with nominal supplies (3.3 V, which is V1) and a second set (V2) is captured with an additional ac signal (330 mV peak at 50 Hz) introduced onto the supplies. Then, the PSRR is expressed as PSRR = 20 log10(V2/V1). Signal-to-Noise Ratio (SNR) SNR is calculated by inputting a 50 Hz signal, and samples are acquired for 2 sec. The amplitudes for each frequency up to the bandwidth given in Table 1 as the ADC output bandwidth (−3 dB) are calculated. To determine the SNR, the signal at 50 Hz is compared to the sum of the power from all the other frequencies, removing power from its harmonics. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is calculated by inputting a 50 Hz signal, and samples are acquired for 2 sec. The amplitudes for each frequency up to the bandwidth given in Table 1 as the ADC output bandwidth (−3 dB) are calculated. To determine the SINAD, the signal at 50 Hz is compared to the sum of the power from all the other frequencies. The value for SINAD is expressed in decibels. Total Harmonic Distortion (THD) THD is calculated by inputting a 50 Hz signal, and samples are acquired for over 2 sec. The amplitudes for each frequency up to the bandwidth given in Table 1 as the ADC output bandwidth (−3 dB) are calculated. To determine the THD, the amplitudes of the 50 Hz harmonics up to the bandwidth are root sum squared. The value for THD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is calculated by inputting a 50 Hz signal, and samples are acquired for over 2 sec. The amplitudes for each frequency up to the bandwidth given in Table 1 as the ADC output bandwidth (−3 dB) are calculated. To determine the SFDR, the amplitude of the largest signal that is not a harmonic of 50 Hz is recorded. The value for SFDR is expressed in decibels. ADC Output Pass Band The ADC output pass band is the bandwidth within 0.1 dB, resulting from the digital filtering in the sinc4 and sinc4 + IIR LPF. ADC Output Bandwidth The ADC output bandwidth is the bandwidth within −3 dB, resulting from the digital filtering in the sinc4 and sinc4 + IIR LPF. Gain drift is measured in ppm/°C. Rev. A | Page 25 of 72 ADE9000 Data Sheet THEORY OF OPERATION MEASUREMENTS Current Channel Gain, xIGAIN Current Channel The ADE9000 provides current gain calibration registers (AIGAIN, BIGAIN, CIGAIN and NIGAIN), one for each current channel. The ADE9000 has three phase current channels and one neutral current channel. The phase current channel datapath for IA, IB, and IC is shown in Figure 56 and datapath for the neutral channel is shown in Figure 57. The current channel gain varies with xIGAIN as shown in the following equation: Current Channel Gain = (1 + (xIGAIN/227)) ADC_REDIRECT Multiplexer The ADE9000 provides a multiplexer that allows any ADC output to be redirected to any digital processing datapath (see Figure 58). By default, each modulator is mapped to its corresponding datapath. xI_PCF WF_SRC WF_CAP_SEL VIN FAST RMS½, 10 CYCLE RMS/ 12 CYCLE RMS +1V WAVEFORM BUFFER 0V RMS_SRC_SEL RESAMPLING ZX_SRC_SEL REFERENCE Σ-Δ MODULATOR VIN ADC_ REDIRECT MUX SINC4 LPF HPFDIS xIGAINx FUNDAMENTAL AND TOTAL ACTIVE AND REACTIVE POWER CALCULATIONS INTEN PHASE COMP 4:1 HPF IB = –IA – IC IM 1REGISTER CURRENT PEAK DETECTION MTEN xIGAIN IP ZX DETECTION INTEGRATOR ICONSEL 1 FUNDAMENTAL AND TOTAL RMS, VA, THD CALCULATIONS ACCMODE, BIT ICONSEL ONLY AFFECTS IB CHANNEL CALCULATION. Figure 56. Current Channel (IA, IB, IC) Datapath NI_PCF VIN WF_SRC WF_CAP_SEL +1V WAVEFORM BUFFER 0V RESAMPLING FAST RMS½, 10 CYCLE RMS/ 12 CYCLE RMS RMS_SRC_SEL –1V NIGAIN INP ADC_ REDIRECT MUX SINC4 LPF ININTEN NPHCAL NEUTRAL CURRENT RMS VECTOR CURRENT SUM CALCULATIONS PHASE COMP 4:1 HPF INTEGRATOR INN Figure 57. Neutral Current Channel (IN) Datapath IA MODULATOR IA_MOD IB_MOD REFERENCE IC_MOD VIN Σ-Δ MODULATOR IN_MOD IA_MOD VA_MOD VB_MOD VC_MOD IA_MOD IA DIGITAL DATAPATH 000 001 010 011 100 SINC4 LPF 4:1 101 110 111 AI_SINC_DAT AI_LPF_DAT IA_DIN NOTES 1. Ix_MOD AND Vx_MOD ARE THE RESPECTIVE MODULATOR OUTPUT. Figure 58. ADC_REDIRECT Modulator to Digital Datapath Multiplexing Rev. A | Page 26 of 72 15210-055 Σ-Δ MODULATOR VIN HPFDIS 15210-057 REFERENCE 8kSPS 32kSPS ANALOG INPUT RANGE 15210-056 ANALOG INPUT RANGE 8kSPS 32kSPS –1V Data Sheet ADE9000 IB Calculation Using ICONSEL Multipoint Phase and Gain Calibration Write to the ICONSEL bit in the ACCMODE register to calculate IB = −IA − IC. This setting can help save the cost of a current transformer in some 3-wire delta configurations. A high-pass filter removes dc offsets for accurate rms and energy measurements. It is enabled by default with a corner frequency is 1.25 Hz. The ADE9000 allows multipoint gain and phase compensation with hysteresis on the IA, IB, and IC current channels. The current channel gain and phase compensation vary as a function of the calculated input current rms amplitude in xIRMS. There are five gain registers (xIGAIN0 to xIGAIN4) and five phase calibration registers (xPHCAL0 to xPHCAL4) for each channel. Set the MTEN bit in the CONFIG0 register to enable multipoint gain and phase calibration. MTEN = 0 by default. To disable the high-pass filter on all current and voltage channels set the HPFDIS bit in the CONFIG0 register. The corner frequency is configured with the HPF_CRN bits in the CONFIG2 register. The gain and phase calibration factor is applied based on the xIRMS current amplitude and the MTTHR_Lx and the MTTHR_Hx register values, as shown in Figure 59. High-Pass Filter Digital Integrator xIGAIN4 xPHCAL4 GAIN, PHASE CORRECTION A digital integrator is included to allow easy interfacing to di/dt current sensors, also known as Rogowski coils. To configure the digital integrator use the INTEN and ININTEN bits in the CONFIG0 register. It is disabled by default. If the integrator is enabled, set the DICOEFF value to 0xFFFFE000. xIGAIN0 xPHCAL0 xIGAIN1 xPHCAL1 xIGAIN2 xPHCAL2 X X X xIGAIN3 xPHCAL3 X X REGION 0 Phase Compensation MTTHR_L2, MTTHR_H1 REGION 1 MTTHR_L3, MTTHR_H2 REGION 2 MTTHR_L4, MTTHR_H3 REGION 3 MTTHR_H4 = FULL SCALE REGION 4 15210-058 IRMS MTTHR_L1 , MTTHR_H0 MTTHR_L0 =0 Figure 59. Multipoint Phase and Gain Calibration Voltage Channel The ADE9000 provides a phase compensation register for each current channel: APHCALx, BPHCALx, CPHCALx, and NPHCAL. The ADE9000 has three voltage channels. The datapaths for the VA, VB, and VC voltage channels is shown in Figure 60. The xVGAIN registers calibrate the voltage channel of each phase. The xVGAIN registers have the same scaling as the xIGAIN registers. The phase calibration range is −15° to +2.25° at 50 Hz and −15° to +2.7° at 60 Hz. RMS and Power Measurements Use the following equation to calculate the xPHCALx value for a given phase correction (φ)° angle. Phase correction (φ)° is positive to correct a current that lags the voltage, and negative to correct a current that leads the voltage, as seen in a current transformer. The ADE9000 calculates total and fundamental values of rms current, rms voltage, active power, reactive power, and apparent power. The fundamental algorithm requires initialization of the network frequency using the SELFREQ bit in the ACCMODE register and the nominal voltage in the VLEVEL register. Calculate VLEVEL value according to the following equation:  sin(ϕ – ω) + sin ω  27  ×2 xPHCALx =   sin(2ω – ϕ)    VLEVEL = x × 1,444,084 ω = 2π × fLINE/fDSP where x is the dynamic range that the nominal input signal is at with respect to full scale. where: fLINE is the line frequency. fDSP is 8 kHz. For instance, if the signal is at ½ of full scale, x = 2. VLEVEL = 2 × 1,444,084 xV_PCF WF_SRC WF_CAP_SEL WAVEFORM BUFFER RMS_SRC_SEL FAST RMS½, 10 CYCLE RMS/ 12 CYCLE RMS RESAMPLING ZERO-CROSSING DETECTION xVGAIN VP V IN Σ-Δ MODULATOR ADC_ REDIRECT MUX SINC4 LPF VA = VA – VB; VB = VA – VC; VC = VC – VB; 100 VB = – VA VB = –VA – VC VB = VA – VC 011 010 001 000 4:1 HPFDIS HPF VM 1VCONSEL ZX_SRC_SEL SUPPORTS SEVERAL 3-WIRE AND 4-WIRE HARDWARE CONFIGURATIONS. Figure 60. Voltage Channel Datapath Rev. A | Page 27 of 72 VOLTAGE PEAK DETECTION FUNDAMENTAL AND TOTAL ACTIVE AND REACTIVE POWER CALCULATIONS PHASE COMP FUNDAMENTAL AND TOTAL RMS, VA, THD CALCULATIONS 15210-059 REFERENCE 8kSPS 32kSPS VCONSEL1 ADE9000 Data Sheet Total and Fundamental RMS The active power calculations, one for each channel (AWATT, BWATT, and CWATT), are updated every 8 kSPS. The fundamental active power is also updated every 8 kSPS and is available in the AFWATT, BFWATT, and CFWATT registers. With full-scale inputs, the xWATT and xFWATT value is 20,694,066 decimals. The ADE9000 offers total and fundamental current and voltage rms measurements on all phase channels. The datapath is shown in Figure 61. xRMSOS Enable the LPF2 (DISAPLPF = 0) for normal operation. Disable LFP2 by setting DISAPLPF in the CONFIG0 register to obtain instantaneous total active power. DISAPLPF is zero at reset. 215 √ x2 LPF2 The total and fundamental measurements can be calibrated for gain and offset. The following equations indicate how the gain and offset calibration registers modify the results in the corresponding power registers: xRMS +0.064% –0.064% 0 15210-060 52702092  xPGAIN  xWATT = 1 +  xWATT0 + xWATTOS 2 27   Figure 61. Filter-Based Total RMS The total rms calculations, one for each channel (AIRMS, BIRMS, CIRMS, NIRMS, AVRMS, BVRMS, and CVRMS), are updated every 8 kSPS. The fundamental rms calculations available in the AIFRMS, BIFRMS, CIFRMS, AVFRMS, BVFRMS, and CVFRMS registers are also updated every 8 kSPS. The fundamental rms is not available for the neutral channel. The xRMS and xFRMS value at full scale is 52,702,092 decimals. The total and fundamental rms measurements can be calibrated for gain and offset. Perform gain calibration on the respective current and voltage channel datapath. The following equations indicate how the offset calibration registers modify the result in corresponding rms registers:  xPGAIN  xFWATT = 1 +  xFWATT0 + xFWATTOS 2 27   xPGAIN is a common gain to total and fundamental components of active, reactive, and apparent powers. Total and Fundamental Reactive Power The ADE9000 offers total and fundamental reactive power measurements on all channels. Figure 63 shows how to perform the total reactive power calculation. 90 DEGREE PHASE SHIFT AI_PCF xRMS = xRMS0 2 + 215 × xRMOSOS The reactive power calculations, one for each channel (AVAR, BVAR, and CVAR) are updated every 8 kSPS. The fundamental reactive power is also updated every 8 kSPS and is available in the AFVAR, BFVAR, and CFVAR registers. With full-scale inputs, the xVAR and xFVAR value is 20,694,066. Enable the LPF2 (DISRPLPF = 0) for normal operation. Disable LFP2 by setting DISRPLPF in the CONFIG0 register to obtain instantaneous total reactive power. DISRPLPF is 0 at reset. The ADE9000 offers total and fundamental active power measurements on all channels. To calculated the total active power for Phase A, see Figure 62. The following equations indicate how the gain and offset calibration registers modify the result in the corresponding power registers: AWATTOS  xPGAIN  xVAR = 1 +  xVAR0 + xVAROS 2 27   ENERGY/ POWER/ CF ACCUMULATION AV_PCF 15210-061 AWATT ENERGY/ POWER/ CF ACCUMULATION Figure 63. Total Reactive Power, AVAR, Calculation Total and Fundamental Active Power LPF2 AVAROS AV_PCF The ADE9000 also calculates the rms of the sum of IA + IB + IC ± IN and stores the result in ISUMRMS. The ISUM_CFG bits in the CONFIG0 register configure the components included in summation. DISAPLPF APGAIN AVAR xFRMS = xFRMS0 2 + 215 × xFRMOSOS AI_PCF DISRPLPF LPF2 where xRMS0 is the initial xRMS register value before offset calibration. APGAIN π 2 15210-062 xV_PCF or xI_PCF VOLTAGE OR CURRENT CHANNEL WAVEFORM Figure 62. Total Active Power, AWATT, Calculation for Phase A Rev. A | Page 28 of 72  xPGAIN  xFVAR = 1 +  xFVAR0 + xFVAROS 2 27   Data Sheet ADE9000 Total and Fundamental Apparent Power Energy Accumulation The ADE9000 offers total and fundamental apparent power measurements on all channels. See Figure 64 for how to calculate the total apparent power for Phase A. The energy is accumulated into a 42-bit signed internal energy register at 8 kSPS. The internal register can accumulate a user defined number of samples or half line cycles configured by EGY_TMR_MODE bit in the EP_CFG register. When half line cycle accumulation is enabled, configure the zero-crossing source using the ZX_SEL bits in the ZX_LP_SEL register. The number of samples or half line cycles is set in the EGY_TIME register. The maximum value of EGY_TIME is 8191d. With full-scale inputs, the internal register overflows in 13.3 sec. For a 50 Hz signal, EGY_TIME must be lower than 1329 decimals to prevent overflow during half line cycle accumulation. AIRMSOS 215 APGAIN AIRMS LPF2 AVRMS x2 LPF2 VNOM 215 0 AVA ENERGY/ POWER/ CF ACCUMUL ATION 1 VNOMx_EN AIRMSOS After EGY_TIME + 1 samples or half line cycles, the EGYRDY bit is set in the STATUS0 register and the energy register is updated. The data from the internal energy register is added or latched to the user energy register depending on the EGY_LD_ACCUM bit setting in the EP_CFG register. Figure 64. Total Apparent Power, AVA, Calculation for Phase A The total apparent power calculations, one for each channel (AVA, BVA, and CVA) are updated every 8 kSPS. The fundamental apparent power is also updated every 8 kSPS and is available in the AFVA, BFVA and CFVA registers. With full-scale inputs, the xVA and xFVA value is 20,694,066 decimals. The energy register is signed and is 45 bits wide, split between two 32-bit registers, as shown in Figure 65. The user energy can reset on a read using the RD_RST_EN bit in the EP_CFG register. With full-scale inputs, the user energy register overflows in 106.3 sec. The ADE9000 offers a register (VNOM) that can be set to a value to correspond to the desired voltage rms value. If the VNOMx_EN bits in the CONFIG0 register are set, VNOM multiplies by xIRMS when calculating xVA. Power Accumulation The ADE9000 accumulates the total and fundamental values of active, reactive, and apparent power for all the three phases into respective xWATT_ACC and xFWATT_ACC, xVAR_ACC and xFVAR_ACC, and xVA_ACC, and xFVA_ACC 32-bit signed registers. The number of samples accumulated is set using the PWR_TIME register. The PWRRDY bit in the STATUS0 register is set after PWR_TIME + 1 samples accumulate at 8 kSPS. The maximum value of the PWR_TIME register is 8191 decimals, and the maximum power accumulation time is 1.024 sec. No Load Detection, Energy Accumulation, and Power Accumulation Features The ADE9000 calculates the total and fundamental values of active, reactive, and apparent energy for all the three phases. The ADE9000 can have signed, absolute, positive, or negative only accumulation on active and reactive energies using the WATTACC and VARACC bits in the ACCMODE register. The default accumulation mode is signed. The xSIGN bits in the PHSIGN register indicate the sign of accumulated powers over the PWR_TIME interval. The PWR_ SIGN_SEL[1:0] bits allow the user to select whether the power sign change follows the total or fundamental energies. When sign of the accumulated power changes, the corresponding REVx bits in the STATUS0 register are set and IRQ0 generates an interrupt. No Load Detection Feature The ADE9000 has a no load detection for each phase and energy to prevent energy accumulation due to noise. If the accumulated energy over the user defined time period is below the user defined threshold, zero energy is accumulated into the energy register. The NOLOAD_TMR bits in the EP_CFG register determine the no load time period and the ACT_NL_LVL, REACT_NL_LVL, and APP_NL_LVL registers contain the user defined no load threshold. The no load status is available in the PHNOLOAD register, the IRQ1 interrupt, and the EVENT pin. The ADE9000 allows the user to accumulate total active power and VAR powers into separate positive and negative values into the PWATT_ACC and NWATT_ACC, and PVAR_ACC and NVAR_ ACC registers. A new accumulation from zero begins when the power update interval set in PWR_TIMER elapses. fDSP AWATT 41 + 31 0 INTERNAL ENERGY ACCUMULATOR 13 12 AWATTHR_LO AWATTHR_HI 31 0 31 12 0 Figure 65. Internal Energy Register to AWATTHR_HI and AWATTHR_LO Rev. A | Page 29 of 72 15210-165 AI_PCF x2 15210-063 AI_PCF ADE9000 Data Sheet Digital to Frequency Conversion—CFx Output Configuring the CFx Pulse Width The ADE9000 includes four pulse outputs that are proportional to the energy accumulation in the CF1 through CF4 output pins. Figure 66 shows a block diagram of the CFx pulse generation. CF3 is multiplexed with ZX, and CF4 is multiplexed with EVENT and DREADY. The value of the CFx_LT and the CF_LTMR bits in the CF_LCFG register determines the pulse width. Energy and Phase Selection CFx Pulse Sign The CFxSEL bits in the CFMODE register select which type of energy to output on the CFx pins. The TERMSELx bits in the COMPMODE register select which phase energies to include in the CFx output. For example, with CF1SEL = 000 and TERMSEL1 = 111, CF1 indicates the total active power output of Phase A, Phase B, and Phase C. 000 001 xVA 010 xWATT xFVAR xFVA 110 xWATT 111 CFxSEL To clear the accumulation in the digital to frequency converter and CFDEN counter, write 1 to the CF_ACC_CLR bit in the CONFIG1 register. The CF_ACC_CLR bit automatically clears itself. 4.096MHz TERMSELx fDSP 011 xWATT Clearing the CFx Accumulator PHASE A + 100 101 The SUMxSIGN bits in the PHSIGN register indicate whether the sum of the energy that went into the last CFx pulse is positive or negative. The REVPSUMx bits in the STATUS0 register and the EVENT_STATUS register indicate if the CFx polarity changed sign. This feature generates an interrupt on IRQ0. PHASE B TERMSELx + + 512 DIGITAL TO FREQUENCY CFxDIS CFx BITS ÷ PHASE C CFxDEN CFx_LT TERMSELx WTHR 000 VARTHR 001 VATHR 010 WTHR 011 VARTHR 100 VATHR 101 WTHR 110 WTHR 111 PULSE WIDTH CONFIGURATION CFx PIN CF_LTMR CF_ACC_CLR CFxSEL ADE9000 Figure 66. Digital to Frequency Conversion for CFx Rev. A | Page 30 of 72 15210-065 xWATT xVAR The maximum CFx with threshold (xTHR) = 0x00100000 and CFxDEN = 2 is 78.9 kHz. It is recommended to have xTHR = 0x00100000. Data Sheet ADE9000 VCONSEL1 VB = –VA xVGAIN VB = –VA – VC VB = VA – VC 100 ZX_SRC_SEL HPFDIS 011 ÷32 010 001 000 ZX DETECTION LPF1 PHASE COMP HPF xV_PCF 15210-066 VA = VA – VB; VB = VA – VC; VC = VC – VB; 1VCONSEL SUPPORTS SEVERAL 3-WIRE AND 4-WIRE HARDWARE CONFIGURATIONS. Figure 67. Voltage Channel Signal Chain Preceding Zero-Crossing Detection MTEN ZX_SRC_SEL xIGAIN HPFDIS xIGAINx INTEN ZX DETECTION ÷32 LPF1 PHASE COMP HPF IB = –IA – IC xI_PCF INTEGRATOR 15210-166 ICONSEL1 1ICONSEL ONLY AFFECTS IB CHANNEL CALCULATION. Figure 68. Current Channel Signal Chain Preceding Zero-Crossing Detection POWER QUALITY MEASUREMENTS Zero-Crossing Detection The ADE9000 offers zero-crossing detection on the VA, VB, VC, IA, IB, and IC input signals. The neutral current channel, IN, does not contain a zero-crossing detection circuit. Figure 67 and Figure 68 show the current and voltage channel datapaths preceding zero-crossing detection. Use the ZX_SRC_SEL bit in the CONFIG0 register to select data before the high-pass filter or after phase compensation to configure the inputs to zero-crossing detection. ZX_SRC_SEL is zero by default after reset. To provide protection from noise, voltage channel zero-crossing events (ZXVA, ZXVB, and ZXVC) do not generate if the absolute value of the LPF1 output voltage is smaller than the threshold, ZXTHRSH. The current channel zero-crossing detection outputs (ZXIA, ZXIB, and ZXIC) are active for all input signals levels. Calculate the zero-crossing threshold, ZXTHRSH, from the following equation: The ADE9000 can calculate the combined zero crossings for all three phases as (VA + VB − VC)/2 by configuring the ZX_SEL bits in the ZX_LP_SEL register. If VCONSEL is not equal to 0, the VB component in the combined zero-crossing circuit is set to zero. The zero-crossing detection circuits have two different output rates: 8 kSPS and 1024 kSPS. The 8 kSPS zero-crossing signal calculates the line period, updates the ZXx bits in the STATUS1 register, and monitors the zero-crossing timeout, phase sequence error detection, resampling, and energy accumulation functions. The 1024 kSPS zero-crossing signal calculates the angle and updates the zero-crossing output on the CF3/ZX pin. CF3/ZX The CF3/ZX pin can output zero crossings using the CF3_CFG bit in the CONFIG1 register. To configure the source for zero crossing, use the ZX_SEL bits in ZX_LP_SEL register. The CF3/ZX output pin goes from low to high when a negative to positive transition is detected and from high to low when a positive to negative transition occurs. Zero-Crossing Timeout ZXTHRSH = (V _ PCF at Full Scale)× (LPF1 Attenuation) If a zero crossing is not received after (ZXTOUT + 1)/8000 sec, the corresponding ZXTOx bit in the STATUS1 register is set and generates an interrupt on the IRQ1 pin. x × 32 × 2 8 where V_PCF at Full Scale is ±74,532,013 decimals. LPF1 Attenuation is 0.86 at 50 Hz, and 0.81 at 60 Hz. x is the dynamic range below which the voltage channel zerocrossing must be blocked. Rev. A | Page 31 of 72 ADE9000 Data Sheet Line Period Calculation Phase Sequence Error Detection The ADE9000 calculates the line period for the Phase A, Phase B, and Phase C voltages, and the combined voltage signal, and the results are available in the APERIOD, BPERIOD, CPERIOD, and COM_PERIOD registers, respectively. The ADE9000 monitors phase sequences and sets the SEQERR bit in the STATUS1 register if a sequence error occurs or a phase drops below ZXTHRSH. SEQ_CYC determines the number of cycles to monitor to generate the sequence error. To generate an interrupt on IRQ1, set the SEQERR bit in the MASK1 register. Calculate the line period, tL, from the xPERIOD register, according to the following equation: tL = xPERIOD + 1 8000 × 216 Fast RMS½ Measurement RMS½ is an rms measurement performed over one line cycle, updated every half cycle. This measurement is provided for voltage and current on all phases plus the neutral current. All the half cycle rms measurements are performed over the same time interval and update at the same time, as indicated by the RMSONERDY bit in the STATUS0 register. The results are stored in the AIRMSONE, BIRMSONE, CIRMSONE, NIRMSONE, AVRMSONE, BVRMSONE, and CVRMSONE registers. The xRMSONE register reading with full-scale inputs is 52,702,092d. (sec) If the calculated period value is outside the range of 40 Hz to 70 Hz, or if zero crossings for that phase are not detected, the xPERIOD register is coerced to correspond to 50 Hz or 60 Hz, depending on SELFREQ bit in the ACCMODE register. LP_SEL COM_PERIOD CPERIOD BPERIOD APERIOD 11 10 01 00 UPERIOD_SEL WF_CAP_SEL WF_SRC SINC4 OUTPUT SINC4 + IIR LPF OUPUT xI_PCF, xV_PCF WAVEFORM BUFFER It is recommended to select the data before the high-pass filter for the fast rms measurement by setting the RMS_SRC_SEL bit in the CONFIG0 register. RESAMPLING USER_PERIOD 15210-067 FAST RMS½ 10 CYCLE RMS/ 12 CYCLE RMS The LP_SEL bits in the ZX_LP_SEL register select which line period measurement sets the number of samples used in the rms½ measurement. Alternatively, set the UPERIOD_SEL bit in the CONFIG2 register to set desired period in the USER_PERIOD register for line period measurement. An offset correction register is available for improved performance with small input signal levels, xRMSONEOS. Figure 69. Line Period Selection for Resampling Angle Measurement The ADE9000 provides nine angle measurements. ANGL_IA_IB, ANGL_IB_IC, and ANGL_IA_IC provide phase angle between currents. ANGL_VA_VB, ANGL_VB_VC, and ANGL_VA_VC provide phase angle between voltages. ANGL_VA_IA, ANGL_VB_IB, and ANGL_VC_IC provide phase angle between voltage and currents. To convert angle register reading to degrees, use the following equations. The signal chain is shown in Figure 70. For a 50 Hz system, Angle (Degrees) = ANGL_x_y × 0.017578125 For a 60 Hz system, Angle (Degrees) = ANGL_x_y × 0.02109375 INTEN PHASE COMP HPF INTEGRATOR xI_PCF RMS_SRC_SEL COM_PERIOD CPERIOD BPERIOD APERIOD 11 10 01 00 xIRMSONEOS FAST RMS½ xIRMS1012OS 10 CYCLE RMS/ 12 CYCLE RMS SELFREQ RESAMPLING REGISTER ZX_LP_SEL, BIT LP_SEL USER_PERIOD UPERIOD_SEL xIRMSONE xIRMS1012 WAVEFORM BUFFER 15210-068 HPFDIS CURRENT CHANNEL SAMPLES Figure 70. RMS½, 10 Cycle RMS, and 12 Cycle RMS Measurements 10 Cycle RMS/12 Cycle RMS The 10 cycle rms/12 cycle rms measurement is performed over 10 cycles on a 50 Hz network or 12 cycles on a 60 Hz network. Rev. A | Page 32 of 72 Data Sheet ADE9000 The SELFREQ bit in the ACCMODE register selects whether the network is 50 Hz or 60 Hz. Then, the UPERIOD_SEL bit in the CONFIG2 register selects whether to use a measured line period or a user configured value in the USER_PERIOD register to set the number of samples used in the calculation. The PEAKSEL bits in the CONFIG3 register allow the user to select which phases to monitor. An offset correction register is available for improved performance with small input signal levels, xRMS1012OS. The xRMS1012 register reading with full-scale inputs is 52,702,092d. Similarly, VPEAK stores the peak voltage value in the VPEAKVAL bits. VPEAKVAL is equal to xV_PCF/25. After a read, the VPEAK and IPEAK registers reset. The signal chain is shown in Figure 70. Power Factor Dip and Swell Indication The power factor calculation, one for each channel (APF, BPF, and CPF), is updated every 1.024 sec. Similarly, if the voltage goes above a threshold specified in the SWELL_LVL register for a user configured number of half cycles in the SWELL_CYC register, the corresponding SWELLA, SWELLB, and SWELLC bits are set in the STATUS1 register. The maximum rms½ value measured during the dip is stored in the corresponding SWELLA, SWELLB, and SWELLC registers. The dip and swell event generates an interrupt on the IRQ1 pin and also generates an event on the CF4/EVENT/DREADY pin. The sign of the APF calculation follows the sign of AWATT. To determine if power factor is leading or lagging, refer to the sign of the total or fundamental reactive energy and the sign of the xPF or xWATT value, as indicated in Figure 71. WATT (–) VAR (–) QUADRANT III INDUCTIVE: CURRENT LAGS VOLTAGE The OC_EN bits in the CONFIG3 register select which phases to monitor for overcurrent events. The OIPHASE bits in the OISTATUS register indicate which current channels exceeded the threshold. The overcurrent value is stored in the corresponding OIA, OIB, or OIC registers. POWER FACTOR 1 = 0.866 CAP θ1 = –30° CAPACITIVE: CURRENT LEADS VOLTAGE WATT θ2 = 60° POWER FACTOR 2 = 0.5 IND CAPACITIVE: CURRENT LEADS VOLTAGE INDUCTIVE: CURRENT LAGS VOLTAGE WATT (–) VAR (+) QUADRANT II Overcurrent Indication The ADE9000 monitors the rms½ value on current channels to determine overcurrent events. If a rms½ current is greater than the user configured threshold in the OILVL register, the OI bit in the STATUS1 register is set. The overcurrent event generates an interrupt on the IRQ1 pin. WATT (+) VAR (–) QUADRANT IV WATT (+) VAR (+) QUADRANT I 90° LAGGING WATT(+) INDICATES POWER RECEIVED (IMPORTED FROM GRID) WATT(–) INDICATES POWER DELIVERED (EXPORTED TO GRID) 15210-069 The ADE9000 monitors rms½ value on voltage channels to determine a dip and swell event. If the voltage goes below a threshold specified in the DIP_LVL register for a user configured number of half cycles in the DIP_CYC register, the corresponding DIPA, DIPB, and DIPC bits are set in the STATUS1 register. The minimum rms½ value measured during the dip is stored in the corresponding DIPA, DIPB, and DIPC registers. The IPEAK register stores the peak current value in the IPEAKVAL bits and indicates which phase currents reached the value in the IPPHASE bits. IPEAKVAL is equal to xI_PCF/25. Figure 71. Active Power and VAR Sign for Capacitive and Inductive Loads The power factor result is stored in 5.27 format. The highest power factor value is 0x07FF FFFF, which corresponds to a power factor of 1. A power factor of −1 is stored as 0xF800 0000. To determine the power factor from the xPF register value, use the following equation: Power Factor = xPF × 2−27 Total Harmonic Distortion (THD) A THD calculation is available on the IA, IB, IC, VA, VB, and VC channels in the AITHD, BITHD, CITHD, AVTHD, BVTHD, and CVTHD registers, respectively. THD updates once every second. The THD calculation is stored in signed 5.27 format. The highest THD value is 0x2000 0000, which corresponds to a THD of 400%. To calculate the THD value as a percentage, use the following equation: %THD on Current Channel A = AITHD × 2−27 × 100% Peak Detection The ADE9000 records the peak value measured on the current and voltage channels from the xI_PCF and xV_PCF waveforms. Resampling 128 Points per Cycle The ADE9000 resamples the input data to provide 128 points per line cycle, independent of the input line frequency. The resampled data is available for all current channels and voltage Rev. A | Page 33 of 72 ADE9000 Data Sheet During manufacturing of each device, the TEMP_GAIN and TEMP_OFFSET bits of Register TEMP_TRIM are programed. To configure the temperature sensor, program the TEMP_CFG register. channels in the waveform buffer. Each resampled waveform sample is stored as a 16-bit signed integer in the waveform buffer. Temperature The temperature reading is available in the TEMP_RSLT register. To convert the temperature range into Celsius, use the following equation: Temperature (°C) = TEMP_RSLT × (−TEMP_GAIN/65536) + (TEMP_OFFSET/32) Rev. A | Page 34 of 72 Data Sheet ADE9000 WAVEFORM BUFFER The ADE9000 has a waveform buffer comprised of 2048, 32-bit memory locations. To configure the data into the waveform buffer, use the WF_SRC and WF_CAP_SEL bits in the WFB_CFG register. The data can come from the following four locations, as follows: • • • • Sinc4 outputs at 32 kSPS. The waveform buffer holds 8 ms of waveform data per channel. Sinc4 + IIR LPF output at 8 kSPS. The waveform buffer holds 32 ms of waveform data per channel. Current and voltage channel waveforms processed by the DSP at 8 kSPS. The waveform buffer holds 32 ms of waveform data per channel. Resampled waveforms with 128 points per line cycle processed by the DSP. The data rate varies with the line period. The waveform buffer holds 80 ms of waveform data per channel. The ADE9000 allows a selection of events to trigger waveform buffer captures, and there is an option to store the current waveform buffer address during an event to allow the user to synchronize the event with the waveform samples. The following waveform buffer actions are associated with an event when the buffer is filling continuously: • • • Use the SPI burst read mode to read the waveform buffer contents. The default value bursts out all the channels in the waveform buffer. The waveform buffer generates an interrupt on IRQ0 after the last address is filled. The DSP must be on to use the waveform buffer. The waveform buffer offers the following different filling modes for use with fixed data rate samples: • • Stops filling on trigger Centers capture around trigger Saves the event address and keeps filling Stop when buffer is full Continuous filling Rev. A | Page 35 of 72 ADE9000 Data Sheet INTERRUPTS/EVENTS The ADE9000 has three pins (IRQ0, IRQ1, and CF4/EVENT/ DREADY) that can be used as interrupts to the host processor. The IRQ0 and IRQ1 pins go low when an enabled interrupt occurs and stay low until the event is acknowledged by setting the corresponding status bit in the STATUS0 and STATUS1 registers, respectively. The bits in MASK0 and MASK1 configure respective interrupts. The EVENT function, which can multiplex with the CF4 and DREADY options, tracks the state of the enabled signals and goes low and high with these internal signals. The CF4_CFG bits in CONFIG1 register set the CF4/EVENT/DREADY pin functionality. The CF4/EVENT/ DREADY pin is useful for measuring the duration of events, such as dips or swells, externally. Rev. A | Page 36 of 72 Data Sheet ADE9000 ACCESSING ON-CHIP DATA SPI PROTOCOL OVERVIEW The ADE9000 has an SPI-compatible interface, consisting of four pins: SCLK, MOSI, MISO, and SS. The ADE9000 is always an SPI slave; it never initiates SPI communication. The SPI interface is compatible with 16-bit and 32-bit read/write operations. The maximum serial clock frequency supported by this interface is 20 MHz. The ADE9000 provides SPI burst read functionality on certain registers and the waveform buffer that allows multiple registers to be read after sending one CMD_HDR. DON’T CARE BITS 3 2 ADDR[11:0] R/W READ = 1 WRITE = 0 0 xxx 15210-172 ADDRESS TO BE ACCESSED 15 Figure 72. Command Header, CMD_HDR The ADE9000 SPI port calculates a 16-bit cyclic redundancy check (CRC-16) of the data sent out on its MOSI pin so that the integrity of the data received by the master can be checked. The CRC of the data sent out on the MOSI pin during the last register read is offered in a 16-bit register, CRC_SPI, and can be appended to the SPI read data as part of the SPI transaction. ADDITIONAL COMMUNICATION VERIFICATION REGISTERS The ADE9000 includes three registers that allow SPI operation verification. The LAST_CMD (Address 0x4AE), LAST_DATA_16 (Address 0x4AC), and LAST_DATA_32 (Address 0x423) registers record the received CMD_HDR and the last read or transmitted data. CRC OF CONFIGURATION REGISTERS The configuration register CRC feature in the ADE9000 monitors certain external and internal register values. It also optionally includes 15 registers that are individually selectable in the CRC_OPTEN register. The result is stored in the CRC_RSLT register. The ADE9000 generates an interrupt on IRQ1 if any of the monitored registers change the value of the CRC_RSLT register. CONFIGURATION LOCK The configuration lock feature prevents changes to the ADE9000 configuration. To enable this feature, write 0x3C64 to the WR_LOCK register. To disable the feature, write 0x4AD1. To determine whether this feature is active, read the WR_LOCK register, which reads as 1 if the protection is enabled and 0 if it is disabled. When this feature is enabled, it prevents writing to addresses from Address 0x000 to Address 0x073 and Address 0x400 to Address 0x4FE. Rev. A | Page 37 of 72 ADE9000 Data Sheet REGISTER MAP Table 6. Register Map Address 0x000 0x001 Name AIGAIN AIGAIN0 0x002 AIGAIN1 0x003 AIGAIN2 0x004 AIGAIN3 0x005 AIGAIN4 0x006 APHCAL0 0x007 APHCAL1 0x008 APHCAL2 0x009 APHCAL3 0x00A APHCAL4 0x00B 0x00C 0x00D 0x00E AVGAIN AIRMSOS AVRMSOS APGAIN 0x00F 0x010 0x011 0x012 AWATTOS AVAROS AFWATTOS AFVAROS Description Phase A current gain adjust. Phase A multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, AIGAIN0 through AIGAIN5, is applied based on the AIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase A multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, AIGAIN0 through AIGAIN5, is applied based on the AIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase A multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, AIGAIN0 through AIGAIN5, is applied based on the AIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase A multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, AIGAIN0 through AIGAIN5, is applied based on the AIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase A multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, AIGAIN0 through AIGAIN5, is applied based on the AIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase A multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the APHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the APHCAL0 through APHCAL4 value is applied based on the AIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase A multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the APHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the APHCAL0 through APHCAL4 value is applied based on the AIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase A multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the APHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the APHCAL0 through APHCAL4 value is applied based on the AIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase A multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the APHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the APHCAL0 through APHCAL4 value is applied based on the AIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase A multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the APHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the APHCAL0 through APHCAL4 value is applied based on the AIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase A voltage gain adjust. Phase A current rms offset for the filter-based AIRMS calculation. Phase A voltage rms offset for the filter-based AVRMS calculation. Phase A power gain adjust for the AWATT, AVA, AVAR, AFWATT, AFVA, and AFVAR calculations. Phase A total active power offset correction for the AWATT calculation. Phase A total reactive power offset correction for the AVAR calculation. Phase A fundamental active power offset correction for the AFWATT calculation. Phase A fundamental reactive power offset correction for the AFVAR calculation. Rev. A | Page 38 of 72 Reset 0x00000000 0x00000000 Access R/W R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 0x00000000 0x00000000 0x00000000 R/W R/W R/W R/W 0x00000000 0x00000000 0x00000000 0x00000000 R/W R/W R/W R/W Data Sheet Address 0x013 0x014 0x015 0x016 0x017 0x018 0x020 0x021 Name AIFRMSOS AVFRMSOS AVRMSONEOS AIRMSONEOS AVRMS1012OS AIRMS1012OS BIGAIN BIGAIN0 0x022 BIGAIN1 0x023 BIGAIN2 0x024 BIGAIN3 0x025 BIGAIN4 0x026 BPHCAL0 0x027 BPHCAL1 0x028 BPHCAL2 0x029 BPHCAL3 0x02A BPHCAL4 0x02B 0x02C 0x02D 0x02E BVGAIN BIRMSOS BVRMSOS BPGAIN 0x02F BWATTOS ADE9000 Description Phase A current rms offset for the fundamental current rms, AIFRMS calculation. Phase A voltage rms offset for the fundamental voltage rms, AVFRMS calculation. Phase A voltage rms offset for the fast rms½ AVRMSONE calculation. Phase A current rms offset for the fast rms½ AIRMSONE calculation. Phase A voltage rms offset for the 10 cycle rms/12 cycle rms AVRMS1012 calculation. Phase A current rms offset for the 10 cycle rms/12 cycle rms AIRMS1012 calculation. Phase B current gain adjust. Phase B multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, BIGAIN0 through BIGAIN5, is applied based on the BIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase B multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, BIGAIN0 through BIGAIN5, is applied based on the BIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase B multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, BIGAIN0 through BIGAIN5, is applied based on the BIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase B multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, BIGAIN0 through BIGAIN5, is applied based on the BIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase B multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, BIGAIN0 through BIGAIN5, is applied based on the BIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase B multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the BPHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the BPHCAL0 through BPHCAL4 value is applied based on the BIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase B multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the BPHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the BPHCAL0 through BPHCAL4 value is applied based on the BIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase B multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the BPHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the BPHCAL0 through BPHCAL4 value is applied based on the BIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase B multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the BPHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the BPHCAL0 through BPHCAL4 value is applied based on the BIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase B multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the BPHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the BPHCAL0 through BPHCAL4 value is applied based on the BIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase B voltage gain adjust. Phase B current rms offset for the BIRMS calculation. Phase B voltage rms offset for the BVRMS calculation. Phase B power gain adjust for the BWATT, BVA, BVAR, BFWATT, BFVA, and BFVAR calculations. Phase B total active power offset correction for the BWATT calculation. Rev. A | Page 39 of 72 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 0x00000000 0x00000000 0x00000000 R/W R/W R/W R/W 0x00000000 R/W ADE9000 Address 0x030 0x031 0x032 0x033 0x034 0x035 0x036 0x037 0x038 0x040 0x041 Name BVAROS BFWATTOS BFVAROS BIFRMSOS BVFRMSOS BVRMSONEOS BIRMSONEOS BVRMS1012OS BIRMS1012OS CIGAIN CIGAIN0 0x042 CIGAIN1 0x043 CIGAIN2 0x044 CIGAIN3 0x045 CIGAIN4 0x046 CPHCAL0 0x047 CPHCAL1 0x048 CPHCAL2 0x049 CPHCAL3 0x04A CPHCAL4 0x04B 0x04C 0x04D CVGAIN CIRMSOS CVRMSOS Data Sheet Description Phase B total reactive power offset correction for the BVAR calculation. Phase B fundamental active power offset correction for the BFWATT calculation. Phase B fundamental reactive power offset correction for the BFVAR calculation. Phase B current rms offset for the fundamental current rms BIFRMS calculation. Phase B voltage rms offset for the fundamental voltage rms BVFRMS calculation. Phase B voltage rms offset for the fast rms½ BVRMSONE calculation. Phase B current rms offset for the fast rms½ BIRMSONE calculation. Phase B voltage rms offset for the 10 cycle rms/12 cycle rms BVRMS1012 calculation. Phase B current rms offset for the 10 cycle rms/12 cycle rms BVRMS1012 calculation. Phase C current gain adjust. Phase C multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, CIGAIN0 through CIGAIN5, is applied based on the CIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase C multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, CIGAIN0 through CIGAIN5, is applied based on the CIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase C multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, CIGAIN0 through CIGAIN5, is applied based on the CIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase C Multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, CIGAIN0 through CIGAIN5, is applied based on the CIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase C Multipoint gain correction factor. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, an additional gain factor, CIGAIN0 through CIGAIN5, is applied based on the CIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase C multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the CPHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the CPHCAL0 through CPHCAL4 value is applied, based on the CIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase C multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the CPHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the CPHCAL0 through CPHCAL4 value is applied, based on the CIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase C multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the CPHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the CPHCAL0 through CPHCAL4 value is applied, based on the CIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase C multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the CPHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the CPHCAL0 through CPHCAL4 value is applied, based on the CIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase C multipoint phase correction factor. If multipoint phase and gain calibration is disabled, with MTEN = 0 in the CONFIG0 register, the CPHCAL0 phase compensation is applied. If multipoint phase and gain correction is enabled, with MTEN = 1, the CPHCAL0 through CPHCAL4 value is applied, based on the CIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Phase C voltage gain adjust. Phase C current rms offset for the CIRMS calculation. Phase C voltage rms offset for the CVRMS calculation. Rev. A | Page 40 of 72 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 0x00000000 0x00000000 R/W R/W R/W Data Sheet Address 0x04E Name CPGAIN 0x04F 0x050 0x051 0x052 0x053 0x054 0x055 0x056 0x057 0x058 0x060 0x061 CWATTOS CVAROS CFWATTOS CFVAROS CIFRMSOS CVFRMSOS CVRMSONEOS CIRMSONEOS CVRMS1012OS CIRMS1012OS CONFIG0 MTTHR_L0 0x062 0x063 0x064 0x065 0x066 0x067 0x068 0x069 0x06A 0x06B 0x06C 0x06D 0x06E 0x06F 0x070 0x071 MTTHR_L1 MTTHR_L2 MTTHR_L3 MTTHR_L4 MTTHR_H0 MTTHR_H1 MTTHR_H2 MTTHR_H3 MTTHR_H4 NIRMSOS ISUMRMSOS NIGAIN NPHCAL NIRMSONEOS NIRMS1012OS VNOM 0x072 DICOEFF 0x073 ISUMLVL 0x20A 0x20B 0x20C 0x20D 0x20E 0x20F 0x210 0x211 0x212 0x213 0x214 0x215 0x216 0x217 AI_PCF AV_PCF AIRMS AVRMS AIFRMS AVFRMS AWATT AVAR AVA AFWATT AFVAR AFVA APF AVTHD ADE9000 Description Phase C power gain adjust for the CWATT, CVA, CVAR, CFWATT, CFVA, and CFVAR calculations. Phase C total active power offset correction for the CWATT calculation. Phase C total reactive power offset correction for the CVAR calculation. Phase C fundamental active power offset correction for the CFWATT calculation. Phase C fundamental reactive power offset correction for the CFVAR calculation. Phase C current rms offset for the fundamental current rms CIFRMS calculation. Phase C voltage rms offset for the fundamental voltage rms CVFRMS calculation. Phase C voltage rms offset for the fast rms½ CVRMSONE calculation. Phase C current rms offset for the fast rms½ CIRMSONE calculation. Phase C voltage rms offset for the 10 cycle rms/12 cycle rms CVRMS1012 calculation. Phase C current rms offset for the 10 cycle rms/12 cycle rms CIRMS1012 calculation. Configuration Register 0. Multipoint phase/gain threshold. If MTEN = 1 in the CONFIG0 register, the MTGNTHR_Lx and MTGNTHR_Hx registers set up the ranges in which to apply each set of corrections, allowing hysteresis. See the Multipoint Phase and Gain Calibration section for more information. Multipoint phase/gain threshold. See MTTHR_L0 for more information. Multipoint phase/gain threshold. See MTTHR_L0 for more information. Multipoint phase/gain threshold. See MTTHR_L0 for more information. Multipoint phase/gain threshold. See MTTHR_L0 for more information. Multipoint phase/gain threshold. See MTTHR_L0 for more information. Multipoint phase/gain threshold. See MTTHR_L0 for more information. Multipoint phase/gain threshold. See MTTHR_L0 for more information. Multipoint phase/gain threshold. See MTTHR_L0 for more information. Multipoint phase/gain threshold. See MTTHR_L0 for more information. Neutral current rms offset for the NIRMS calculation. Offset correction for the ISUMRMS calculation based on the sum of IA + IB + IC ± IN. Neutral current gain adjust. Neutral current phase compensation. Neutral current rms offset for the fast rms½ NIRMSONE calculation. Neutral current rms offset for the 10 cycle rms/12 cycle rms NIRMS1012 calculation. Nominal phase voltage rms used in the computation of apparent power, xVA, when the VNOMx_EN bit is set in the CONFIG0 register. Value used in the digital integrator algorithm. If the integrator is turned on, with INTEN or ININTEN equal to one in the CONFIG0 register, it is recommended to set this value to 0xFFFFE000. Threshold to compare ISUMRMS against. Configure this register to receive a MISMTCH indication in STATUS0 if ISUMRMS exceeds this threshold. Instantaneous Phase A current channel waveform processed by the DSP at 8 kSPS. Instantaneous Phase A voltage channel waveform processed by the DSP at 8 kSPS. Phase A filter-based current rms value, updates at 8 kSPS. Phase A filter-based voltage rms value, updates at 8 kSPS. Phase A current fundamental rms, updates at 8 kSPS. Phase A voltage fundamental RMS, updates at 8 kSPS. Phase A low-pass filtered total active power, updated at 8 kSPS. Phase A low-pass filtered total reactive power, updated at 8 kSPS. Phase A total apparent power, updated at 8 kSPS. Phase A fundamental active power, updated at 8 kSPS. Phase A fundamental reactive power, updated at 8 kSPS. Phase A fundamental apparent power, updated at 8 kSPS. Phase A power factor, updated every 1.024 sec. Phase A voltage THD, updated every 1.024 sec. Rev. A | Page 41 of 72 Reset 0x00000000 Access R/W 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 R R R R R R R R R R R R R R ADE9000 Address 0x218 0x219 0x21A 0x21B Name AITHD AIRMSONE AVRMSONE AIRMS1012 0x21C AVRMS1012 0x21D AMTREGION 0x22A 0x22B 0x22C 0x22D 0x22E 0x22F 0x230 0x231 0x232 0x233 0x234 0x235 0x236 0x237 0x238 0x239 0x23A 0x23B BI_PCF BV_PCF BIRMS BVRMS BIFRMS BVFRMS BWATT BVAR BVA BFWATT BFVAR BFVA BPF BVTHD BITHD BIRMSONE BVRMSONE BIRMS1012 0x23C BVRMS1012 0x23D BMTREGION 0x24A 0x24B 0x24C 0x24D 0x24E 0x24F 0x250 0x251 0x252 0x253 0x254 0x255 0x256 0x257 0x258 0x259 CI_PCF CV_PCF CIRMS CVRMS CIFRMS CVFRMS CWATT CVAR CVA CFWATT CFVAR CFVA CPF CVTHD CITHD CIRMSONE Data Sheet Description Phase A current THD, updated every 1.024 sec. Phase A current fast rms½ calculation, one cycle rms updated every half cycle. Phase A voltage fast rms½ calculation, one cycle rms updated every half cycle. Phase A current fast 10 cycle rms/12 cycle rms calculation. The calculation is performed over 10 cycles if SELFREQ = 0 for a 50 Hz network or over 12 cycles if SELFREQ = 1 for a 60 Hz network, in the ACCMODE register. Phase A voltage fast 10 cycle rms/12 cycle rms calculation. The calculation is performed over 10 cycles if SELFREQ = 0 for a 50 Hz network or over 12 cycles if SELFREQ = 1 for a 60 Hz network, in the ACCMODE register. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, this register indicate which AIGAINx and APHCALx is currently being used. Instantaneous Phase B current channel waveform processed by the DSP at 8 kSPS. Instantaneous Phase B voltage channel waveform processed by the DSP at 8 kSPS. Phase B filter-based current rms value, updates at 8 kSPS. Phase B filter-based voltage rms value, updates at 8 kSPS. Phase B current fundamental rms, updates at 8 kSPS. Phase B voltage fundamental rms, updates at 8 kSPS. Phase B low-pass filtered total active power, updated at 8 kSPS. Phase B low-pass filtered total reactive power, updated at 8 kSPS. Phase B total apparent power, updated at 8 kSPS. Phase B fundamental active power, updated at 8 kSPS. Phase B fundamental reactive power, updated at 8 kSPS. Phase B fundamental apparent power, updated at 8 kSPS. Phase B power factor, updated every 1.024 sec. Phase B voltage THD, updated every 1.024 sec. Phase B current THD, updated every 1.024 sec. Phase B current fast rms½ calculation, one cycle rms updated every half cycle. Phase B voltage fast rms½ calculation, one cycle rms updated every half cycle. Phase B current fast 10 cycle rms/12 cycle rms calculation. The calculation is performed over 10 cycles if SELFREQ = 0 for a 50 Hz network or over 12 cycles if SELFREQ = 1 for a 60 Hz network, in the ACCMODE register. Phase B voltage fast 10 cycle rms/12 cycle rms calculation. The calculation is performed over 10 cycles if SELFREQ = 0 for a 50 Hz network or over 12 cycles if SELFREQ = 1 for a 60 Hz network, in the ACCMODE register. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the COFIG0 register, this register indicate which BIGAINx and BPHCALx is currently being used. Instantaneous Phase C current channel waveform processed by the DSP at 8 kSPS. Instantaneous Phase C voltage channel waveform processed by the DSP at 8 kSPS. Phase C filter-based current rms value, updates at 8 kSPS. Phase C filter-based voltage rms value, updates at 8 kSPS. Phase C current fundamental rms, updates at 8 kSPS. Phase C voltage fundamental rms, updates at 8 kSPS. Phase C low-pass filtered total active power, updated at 8 kSPS. Phase C low-pass filtered total reactive power, updated at 8 kSPS. Phase C total apparent power, updated at 8 kSPS. Phase C fundamental active power, updated at 8 kSPS. Phase C fundamental reactive power, updated at 8 kSPS. Phase C fundamental apparent power, updated at 8 kSPS. Phase C power factor, updated every 1.024 sec. Phase C voltage THD, updated every 1.024 sec. Phase C current total THD, updated every 1.024 sec. Phase C current fast rms½ calculation, one cycle rms updated every half cycle. Rev. A | Page 42 of 72 Reset 0x00000000 0x00000000 0x00000000 0x00000000 Access R R R R 0x00000000 R 0x0000000F R 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 R R R R R R R R R R R R R R R R R R 0x00000000 R 0x0000000F R 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 R R R R R R R R R R R R R R R R Data Sheet Address 0x25A 0x25B Name CVRMSONE CIRMS1012 0x25C CVRMS1012 0x25D CMTREGION 0x265 0x266 0x267 0x268 NI_PCF NIRMS NIRMSONE NIRMS1012 0x269 0x26A ISUMRMS VERSION2 0x2E5 0x2E6 AWATT_ACC AWATTHR_LO 0x2E7 AWATTHR_HI 0x2EF 0x2F0 AVAR_ACC AVARHR_LO 0x2F1 AVARHR_HI 0x2F9 0x2FA AVA_ACC AVAHR_LO 0x2FB AVAHR_HI 0x303 AFWATT_ACC 0x304 AFWATTHR_LO 0x305 AFWATTHR_HI 0x30D AFVAR_ACC 0x30E AFVARHR_LO 0x30F AFVARHR_HI 0x317 AFVA_ACC 0x318 AFVAHR_LO 0x319 AFVAHR_HI 0x321 0x322 BWATT_ACC BWATTHR_LO ADE9000 Description Phase C voltage fast rms½ calculation, one cycle rms updated every half cycle. Phase C current fast 10 cycle rms/12 cycle rms calculation. The calculation is performed over 10 cycles if SELFREQ = 0 for a 50 Hz network or over 12 cycles if SELFREQ = 1 for a 60 Hz network, in the ACCMODE register. Phase C voltage fast 10 cycle rms/12 cycle rms calculation. The calculation is performed over 10 cycles if SELFREQ = 0 for a 50 Hz network or over 12 cycles if SELFREQ = 1 for a 60 Hz network, in the ACCMODE register. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, these bits indicate which CIGAINx and CPHCALx is currently being used. Instantaneous neutral current channel waveform processed by the DSP at 8 kSPS. Neutral current filter-based rms value. Neutral current fast rms½ calculation, one cycle rms updated every half cycle. Neutral current fast 10 cycle rms/12 cycle rms calculation. The calculation is performed over 10 cycles if SELFREQ = 0 for a 50 Hz network or over 12 cycles if SELFREQ = 1 for a 60 Hz network, in the ACCMODE register. Filter-based rms based on the sum of IA + IB + IC ± IN. This register indicates the version of the metrology algorithms after the user writes run = 1 to start the measurements. Phase A accumulated total active power, updated after PWR_TIME 8 kSPS samples. Phase A accumulated total active energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated total active energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated total reactive power, updated after PWR_TIME 8 kSPS samples. Phase A accumulated total reactive energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated total reactive energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated total apparent power, updated after PWR_TIME 8 kSPS samples. Phase A accumulated total apparent energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated total apparent energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated fundamental active power, updated after PWR_TIME 8 kSPS samples. Phase A accumulated fundamental active energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated fundamental active energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated fundamental reactive power, updated after PWR_TIME 8 kSPS samples. Phase A accumulated fundamental reactive energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated fundamental reactive energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated fundamental apparent power, updated after PWR_TIME 8 kSPS samples. Phase A accumulated fundamental apparent energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated fundamental apparent energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase B accumulated total active power, updated after PWR_TIME 8 kSPS samples. Phase B accumulated total active energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Rev. A | Page 43 of 72 Reset 0x00000000 0x00000000 Access R R 0x00000000 R 0x0000000F R 0x00000000 0x00000000 0x00000000 0x00000000 R R R R 0x00000000 0x0000000C R R 0x00000000 0x00000000 R R 0x00000000 R 0x00000000 0x00000000 R R 0x00000000 R 0x00000000 0x00000000 R R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 0x00000000 R R ADE9000 Address 0x323 Name BWATTHR_HI 0x32B 0x32C BVAR_ACC BVARHR_LO 0x32D BVARHR_HI 0x335 0x336 BVA_ACC BVAHR_LO 0x337 BVAHR_HI 0x33F BFWATT_ACC 0x340 BFWATTHR_LO 0x341 BFWATTHR_HI 0x349 BFVAR_ACC 0x34A BFVARHR_LO 0x34B BFVARHR_HI 0x353 BFVA_ACC 0x354 BFVAHR_LO 0x355 BFVAHR_HI 0x35D 0x35E CWATT_ACC CWATTHR_LO 0x35F CWATTHR_HI 0x367 0x368 CVAR_ACC CVARHR_LO 0x369 CVARHR_HI 0x371 0x372 CVA_ACC CVAHR_LO 0x373 CVAHR_HI 0x37B CFWATT_ACC 0x37C CFWATTHR_LO 0x37D CFWATTHR_HI 0x385 CFVAR_ACC 0x386 CFVARHR_LO Data Sheet Description Phase B accumulated total active energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase B accumulated total reactive power, updated after PWR_TIME 8 kSPS samples. Phase B accumulated total reactive energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase B accumulated total reactive energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase B accumulated total apparent power, updated after PWR_TIME 8 kSPS samples. Phase B accumulated total apparent energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase B accumulated total apparent energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase B accumulated fundamental active power, updated after PWR_TIME 8 kSPS samples. Phase B accumulated fundamental active energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase B accumulated fundamental active energy, MSB. Updated according to the settings in EP_CFG and EGY_TIME registers. Phase B accumulated fundamental reactive power, updated after PWR_TIME 8 kSPS samples. Phase B accumulated fundamental reactive energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase B accumulated fundamental reactive energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase B accumulated fundamental apparent power, updated after PWR_TIME 8 kSPS samples. Phase B accumulated fundamental apparent energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase B accumulated fundamental apparent energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase C accumulated total active power, updated after PWR_TIME 8 kSPS samples. Phase C accumulated total active energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase C accumulated total active energy, MSB. Updated according to the settings in the P_CFG and EGY_TIME registers. Phase C accumulated total reactive power, updated after PWR_TIME 8 kSPS samples. Phase C accumulated total reactive energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase C accumulated total reactive energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase C accumulated total apparent power, updated after PWR_TIME 8 kSPS samples. Phase C accumulated total apparent energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase C accumulated total apparent energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase C accumulated fundamental active power, updated after PWR_TIME 8 kSPS samples. Phase C accumulated fundamental active energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase C accumulated fundamental active energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase C accumulated fundamental reactive power, updated after PWR_TIME 8 kSPS samples. Phase C accumulated fundamental reactive energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Rev. A | Page 44 of 72 Reset 0x00000000 Access R 0x00000000 0x00000000 R R 0x00000000 R 0x00000000 0x00000000 R R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 0x00000000 R R 0x00000000 R 0x00000000 0x00000000 R R 0x00000000 R 0x00000000 0x00000000 R R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R Data Sheet Address 0x387 Name CFVARHR_HI 0x38F CFVA_ACC 0x390 CFVAHR_LO 0x391 CFVAHR_HI 0x397 PWATT_ACC 0x39B NWATT_ACC 0x39F PVAR_ACC 0x3A3 NVAR_ACC 0x400 0x401 0x402 0x403 0x404 0x405 0x406 0x407 0x409 0x40A IPEAK VPEAK STATUS0 STATUS1 EVENT_STATUS MASK0 MASK1 EVENT_MASK OILVL OIA 0x40B OIB 0x40C OIC 0x40D OIN 0x40E USER_PERIOD 0x40F VLEVEL 0x410 0x411 0x412 0x413 0x414 0x415 0x416 0x417 0x418 0x419 0x41A 0x41B DIP_LVL DIPA DIPB DIPC SWELL_LVL SWELLA SWELLB SWELLC APERIOD BPERIOD CPERIOD COM_PERIOD 0x41C ACT_NL_LVL ADE9000 Description Phase C accumulated fundamental reactive energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase C accumulated fundamental apparent power, updated after PWR_TIME 8 kSPS samples. Phase C accumulated fundamental apparent energy, LSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase C accumulated fundamental apparent energy, MSB. Updated according to the settings in the EP_CFG and EGY_TIME registers. Accumulated positive total active power, MSB, from AWATT, BWATT, and CWATT registers, updated after PWR_TIME 8 kSPS samples. Accumulated Negative total active power, MSB, from AWATT, BWATT, and CWATT registers, updated after PWR_TIME 8 kSPS samples. Accumulated positive total reactive power, MSB, from AVAR, BVAR, and CVAR registers, updated after PWR_TIME 8 kSPS samples. Accumulated Negative total reactive power, MSB, from AVAR, BVAR, and CVAR registers, updated after PWR_TIME 8 kSPS samples. Current peak register. Voltage peak register. Status Register 0. Status Register 1. Event status register. Interrupt Enable Register 0. Interrupt Enable Register 1. Event enable register. Over current detection threshold level. Phase A overcurrent rms½ value. If a phase is enabled, with the OC_ENA bit set in the CONFIG3 register and AIRMSONE greater than the OILVL threshold, this value is updated. Phase B overcurrent rms½ value. If a phase is enabled, with the OC_ENB bit set in the CONFIG3 register and BIRMSONE greater than the OILVL threshold, this value is updated. Phase C overcurrent rms½ value. If a phase is enabled, with the OC_ENC bit set in the CONFIG3 register and CIRMSONE greater than the OILVL threshold, this value is updated. Neutral current overcurrent rms½ value. If enabled, with the OC_ENN bit set in the CONFIG3 register and NIRMSONE greater than the OILVL threshold, this value is updated. User configured line period value used for resampling, fast rms½ and 10 cycle rms/ 12 cycle rms when the UPERIOD_SEL bit in the CONFIG2 register is set. Register used in the algorithm that computes the fundamental active, reactive, and apparent powers as well as the fundamental IRMS and VRMS values. Voltage RMS½ dip detection threshold level. Phase A voltage rms½ value during a dip condition. Phase B voltage rms½ value during a dip condition. Phase C voltage rms½ value during a dip condition. Voltage rms½ swell detection threshold level. Phase A voltage rms½ value during a swell condition. Phase B voltage rms½ value during a swell condition. Phase C voltage rms½ value during a swell condition. Line period on Phase A voltage. Line period on Phase B voltage. Line period on Phase C voltage. Line period measurement on combined signal from Phase A, Phase B, and Phase C voltages. No load threshold in the total and fundamental active power datapath. Rev. A | Page 45 of 72 Reset 0x00000000 Access R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 R 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00FFFFFF 0x00000000 R R R/W R/W R R/W R/W R/W R/W R 0x00000000 R 0x00000000 R 0x00000000 R 0x00500000 R/W 0x00045D45 R/W 0x00000000 0x007FFFFF 0x007FFFFF 0x007FFFFF 0x00FFFFFF 0x00000000 0x00000000 0x00000000 0x00A00000 0x00A00000 0x00A00000 0x00A00000 R/W R R R R/W R R R R R R R 0x0000FFFF R/W ADE9000 Address 0x41D 0x41E 0x41F 0x420 Name REACT_NL_LVL APP_NL_LVL PHNOLOAD WTHR 0x421 VARTHR 0x422 VATHR 0x423 LAST_DATA_32 0x424 0x425 0x472 0x474 0x480 0x481 0x482 0x483 0x484 0x485 0x486 0x487 0x488 0x489 0x48A 0x48B 0x48C 0x48F 0x490 0x491 0x492 0x493 0x494 0x495 0x496 0x497 0x498 0x499 0x49A ADC_REDIRECT CF_LCFG PART_ID TEMP_TRIM RUN CONFIG1 ANGL_VA_VB ANGL_VB_VC ANGL_VA_VC ANGL_VA_IA ANGL_VB_IB ANGL_VC_IC ANGL_IA_IB ANGL_IB_IC ANGL_IA_IC DIP_CYC SWELL_CYC OISTATUS CFMODE COMPMODE ACCMODE CONFIG3 CF1DEN CF2DEN CF3DEN CF4DEN ZXTOUT ZXTHRSH ZX_LP_SEL 0x49C SEQ_CYC 0x49D 0x4A0 0x4A1 PHSIGN WFB_CFG WFB_PG_IRQEN 0x4A2 0x4A3 WFB_TRG_CFG WFB_TRG_STAT Data Sheet Description No load threshold in the total and fundamental reactive power datapath. No load threshold in the total and fundamental apparent power datapath. Phase no load register. Sets the maximum output rate from the digital to frequency converter for the total and fundamental active power for the CFx calibration pulse output. It is recommended to write WTHR = 0x0010_0000. Sets the maximum output rate from the digital to frequency converter for the total and fundamental reactive power for the CFx calibration pulse output. It is recommended to write VARTHR = 0x0010_0000. Sets the maximum output rate from the digital to frequency converter for the total and fundamental apparent power for the CFx calibration pulse output. It is recommended to write VATHR = 0x0010_0000. This register holds the data read or written during the last 32-bit transaction on the SPI port. This register allows any ADC output to be redirected to any digital datapath. CFx calibration pulse width configuration register. This register identifies the IC. If the ADE9000_ID bit = 1, the IC is the ADE9000. Temperature sensor gain and offset, calculated during the manufacturing process. Write this register to 1 to start the measurements. Configuration Register 1. Time between positive to negative zero crossings on Phase A and Phase B voltages. Time between positive to negative zero crossings on Phase B and Phase C voltages. Time between positive to negative zero crossings on Phase A and Phase C voltages. Time between positive to negative zero crossings on Phase A voltage and current. Time between positive to negative zero crossings on Phase B voltage and current. Time between positive to negative zero crossings on Phase C voltage and current. Time between positive to negative zero crossings on Phase A and Phase B current. Time between positive to negative zero crossings on Phase B and Phase C current. Time between positive to negative zero crossings on Phase A and Phase C current. Voltage rms½ dip detection cycle configuration. Voltage rms½ swell detection cycle configuration. Overcurrent status register. CFx configuration register. Computation mode register. Accumulation mode register. Configuration Register 3. CF1 denominator register. CF2 denominator register. CF3 denominator register. CF4 denominator register. Zero-crossing timeout configuration register. Voltage channel zero-crossing threshold register. This register selects which zero crossing and which line period measurement are used for other calculations. Number of line cycles used for phase sequence detection. It is recommended to set this register to 1. Power sign register. Waveform buffer configuration register. This register enables interrupts to occur after specific pages of the waveform buffer are filled. This register enables events to trigger a capture in the waveform buffer. This register indicates the last page that was filled in the waveform buffer and the location of trigger events. Rev. A | Page 46 of 72 Reset 0x0000FFFF 0x0000FFFF 0x00000000 0x0000FFFF Access R/W R/W R R/W 0x0000FFFF R/W 0x0000FFFF R/W 0x00000000 R 0x001FFFFF 0x00000000 0x00100000 0x00000000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 0xF000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0009 0x001E R/W R/W R R/W R/W R/W R R R R R R R R R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00FF R/W 0x0000 0x0000 0x0000 R R/W R/W 0x0000 0x0000 R/W R/W Data Sheet Address 0x4A4 0x4A8 0x4A9 Name CONFIG5 CRC_RSLT CRC_SPI 0x4AC LAST_DATA_16 0x4AE LAST_CMD 0x4AF 0x4B0 0x4B1 0x4B2 0x4B4 0x4B5 CONFIG2 EP_CFG PWR_TIME EGY_TIME CRC_FORCE CRC_OPTEN 0x4B6 0x4B7 0x4B9 0x4BA 0x4BF 0x4E0 0x4F0 0x4FE TEMP_CFG TEMP_RSLT PGA_GAIN CHNL_DIS WR_LOCK VAR_DIS RESERVED1 Version 0x500 0x501 0x502 0x503 0x504 0x505 0x506 0x510 0x511 0x512 0x513 0x514 0x515 0x516 0x600 0x601 0x602 0x603 0x604 0x605 0x606 0x607 0x608 0x609 0x60A 0x60B 0x60C 0x60D AI_SINC_DAT AV_SINC_DAT BI_SINC_DAT BV_SINC_DAT CI_SINC_DAT CV_SINC_DAT NI_SINC_DAT AI_LPF_DAT AV_LPF_DAT BI_LPF_DAT BV_LPF_DAT CI_LPF_DAT CV_LPF_DAT NI_LPF_DAT AV_PCF_1 BV_PCF_1 CV_PCF_1 NI_PCF_1 AI_PCF_1 BI_PCF_1 CI_PCF_1 AIRMS_1 BIRMS_1 CIRMS_1 AVRMS_1 BVRMS_1 CVRMS_1 NIRMS_1 ADE9000 Description Configuration Register 5. This register holds the CRC of the configuration registers. This register holds the 16-bit CRC of the data sent out on the MOSI pin during the last SPI register read. This register holds the data read or written during the last 16-bit transaction on the SPI port. This register holds the address and read/write operation request (CMD_HDR) for the last transaction on the SPI port. Configuration Register 2. Energy and power accumulation configuration. Power update time configuration. Energy accumulation update time configuration. This register forces an update of the CRC of configuration registers. This register selects which registers are optionally included in the configuration register CRC feature. Temperature sensor configuration register. Temperature measurement result. This register configures the PGA gain for each ADC. ADC channel enable/disable. This register enables the configuration lock feature. Enables/disables total reactive power calculation. This register is reserved. Version of ADE9000 IC. Use Logical AND 16-bit value with 0xFFC0 to obtain the current version. The current version is 0x00C0 Current channel A ADC waveforms from the sinc4 output at 32 kSPS. Voltage channel A ADC waveforms from the sinc4 output at 32 kSPS. Current channel B ADC waveforms from the sinc4 output at 32 kSPS. Voltage channel B ADC waveforms from the sinc4 output at 32 kSPS. Current channel C ADC waveforms from the sinc4 output at 32 kSPS. Voltage channel C ADC waveforms from the sinc4 output at 32 kSPS. Neutral current channel ADC waveforms from the sinc4 output at 32 kSPS. Current channel A ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. Voltage channel A ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. Current channel B ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. Voltage channel B ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. Current channel C ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. Voltage channel C ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. Neutral current channel ADC waveforms from the sinc4 + IIR LPF output at 8 kSPS. SPI burst read accessible. Registers organized functionally. See AV_PCF. SPI burst read accessible. Registers organized functionally. See BV_PCF. SPI burst read accessible. Registers organized functionally. See CV_PCF. SPI burst read accessible. Registers organized functionally. See NI_PCF. SPI burst read accessible. Registers organized functionally. See AI_PCF. SPI burst read accessible. Registers organized functionally. See BI_PCF. SPI burst read accessible. Registers organized functionally. See CI_PCF. SPI burst read accessible. Registers organized functionally. See AIRMS. SPI burst read accessible. Registers organized functionally. See BIRMS. SPI burst read accessible. Registers organized functionally. See CIRMS. SPI burst read accessible. Registers organized functionally. See AVRMS. SPI burst read accessible. Registers organized functionally. See BVRMS. SPI burst read accessible. Registers organized functionally. See CVRMS. SPI burst read accessible. Registers organized functionally. See NIRMS. Rev. A | Page 47 of 72 Reset 0x0063 0x0000 0x0000 Access R/W R R 0x0000 R 0x0000 R 0x0C00 0x0000 0x00FF 0x00FF 0x0000 0x0000 R/W R/W R/W R/W R/W R/W 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x00FE R/W R R/W R/W R/W R/W R R 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ADE9000 Address 0x60E 0x60F 0x610 0x611 0x612 0x613 0x614 0x615 0x616 0x617 0x618 0x619 0x61A 0x61B 0x61C 0x61D 0x61E 0x61F 0x620 0x621 0x622 0x623 0x624 0x625 0x626 0x627 0x628 0x629 0x62A 0x62B 0x62C 0x62D 0x62E 0x62F 0x630 0x631 0x632 0x633 0x634 0x635 0x636 0x637 0x638 0x639 0x63A 0x63B 0x63C 0x680 0x681 0x682 0x683 Name AWATT_1 BWATT_1 CWATT_1 AVA_1 BVA_1 CVA_1 AVAR_1 BVAR_1 CVAR_1 AFVAR_1 BFVAR_1 CFVAR_1 APF_1 BPF_1 CPF_1 AVTHD_1 BVTHD_1 CVTHD_1 AITHD_1 BITHD_1 CITHD_1 AFWATT_1 BFWATT_1 CFWATT_1 AFVA_1 BFVA_1 CFVA_1 AFIRMS_1 BFIRMS_1 CFIRMS_1 AFVRMS_1 BFVRMS_1 CFVRMS_1 AIRMSONE_1 BIRMSONE_1 CIRMSONE_1 AVRMSONE_1 BVRMSONE_1 CVRMSONE_1 NIRMSONE_1 AIRMS1012_1 BIRMS1012_1 CIRMS1012_1 AVRMS1012_1 BVRMS1012_1 CVRMS1012_1 NIRMS1012_1 AV_PCF_2 AI_PCF_2 AIRMS_2 AVRMS_2 Data Sheet Description SPI burst read accessible. Registers organized functionally. See AWATT. SPI burst read accessible. Registers organized functionally. See BWATT. SPI burst read accessible. Registers organized functionally. See CWATT. SPI burst read accessible. Registers organized functionally. See AVA. SPI burst read accessible. Registers organized functionally. See BVA. SPI burst read accessible. Registers organized functionally. See CVA. SPI burst read accessible. Registers organized functionally. See AVAR. SPI burst read accessible. Registers organized functionally. See BVAR. SPI burst read accessible. Registers organized functionally. See CVAR. SPI burst read accessible. Registers organized functionally. See AFVAR. SPI burst read accessible. Registers organized functionally. See BFVAR. SPI burst read accessible. Registers organized functionally. See CFVAR. SPI burst read accessible. Registers organized functionally. See APF. SPI burst read accessible. Registers organized functionally. See BPF. SPI burst read accessible. Registers organized functionally. See CPF. SPI burst read accessible. Registers organized functionally. See AVTHD. SPI burst read accessible. Registers organized functionally. See BVTHD. SPI burst read accessible. Registers organized functionally. See CVTHD. SPI burst read accessible. Registers organized functionally. See AITHD. SPI burst read accessible. Registers organized functionally. See BITHD. SPI burst read accessible. Registers organized functionally. See CITHD. SPI burst read accessible. Registers organized functionally. See AFWATT. SPI burst read accessible. Registers organized functionally. See BFWATT. SPI burst read accessible. Registers organized functionally. See CFWATT. SPI burst read accessible. Registers organized functionally. See AFVA. SPI burst read accessible. Registers organized functionally. See BFVA. SPI burst read accessible. Registers organized functionally. See CFVA. SPI burst read accessible. Registers organized functionally. See AFIRMS. SPI burst read accessible. Registers organized functionally. See BFIRMS. SPI burst read accessible. Registers organized functionally. See CFIRMS. SPI burst read accessible. Registers organized functionally. See AFVRMS. SPI burst read accessible. Registers organized functionally. See BFVRMS. SPI burst read accessible. Registers organized functionally. See CFVRMS. SPI burst read accessible. Registers organized functionally. See AIRMSONE. SPI burst read accessible. Registers organized functionally. See BIRMSONE. SPI burst read accessible. Registers organized functionally. See CIRMSONE. SPI burst read accessible. Registers organized functionally. See AVRMSONE. SPI burst read accessible. Registers organized functionally. See BVRMSONE. SPI burst read accessible. Registers organized functionally. See CVRMSONE. SPI burst read accessible. Registers organized functionally. See NIRMSONE. SPI burst read accessible. Registers organized functionally. See AIRMS1012. SPI burst read accessible. Registers organized functionally. See BIRMS1012. SPI burst read accessible. Registers organized functionally. See CIRMS1012. SPI burst read accessible. Registers organized functionally. See AVRMS1012. SPI burst read accessible. Registers organized functionally. See BVRMS1012. SPI burst read accessible. Registers organized functionally. See CVRMS1012. SPI burst read accessible. Registers organized functionally. See NIRMS1012. SPI burst read accessible. Registers organized by phase. See AV_PCF. SPI burst read accessible. Registers organized by phase. See AI_PCF. SPI burst read accessible. Registers organized by phase. See AIRMS. SPI burst read accessible. Registers organized by phase. See AVRMS. Rev. A | Page 48 of 72 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Data Sheet Address 0x684 0x685 0x686 0x687 0x688 0x689 0x68A 0x68B 0x68C 0x68D 0x68E 0x68F 0x690 0x691 0x692 0x693 0x694 0x695 0x696 0x697 0x698 0x699 0x69A 0x69B 0x69C 0x69D 0x69E 0x69F 0x6A0 0x6A1 0x6A2 0x6A3 0x6A4 0x6A5 0x6A6 0x6A7 0x6A8 0x6A9 0x6AA 0x6AB 0x6AC 0x6AD 0x6AE 0x6AF 0x6B0 0x6B1 0x6B2 0x6B3 0x6B4 0x6B5 0x6B6 Name AWATT_2 AVA_2 AVAR_2 AFVAR_2 APF_2 AVTHD_2 AITHD_2 AFWATT_2 AFVA_2 AFIRMS_2 AFVRMS_2 AIRMSONE_2 AVRMSONE_2 AIRMS1012_2 AVRMS1012_2 BV_PCF_2 BI_PCF_2 BIRMS_2 BVRMS_2 BWATT_2 BVA_2 BVAR_2 BFVAR_2 BPF_2 BVTHD_2 BITHD_2 BFWATT_2 BFVA_2 BFIRMS_2 BFVRMS_2 BIRMSONE_2 BVRMSONE_2 BIRMS1012_2 BVRMS1012_2 CV_PCF_2 CI_PCF_2 CIRMS_2 CVRMS_2 CWATT_2 CVA_2 CVAR_2 CFVAR_2 CPF_2 CVTHD_2 CITHD_2 CFWATT_2 CFVA_2 CFIRMS_2 CFVRMS_2 CIRMSONE_2 CVRMSONE_2 ADE9000 Description SPI burst read accessible. Registers organized by phase. See AWATT. SPI burst read accessible. Registers organized by phase. See AVA. SPI burst read accessible. Registers organized by phase. See AVAR. SPI burst read accessible. Registers organized by phase. See AFVAR. SPI burst read accessible. Registers organized by phase. See APF. SPI burst read accessible. Registers organized by phase. See AVTHD. SPI burst read accessible. Registers organized by phase. See AITHD. SPI burst read accessible. Registers organized by phase. See AFWATT. SPI burst read accessible. Registers organized by phase. See AFVA. SPI burst read accessible. Registers organized by phase. See AFIRMS. SPI burst read accessible. Registers organized by phase. See AFVRMS. SPI burst read accessible. Registers organized by phase. See AIRMSONE. SPI burst read accessible. Registers organized by phase. See AVRMSONE. SPI burst read accessible. Registers organized by phase. See AIRMS1012. SPI burst read accessible. Registers organized by phase. See AVRMS1012. SPI burst read accessible. Registers organized by phase. See BV_PCF. SPI burst read accessible. Registers organized by phase. See BI_PCF. SPI burst read accessible. Registers organized by phase. See BIRMS. SPI burst read accessible. Registers organized by phase. See BVRMS. SPI burst read accessible. Registers organized by phase. See BWATT. SPI burst read accessible. Registers organized by phase. See BVA. SPI burst read accessible. Registers organized by phase. See BVAR. SPI burst read accessible. Registers organized by phase. See BFVAR. SPI burst read accessible. Registers organized by phase. See BPF. SPI burst read accessible. Registers organized by phase. See BVTHD. SPI burst read accessible. Registers organized by phase. See BITHD. SPI burst read accessible. Registers organized by phase. See BFWATT. SPI burst read accessible. Registers organized by phase. See BFVA. SPI burst read accessible. Registers organized by phase. See BFIRMS. SPI burst read accessible. Registers organized by phase. See BFVRMS. SPI burst read accessible. Registers organized by phase. See BIRMSONE. SPI burst read accessible. Registers organized by phase. See BVRMSONE. SPI burst read accessible. Registers organized by phase. See BIRMS1012. SPI burst read accessible. Registers organized by phase. See BVRMS1012. SPI burst read accessible. Registers organized by phase. See CV_PCF. SPI burst read accessible. Registers organized by phase. See CI_PCF. SPI burst read accessible. Registers organized by phase. See CIRMS. SPI burst read accessible. Registers organized by phase. See CVRMS. SPI burst read accessible. Registers organized by phase. See CWATT. SPI burst read accessible. Registers organized by phase. See CVA. SPI burst read accessible. Registers organized by phase. See CVAR. SPI burst read accessible. Registers organized by phase. See CFVAR. SPI burst read accessible. Registers organized by phase. See CPF. SPI burst read accessible. Registers organized by phase. See CVTHD. SPI burst read accessible. Registers organized by phase. See CITHD. SPI burst read accessible. Registers organized by phase. See CFWATT. SPI burst read accessible. Registers organized by phase. See CFVA. SPI burst read accessible. Registers organized by phase. See CFIRMS. SPI burst read accessible. Registers organized by phase. See CFVRMS. SPI burst read accessible. Registers organized by phase. See CIRMSONE. SPI burst read accessible. Registers organized by phase. See CVRMSONE. Rev. A | Page 49 of 72 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ADE9000 Address 0x6B7 0x6B8 0x6B9 0x6BA 0x6BB 0x6BC Name CIRMS1012_2 CVRMS1012_2 NI_PCF_2 NIRMS_2 NIRMSONE_2 NIRMS1012_2 Data Sheet Description SPI burst read accessible. Registers organized by phase. See CIRMS1012. SPI burst read accessible. Registers organized by phase. See CVRMS1012. SPI burst read accessible. Registers organized by phase. See NI_PCF. SPI burst read accessible. Registers organized by phase. See NIRMS. SPI burst read accessible. Registers organized by phase. See NIRMSONE. SPI burst read accessible. Registers organized by phase. See NIRMS1012. Rev. A | Page 50 of 72 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Access R/W R/W R/W R/W R/W R/W Data Sheet ADE9000 REGISTER DETAILS Table 7 details the registers of the ADE9000 that have bit fields. Additional registers listed in Table 6 do not have bit fields. Table 7. Register Details Addr. Name 0x060 CONFIG0 Bits Bit Name [31:14] RESERVED 13 DISRPLPF 12 DISAPLPF 11 ININTEN 10 VNOMC_EN 9 VNOMB_EN 8 VNOMA_EN 7 RMS_SRC_SEL 6 ZX_SRC_SEL 5 INTEN 4 MTEN 3 HPFDIS 2 [1:0] RESERVED ISUM_CFG Settings Description Reserved. Set this bit to disable the low-pass filter in the total reactive power datapath. Set this bit to disable the low-pass filter in the total active power datapath. Set this bit to enable the digital integrator in the neutral current channel. Set this bit to use the nominal phase voltage rms, VNOM, in the computation of Phase C total apparent power, CVA. Set this bit to use the nominal phase voltage rms, VNOM, in the computation of Phase B total apparent power, BVA. Set this bit to use the nominal phase voltage rms, VNOM, in the computation of Phase A total apparent power, AVA. This bit selects which samples are used for the rms½ and 10 cycle rms/12 cycle rms calculation. 0 xI_PCF waveforms, after the high-pass filter and integrator. 1 ADC samples, before the high-pass filter and integrator. This bit selects whether data going into the zerocrossing detection circuit comes before the high-pass filter, integrator, and phase compensation or afterwards. 0 After the high-pass filter, integrator, and phase compensation. 1 Before the high-pass filter, integrator, and phase compensation. Set this bit to enable the integrators in the phase current channels. The neutral current channel integrator is managed by the ININTEN bit in the CONFIG0 register. Set this bit to enable multipoint phase and gain compensation. If enabled, an additional gain factor, xIGAIN0 through xIGAIN5, is applied to the current channel based on the xIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values. Set this bit to disable high-pass filters in all the voltage and current channels. Reserved. ISUM calculation configuration. 00 ISUM = AI_PCF + BI_PCF + CI_PCF (for approximated neutral current rms calculation). 01 ISUM = AI_PCF + BI_PCF + CI_PCF + NI_PCF (to determine mismatch between neutral and phase currents). 10 ISUM = AI_PCF + BI_PCF + CI_PCF − NI_PCF (to determine mismatch between neutral and phase currents). 11 ISUM = AI_PCF + BI_PCF + CI_PCF (for approximated neutral current rms calculation). Rev. A | Page 51 of 72 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W ADE9000 Data Sheet Addr. Name 0x21D AMTREGION Bits [31:4] [3:0] Bit Name RESERVED AREGION 0x23D BMTREGION [31:4] [3:0] RESERVED BREGION 0x25D CMTREGION [31:4] [3:0] RESERVED CREGION 0x400 IPEAK [31:27] RESERVED [26:24] IPPHASE [23:0] IPEAKVAL Settings Description Reserved. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, these bits indicate which AIGAINx and APHCALx is currently being used 0000 AIGAIN0, APHCAL0. 0001 AIGAIN1, APHCAL1. 0010 AIGAIN2, APHCAL2. 0011 AIGAIN3, APHCAL3. 0100 AIGAIN4, APHCAL4. 1111 This feature is disabled because MTEN = 0 in the CONFIG0 register. Reserved. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, these bits indicate which BIGAINx and BPHCALx is currently being used. 0000 BIGAIN0, BPHCAL0. 0001 BIGAIN1, BPHCAL1. 0010 BIGAIN2, BPHCAL2. 0011 BIGAIN3, BPHCAL3. 0100 BIGAIN4, BPHCAL4. 1111 This feature is disabled because MTEN = 0 in the CONFIG0 register. Reserved. If multipoint gain and phase compensation is enabled, with MTEN = 1 in the CONFIG0 register, these bits indicate which CIGAINx and CPHCALx is currently being used. 0000 CIGAIN0, CPHCAL0. 0001 CIGAIN1, CPHCAL1. 0010 CIGAIN2, CPHCAL2. 0011 CIGAIN3, CPHCAL3. 0100 CIGAIN4, CPHCAL4. 1111 This feature is disabled because MTEN = 0 in the CONFIG0 register. Reserved. These bits indicate which phases generate the IPEAKVAL value. Note that the PEAKSEL, Bits[4:2] in the CONFIG3 register determine which current channel to monitor the peak value on. When IPPHASE, Bit 0 is set to 1, Phase A current is generated by the IPEAKVAL, Bits[23:0] value. Similarly, IPPHASE, Bit 1 indicates that the Phase B and IPPHASE, Bit 2 indicates that the Phase C current generated the peak value. The IPEAK register stores the absolute value of the peak current. IPEAK is equal to xI_PCF/25. Rev. A | Page 52 of 72 Reset 0x0 0xF Access R R 0x0 0xF R R 0x0 0xF R R 0x0 0x0 R R 0x0 R Data Sheet Addr. Name 0x401 VPEAK ADE9000 Bits Bit Name [31:27] RESERVED [26:24] VPPHASE [23:0] 0x402 STATUS0 VPEAKVAL [31:26] RESERVED 25 TEMP_RDY 24 MISMTCH 23 COH_WFB_FULL 22 WFB_TRIG 21 THD_PF_RDY 20 RMS1012RDY 19 RMSONERDY 18 PWRRDY 17 PAGE_FULL 16 WFB_TRIG_IRQ 15 DREADY 14 CF4 13 CF3 12 CF2 11 CF1 Settings Description Reserved. These bits indicate which phase(s) generate the VPEAKVAL value. Note that the PEAKSEL, Bits[4:2] in the CONFIG3 register determine which voltage channels to monitor the peak value on. When VPPHASE, Bit 0 is 1, the Phase A voltage generated the VPEAKVAL, Bits[23:0] value. Similarly, VPPHASE, Bit 1 indicates Phase B and VPPHASE, Bit 2 indicates that the Phase C voltage generated the peak value. The VPEAK register stores the absolute value of the peak voltage. VPEAK is equal to xV_PCF/25. Reserved. This bit goes high to indicate when a new temperature measurement is available. This bit is set to indicate a change in the relationship between ISUMRMS and ISUMLVL. This bit is set when the waveform buffer is full with resampled data, which is selected when WF_CAP_SEL = 0 in the WFB_CFG register. This bit is set when one of the events configured in WFB_TRIG_CFG occurs. This bit goes high to indicate when the THD and power factor measurements update, every 1.024 sec. This bit is set when the 10 cycle rms/12 cycle rms values update. This bit is set when the fast rms½ rms values update. This bit is set when the power values in the xWATT_ACC, xVA_ACC, xVAR_ACC, xFWATT_ACC, xFVA_ACC, and xFVAR_ACC registers update, after PWR_TIME 8 kSPS samples. This bit is set when a page enabled in the WFB_PG_IRQEN register is filled with fixed data rate samples, when WF_CAP_SEL bit in the WFB_CFG register is equal to zero. This bit is set when the waveform buffer stops filling after an event configured in WFB_TRIG_CFG occurs. This happens with fixed data rate samples only, when WF_CAP_SEL bit in the WFB_CFG register is equal to zero. This bit is set when new waveform samples are ready. The update rate depends on the data selected in the WF_SRC bits in the WFB_CFG register. This bit is set when a CF4 pulse is issued, when the CF4 pin goes from a high to low state. This bit is set when a CF3 pulse is issued, when the CF3 pin goes from a high to low state. This bit is set when a CF2 pulse is issued, when the CF2 pin goes from a high to low state. This bit is set when a CF1 pulse is issued, when the CF1 pin goes from a high to low state. Rev. A | Page 53 of 72 Reset 0x0 0x0 Access R R 0x0 R 0x0 0x0 R R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 ADE9000 Addr. Name 0x403 STATUS1 Data Sheet Bits 10 Bit Name REVPSUM4 9 REVPSUM3 8 REVPSUM2 7 REVPSUM1 6 REVRPC 5 REVRPB 4 REVRPA 3 REVAPC 2 REVAPB 1 REVAPA 0 EGYRDY 31 ERROR3 30 ERROR2 29 ERROR1 28 ERROR0 Settings Description This bit is set to indicate if the CF4 polarity changed sign. For example, if the last CF4 pulse was positive reactive energy and the next CF4 pulse is negative reactive energy, the REVPSUM4 bit is set. This bit is updated when a CF4 pulse is output, when the CF4 pin goes from high to low. This bit is set to indicate if the CF3 polarity changed sign. See REVPSUM4. This bit is set to indicate if the CF2 polarity changed sign. See REVPSUM4. This bit is set to indicate if the CF1 polarity changed sign. See REVPSUM4. This bit indicates if the Phase C total or fundamental reactive power has changed sign. The PWR_SIGN_SEL bit in the EP_CFG register selects whether total or fundamental reactive power is monitored. This bit is updated when the power values in the xVAR_ACC and xFVAR_ACC registers update, after PWR_TIME 8 kSPS samples. This bit indicates if the Phase B total or fundamental reactive power has changed sign. See REVRPC. This bit indicates if the Phase A total or fundamental reactive power has changed sign. See REVRPC. This bit indicates if the Phase C total or fundamental active power has changed sign. The PWR_SIGN_SEL bit in the EP_CFG register selects whether total or fundamental active power is monitored. This bit is updated when the power values in the xWATT_ACC and xFWATT_ACC registers update, after PWR_TIME 8 kSPS samples. This bit indicates if the Phase B total or fundamental active power has changed sign. See REVAPC. This bit indicates if the Phase A total or fundamental active power has changed sign. See REVAPC. This bit is set when the power values in the xWATTHR xVAHR, xVARHR, xFVARHR, xFWATTHR, xFVAHR registers update, after EGY_TIME 8 kSPS samples or line cycles, depending on the EGY_TMR_MODE bit in the EP_CFG register. This bit indicates an error and generates a nonmaskable interrupt. Issue a software or hardware reset to clear this error. This bit indicates that an error was detected and corrected. No action is required. This bit indicates an error and generates a nonmaskable interrupt. Issue a software or hardware reset to clear this error. This bit indicates an error and generates a nonmaskable interrupt. Issue a software or hardware reset to clear this error. Rev. A | Page 54 of 72 Reset 0x0 Access R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R 0x0 R Data Sheet Addr. Name ADE9000 Bits 27 Bit Name CRC_DONE 26 CRC_CHG 25 DIPC 24 DIPB 23 DIPA 22 SWELLC 21 SWELLB 20 SWELLA 19 18 RESERVED SEQERR 17 OI 16 RSTDONE 15 ZXIC 14 ZXIB 13 ZXIA 12 ZXCOMB 11 ZXVC 10 ZXVB 9 ZXVA 8 ZXTOVC 7 ZXTOVB 6 ZXTOVA 5 VAFNOLOAD Settings Description This bit is set to indicate when the configuration register CRC calculation is complete, after initiated by writing the FORCE_CRC_UPDATE bit in the CRC_FORCE register. This bit is set if any of the registers monitored by the configuration register CRC change value. The CRC_RSLT register holds the new configuration register CRC value. This bit is set to indicates Phase C voltage entered or exited a dip condition. This bit is set to indicates Phase B voltage entered or exited a dip condition. This bit is set to indicates Phase A voltage entered or exited a dip condition. This bit is set to indicates Phase C voltage entered or exited a swell condition. This bit is set to indicates Phase B voltage entered or exited a swell condition. This bit it set to indicates Phase A voltage entered or exited a swell condition. Reserved. This bit is set to indicate a phase sequence error on the Phase voltage zero crossings. This bit is set to indicate that an overcurrent event occurred on one of the phases indicated in the OISTATUS register. This bit is set to indicate that the IC finished its power-up sequence after a reset or after changing between PSM3 operating mode to PSM0, which indicates that the user can configure the IC via the SPI port. When this bit is set to 1, it indicates a zero crossing is detected on Phase C current. When this bit is set to 1, it indicates a zero crossing is detected on Phase B current. When this bit is set to 1, it indicates a zero crossing is detected on Phase A current. When this bit is set, it indicates a zero crossing is detected on the combined signal from VA, VB, and VC. When this bit is set, it indicates a zero crossing is detected on the Phase C voltage channel. When this bit is set, it indicates a zero crossing is detected on the Phase B voltage channel. When this bit is set, it indicates a zero crossing is detected on the Phase A voltage channel. This bit is set to indicate a zero-crossing timeout on Phase C. This means that a zero crossing on the Phase C voltage is missing. This bit is set to indicate a zero-crossing timeout on Phase B. This means that a zero crossing on the Phase B voltage is missing. This bit is set to indicate a zero-crossing timeout on Phase A. This means that a zero crossing on the Phase A voltage is missing. This bit is set when one or more phase fundamental apparent energy enters or exits the no load condition. The phase is indicated in the PHNOLOAD register. Rev. A | Page 55 of 72 Reset 0x0 Access R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 0x0 R R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 ADE9000 Addr. Name Data Sheet Bits 4 Bit Name RFNOLOAD 3 AFNOLOAD 2 VANLOAD 1 RNLOAD 0 ANLOAD 0x404 EVENT_STATUS [31:17] RESERVED 16 DREADY 15 VAFNOLOAD 14 RFNOLOAD 13 AFNOLOAD 12 VANLOAD 11 RNLOAD 10 ANLOAD 9 REVPSUM4 Settings Description This bit is set when one or more phase fundamental reactive energy enters or exits the no load condition. The phase is indicated in the PHNOLOAD register. This bit is set when one or more phase fundamental active energy enters or exits the no load condition. The phase is indicated in the PHNOLOAD register. This bit is set when one or more phase total apparent energy enters or exits the no load condition. The phase is indicated in the PHNOLOAD register. This bit is set when one or more phase total reactive energy enters or exits the no load condition. The phase is indicated in the PHNOLOAD register. This bit is set when one or more phase total active energy enters or exits the no load condition. The phase is indicated in the PHNOLOAD register. Reserved. This bit changes from a zero to a one when new waveform samples are ready. The update rate depends on the data selected in the WF_SRC bits in the WFB_CFG register. This bit is set when the fundamental apparent energy accumulations in all phases are out of no load. This bit goes to zero when one or more phases of total apparent energy accumulation goes into no load. This bit is set when the fundamental reactive energy accumulations in all phases are out of no load. This bit goes to zero when one or more phases of fundamental reactive energy accumulation goes into no load. This bit is set when the fundamental active energy accumulations in all phases are out of no load. This bit goes to zero when one or more phases of fundamental active energy accumulation goes into no load. This bit is set when the total apparent energy accumulations in all phases are out of no load. This bit goes to zero when one or more phases of total apparent energy accumulation goes into no load. This bit is set when the total reactive energy accumulations in all phases are out of no load. This bit goes to zero when one or more phases of total reactive energy accumulation goes into no load. This bit is set when the total active energy accumulations in all phases are out of no load. This bit goes to zero when one or more phases of total active energy accumulation goes into no load. This bit indicates the sign of the last CF4 pulse. A zero indicates that the pulse was from negative energy and a one indicates that the energy was positive. This bit is updated when a CF4 pulse is output, when the CF4 pin goes from high to low. Rev. A | Page 56 of 72 Reset 0x0 Access R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 0x0 R R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet Addr. Name 0x405 MASK0 ADE9000 Bits 8 Bit Name REVPSUM3 7 REVPSUM2 6 REVPSUM1 5 SWELLC 4 SWELLB 3 SWELLA 2 DIPC 1 DIPB 0 DIPA [31:26] RESERVED 25 TEMP_RDY_MASK 24 MISMTCH 23 COH_WFB_FULL 22 WFB_TRIG 21 THD_PF_RDY 20 RMS1012RDY 19 RMSONERDY 18 PWRRDY Settings Description This bit indicates the sign of the last CF3 pulse. A zero indicates that the pulse was from negative energy and a one indicates that the energy was positive. This bit is updated when a CF3 pulse is output, when the CF3 pin goes from high to low. This bit indicates the sign of the last CF2 pulse. A zero indicates that the pulse was from negative energy and a one indicates that the energy was positive. This bit is updated when a CF2 pulse is output, when the CF2 pin goes from high to low. This bit indicates the sign of the last CF1 pulse. A zero indicates that the pulse was from negative energy and a one indicates that the energy was positive. This bit is updated when a CF1 pulse is output, when the CF1 pin goes from high to low. This bit is equal to one when the Phase C voltage is in the swell condition and is zero when it is not in a swell condition. This bit is equal to one when the Phase B voltage is in the swell condition and is zero when it is not in a swell condition. This bit is equal to one when the Phase A voltage is in the swell condition and is zero when it is not in a swell condition. This bit is equal to one when the Phase C voltage is in the dip condition and is zero when it is not in a dip condition. This bit is equal to one when the Phase B voltage is in the dip condition and is zero when it is not in a dip condition This bit is equal to one when the Phase A voltage is in the dip condition and is zero when it is not in a dip condition. Reserved. Set this bit to enable an interrupt when a new temperature measurement is available. Set this bit to enable an interrupt when there is a change in the relationship between ISUMRMS and ISUMLVL. Set this bit to enable an interrupt when the waveform buffer is full with resampled data, which is selected when WF_CAP_SEL = 0 in the WFB_CFG register. Set this bit to enable an interrupt when one of the events configured in WFB_TRIG_CFG occurs. Set this bit to enable an interrupt when the THD and power factor measurements are updated, every 1.024 sec. Set this bit to enable an interrupt when the 10 cycle rms/12 cycle rms values are updated. Set this bit to enable an interrupt when the fast rms½ values are updated. Set this bit to enable an interrupt when the power values in the xWATT_ACC, xVA_ACC, xVAR_ACC, xFWATT_ACC, xFVA_ACC, and xFVAR_ACC registers update, after PWR_TIME 8 kSPS samples. Rev. A | Page 57 of 72 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W ADE9000 Addr. Name Data Sheet Bits 17 Bit Name PAGE_FULL 16 WFB_TRIG_IRQ 15 DREADY 14 CF4 13 CF3 12 CF2 11 CF1 10 REVPSUM4 9 REVPSUM3 8 REVPSUM2 7 REVPSUM1 6 REVRPC 5 REVRPB 4 REVRPA 3 REVAPC 2 REVAPB 1 REVAPA 0 EGYRDY Settings Description Set this bit to enable an interrupt when a page enabled in the WFB_PG_IRQEN register is filled. Set this bit to enable an interrupt when This bit is set when the waveform buffer has stopped filling after an event configured in WFB_TRIG_CFG occurs. Set this bit to enable an interrupt when new waveform samples are ready. The update rate depends on the data selected in the WF_SRC bits in the WFB_CFG register. Set this bit to enable an interrupt when the CF4 pulse is issued, when the CF4 pin goes from a high to low state. Set this bit to enable an interrupt when the CF3 pulse is issued, when the CF3 pin goes from a high to low state. Set this bit to enable an interrupt when the CF2 pulse is issued, when the CF2 pin goes from a high to low state. Set this bit to enable an interrupt when the CF1 pulse is issued, when the CF1 pin goes from a high to low state. Set this bit to enable an interrupt when the CF4 polarity changed sign. Set this bit to enable an interrupt when the CF3 polarity changed sign. Set this bit to enable an interrupt when the CF2 polarity changed sign. Set this bit to enable an interrupt when the CF1 polarity changed sign. Set this bit to enable an interrupt when the Phase C total or fundamental reactive power has changed sign. Set this bit to enable an interrupt when the Phase C total or fundamental reactive power has changed sign. Set this bit to enable an interrupt when the Phase A total or fundamental reactive power has changed sign. Set this bit to enable an interrupt when the Phase C total or fundamental active power has changed sign. Set this bit to enable an interrupt when the Phase B total or fundamental active power has changed sign. Set this bit to enable an interrupt when the Phase A total or fundamental active power has changed sign. Set this bit to enable an interrupt when the power values in the xWATTHR, xVAHR xVARHR xFWATTHR, xFVAHR, and xFVARHR registers update, after EGY_TIME 8 kSPS samples or line cycles, depending on the EGY_TMR_MODE bit in the EP_CFG register. Rev. A | Page 58 of 72 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet Addr. Name 0x406 MASK1 ADE9000 Bits 31 Bit Name ERROR3 30 29 ERROR2 ERROR1 28 ERROR0 27 CRC_DONE 26 CRC_CHG 25 DIPC 24 DIPB 23 DIPA 22 SWELLC 21 SWELLB 20 SWELLA 19 18 RESERVED SEQERR 17 OI 16 15 RESERVED ZXIC 14 ZXIB 13 ZXIA 12 ZXCOMB 11 ZXVC 10 ZXVB 9 ZXVA Settings Description Set this bit to enable an interrupt if ERROR3 occurs. Issue a software reset or hardware reset to clear this error. Set this bit to enable an interrupt if ERROR2 occurs. This interrupt is not maskable. Issue a software reset or hardware reset to clear this error. This interrupt is not maskable. Issue a software reset or hardware reset to clear this error. Set this bit to enable an interrupt when the configuration register CRC calculation is complete, after initiated by writing the FORCE_CRC_UPDATE bit in the CRC_FORCE register. Set this bit to enable an interrupt if any of the registers monitored by the configuration register CRC change value. The CRC_RSLT register holds the new configuration register CRC value. Set this bit to enable an interrupt when the Phase C voltage enters a dip condition Set this bit to enable an interrupt when the Phase B voltage enters a dip condition. Set this bit to enable an interrupt when the Phase A voltage enters a dip condition. Set this bit to enable an interrupt when the Phase C voltage enters a swell condition. Set this bit to enable an interrupt when the Phase B voltage enters a swell condition. Set this bit to enable an interrupt when the Phase A voltage enters a swell condition. Reserved. Set this bit to enable an interrupt when on a phase sequence error on the phase voltage zero crossings. Set this bit to enable an interrupt when one of the currents enabled in the OC_EN bits in the CONFIG3 register enters an overcurrent condition. Reserved. Set this bit to enable an interrupt when a zero crossing is detected on the Phase C current channel. Set this bit to enable an interrupt when a zero crossing is detected on the Phase B current channel. Set this bit to enable an interrupt when a zero crossing is detected on the Phase A current channel. Set this bit to enable an interrupt when a zero crossing is detected on the combined signal from VA, VB, and VC. Set this bit to enable an interrupt when a zero crossing is detected on the Phase C voltage channel. Set this bit to enable an interrupt when a zero crossing is detected on the Phase B voltage channel. Set this bit to enable an interrupt when a zero crossing is detected on the Phase A voltage channel. Rev. A | Page 59 of 72 Reset 0x0 Access R/W 0x0 0x0 R/W R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W ADE9000 Addr. Name 0x407 EVENT_MASK Data Sheet Bits 8 Bit Name ZXTOVC 7 ZXTOVB 6 ZXTOVA 5 VAFNOLOAD 4 RFNOLOAD 3 AFNOLOAD 2 VANLOAD 1 RNLOAD 0 ANLOAD [31:17] RESERVED 16 DREADY 15 VAFNOLOAD 14 RFNOLOAD 13 AFNOLOAD 12 VANLOAD 11 RNLOAD 10 ANLOAD 9 REVPSUM4 Settings Description Set this bit to enable an interrupt when there is a zero-crossing timeout on Phase C. This means that a zero crossing on the Phase C voltage is missing. Set this bit to enable an interrupt when there is a zero-crossing timeout on Phase B. This means that a zero crossing on the Phase B voltage is missing. Set this bit to enable an interrupt when there is a zero-crossing timeout on Phase A. This means that a zero crossing on the Phase A voltage is missing. Set this bit to enable an interrupt when one or more phase fundamental apparent energy enters or exits the no load condition. Set this bit to enable an interrupt when one or more phase total reactive energy enters or exits the no load condition. Set this bit to enable an interrupt when one or more phase fundamental active energy enters or exits the no load condition. Set this bit to enable an interrupt when one or more phase total apparent energy enters or exits the no load condition. Set this bit to enable an interrupt when one or more phase total reactive energy enters or exits the no load condition. Set this bit to enable an interrupt when one or more phase total active energy enters or exits the no load condition. Reserved. Set this bit to enable the EVENT pin to go low when new waveform samples are ready. The update rate depends on the data selected in the WF_SRC bits in the WFB_CFG register. Set this bit to enable the EVENT pin to go low when one or more phases of fundamental apparent energy accumulation goes into no load. Set this bit to enable the EVENT pin to go low when one or more phases of fundamental reactive energy accumulation goes into no load. Set this bit to enable the EVENT pin to go low when one or more phases of fundamental active energy accumulation goes into no load. Set this bit to enable the EVENT pin to go low when one or more phases of total apparent energy accumulation goes into no load. Set this bit to enable the EVENT pin to go low when one or more phases of total reactive energy accumulation goes into no load. Set this bit to enable the EVENT pin to go low when one or more phases of total active energy accumulation goes into no load. Set this bit to enable the EVENT pin to go low to indicate if the last CF4 pulse was from negative energy. This bit is updated when a CF4 pulse is output, when the CF4 pin goes from high to low. Rev. A | Page 60 of 72 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet Addr. Name 0x409 OILVL 0x40A OIA ADE9000 Bits 8 Bit Name REVPSUM3 7 REVPSUM2 6 REVPSUM1 5 SWELLCEN 4 SWELLBEN 3 SWELLAEN 2 DIPCEN 1 DIPBEN 0 DIPAEN [31:24] [23:0] [31:24] [23:0] RESERVED OILVL_VAL RESERVED OI_VAL 0x40B OIB [31:24] RESERVED [23:0] OIB_VAL 0x40C OIC [31:24] RESERVED [23:0] OIC_VAL 0x40D OIN [31:24] RESERVED [23:0] OIN_VAL 0x40F VLEVEL [31:24] RESERVED [23:0] VLEVEL_VAL Settings Description Set this bit to enable the EVENT pin to go low to indicate if the last CF3 pulse was from negative energy. This bit is updated when a CF3 pulse is output, when the CF3 pin goes from high to low. Set this bit to enable the EVENT pin to go low to indicate if the last CF2 pulse was from negative energy. This bit is updated when a CF2 pulse is output, when the CF2 pin goes from high to low. Set this bit to enable the EVENT pin to go low to indicate if the last CF1 pulse was from negative energy. This bit is updated when a CF1 pulse is output, when the CF1 pin goes from high to low. Set this bit to enable the EVENT pin to go low to indicate that the Phase C voltage is in a swell condition. Set this bit to enable the EVENT pin to go low to indicate that the Phase B voltage is in a swell condition. Set this bit to enable the EVENT pin to go low to indicate that the Phase A voltage is in a swell condition. Set this bit to enable the EVENT pin to go low to indicate that the Phase C voltage is in a dip condition. Set this bit to enable the EVENT pin to go low to indicate that the Phase B voltage is in a dip condition. Set this bit to enable the EVENT pin to go low to indicate that the Phase A voltage is in a dip condition. Reserved. Over current detection threshold level. Reserved. Phase A overcurrent rms½ value. If a phase is enabled, with the OC_ENA bit set in the CONFIG3 register and AIRMSONE greater than the OILVL threshold, this value is updated. Reserved. Phase B overcurrent rms½ value. If a phase is enabled, with the OC_ENB bit set in the CONFIG3 register and BIRMSONE greater than the OILVL threshold, this value is updated. Reserved. Phase C overcurrent rms½ value. If a phase is enabled, with the OC_ENC bit set in the CONFIG3 register and CIRMSONE greater than the OILVL threshold, this value is updated. Reserved. Neutral current overcurrent rms½ value. If enabled, with the OC_ENN bit set in the CONFIG3 register and NIRMSONE greater than the OILVL threshold, this value is updated. Reserved. Register used in the algorithm that computes the fundamental active, reactive, and apparent powers, as well as the fundamental IRMS and VRMS values. Rev. A | Page 61 of 72 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0xFFFFFF 0x0 0x0 R R/W R R 0x0 0x0 R R 0x0 0x0 R R 0x0 0x0 R R 0x0 R 0x45D45 R/W ADE9000 Addr. Name 0x410 DIP_LVL 0x411 DIPA 0x412 DIPB 0x413 DIPC 0x414 SWELL_LVL 0x415 SWELLA Data Sheet Bits [31:24] [23:0] [31:24] [23:0] [31:24] [23:0] [31:24] [23:0] [31:24] [23:0] [31:24] [23:0] Bit Name RESERVED DIPLVL RESERVED DIPA_VAL RESERVED DIPB_VAL RESERVED DIPC_VAL RESERVED SWELLLVL RESERVED SWELLA_VAL 0x416 SWELLB [31:24] RESERVED [23:0] SWELLB_VAL 0x417 SWELLC [31:24] RESERVED [23:0] SWELLC_VAL 0x41F PHNOLOAD [31:18] RESERVED 17 CFVANL 16 CFVARNL 15 CFWATTNL 14 CVANL 13 CVARNL 12 CWATTNL 11 BFVANL 10 BFVARNL 9 BFWATTNL 8 BVANL 7 BVARNL 6 BWATTNL 5 AFVANL 4 AFVARNL 3 AFWATTNL 2 AVANL 1 AVARNL 0 AWATTNL Settings Description Reserved. Voltage rms½ dip detection threshold level. Reserved. Phase A voltage rms½ value during a dip condition. Reserved. Phase B voltage rms½ value during a dip condition. Reserved. Phase C voltage rms½ value during a dip condition. Reserved. Voltage rms½ swell detection threshold level. Reserved. Phase A voltage rms½ value during a swell condition. Reserved. Phase B voltage rms½ value during a swell condition. Reserved. Phase C voltage rms½ value during a swell condition. Reserved. This bit is set if the Phase C fundamental apparent energy is in no load. This bit is set if the Phase C fundamental reactive energy is in no load. This bit is set if the Phase C fundamental active energy is in no load. This bit is set if the Phase C total apparent energy is in no load. This bit is set if the Phase B total reactive energy is in no load. This bit is set if the Phase C total active energy is in no load. This bit is set if the Phase B fundamental apparent energy is in no load. This bit is set if the Phase B fundamental reactive energy is in no load. This bit is set if the Phase B fundamental active energy is in no load. This bit is set if the Phase B total apparent energy is in no load. This bit is set if the Phase B total reactive energy is in no load. This bit is set if the Phase B total active energy is in no load. This bit is set if the Phase A fundamental apparent energy is in no load. This bit is set if the Phase A fundamental reactive energy is in no load. This bit is set if the Phase A fundamental active energy is in no load. This bit is set if the Phase A total apparent energy is in no load. This bit is set if the Phase A total reactive energy is in no load. This bit is set if the Phase A total active energy is in no load. Rev. A | Page 62 of 72 Reset 0x0 0x0 0x0 0x7FFFFF 0x0 0x7FFFFF 0x0 0x7FFFFF 0x0 0xFFFFFF 0x0 0x0 Access R R/W R R R R R R R R/W R R 0x0 0x0 R R 0x0 0x0 R R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet ADE9000 Addr. Name Bits Bit Name 0x424 ADC_REDIRECT [31:21] RESERVED [20:18] VC_DIN [17:15] VB_DIN [14:12] VA_DIN 0x425 CF_LCFG [11:9] IN_DIN [8:6] IC_DIN [5:3] IB_DIN [2:0] IA_DIN [31:23] RESERVED 22 CF4_LT 21 CF3_LT 20 CF2_LT 19 CF1_LT [18:0] CF_LTMR Settings Description Reserved. VC channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 000 IA ADC data. 001 IB ADC data. 010 IC ADC data. 011 IN ADC data. 100 VA ADC data. 101 VB ADC data. 110 VC ADC data. 111 VC ADC data. VB channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 111 VB ADC data. VA channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 111 VA ADC data. IN channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 111 IN ADC data. IC channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 111 IC ADC data. IB channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 111 IB ADC data. IA channel data can be selected from all channels. The bit descriptions for 000b through 110b match VC_DIN. When the value is equal to 111b, then 111 IA ADC data. Reserved. If this bit is set, the CF4 pulse width is determined by the CF_LTMR register value. If this bit is equal to zero, then the active low pulse width is set at 80 ms for frequencies lower than 6.25 Hz. If this bit is set, the CF3 pulse width is determined by the CF_LTMR register value. If this bit is equal to zero, the active low pulse width is set at 80 ms for frequencies lower than 6.25 Hz. If this bit is set, the CF2 pulse width is determined by the CF_LTMR register value. If this bit is equal to zero, the active low pulse width is set at 80 ms for frequencies lower than 6.25 Hz. If this bit is set, the CF1 pulse width is determined by the CF_LTMR register value. If this bit is equal to zero, the active low pulse width is set at 80 ms for frequencies lower than 6.25 Hz. If the CFx_LT bit in the CF_LCFG register is set, this value determines the active low pulse width of the CFx pulse. Rev. A | Page 63 of 72 Reset 0x0 0x7 Access R R/W 0x7 R/W 0x7 R/W 0x7 R/W 0x7 R/W 0x7 R/W 0x7 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W ADE9000 Addr. Name 0x472 PART_ID 0x474 TEMP_TRIM 0x481 CONFIG1 Data Sheet Bits [31:21] 20 [19:0] [31:16] Bit Name RESERVED ADE9000_ID RESERVED TEMP_OFFSET Settings Description Reserved. This bit is set to identify an ADE9000 IC. Reserved. Offset of temperature sensor, calculated during the manufacturing process. [15:0] TEMP_GAIN Gain of temperature sensor, calculated during the manufacturing process. 15 EXT_REF Set this bit if using an external voltage reference. [14:13] RESERVED Reserved. 12 IRQ0_ON_IRQ1 Set this bit to combine all the interrupts onto a single interrupt pin, IRQ1, instead of using two pins, IRQ0 and IRQ1. Note that the IRQ0 pin still indicates the enabled IRQ0 events while in this mode and the IRQ1pin indicates both IRQ1 and IRQ0 events. 11 BURST_EN Set this bit to enable burst read functionality on the registers from Address 0x500 to Address 0x63C or Address 0x680 to Address 0x6BC. Note that this bit disables the CRC being appended to SPI register reads. 10 DIP_SWELL_IRQ_MODE Set interrupt mode for dip/swell. 0 Receive continuous interrupts after every DIP_CYC/SWELL_CYC cycles. 1 Receive one interrupt when entering dip/swell mode and another interrupt when exiting dip/swell mode. [9:8] PWR_SETTLE These bits configure the time for the power and filter-based rms measurements to settle before starting the power, energy, and CF accumulations. 0: 64 ms. 1: 128 ms. 2: 256 ms. 3: 0 ms. [7:6] RESERVED Reserved. 5 CF_ACC_CLR Set this bit to clear the accumulation in the digital to frequency converter and the CFDEN counter. Note that this bit automatically clears itself. 4 RESERVED Reserved. [3:2] CF4_CFG These bits select which function to output on the CF4 pin. 00 CF4, from digital to frequency converter. 01 CF4, from digital to frequency converter. 10 EVENT. 11 DREADY. 1 CF3_CFG This bit selects which function to output on the CF3 pin. 0 CF3, from digital to frequency converter. 1 Zero-crossing output selected by the ZX_SEL bits in the ZX_LP_SEL register. 0 SWRST Set this bit to initiate a software reset. Note that this bit is self clearing. Rev. A | Page 64 of 72 Reset 0x0 0x1 0x0 0x0 Access R R R R/W 0x0 R/W 0x0 0x0 0x0 R/W R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R W 0x0 0x0 R R/W 0x0 R/W 0x0 W1 Data Sheet ADE9000 Addr. Name 0x48F OISTATUS Bits [15:4] [3:0] Bit Name RESERVED OIPHASE 0x490 CFMODE 15 CF4DIS 14 13 12 [11:9] CF3DIS CF2DIS CF1DIS CF4SEL [8:6] CF3SEL [5:3] CF2SEL [2:0] CF1SEL 0x491 COMPMODE 0x492 ACCMODE [15:12] RESERVED [11:9] TERMSEL4 [8:6] TERMSEL3 [5:3] TERMSEL2 [2:0] TERMSEL1 [15:9] 8 RESERVED SELFREQ 7 ICONSEL Settings Description Reserved. OIPHASE, Bit 0 indicates Phase A is above OILVL. OIPHASE, Bit 1 indicates Phase B is above OILVL. OIPHASE, Bit 2 indicates Phase C is above OILVL. OIPHASE, Bit 3 indicates Phase N is above OILVL. CF4 output disable. Set this bit to disable the CF4 output and bring the pin high. Note that when this bit is set, the CFx bit in STATUS0 is not set when a CF pulse is accumulated in the digital to frequency converter. CF3 output disable. See CF4DIS. CF2 output disable. See CF4DIS. CF1 output disable. See CF4DIS Type of energy output on the CF4 pin. Configure TERMSEL4 in the COMPMODE register to select which phases are included. 000 Total active power. 001 Total reactive power. 010 Total apparent power. 011 Fundamental active power. 100 Fundamental reactive power. 101 Fundamental apparent power. 110 Total active power. 111 Total active power. Selects type of energy output on CF3 pin. See CF4SEL. Selects type of energy output on CF2 pin. See CF4SEL. Selects type of energy output on CF1 pin. See CF4SEL. Reserved. Phases to include in CF4 pulse output. Set TERMSEL4, Bit 2 to 1 to include Phase C in the CF4 pulse output. Similarly, set TERMSEL4, Bit 1 to include Phase B, and TERMSEL4, Bit 0 for Phase A. Phases to include in CF3 pulse output. See TERMSEL4. Phases to include in CF2 pulse output. See TERMSEL4. Phases to include in CF1 pulse output. See TERMSEL4. Reserved. Use this bit to configure the IC for a 50 Hz or 60 Hz system. This setting is used in the fundamental power measurements and to set the default line period used for VRMS½, 10 cycle rms/ 12 cycle rms and resampling calculations if a zero crossing is not present. 0 50 Hz. 1 60 Hz. Set this bit to calculate the current flowing through IB from the IA and IC measurements. If this bit is set, IB = −IA − IC. Rev. A | Page 65 of 72 Reset 0x0 0x0 Access R R 0x0 R/W 0x0 0x0 0x0 0x0 R/W R/W R/W R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W ADE9000 Addr. Name 0x493 CONFIG3 0x49A ZX_LP_SEL Data Sheet Bits [6:4] Bit Name VCONSEL [3:2] VARACC [1:0] WATTACC [15:12] OC_EN [11:5] [4:2] RESERVED PEAKSEL [1:0] [15:5] [4:3] RESERVED RESERVED LP_SEL [2:1] ZX_SEL 0 RESERVED Settings Description 3-wire and 4-wire hardware configuration selection. 000 4-wire wye. 001 3-wire delta. VB' = VA − VC. 010 4-wire wye, nonBlondel compliant. VB' = −VA − VC. 011 4-wire delta, nonBlondel compliant. VB' = −VA. 100 3-wire delta. VA' = VA − VB; VB' = VA − VC; VC' = VC − VB. Total and fundamental reactive power accumulation mode for energy registers and CFx pulses. 00 Signed accumulation mode. 01 Absolute value accumulation mode. 10 Positive accumulation mode. 11 Negative accumulation mode. Total and fundamental active power accumulation mode for energy registers and CFx pulses. See VARACC. Overcurrent detection enable. OC_EN[3:0] bits can all be set to 1 simultaneously to allow overcurrent detection on all three phases and/or neutral simultaneously. Bit 12. When OC_EN[3] is set to 1, Phase A is selected for the overcurrent detection. Bit 13. When OC_EN[2] is set to 1, Phase B is selected for the overcurrent detection. Bit 14. When OC_EN[1] is set to 1, Phase C is selected for the overcurrent detection. Bit 15. When OC_EN[0] is set to 1, the neutral line is selected for the overcurrent detection. Reserved. Set this bit to select which phase(s) to monitor peak voltages and currents on. Write 1 to PEAKSEL, Bit 0 to enable Phase A peak detection. Similarly, PEAKSEL, Bit 1 enables Phase B peak detection, and PEAKSEL, Bit 2 enables Phase C peak detection. Reserved. Reserved. Selects line period measurement used for VRMS½ cycle, 10 cycle rms/12 cycle rms, and resampling. 00 APERIOD, line period measurement from Phase A voltage. 01 BPERIOD, line period measurement from Phase B voltage. 10 CPERIOD, line period measurement from Phase C voltage. 11 COM_PERIOD, line period measurement on combined signal from VA, VB, and VC. Selects the zero-crossing signal, which can be routed to the CF3/ZX output pin and used for line cycle energy accumulation. 00 ZXVA, Phase A voltage zero-crossing signal. 01 ZXVB, Phase B voltage zero-crossing signal. 10 ZXVC, Phase C voltage zero-crossing signal. 11 ZXCOMB, zero crossing on combined signal from VA, VB, and VC. Reserved. Rev. A | Page 66 of 72 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0xF R/W 0x0 0x0 R R/W 0x0 0x0 0x3 R R R/W 0x3 R/W 0x0 R Data Sheet Addr. Name 0x49D PHSIGN 0x4A0 WFB_CFG ADE9000 Bits Bit Name [15:10] RESERVED 9 SUM4SIGN 8 SUM3SIGN 7 SUM2SIGN 6 SUM1SIGN 5 CVARSIGN 4 CWSIGN 3 BVARSIGN 2 BWSIGN 1 AVARSIGN 0 AWSIGN [15:13] RESERVED 12 WF_IN_EN [11:10] RESERVED [9:8] WF_SRC [7:6] WF_MODE Settings Description Reserved. Sign of the sum of the powers included in the CF4 datapath. The CF4 energy is positive if this bit is clear and negative if this bit is set. Sign of the sum of the powers included in the CF3 datapath. The CF3 energy is positive if this bit is clear and negative if this bit is set. Sign of the sum of the powers included in the CF2 datapath. The CF2 energy is positive if this bit is clear and negative if this bit is set. Sign of the sum of the powers included in the CF1 datapath. The CF1 energy is positive if this bit is clear and negative if this bit is set. Phase C reactive power sign bit. The PWR_SIGN_ SEL bit in the EP_CFG selects whether this feature monitors total or fundamental reactive power. Phase C active power sign bit. The PWR_SIGN_SEL bit in the EP_CFG selects whether this feature monitors total or fundamental active power. Phase B reactive power sign bit. The PWR_SIGN_ SEL bit in the EP_CFG selects whether this feature monitors total or fundamental reactive power. Phase B active power sign bit. The PWR_SIGN_SEL bit in the EP_CFG selects whether this feature monitors total or fundamental active power. Phase A reactive power sign bit. The PWR_SIGN_ SEL bit in the EP_CFG selects whether this feature monitors total or fundamental reactive power. Phase A active power sign bit. The PWR_SIGN_SEL bit in the EP_CFG selects whether this feature monitors total or fundamental active power. Reserved. This setting determines whether the IN waveform samples are read out of the waveform buffer through the SPI. 0 IN waveform samples are not read out of waveform buffer through the SPI. 1 IN waveform samples are read out of waveform buffer through the SPI. Reserved. Waveform buffer source and DREADY (data ready update rate) selection. 00 Sinc4 output at 32 kSPS. 01 Reserved. 10 Sinc4 + IIR LPF output at 8 kSPS. 11 Current and voltage channel waveform samples, processed by the DSP (xI_PCF, xV_PCF) at 8 kSPS. Fixed data rate waveforms filling and trigger based modes. 00 Stop when waveform buffer is full. 01 Continuous fill—stop only on enabled trigger events. 10 Continuous filling—center capture around enabled trigger events. 11 Continuous fill—save event address of enabled trigger events. Rev. A | Page 67 of 72 Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W ADE9000 Addr. Name Data Sheet Bits 5 Bit Name WF_CAP_SEL 4 WF_CAP_EN [3:0] BURST_CHAN 0x4A2 WFB_TRG_CFG [15:11] RESERVED 10 TRIG_FORCE 9 8 7 6 5 4 3 2 1 0 0x4A3 WFB_TRG_STAT [15:12] 11 [10:0] ZXCOMB ZXVC ZXVB ZXVA ZXIC ZXIB ZXIA OI SWELL DIP WFB_LAST_PAGE RESERVED WFB_TRIG_ADDR Settings Description This bit selects whether the waveform buffer is filled with resampled data or fixed data rate data, selected in the WF_CAP_SEL bits. 0 Resampled data. 1 Fixed data rate data. When this bit is set, a waveform capture is started. 0 The waveform capture is disabled. The waveform buffer contents are maintained. 1 The waveform capture is started, according to the type of capture in WF_CAP_SEL and the WF_SRC bits when this bit goes from a 0 to a 1. Selects which data to read out of the waveform buffer through SPI. 0000 All channels. 0001 IA and VA. 0010 IB and VB. 0011 IC and VC. 1000 IA. 1001 VA. 1010 IB. 1011 VB. 1100 IC. 1101 VC. 1110 IN if WF_IN_EN = 1 in the WFB_CFG register. 1111 Single address read (SPI burst read mode is disabled). Reserved. Set this bit to trigger an event to stop the waveform buffer filling. Zero crossing on combined signal from VA, VB, and VC. Phase C voltage zero crossing. Phase B voltage zero crossing. Phase A voltage zero crossing. Phase C current zero crossing. Phase B current zero crossing. Phase A current zero crossing. Over current event in any phase. Swell event in any phase. Dip event in any phase. These bits indicate which page of the waveform buffer was filled last, when filling with fixed rate data samples. Reserved. These bits hold the address of the last sample put into the waveform buffer after a trigger event occurred, which is within a sample or two of when the actual trigger event occurred. Rev. A | Page 68 of 72 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x0 0x0 R R Data Sheet Addr. Name 0x4AF CONFIG2 ADE9000 Bits Bit Name [15:13] RESERVED 12 UPERIOD_SEL [11:9] 0x4B0 EP_CFG HPF_CRN [8:0] RESERVED [15:13] NOLOAD_TMR [12:8] 7 RESERVED PWR_SIGN_SEL[1] 6 PWR_SIGN_SEL[0] 5 RD_RST_EN 4 EGY_LD_ACCUM [3:2] RESERVED Settings Description Reserved. Set this bit to use a user configured line period, in USER_PERIOD, for the VRMS½, 10 cycle rms/ 12 cycle rms and resampling calculation. If this bit is clear, the phase voltage line period selected by the LP_SEL[1:0] bits in the ZX_LP_SEL register is used. High-pass filter corner (f3dB) enabled when the HPFDIS bit in the CONFIG0 register is equal to zero. 000 77.39 Hz. 001 39.275 Hz. 010 19.79 Hz. 011 9.935 Hz. 100 4.98 Hz. 101 2.495 Hz. 110 1.25 Hz. 111 0.625 Hz. Reserved. This register configures how many 8 kSPS samples to evaluate the no load condition over. 000 64 samples. 001 128 samples. 010 256 samples. 011 512 samples. 100 1024 samples. 101 2048 samples. 110 4096 samples. 111 Disable no load threshold. Reserved. Selects whether the REVRPx bit follows the sign of the total or fundamental reactive power. 0 Total reactive power. 1 Fundamental reactive power. Selects whether the REVAPx bit follows the sign of the total or fundamental active power. 0 Total active power. 1 Fundamental active power. Set this bit to enable the energy register read with reset feature. If this bit is set, when one of the xWATTHR, xVAHR, xVARH, xFWATTHR, xFVAHR, and xFVARHR register is read, it is reset and begins accumulating energy from zero. If this bit is equal to zero, the internal energy register is added to the user accessible energy register. If the bit is set, the internal energy register overwrites the user accessible energy register when the EGYRDY event occurs. Reserved. Rev. A | Page 69 of 72 Reset 0x0 0x0 Access R R/W 0x6 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R ADE9000 Addr. Name Data Sheet Bits 1 0 0x4B4 CRC_FORCE [15:1] 0 0x4B5 CRC_OPTEN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x4B6 TEMP_CFG [15:4] 3 2 Bit Name EGY_TMR_MODE Settings Description This bit determines whether energy is accumulated based on the number of 8 kSPS samples or zero-crossing events configured in the EGY_TIME register. 0 Accumulate energy based on 8 kSPS samples. 1 Accumulate energy based on the zero crossing selected by the ZX_SEL bits in the ZX_LP_SEL register. EGY_PWR_EN Set this bit to enable the energy and power accumulator, when the run bit is also set. RESERVED Reserved. FORCE_CRC_UPDATE Write this bit to force the configuration register CRC calculation to start. When the calculation is complete, the CRC_DONE bit is set in the STATUS1 register. CRC_WFB_TRG_CFG_EN Set this bit to include the WFB_TRG_CFG register in the configuration register CRC calculation. CRC_WFB_PG_IRQEN Set this bit to include the WFB_PG_IRQEN register in the configuration register CRC calculation. CRC_WFB_CFG_EN Set this bit to include the WFB_CFG register in the configuration register CRC calculation. CRC_SEQ_CYC_EN Set this bit to include the SEQ_CYC register in the configuration register CRC calculation. CRC_ZXLPSEL_EN Set this bit to include the ZX_LP_SEL register in the configuration register CRC calculation. CRC_ZXTOUT_EN Set this bit to include the CRC_ZXTOUT_EN register in the configuration register CRC calculation. CRC_APP_NL_LVL_EN Set this bit to include the APP_NL_LVL register in the configuration register CRC calculation. CRC_REACT_NL_LVL_EN Set this bit to include the REACT_NL_LVL register in the configuration register CRC calculation. CRC_ACT_NL_LVL_EN Set this bit to include the ACT_NL_LVL register in the configuration register CRC calculation. CRC_SWELL_CYC_EN Set this bit to include the SWELL_CYC register in the configuration register CRC calculation. CRC_SWELL_LVL_EN Set this bit to include the SWELL_LVL register in the configuration register CRC calculation. CRC_DIP_CYC_EN Set this bit to include the DIP_CYC register in the configuration register CRC calculation. CRC_DIP_LVL_EN Set this bit to include the DIP_LVL register in the configuration register CRC calculation. CRC_EVENT_MASK_EN Set this bit to include the EVENT_MASK register in the configuration register CRC calculation. CRC_MASK1_EN Set this bit to include the MASK1 register in the configuration register CRC calculation. CRC_MASK0_EN Set this bit to include the MASK0 register in the configuration register CRC calculation. RESERVED Reserved. TEMP_START Set this bit to manually request a new temperature sensor reading. The new temperature reading is available in 1 ms, indicated by the TEMP_RDY bit in the STATUS0 register. Note that this bit is self clearing. TEMP_EN Set this bit to enable the temperature sensor. Rev. A | Page 70 of 72 Reset 0x0 Access R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R W1 0x0 R/W Data Sheet ADE9000 Addr. Name Bits [1:0] Bit Name TEMP_TIME 0x4B7 TEMP_RSLT [15:12] [11:0] [15:14] [13:12] RESERVED TEMP_RESULT RESERVED VC_GAIN 0x4B9 PGA_GAIN [11:10] VB_GAIN [9:8] VA_GAIN [7:6] IN_GAIN 0x4BA CHNL_DIS 0x4E0 VAR_DIS [5:4] [3:2] [1:0] [15:7] 6 5 4 3 2 1 0 [15:1] 0 IC_GAIN IB_GAIN IA_GAIN RESERVED VC_DISADC VB_DISADC VA_DISADC IN_DISADC IC_DISADC IB_DISADC IA_DISADC RESERVED VARDIS Settings Description Select the number of temperature readings to average. 0 1 sample. New temperature measurement every 1 ms. 1 256 samples. New temperature measurement every 256 ms. 10 512 samples. New temperature measurement every 512 ms. 11 1024 samples. New temperature measurement every 1 sec. Reserved. 12-bit temperature sensor result. Reserved. PGA gain for voltage Channel C ADC. 00 Gain = 1. 01 Gain = 2. 10 Gain = 4. 11 Gain = 4. PGA gain for Voltage Channel B ADC. See VC_GAIN. PGA gain for Voltage Channel A ADC. See VC_GAIN. PGA gain for neutral current channel ADC. See VC_GAIN. PGA gain for Current Channel C ADC. See VC_GAIN. PGA gain for Voltage Channel B ADC. See VC_GAIN. PGA gain for Current Channel A ADC. See VC_GAIN. Reserved. Set this bit to one to disable the ADC. Set this bit to one to disable the ADC. Set this bit to one to disable the ADC. Set this bit to one to disable the ADC. Set this bit to one to disable the ADC. Set this bit to one to disable the ADC. Set this bit to one to disable the ADC. Reserved. Set this bit to disable the total VAR calculation. This bit must be set before writing the run bit for proper operation. Rev. A | Page 71 of 72 Reset 0x0 Access R/W 0x0 0x0 0x0 0x0 R R R R/W 0x0 0x0 0x0 R/W R/W R/W 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R R/W ADE9000 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 31 30 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 40 1 0.50 BSC 4.70 4.60 SQ 4.50 EXPOSED PAD TOP VIEW PKG-005131/005253 0.80 0.75 0.70 END VIEW SEATING PLANE 0.45 0.40 0.35 10 11 21 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5 10-12-2016-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 73. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm × 6 mm Body and 0.75 mm Package Height (CP-40-7) Dimensions shown in millimeters ORDERING GUIDE Model1 ADE9000ACPZ ADE9000ACPZ-RL EVAL-ADE9000EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP] 40-Lead Lead Frame Chip Scale Package [LFCSP], 13” Tape and Reel Evaluation Board Z = RoHS Compliant Part. ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15210-0-6/17(A) Rev. A | Page 72 of 72 Package Option CP-40-7 CP-40-7