Data Sheet
ADES1830/ADES1831
16-Channel Multicell Battery Monitor
FEATURES
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GENERAL DESCRIPTION
Measures up to 16 battery cells in series
Maximum lifetime TME: ±1.8 mV at 3.3 V per cell for ADES1830
and ±5 mV for ADES1831 (–40°C to +105°C)
Simultaneous and continuous measurement of cell voltages
Configurable integrated low-pass filtering
Stackable architecture for high voltage battery packs
Built-in isoSPI
► 2 Mbps isolated serial communications
► Uses a single twisted pair, up to 20 meters per segment
► Low EMI susceptibility and emissions
► Bidirectional for broken wire protection
► Capacitor or transformer-coupled
Hot plug tolerant without external protection
Passive cell balancing up to 300 mA per channel with programmable PWM
Up to 9 general-purpose analog inputs or digital I/O
► Temperature or other sensor inputs
► Configurable as an I2C or SPI controller
4 μA sleep mode supply current
Provisions for bus bars
APPLICATIONS
Utility energy storage
► Commercial and Industrial energy storage
► Residential energy storage
► Backup battery systems
►
The ADES1830/ADES1831 are multicell battery stack monitors that
measures up to 16 series connected battery cells with a lifetime total measurement error (TME) of less than 2 mV for the ADES1830
and less than 5 mV for the ADES1831 over the full temperature
range. The measurement input range of −2 V to +5.5 V makes the
ADES1830/ADES1831 suitable for most battery chemistries and
allows measurement of voltages across bus bars. Provisions are
made for bypassing bus bars without dedicating any measurement
channels.
All cells can be measured simultaneously and redundantly with
two individual analog-to-digital converters (ADCs). The continuously
operating ADCs with a high sampling rate of 4.096 MHz allow
reduced external analog filtering and aliasing free measurement
results. Higher noise reduction can be achieved by subsequent
programmable infinite impulse response (IIR) filters.
Multiple ADES1830/ADES1831 devices can be connected in series,
permitting simultaneous cell monitoring of long, high voltage battery
strings. Each ADES1830/ADES1831 has an isolated serial port
interface (isoSPI™) for high speed, RF immune, long distance communications. Multiple devices are connected in a daisy chain with
one host processor connection. This daisy chain can be operated
bidirectionally, ensuring communication integrity even in the event
of a fault along the communication path.
The ADES1830/ADES1831 can be powered from the battery stack
or an isolated supply. The ADES1830/ADES1831 include passive
balancing with individual pulse width modulation (PWM) duty cycle
control and up to 300 mA discharge current for each cell. Other
features include an on-board 5 V regulator, up to 9 general-purpose
inputs/outputs, and a sleep mode, where current consumption is
reduced to 4 µA.
Rev. A
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Data Sheet
ADES1830/ADES1831
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
General Description...............................................1
Typical Application Circuit......................................4
Functional Block Diagram......................................5
Specifications........................................................ 6
isoSPI Pulse Timing Specifications.................... 9
SPI Timing Requirements................................ 10
isoSPI Timing Specifications............................ 10
Absolute Maximum Ratings................................. 11
Thermal Resistance..........................................11
Electrostatic Discharge (ESD) Ratings ............11
ESD Caution.....................................................11
Pin Configurations and Function Descriptions.....12
Typical Performance Characteristics................... 13
Theory of Operation.............................................15
Core State Descriptions................................... 15
isoSPI State Description...................................16
Power Supply...................................................... 17
Cell Voltage Measurements.................................18
C-ADC and S-ADC Operations and
Commands..................................................... 18
Continuous or Single Shot Measurements.......19
Redundant Measurements............................... 19
Discharge During Measurements.....................19
Open Wire Switches.........................................20
Internal Digital Filtering.....................................20
GPIO and Device Parameter Measurements...... 22
AUX ADC Operation and Commands.............. 22
System Diagnostic...............................................23
Cell Measurement Diagnostic and Reporting...23
Cell Open Wire Detection.................................23
Algorithm for Cell Measurement with
Diagnostics ....................................................24
GPIO Measurement Diagnostic........................25
GPIO Open Wire Detection.............................. 25
Communication Diagnostic and Reporting....... 25
Thermal Shutdown........................................... 25
Test Mode Detection.........................................25
Sleep State Detection.......................................25
Soft Reset Command....................................... 25
Revision Code.................................................. 25
Serial ID............................................................25
Clear ADC Memory Commands.......................26
Clear Flag Command....................................... 26
Clear Overvoltage and Undervoltage
Command.......................................................27
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Cell Discharge and PWM for Discharge.............. 28
Sx Pin Muting................................................... 28
Cell Discharge with Cell Measurements and
Diagnostics ....................................................29
Watchdog and Discharge Timer.......................... 30
Discharge Timer Monitor.................................. 30
Low Power Cell Monitoring (LPCM).................... 31
LPCM Operation...............................................31
LPCM Bridgeless Timeout Monitor...................34
LPCM with Reversible isoSPI...........................35
Using the LPCM and Discharge Timer.............36
LPCM Expanded State Diagram...................... 36
LPCM Power Consumption.............................. 37
LPCM System Diagnostics...............................37
I2C/SPI Controller Using GPIOs ......................... 40
COMM Register................................................40
COMM Commands...........................................41
Timing Specifications of I2C and SPI
Controller........................................................43
Serial Interface Overview.................................... 44
4-Wire SPI Physical Layer................................44
Reversible 2-Wire isoSPI Physical Layer......... 45
Network Layer..................................................... 51
Command PEC................................................ 51
Data PEC......................................................... 51
Command Counter........................................... 51
Polling Methods................................................52
Bus Protocols................................................... 54
Commands.......................................................... 55
Read All and Snapshot Commands................. 58
Read All Commands........................................ 58
Snapshot Commands.......................................58
Retention Register Commands........................ 58
Memory Map........................................................59
Applications Information...................................... 75
Providing Power by Linear Regulator...............75
Input Filtering....................................................75
Cell Balancing ................................................. 76
Cell Depopulation............................................. 76
Bus Bar Monitoring and Bypassing.................. 77
Internal Protection............................................ 78
Current Measurement Capabilities...................78
Outline Dimensions............................................. 79
Ordering Guide.................................................79
Evaluation Board.............................................. 79
Rev. A | 2 of 79
Data Sheet
ADES1830/ADES1831
TABLE OF CONTENTS
REVISION HISTORY
10/2024—Rev. 0 to Rev. A
Changes to Figure 2........................................................................................................................................ 5
Change to Internal Digital Filtering Section....................................................................................................20
Change to Using the LPCM and Discharge Timer Section............................................................................36
Change to Figure 42...................................................................................................................................... 77
3/2024—Revision 0: Initial Version
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Rev. A | 3 of 79
Data Sheet
ADES1830/ADES1831
TYPICAL APPLICATION CIRCUIT
Figure 1. Typical Application Circuit
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Rev. A | 4 of 79
Data Sheet
ADES1830/ADES1831
FUNCTIONAL BLOCK DIAGRAM
Figure 2. Functional Block Diagram
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Rev. A | 5 of 79
Data Sheet
ADES1830/ADES1831
SPECIFICATIONS
Specifications apply over the full V+ operating voltage range and full operating junction temperature range (TJ = −40°C to +105°C), unless
otherwise noted.
Table 1. C-ADC DC Specifications
Parameter
Symbol
MEASUREMENT RESOLUTION
DIFFERENTIAL INPUT RANGE
VDIF
ADC OFFSET VOLTAGE1
ADC GAIN ERROR1
ADC UPDATE RATE
ADC TRANSITION NOISE
LIFETIME CELL TOTAL MEASUREMENT C-TME
ERROR
INPUT LEAKAGE CURRENT
DIFFERENTIAL INPUT RESISTANCE
DIFFERENTIAL INPUT RESISTANCE
DURING OPEN WIRE DETECTION
ADC SAMPLING FREQUENCY
1
RIN_ADC
Test Conditions/Comments
Min
Typ
Max
0.15
−0.1 V < (Cx to V−) < 80 V
−2
0.9
VDIF ≤ ±2.0 V
VDIF ≤ 3.3 V
VDIF ≤ 4.5 V (ADES1830)
VDIF ≤ 4.5 V (ADES1831)
VDIF ≤ 5.5 V
ADC off
ADC on
fS
+5.5
±0.1
±0.01
1
40
1.1
Unit
mV/bit
V
mV
%
kHz
μV rms
±1.5
±1.8
±2
±5
±3
±250
3
mV
mV
mV
mV
mV
nA
MΩ
kΩ
1.6
0
2.2
1.75
3.7
4.1
4.5
MHz
Min
Typ
Max
Unit
The ADC specifications are guaranteed by the total measurement error specification.
Table 2. S-ADC DC Specifications
Parameter
MEASUREMENT RESOLUTION
INPUT RANGE
ADC OFFSET VOLTAGE2
ADC GAIN ERROR2
ADC UPDATE RATE
ADC TRANSITION NOISE
S-ADC TOTAL MEASUREMENT ERROR
Symbol
Test Conditions/Comments
1.51
VDIF_S
−0.1 V < (Sx to V−) < 80 V
−0.3
110
+5.5
±0.2
±0.03
125
20
140
mV/bit
V
mV
%
Hz
μV rms
S-TME
INPUT LEAKAGE CURRENT
DIFFERENTIAL INPUT RESISTANCE
DIFFERENTIAL INPUT RESISTANCE
DURING OPEN WIRE DETECTION
GAIN DURING OPEN WIRE DETECTION
ADC SAMPLING FREQUENCY
fS
0 V ≤ VDIF_S ≤ 4.5 V
VDIF_S ≤ 5.5 V
ADC off, VDIF_S = 5.5 V
ADC on
No open wire fault
1
10
1.8
20
85
3.7
90
4.1
±7
±8
±300
2.6
mV
mV
nA
MΩ
kΩ
95
4.5
%
MHz
1
The S-ADC result registers are normalized to the weight of the C-ADC results, allowing to apply the same voltage conversion function. See the register description for
details.
2
The ADC specifications are guaranteed by the total measurement error specification.
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Rev. A | 6 of 79
Data Sheet
ADES1830/ADES1831
SPECIFICATIONS
Table 3. Auxiliary (AUX) ADC DC Specifications
Parameter
MEASUREMENT RESOLUTION
INPUT RANGE
ADC OFFSET VOLTAGE1
ADC GAIN ERROR1
ADC UPDATE RATE
ADC TRANSITION NOISE
GPIOx TOTAL MEASUREMENT
ERROR
DIAGNOSTIC MEASUREMENTS
INPUT LEAKAGE CURRENT
INPUT RESISTANCE
INPUT CURRENT DURING OPEN
WIRE DETECTION
Test Conditions/Comments
Min
GPIOx to V−
−0.3
Max
0.15
VREG
−0.2
±0.01
1
50
0.9
0 V < GPIOx to V− ≤ 3.3 V
3.3 V < GPIOx to V− ≤ 5 V
Internal temperature, T = maximum specified
temperature
VREG pin
VREF2, VRES
Digital supply voltage, VREGD
V+ to V−, V+ > 20 V
−0.1 V ≤ S1N to V− ≤ 0.1 V
AUX ADC off, GPIOx = 5 V
AUX ADC on
Pull-down current: GPIOx > 1.5 V
1.1
mV/bit
V
mV
%
kHz
μV rms
mV
mV
°C
1.5
−140
±0.1
±0.02
±0.1
±0.05
±0.02
10
2.7
−200
±0.25
±0.2
±1.6
+0.5
0.2
±250
3.5
−260
%
%
%
%
%
nA
MΩ
μA
140
3.7
200
4.1
260
4.5
μA
MHz
−1
Pull-up current: GPIOx < VREG − 1.5 V
Unit
±2.8
±4.2
±5
ADC SAMPLING FREQUENCY
1
Typ
The ADC specifications are guaranteed by the total measurement error specification.
Table 4. AUX2 ADC DC Specifications
Parameter
MEASUREMENT RESOLUTION
INPUT RANGE
ADC OFFSET VOLTAGE2
ADC GAIN ERROR2
ADC UPDATE RATE
ADC TRANSITION NOISE
GPIOx TOTAL MEASUREMENT ERROR
INPUT LEAKAGE CURRENT
INPUT RESISTANCE
ADC SAMPLING FREQUENCY
Test Conditions/Comments
Min
Typ
Max
1.51
GPIOx to V−
−0.3
110
0 V ≤ GPIOx to V− ≤ 3.3 V
3.3 V < GPIOx to V− ≤ 5 V
AUX2 ADC off, GPIOx = 5 V
AUX2 ADC on
1.5
3.7
VREG
±0.2
±0.05
125
25
10
2.7
4.1
140
±6
±8
±250
3.5
4.5
Unit
mV/bit
V
mV
%
Hz
μV rms
mV
mV
nA
MΩ
MHz
1
The AUX2 ADC result registers are normalized to the weight of the AUX ADC results, allowing to apply the same voltage conversion function. See register description for
details.
2
The ADC specifications are guaranteed by the total measurement error specification.
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Rev. A | 7 of 79
Data Sheet
ADES1830/ADES1831
SPECIFICATIONS
Table 5. Voltage Reference Specifications
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
FIRST REFERENCE VOLTAGE
FIRST REFERENCE VOLTAGE TEMPERATURE
COEFFICIENT (TC)
FIRST REFERENCE VOLTAGE HYSTERESIS
FIRST REFERENCE VOLTAGE LONG-TERM DRIFT
SECOND REFERENCE VOLTAGE
VREF1 pin, no load
VREF1 pin, no load
3
3.2
3
3.3
V
ppm/°C
OUTPUT CURRENT
SECOND REFERENCE VOLTAGE TC
SECOND REFERENCE VOLTAGE HYSTERESIS
SECOND REFERENCE VOLTAGE LONG-TERM DRIFT
VREF1 pin, no load
VREF1 pin, no load
VREF2 pin, no load
VREF2 pin, 1 kΩ load to V−
∆VREF2 < ± 2 mV
VREF2 pin, no load
VREF2 pin, no load
VREF2 pin, no load
2.994
2.994
−0.2
20
20
3
3
ppm
ppm/√kHr
V
V
mA
ppm/°C
ppm
ppm/√kHr
3.006
3.006
+5
10
100
60
Table 6. General DC Specifications
Parameter
Test Conditions/Comments
V+ SUPPLY CURRENT (See Figure 14)
Core in sleep, isoSPI in idle
Core in sleep, isoSPI in idle, VREG = 0 V, V+ = 60 V
Core in sleep, isoSPI in idle,VREG = 5 V, V+ = 60 V
Core in standby or extended balancing, V+ = 60 V
Core in REFUP or measure or discharge timer monitor (DTM) measure,
V+ = 60 V
VREG SUPPLY CURRENT (See Figure 14)
IREG (CORE, MEASURE) = IREG (CORE,
REFUP) + IREG (CORE, ADCs ON)
ADDITIONAL VREG SUPPLY CURRENT IF
isoSPI IN READY OR ACTIVE STATE AND tCLK
= 0.5 μs1
ADDITIONAL VREG SUPPLY CURRENT FROM
DISCHARGING
V+ SUPPLY VOLTAGE
VREG SUPPLY VOLTAGE
THERMAL SHUTDOWN PROCEDURE
DISCHARGE SWITCH ON RESISTANCE
DRIVE PIN OUTPUT
Output Voltage (VDRIVE)
Output Current
TEMPERATURE COEFFICIENT
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Min
Typ
Max
Unit
4
0.3
4
2
10
0.5
10
5
24
0.65
µA
µA
µA
mA
2.2
8
µA
Core in sleep, isoSPI in idle, VREG = 5 V
Core in standby
3
10
25
µA
Core in REFUP
Core in measure or DTM, additional current C-ADCs on
Core in measure, additional current S-ADCs on
Core in measure, additional current AUX ADCs on
isoSPI in idle state
2
4
3
0.4
2.3
4.5
3.9
0.55
0
3
5
4.5
0.75
mA
mA
mA
mA
mA
ISOMD = 0, ready
ISOMD = 0, active
2.6
7
3.2
8.5
3.9
11.5
mA
mA
ISOMD = 1, ready
ISOMD = 1, active write
ISOMD = 1, active read
DCT = 0 and no cell discharge enabled
3.1
7.5
12.5
3.7
9
14
0
4.4
12
18
mA
mA
mA
µA
DCT ≠ 0 and/or some cell discharges asserted
TME specifications met
10
11
4.5
130
80
5.5
SxN = 0 V (x = 1, 2, or 3), SxP = 6 V (x > 3)
0.5
40
40
5
150
1
µA
V
V
°C
Ω
TA = 25°C
ΔVDRIVE < ±100 mV
5.6
−0.2
5.7
5.8
+1
–1.6
4
V
mA
mV/°C
Rev. A | 8 of 79
Data Sheet
ADES1830/ADES1831
SPECIFICATIONS
1
The active state current is calculated from DC measurements. The active state current is the additional average supply current into VREG when there are continuous 2 MHz
communications on the isoSPI ports. Slower clock rates reduce the supply current.
Table 7. Operation Timing Specifications
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
REGULATOR START-UP TIME
WATCHDOG OR DISCHARGE TIMER
REFERENCE WAKE-UP TIME
tWAKE
tSLEEP
tREFUP
VREG generated from DRIVE pin
DCTO[3:0] = 0000
1.8
Added to the conversion time when starting from the
2.7
standby state. tREFUP = 0 when starting from other states.
tREFUP is independent of the number of channels measured
and the ADC mode.
200
2
3.5
500
2.2
4.4
µs
sec
ms
PWM DISCHARGE PERIOD
937
ms
Table 8. Digital Pin DC Specifications
Parameter
Symbol
Test Conditions/Comments
Min
DIGITAL INPUT VOLTAGE HIGH
DIGITAL INPUT VOLTAGE LOW
DIGITAL INPUT LEAKCAGE CURRENT
VIH
VIL
ILEAK(DIG)
2.3
DIGITAL OUTPUT, LOW SDO, GPIOx
VOL(SDO, GPIO)
CSB, SCK, SDI, ISOMD, GPIOx
CSB, SCK, SDI, ISOMD, GPIOx
SDI, ISOMD, GPIOx, SDO at 5 V
CSB, SCK at 5 V
CSB, SCK at 3.5 V
Sinking 4 mA
Parameter
Symbol
Test Conditions/Comments
Min
TRANSMITTER PULSE AMPLITUDE
RECEIVER THRESHOLD SETTING
LEAKAGE CURRENT ON IPx AND IMx
PINS
TRANSMITTER DRIVE CURRENT
COMMON-MODE VOLTAGE
RECEIVER INPUT RESISTANCE
VA
VRX
ILEAK(IP/IM)
VA = |VIP – VIM|, termination resistance = 50 Ω
1
240
DIFFERENTIAL WAKE-UP VOLTAGE
START-UP TIME AFTER WAKE
DETECTION
IDLE TIMEOUT DURATION
VWAKE
tREADY
Typ
Max
Unit
0.8
±1
10
1
0.3
V
V
µA
µA
µA
V
Typ
Max
Unit
1.25
300
1.6
360
10
V
mV
µA
10
mA
V
kΩ
kΩ
mV
µs
6.7
ms
Table 9. isoSPI Specifications
VCM
RIN
Idle state, VIP or VIM, 0 V to VREG
VCM set by the driver
TA = 25°C, IPx and IMx pins not driving
ISOMD = 1, ready state IPA, IMA
ISOMD = 1, ready state IPB, IMB
tDWELL ≥ 240 ns
25
3.2
35
100
400
tIDLE
4.3
5.5
ISOSPI PULSE TIMING SPECIFICATIONS
Table 10. isoSPI Pulse Timing Specifications
Parameter
CHIP SELECT
Half Pulse Width
Signal Filter
Pulse Inversion Delay
Valid Pulse Window
DATA
Half Pulse Width
Signal Filter
Pulse Inversion Delay
Valid Pulse Window
analog.com
Symbol
Test Conditions/Comments Min
Typ
Max
Unit
t½PW(CS)
tFILT(CS)
tINV(CS)
tWNDW(CS)
Transmitter
Receiver
Transmitter
Receiver
120
70
120
220
150
90
155
270
180
110
190
330
ns
ns
ns
ns
t½PW(D)
tFILT(D)
tINV(D)
tWNDW(D)
Transmitter
Receiver
Transmitter
Receiver
40
10
40
70
50
25
55
90
60
35
65
110
ns
ns
ns
ns
Rev. A | 9 of 79
Data Sheet
ADES1830/ADES1831
SPECIFICATIONS
SPI TIMING REQUIREMENTS
Table 11. SPI Timing Requirements
Symbol
1, 2
tCLK
t12
t 22
t32
t42
t52
t61, 2
t71, 2
Parameter
SCK period
SDI setup time before SCK rising edge
SDI hold time after SCK rising edge
SCK low
SCK high
CSB rising edge to CSB falling edge
SCK rising edge to CSB rising edge
CSB falling edge to SCK rising edge
Test Conditions/Comments
Min
tCLK = t3 + t4 ≥ 0.5 µs
tCLK = t3 + t4 ≥ 0.5 µs
0.5
25
100
100
100
2
0.5
0.5
Typ
Max
Unit
µs
ns
ns
ns
ns
µs
µs
µs
1
These timing specifications are dependent on the delay through the cable and include allowances for 50 ns of delay each direction. 50 ns corresponds to 10 m of Cat-5
cable (which has a velocity of propagation of 66% the speed of light). The use of longer cables requires derating these specifications by the amount of additional delay.
2
This specification applies over the full operating temperature range.
ISOSPI TIMING SPECIFICATIONS
Table 12. isoSPI Timing Specifications
Symbol
1, 2
t8
t92
t102
t111, 2
tRTN2
tDSY(CS)2
tDSY(D)2
tLAG2
t5(GOV)2
t6(GOV)2
tBLOCK2
Parameter
SCK falling edge to SDO valid
SCK rising edge to short ±1 transmit
CSB transition to long ±1 transmit
CSB rising edge to SDO rising
Data return delay
Chip select daisy-chain delay
Data daisy-chain delay
Data daisy-chain lag (vs. chip select)
Chip select high to low pulse governor
Data to chip select pulse governor
isoSPI port reversal blocking window
Test Conditions/Comments
(tDSY(D) + t½PW(D)) – (tDSY(CS) + t½PW(CS))
Min
Typ
230
265
150
100
280
0
0.54
0.69
2
185
160
330
70
0.67
0.86
Max
Unit
60
300
100
200
220
200
380
100
0.85
1.1
10
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
1
These specifications do not include rise or fall time of SDO. Although fall time (typically 5 ns due to the internal pull-down transistor) is not a concern, the rising edge
transition time (tRISE) is dependent on the pull-up resistance and load capacitance on the SDO pin. The time constant must be chosen such that SDO meets the setup time
requirements of the MCU.
2
This specification applies over the full operating temperature range.
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Rev. A | 10 of 79
Data Sheet
ADES1830/ADES1831
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 13. Absolute Maximum Ratings
Parameter
Rating
Total Supply Voltage, V+ to V−
Input Pins (Relative to V−)
Cx (x ≤ 16)
C9N
S1N, S1P, S2N
S2P, S3N, S3P
Sx (4 ≤ x ≤ 16)
IPA1, IMA1, IPB, IMB
DRIVE
All Other Pins
Voltage Between Input Pins
SxP to SxN
S2N to S1N
Cx to Cx − 1 (x = 1...8, 10...16)
C9 to C9N
Current In and Out of Pins
SxP to SxN (Discharge Switched Closed)
SxN to SxP (Discharge Switch Open)
Sx When Pulled Below V−
IPA1, IMA1, IPB, IMB
VREG
All Other Pins
Temperature
Operating Range
Junction
Storage Range
Lead (Soldering, 10 sec)
−0.3 V to +85 V
1
−0.3 V to +85 V
−0.3 V to +85 V
−0.3 V to +12 V
−0.3 V to +22 V
−0.3 V to +85 V
−15 V to +15 V
−0.3 V to +7 V
−0.3 V to +6 V
−0.3 V to +12 V
−0.3V to +12 V
−6 V to +12 V
−6 V to +12 V
350 mA
10 mA
10 mA
40 mA
30 mA
10 mA
−40°C to +105°C
150°C
−65°C to +150°C
300°C
IPA and SCK are the same pin. IMA and CSB are the same pin. The absolute
maximum rating for these pins depends on whether Port A is configured for
SPI mode (CSB and SCK) or isoSPI mode (IPA and IMA).
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
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Thermal performance is directly linked to the printed circuit board
(PCB) design and operating environment. Close attention to the
PCB thermal design is required.
Table 14. Thermal Resistance
Package Type1
θJA2, 3
θJCBOT4
θJCTOP5 Unit
CS-72-3
18.2
1.02
9.7
°K/W
1
The exposed pad must be connected to the V− plane for proper thermal
management.
2
Board layout impacts thermal characteristics, such as θJA.
3
θJA is the natural convection junction-to-ambient thermal resistance measured
in a one cubic foot sealed enclosure.
4
θJCBOT is the junction-to-case thermal resistance (bottom).
5
θJCTOP is the junction-to-case thermal resistance (top).
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.
ESD Ratings for ADES1830/ADES1831
Table 15. ESD Ratings for ADES1830/ADES1831
ESD Model
Withstand Threshold (V)
Class
HBM
CDM
±2000
±500
Corners pins: ±750
2
C2B
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Rev. A | 11 of 79
Data Sheet
ADES1830/ADES1831
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration, 72-Lead
Table 16. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2, 5, 8, 11, 14, 17, 20, 23, 27, 30,
33, 36, 39, 42, 45, 48, 50
26
V+
C16 to C1
Positive Supply Pin.
Differential Inputs for Cell Measurement ADCs.
C9N
Negative Terminal of the Ninth C-Measurement Channel. See the Bus Bar Monitoring and Bypassing
section for usage details.
Balance Inputs and Outputs. 16 P-channel metal-oxide semiconductor field effect transistors (PMOSFETs) are connected between SxP and SxN. Inputs to the S-ADCs.
3, 4, 6, 7, 9, 10, 12, 13, 15, 16,
S16P to S1P, S16N to S1N
18, 19, 21, 22, 24, 25, 28, 29, 31,
32, 34, 35, 37, 38, 40, 41, 43, 44,
46, 47, 49, 59
51, 52
IMA, IPA
51, 52, 54, 57
CSB, SCK, SDI, SDO
53
ISOMD
55, 56
58
IMB, IPB
DRIVE
60
61
V−
VREF2
62
63
64 to 72
VREG
VREF1
GPIO9 to GPIO1
Exposed Pad
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Isolated 2-Wire Serial Interface Port A. IPA (plus) and IMA (minus) are a differential input/output pair.
4-Wire SPI. Active low chip select (CSB), serial clock (SCK), and serial data input (SDI) are digital
inputs. Serial data out (SDO) is an open-drain, N-channel metal-oxide semiconductor (NMOS) output
pin. SDO requires a 1 kΩ pull-up resistor.
Serial Interface Mode. Connecting ISOMD to VREG configures the ADES1830/ADES1831 for 2-wire
isolated interface (isoSPI) mode. Connecting ISOMD to V− configures the ADES1830/ADES1831 for
4-wire SPI mode.
Isolated 2-Wire Serial Interface Port B. IPB (plus) and IMB (minus) are a differential input/output pair.
Connect the base of an external negative positive negative (NPN) transistor to this pin. Connect the
collector to V+ and the emitter to VREG.
Negative Supply Pins. The V− pins must be shorted together, external to the IC.
Buffered Second Reference Voltage for Driving Multiple 10 kΩ Thermistors. Bypass with an external 1
μF capacitor.
5 V Regulator Input. Bypass with an external 1 μF capacitor.
ADC Reference Voltage. Bypass with an external 1 μF capacitor. No DC loads allowed.
General-Purpose Inputs/Outputs. Can be used as digital inputs or digital outputs, or as analog inputs
with a measurement range from V− to 5 V. GPIO3 to GPIO5 can be used as an I2C or SPI port.
Exposed Pad. Connect the exposed pad to V−.
Rev. A | 12 of 79
Data Sheet
ADES1830/ADES1831
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Figure 4. C-ADC Change in Measurement Error vs. Time of Operation at
125°C
Figure 7. C-ADC Gain Error Due to IR Reflow
Figure 8. S-ADC Measurement Error at 4.2 V vs. Temperature for 15 Devices
Figure 5. C-ADC Measurement Error at 4.2 V vs. Temperature for 15 Devices
Figure 6. C-ADC Measurement Error vs. Input Voltage (VIN)
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Figure 9. S-ADC Measurement Error vs. VIN
Rev. A | 13 of 79
Data Sheet
ADES1830/ADES1831
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 10. Change in VREF2 Voltage vs. Load Current
Figure 12. Discharge Switch On Resistance vs. Cell Voltage
Figure 11. Change in VDRIVE Voltage vs. Load Current
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Rev. A | 14 of 79
Data Sheet
ADES1830/ADES1831
THEORY OF OPERATION
CORE STATE DESCRIPTIONS
Figure 13. Core State Diagram
Standby State
At first power-up or after a power-on reset (POR), the device
resets and enters the standby state. The standby state allows communicating with the ADES1830/ADES1831, and cell discharge and
balancing can be enabled by writing to the PWM register group.
The reference and the ADCs are off. The watchdog timer and/or
the discharge timer is running. The DRIVE pin powers the VREG
pin to 5.2 V through an external transistor controlled by the DRIVE
pin. VREG can also be powered through an external source. In this
case, the internal regulator must be disabled to avoid contention by
floating the DRIVE pin. The IC can perform PWM discharge in the
standby state.
When a valid ADC command is received, or if the REFON bit is set
to 1 in the Configuration Register Group A, the IC pauses for tREFUP
to allow the reference to power up. Then, the IC enters either the
REFUP or measure state. Otherwise, if no valid commands are
received for tSLEEP, the IC returns to the sleep state if DCTO = 0, or
enters the extended balancing state if DCTO ≠ 0.
Sleep State
When the watchdog timer times out, the ADES1830/ADES1831
enters the sleep state with minimum power consumption. The references and ADCs are powered down. The isoSPI ports are in the
idle state. The DRIVE pin is 0 V. An internal 3 V regulator supplies
power to detect a wake-up signal and to retain 6 bytes of user
programmable data in the retention registers. All other registers are
reset to their default value. If a wake-up signal is received, the
ADES1830/ADES1831 enters the standby state.
REFUP State
REFUP state, the ADCs are off. The reference is powered up so
that the ADES1830/ADES1831 can initiate ADC conversions faster
than from the standby state.
When a valid ADC command is received, the IC moves to the
measure state to begin the conversion. Otherwise, the ADES1830/
ADES1831 returns to the standby state when the REFON bit is set
to 0. If no valid commands are received for tSLEEP, the IC either
returns to the sleep state if DCTO = 0, or enters the extended
balancing state if DCTO ≠ 0.
Measure State
When receiving a valid ADC command (ADCV, ADSV, ADAX, or
ADAX2), the ADES1830/ADES1831 enters the measure state to
perform ADC conversions. When entering this state, the reference
and ADCs are powered.
If the CONT bit in the ADC command is set to 0, the ADES1830/
ADES1831 executes a single conversion cycle according to the
ADC command, updates the corresponding result registers, and
returns to the standby state or REFUP state.
If the CONT bit in the ADC command is set to 1, the ADES1830/
ADES1831 continuously executes conversion cycles according to
the ADC command, updates the corresponding result registers
with a 1 kHz update rate, and feeds the ADC results to the corresponding IIR filter preconfigured according to the filter configuration
register (see the Internal Digital Filtering section for more details). If
a new ADCV, ADSV, ADAX, or ADAX2 command is received during
the conversions, the ongoing conversions of the concerned ADCs
stop, and new measurements start, allowing resynchronization of
multiple ADES1830/ADES1831 devices in a stack.
To reach the REFUP state, the REFON bit in Configuration Register
Group A must be set to 1 using the WRCFGA command. In the
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Rev. A | 15 of 79
Data Sheet
ADES1830/ADES1831
THEORY OF OPERATION
Extended Balancing and DTM Measure States
In the DTM measure state, the ADES1830/ADES1831 periodically
monitors cell voltages while PWM balancing and the discharge
timer are active without interacting with the host controller. The host
must configure the PWM balancing, clear all DCC bits, and set the
DTMEN bit to enable this feature.
If the watchdog timer expires and the discharge timer monitor is
enabled and not timed out, the ADES1830/ADES1831 enters the
extended balancing state in which the configured PWM discharge
continues. From this state, the ADES1830/ADES1831 transitions
every 30 sec to the DTM measure state to measure the cell voltages, compare the result to the overvoltage (OV) and undervoltage
(UV) thresholds, and update the OV and UV flags in the status
register accordingly. When the UV threshold is reached for any
cell, the ADES1830/ADES1831 discontinue the discharge of the
concerned cell. If the cell voltage recovers above the UV threshold,
the discharge of that cell resumes.
The discharge is not muted when cell measurements are performed
in the low power cell monitoring (LPCM) heartbeat mode or DTM
measure state. As a result, measurements are affected by the
voltage drop of the discharge current over the cell cable resistance. The PWM discharge happens asynchronously to the ADC
measurements. Therefore, it is not predictable if a measurement is
altered by the voltage drop. Depending on the cable resistance and
the discharge current, the intended voltage thresholds (VOV, VUV,
CMT_CUV, and CMT_COV) may not be checked accurately.
The ADES1830/ADES1831 transition to the standby state upon
reception of any valid command, or to the sleep state when the
discharge timeout (DCTO) value expires. PWM balancing continues
even when the DCTO value has not expired.
ISOSPI STATE DESCRIPTION
The ADES1830/ADES1831 has two isoSPI ports for daisy-chain
communication: Port A and Port B.
Figure 14. isoSPI State Diagram
Idle State
In the idle state, the isoSPI ports are powered down.
When isoSPI Port A or Port B receives a wake-up signal, the isoSPI
enters the ready state. This transition happens quickly (within
tREADY) if the core is in the standby state. If the core is in the sleep
state when the isoSPI receives a wake-up signal, the IC transitions
to the ready state within tWAKE.
Ready State
In the ready state, the isoSPI ports are ready for communication.
The serial interface current in this state depends on the status of
the ISOMD pin.
If there is no activity (that is, no wake-up signal) on Port A or Port B
for greater than tIDLE, the ADES1830/ADES1831 moves to the idle
state. When the serial interface is transmitting or receiving data, the
ADES1830/ADES1831 moves to the active state.
Active State
The ADES1830/ADES1831 is transmitting/receiving data using one
or both of the isoSPI ports in the active state. The serial interface consumes maximum power in this state. The supply current
increases with the clock frequency as the density of isoSPI pulses
increases.
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Rev. A | 16 of 79
Data Sheet
ADES1830/ADES1831
POWER SUPPLY
The ADES1830/ADES1831 are powered by two pins: V+ and VREG.
The V+ input requires a voltage greater than or equal to 11 V,
independent of the voltage of the cell measurement inputs pins.
V+ provides power mainly to the highly accurate Zener reference
voltage. The VREG input requires 5 V and provides power to the
remaining core circuits and the isoSPI circuitry, and to drive the
discharge switches. The VREG input can be powered through an
external transistor driven by the regulated DRIVE output pin. Alternatively, VREG can be powered by an external supply.
The power consumption varies according to the operational states.
In the sleep state, the ADES1830/ADES1831 consumes 4 µA
provided either entirely by the V+ pin or partly by the VREG pin if the
latter is powered by an external supply. The V+ pin current depends
only on the core state, whereas the VREG pin current depends on
both the core state and isoSPI state and can be divided into two
components.
IREG = IREG(Core) + IREG(isoSPI)
The isoSPI draws current only from the VREG pin. Table 17 provides
equations to approximate the isoSPI current in function of the
isoSPI state.
Table 17. Power Consumption for isoSPI Communication
isoSPI State ISOMD Logic IREG(isoSPI)
Idle
Ready
Active
0
SPI duty cycle).
► IregWr = 9 mA, active write current consumption (2 Mbps, 100%
►
IREG (Core, Measure) = IREG (Core, REFUP) + IREG (Core, ADCs
on)
►
The Specifications section provides an overview of the power
consumption in measure state, dependent on the number of ADCs
used.
►
►
SPI duty cycle).
IregRdy = 3.7 mA, isoSPI ready state current consumption (when
not communicating and tIDLE not elapsed).
duty = 0.8, SPI communication duty cycle, assuming worst case
80%.
wrRatio = 0.3, assuming 30% of commands are write commands
(for example, WRCFGA, WRCFGB, WRPWM....).
IREG(isoSPI) can be estimated as
In a typical example, IREG(Core) can be estimated as
(1)
based on the following assumptions:
►
►
►
►
►
►
►
►
►
time interval (FDTI) (all channels for diagnostics and all GPIOs
(GPIO10 is connected to GND internally and is not available as a
user accessible GPIO)).
tAUX2 = 8 ms, AUX2 conversion time
nAUX2 = 10, number of AUX2 conversions per FDTI
(all 10 GPIOs)
tFDTI = 100 ms, fault detection time interval
tSADC = 8 ms, S-ADC conversion time
nSADC = 3, number of S-ADC conversions per FDTI
IregAUX = 0.55 mA, AUX ADC current consumption (AUX ADC
and AUX2 ADC active)
IregREFUP = 2.3 mA, current consumption in REFUP state, which
is also the base current consumption
IregCADC = 4.5 mA, C-ADC current consumption (for all 16)
IregSADC = 3.9 mA, S-ADC current consumption (for all 16)
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3.7 mA
3.2 mA
Active write: IREG(isoSPI) (ready state) + 2 × t½PW(D)/
tCLK × IDRV
Active read: IREG(isoSPI) (ready state) + 4 × t½PW(D)/
tCLK × IDRV
Active write/read: IREG(isoSPI) (ready state) + 2 ×
t½PW(D)/tCLK × IDRV
As an example, with the following assumptions:
IREG(Core) is thus the sum of the power consumed in the REFUP
state and the additional current consumed by the ADCs.
► tAUX = 1 ms, AUX conversion time
► nAUX = 18, number of AUX conversions per fault detection
0 mA
► IregRd = 14 mA, active read current consumption (2 Mbps, 100%
When measuring, the current drawn depends on the number of
ADCs turned on to measure.
IREG (Core) = IregREFUP + IregCADC + nSADC × tSADC/tFDTI ×
IregSADC + (nAUX × tAUX + nAUX2 × tAUX2)/tFDTI × IregAUX ≈ 8mA
Not
applicable
1
0
1
IREG(isoSPI) = duty × (wrRatio × IregWr + 1− wrRatio ×
IregRd + 1 − duty × IregRdy≈ 11mA
(2)
Total IREG current: 8 mA + 11 mA = 19 mA.
► For the typical application using an external NPN transistor to
generate VREG, this current is taken from MODULE+, to which
V+ is also connected. The typical V+ current consumption
in the measure state is 0.5 mA. As a result, the typical
MODULE+ current consumption is < 20 mA for the assumed
isoSPI communication duty cycle.
►
Rev. A | 17 of 79
Data Sheet
ADES1830/ADES1831
CELL VOLTAGE MEASUREMENTS
C-ADC AND S-ADC OPERATIONS AND
COMMANDS
16 ADCs are dedicated to measure the 16 differential cell inputs
synchronously and are therefore called C-ADCs. C-ADCs feature
an input range of −2 V to +5.5 V and a sampling frequency of ~4
MHz, giving out 16-bit results every 1 ms with an LSB of 150 μV.
Furthermore, every 8 ms an average of the last eight conversions of
the ADC is provided.
16 additional ADCs are dedicated to measure the 16 differential
inputs (SxP and SxN) synchronously with an input range of 0 V
to 5.5 V and a sampling frequency of ~4 MHz, giving out results
every 8 ms. These S-ADCs allow redundant measurement of the
cell voltages using an independent measurement path from the
C-ADCs.
See the Memory Map section for the memory map description for
the representation of the measurement results in the respective
16-bit registers.
Two commands can trigger C-ADC and S-ADC measurements:
ADCV triggers cell voltage conversions with or without redundancy,
and ADSV triggers S-ADC conversions.
If a new ADCV or ADSV is received during the conversions, the
ongoing conversions of the concerned ADCs stop, and new measurements start, allowing resynchronization of multiple ADES1830/
ADES1831 devices in a stack. The corresponding result registers
are reset upon reception of a new ADCV or ADSV.
Table 18. C-ADC and S-ADC Commands
Command
Description
Start Cell Voltage ADC
Conversion and Poll
Status
Start S-ADC
Conversion and Poll
Status
1
CC[10:0] – Command Code
Name
INC1
10
9
8
7
6
5
4
3
2
1
0
ADCV
Yes
0
1
RD
CONT
1
1
DCP
0
RSTF
OW[1]
OW[0]
ADSV
Yes
0
0
1
CONT
1
1
DCP
1
0
OW[1]
OW[0]
INC indicates whether the command counter increments for the command.
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Rev. A | 18 of 79
Data Sheet
ADES1830/ADES1831
CELL VOLTAGE MEASUREMENTS
CONTINUOUS OR SINGLE SHOT
MEASUREMENTS
Both C-ADCs and S-ADCs can be configured to perform a single
measurement (CONT = 0) or continuous measurements (CONT =
1). In continuous mode, the result registers of the corresponding
ADCs are updated at their conversion rate of 1 ms (C-ADC) and 8
ms (S-ADC). To end continuous measurement mode of the respective ADC, send an ADCV or ADSV with CONT = 0. The addressed
ADC then performs a last single shot measurement before turning
off.
REDUNDANT MEASUREMENTS
There are two methods to obtain redundant measurements: a direct
method and an indirect method.
The direct method involves setting the redundancy bit (RD) in an
ADCV command. In this case, the C-ADCs and S-ADCs are both
triggered to provide redundancy. After 8 ms, the average results
of the C-ADCs are compared to the results of the S-ADCs. If the
results do not match within the threshold set by the CTH[2:0] in
Configuration Register A, the CSxFLT flag is set in the Status
Register Group C. A single shot measurement triggered with RD =
1 and CONT = 0 takes 8 ms. If an ADSV is issued with CONT =
0, no further comparison is performed, and the S-ADC performs a
single shot conversion and then stops.
Note that if an ADCV with RD = 1 is issued, the open wire
switches are reset (open) to ensure a proper comparison. The
Algorithm for Cell Measurement with Diagnostics section describes
a sequence of redundant measurements and open wire detection
measurements by means of the S-ADC for high functional safety
coverage.
The indirect method allows synchronizing the S-ADCs to the already running C-ADCs.
If an ADSV is issued with CONT = 1 while the C-ADCs are in
continuous mode, the S-ADCs wait the current C-ADC average of 8
conversions to finish, start conversions synchronous to the CAVG8,
and compare the CAVG8 and S-ADC results. When redundant
measurements with subsequent result comparison are started or
ongoing, the COMP bit in the status register group is set to one for
latent fault coverage.
DISCHARGE DURING MEASUREMENTS
The ADES1830/ADES1831 allow interrupting PWM discharge during measurements to acquire cell voltage without voltage drop in
cabling due to discharge current. The behavior is controlled through
the RD, DCP, and CONT bits, as described in Table 19.
Table 19. ADC Command Control Bits
Inputs
Command
RD3
DCP
CONT PWM Discharge Status1, 2
ADCV
0
1
0
0
1
1
1
0
0
0
X
0
1
0
0
X
X
1
0
1
1
X
X
0
1
0
0
X
1
1
ADSV
Stop ongoing C-ADC conversion and restart for continuous conversion of C-ADC. PWM controlled discharge remains unaffected.
PWM controlled discharge is interrupted. Stop ongoing C-ADC conversion and restart for continuous conversion of C-ADC and
S-ADC to make redundant comparison. PWM discharge remains off if no further command is sent.
PWM controlled discharge is interrupted. Stop ongoing C-ADC conversion and make single-shot conversion of C-ADC and S-ADC
for redundant comparison. PWM discharge remains off for the duration of the redundant C-ADC and S-ADC conversion (8 ms
typical).
Immediately trigger single-shot conversion of C-ADC. Operation of S-ADC and PWM controlled discharge remains unaffected.
Stop ongoing C-ADC conversion and make single-shot conversion of C-ADC (RD = 0) or C-ADC and S-ADC (RD = 1). No effect
on PWM controlled discharge.
Invalid command is ignored. Current operation remains unaffected, CC not incremented.
If C-ADC is converting continuously, the S-ADC is synchronized to the C-ADC to make continuous conversion of C-ADCs and
S-ADCs for redundant comparison. If C-ADC is not converting, only the S-ADC makes continuous conversions. The PWM
controlled discharge is stopped.
PWM controlled discharge is interrupted for single-shot conversion of S-ADC. Operation of C-ADC remains unaffected.
PWM controlled discharge continues during measurement. Single-shot conversion of S-ADC. Operation of C-ADC remains
unaffected.
Current operation remains unaffected, CC not incremented.
1
Discharge always continues if statically enabled through the DCC bits and not interrupted by other higher priority events such as WRCFGA, WRCFGB, mute, and thermal
shutdown.
2
Any ADCV interrupts the ongoing C-ADC conversions and restarts the C-ADCs. So, it is recommended to trigger redundant measurements with the ADSV command every
fault tolerant time interval (FTTI) (ADSV with DCP = 0, CONT = 1).
3
X means 0 or 1.
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Rev. A | 19 of 79
Data Sheet
ADES1830/ADES1831
CELL VOLTAGE MEASUREMENTS
OPEN WIRE SWITCHES
The ADES1830/ADES1831 feature current-limited switches at the
cell measurement inputs, as shown in Figure 2. Activating these
switches detects if the connection to the cell is broken. The open
wire switches in the corresponding measurement path are controlled by the open wire bits (OW[1:0]), as shown in Table 20.
Table 20. Open Wire Switch Control Bits
OW[1]
OW[0]
Open Wire Switches
0
0
0
1
1
0
1
1
All channels: off
Even channels on (S2 and C2, S4 and C4, …) odd
channels off (S1 and C1, S3 and C3, …)
Even channels off (S2 and C2, S4 and C4, …) odd
channels on (S1 and C1, S3 and C3, …)
All channels on
See the Cell Open Wire Detection section for more details.
INTERNAL DIGITAL FILTERING
Figure 15 depicts the overall signal processing within the
ADES1830/ADES1831. The input voltages are sampled by the SADCs and C-ADCs with a sampling frequency of roughly 4.1 MHz.
Both S-ADCs and C-ADCs are oversampling ADCs. Whereas the
C-ADCs provide a new measurement result every 1 ms, the result
of the S-ADCs is updated every 8 ms. The C-ADC measurement
results are then averaged over 8 ms and, if redundancy is required,
compared to the synchronous results of the S-ADCs.
The 16-bit results of the C-ADCs are also fed to configurable IIR
filters for further noise filtering.
Figure 15. Integrated Digital Filters
Y(n) = Y(n – 1) + (X(n) – Y(n − 1))/a
(3)
where:
X(n) represents the nth input.
Y(n) represents the nth output of the filter.
a is the filter parameter given in Table 21.
The −3 dB corner frequency can be chosen between 110 Hz and
0.625 Hz by programming the FC[2:0] bits in the Configuration
Register Group A (see Table 21).
Table 21. IIR Frequency Settings
−3 dB Corner
Frequency
FC[2]
FC[1]
FC[0]
Filter Parameter
Filter Disabled
110
45
21
10
5
1.25
0.625
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
N/A1
2
4
8
16
32
128
256
1
N/A means not applicable.
If all three bits are set to zero, no IIR filtering is applied.
The filtered results are stored in the Filtered Cell Voltage Register
Groups A through E. The IIR filters can be reset by either issuing
a clear filtered cell voltage register group (CLRFC) command or
by setting the reset filter (RSTF) bit in an ADCV command. Furthermore, the filters are reset if the filter corner frequency is changed.
To speed up the settling time, the filters are preloaded with the first
sample arriving after a reset. Note that any C-ADC result, whether
obtained in continuous mode or in single shot mode, is added to
IIR filter. Table 22 summarizes the option of digital filtering with the
ADES1830/ADES1831.
Figure 16 shows the transfer function of the C-ADC results with
an update rate of 1 kHz and the transfer function of their average
over 8 ms, which is equivalent to the transfer function of the S-ADC
and the transfer function after the additional IIR filter with the −3 dB
corner frequency set to 0.625 Hz.
The transfer function of the IIR filter is represented by
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Rev. A | 20 of 79
Data Sheet
ADES1830/ADES1831
CELL VOLTAGE MEASUREMENTS
Figure 16. Filter Transfer Functions
Table 22. Digital Filtering Options
ADC
ADC
Frequency
(fADC)
Filter Output
Rate
Filter Type
Filter Function
C-channel
4.1 MHz
1 kHz
IIR
1-pole low-pass filter
(LPF)
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4.1 MHz
Settle, Step to
0.1% of Final (sec) Specialty
110
0.010
Low frequency LPF
0.025
0.052
0.108
0.218
0.881
1.765
Low frequency LPF
Low frequency LPF
Low frequency LPF
Low frequency LPF
Low frequency LPF
Low frequency LPF
Noise filter and 50 Hz/60 Hz
Average of 8 samples
1 kHz
Finite impulse
response (FIR)
Sinc (ADC)
45
21
10
5
1.25
0.625
56
First order sinc
443
125 Hz
Sinc (ADC)
First order sinc
56
125 Hz
S-channel
−3 dB Corner
Frequency (Hz)
Fast response with good high
frequency filtering
Matches C-channel FIR
Rev. A | 21 of 79
Data Sheet
ADES1830/ADES1831
GPIO AND DEVICE PARAMETER MEASUREMENTS
= 1) or pull-down (PUP = 0) current sources are applied during an
AUX conversion (see the GPIO Open Wire Detection section for
more details).
AUX ADC OPERATION AND COMMANDS
The 9 user available GPIO inputs can be measured redundantly by
two separate unipolar ADCs, both preceded by a multiplexer with
an input range of 0 V to 5.5 V. The main AUX ADC measures the
internal supply voltages (VD and VA), a second reference (VREF2),
and the die temperature (ITEMP) beside the GPIO channels.
To prevent any settling errors, a soak time can be programmed that
delays the start of conversion after the multiplexer has been set.
The soak time is enabled by the SOAKON bit and configured by
OWRNG and OWA in the Configuration Register Group A. If open
wire detection is required by setting the OW bit, the current sources
are switched on when setting the multiplexer setting.
The ADAX command triggers AUX ADC measurements, and the
ADAX2 command triggers AUX2 measurements.
In case of an ADAX or ADAX2 command, the CHx bits select which
auxiliary input is measured, according to Table 24.
Note that the execution of an ADAX or ADAX2 command with
a long soak time can take longer than the watchdog timer to
expire. In these cases, valid commands need to be sent to prevent
the ADES1830/ADES1831 from interrupting the measurement and
going to sleep.
If all AUX inputs must be measured (CH[4:0] = 00000), the AUX
ADCs perform measurements cycling through all inputs (18 channels total) and the corresponding auxiliary registers update. Note
that only GPIOs can be measured by AUX2. Therefore, CH[4] is not
available in the ADAX2 command.
When the ADES1830/ADES1831 receives a new ADAX or ADAX2
command during a conversion, the correspondent ADC is stopped
and restarted. The corresponding result registers are not reset upon
reception of a new ADAX or ADAX2 command.
If the OW bit is set, the corresponding measurements are executed
with open wire detection, which is performed by current sources in
case of the AUX ADC. The pull-up bit decides whether pull-up (PUP
Table 23. AUX Commands
CC[10:0] – Command Code
Command Description
Name
INC1
10
9
8
7
6
5
4
3
2
1
0
Start AUX ADC Conversions and Poll
Status
Start AUX2 ADC Conversions and Poll
Status
ADAX
Yes
1
0
OW
PUP
CH[4]
0
1
CH[3]
CH[2]
CH[1]
CH[0]
ADAX2
Yes
1
0
0
0
0
0
0
CH[3]
CH[2]
CH[1]
CH[0]
1
INC indicates whether the command counter increments for the command.
Table 24. Channel Selection
Name
Function
Value
CH[4:0]
Selection for AUX Inputs, ADAX: CH[4:0], ADAX2:
CH[3:0]
CH[4]
CH[3]
CH[2]
CH[1]
CH[0]
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
…
0
0
0
0
0
1
1
1
1
0
0
1
…
0
0
0
1
1
0
0
1
1
0
1
0
…
1
0
1
0
1
0
1
0
1
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AUX Input
All
GPIO1
GPIO2
…
GPIO9
VREF2
VD
VA
ITEMP
VPV
VMV
VRES
Reserved
Rev. A | 22 of 79
Data Sheet
ADES1830/ADES1831
SYSTEM DIAGNOSTIC
CELL MEASUREMENT DIAGNOSTIC AND
REPORTING
read out by two separate SPI targets whose outputs are compared
(see the Communication Diagnostic and Reporting section).
If cell measurements with redundancy are requested by sending an
ADCV command with RD = 1, the S-ADC results vs. the C-ADC
results are compared. In case of mismatch larger than the threshold programmed in the Control Register Group C, the ADES1830/
ADES1831 sets the corresponding fault bit (CSxFLT) to 1. To avoid
latent faults, the comparators are implemented redundantly, and if
one of the comparators flags a mismatch, it is signaled by setting
CSxFLT.
CELL OPEN WIRE DETECTION
Because the ADES1830/ADES1831 measure cell voltages through
two separate redundant pin pairs, a broken input connection on the
PCB can be detected by comparing the measurements of the corresponding S-channel and C-channel. However, in the application,
the PCB is often wired to the battery by a single cable per battery
pole, as shown in Figure 17.
To ensure detection of faults in the IIR filters following the C-ADCs,
the IIR filters are implemented redundantly and their results are
Figure 17. Open Wire Detection
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Rev. A | 23 of 79
Data Sheet
ADES1830/ADES1831
SYSTEM DIAGNOSTIC
In this configuration, the break of a cable from the PCB to the
battery cells cannot be detected by comparing C-ADC and S-ADC
results because the inputs of both ADCs are still connected on the
PCB. Therefore, the ADES1830/ADES1831 feature a safety mechanism to detect open input wires by means of differential switches
with current limiting resistors between the differential inputs of each
ADC, as shown in Figure 17.
Care must be taken not to activate the differential switches of the
two neighborhood channels simultaneously. Otherwise, the resulting voltage divider between two cells can mask a break of the
common cable between these two cells. Therefore, the ADES1830/
ADES1831 activate open wire switches of odd and even channels
independently.
Activating the differential switch in a C-measurement path causes
the input voltage with intact wiring to reduce. This is due to the
resistive divider of the external filter resistor and the internal 1.75
kΩ resistance in series with the open wire switch (to about 10/12
of the cell voltage in Figure 17). This measurement coarsely diagnoses the resistance of the external filter resistor. Furthermore, the
settling of the input voltage to the new value detects the presence
and coarse value of the filter capacitor. In case of a broken wire, the
input capacitor is fully discharged by the open wire current.
Activating the differential switch in an S-measurement path causes
the input voltage with intact wiring to reduce. This is due to the
internal resistive divider of the internal 1.75 kΩ resistance and the
18 kΩ in series with the open wire switch to about 9/10 of the
cell voltage. In case of a broken wire, the input capacitor is again
discharged by the open wire current.
To detect open wires, an open wire switch in either the C-channel
or the S-channel inputs is enough. Inserting this open wire switch in
the S-ADC inputs runs open wire detection without interrupting the
cell voltage measurement by the C-ADC, therefore preserving the
integrity of the IIR filter result.
ALGORITHM FOR CELL MEASUREMENT WITH
DIAGNOSTICS
Figure 18 shows the timing of an algorithm that performs continuous uninterrupted cell measurements by means of the C-ADC,
and alternates the S-ADC between redundancy and open wire
detection.
Whereas the C-ADC measures cell voltages continuously, the
S-ADC is used sequentially to provide redundant measurement
results and to perform open wire detection on odd and even cells.
Figure 18. Cell Measurement and Diagnose Sequence
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Rev. A | 24 of 79
Data Sheet
ADES1830/ADES1831
SYSTEM DIAGNOSTIC
GPIO MEASUREMENT DIAGNOSTIC
The ADES1830/ADES1831 targets high diagnostic coverage on
temperature measurements if two negative temperature coefficient
(NTC) thermistors are connected to two separate general-purpose
inputs/outputs (GPIOs). To achieve high diagnostic coverage, the
GPIOs can be measured by two redundant measurement paths
formed by the AUX multiplexer and the AUX ADC, and the AUX2
multiplexer and AUX2 ADC. Because the temperature is a slow
varying quantity, a command to start both measurement paths
synchronously is not provided, but each ADC must be started separately by the respective command. The results of the conversion
must be compared in the host controller.
GPIO OPEN WIRE DETECTION
Setting the OW bit in the ADAX command connects current sources
with typically 200 μA to the measurement channels to detect an
open wire or diagnose the proper resistance of the connected NTC.
The PUP bit controls whether the current sources pull the pins up or
down. Results are stored in the auxiliary register groups.
The correct value of the current sources can further be verified for
latent fault coverage by measuring the voltage drop over a 2.5 kΩ
resistor.
When measuring all channels in round-robin (CH[4:0] set to 0
enables all channels), the activated current sources (OW set to 1)
are also applied to the GPIOs, including those that may be used for
the I2C/SPI controller communication (GPIO3 to GPIO5), which can
disturb the serial communication.
COMMUNICATION DIAGNOSTIC AND
REPORTING
Any command or data sent to or read from the ADES1830/
ADES1831 are protected by a cyclic redundancy check (CRC).
See the Command PEC and Data PEC sections for more details.
Furthermore, registers necessary to perform redundant measurements or read their results (for example, C-ADC and S-ADC
result registers) are addressed by redundant SPI targets inside the
ADES1830/ADES1831 to avoid a single point of failure, and their
output is bitwise compared. When a mismatch occurs, the SPIFLT
bit in Status Register Group C is set.
The ADES1830/ADES1831 can diagnose that the SPIFLT diagnostic bit is not stuck by issuing an RDSTATC command with the ERR
bit set to 1.
THERMAL SHUTDOWN
To protect the ADES1830/ADES1831 from overheating, a thermal
shutdown circuit is included inside the IC. If the temperature detected on the die rises above approximately 150°C, the thermal
shutdown circuit trips and causes a POR with the THSD bit in the
STCR1 register to 1. This turns off all discharge switches. The
THSD bit is cleared when the CLRFLAG command is sent, and the
corresponding bit is set to 1 (see the Clear Flag Command section).
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The ADES1830/ADES1831 can diagnose that the THSD diagnostic
bit is not stuck. The FLAG_D[4] bit (Bit 4 in the CFGRA1 register)
can be set to force the THSD bit to be set to 1. When FLAG_D[4]
is written, the THSD bit flips to a 1 and must be cleared using the
CLRFLAG command.
TEST MODE DETECTION
To improve diagnostic capability, the ADES1830/ADES1831 includes a TMODCHK flag in the STRC1 register that indicates
that the part has entered a factory test mode. If this bit is set,
do not trust the behavior of the device. The TMODCHK bit must
be cleared, and if it returns to 0, the device has recovered and
operation can resume.
The ADES1830/ADES1831 can diagnose that the TMODCHK diagnostic bit is not stuck. The FLAG_D[7] bit (Bit 7 in the CFGRA1
register) can be set to force the TMODCHK bit to be set to 1. When
FLAG_D[7] is written, the TMODCHK bit flips to a 1 and must be
cleared using the CLRFLAG command.
SLEEP STATE DETECTION
The ADES1830/ADES1831 includes a flag that indicates if the
device has previously power cycled or entered the sleep state, and
that the registers have reset. The SLEEP bit (RDSTATC) is useful
for the system to check that all ICs in the daisy chain are entering
the low power sleep state. This bit can also be used to verify that
the IC has not erroneously entered the sleep state during regular
operation.
SOFT RESET COMMAND
The soft reset command (SRST) quickly puts all the devices in
the daisy chain into the sleep state. The soft reset command only
needs sufficient time to propagate the command up the stack to
the next device, after which the device enters sleep. This command
achieves two functions: a quick transition to the low power state,
and the ability to reset all of the switched power digital logic.
REVISION CODE
The ADES1830/ADES1831 contains a 4-bit revision code. If software detection of the device revision is necessary, contact the
factory for details. Otherwise, the code can be ignored. However, in
all cases, the values of all bits must be used when calculating the
packet error code (PEC) on data reads.
SERIAL ID
Each ADES1830/ADES1831 is programmed at the factory with a
unique 48-bit serial ID (SID) code stored in the SID register. The
host can read the unique SID code for each device using the
RDSID command.
Rev. A | 25 of 79
Data Sheet
ADES1830/ADES1831
SYSTEM DIAGNOSTIC
this register value of 0x8000 resulting from a CLRAUX command is,
for some registers, different than their default value after power-up.
See the register description in the Memory Map section for their
default values. Clear commands are effective in the REFUP and
measure states.
CLEAR ADC MEMORY COMMANDS
The ADES1830/ADES1831 has four clear ADC commands:
CLRCELL, CLRFC, CLRAUX, and CLRSPIN. These commands
clear the registers that store all ADC conversion results.
The CLRCELL command clears Cell Voltage Register A through
Cell Voltage Register F and the averaged cell voltage registers. The
CLRFC command clears Filtered Cell Voltage Register A through
Filtered Cell Voltage Register F. The CLRSPIN command clears
S-Voltage Register A through S-Voltage Register F. All bytes in
these registers are set to 0x8000 by the respective clear command.
CLEAR FLAG COMMAND
The CLRFLAG command resets the diagnostic flags in Status
Register Group C. The CLRFLAG command requires the system to
send six additional bytes to specify which fault flag is reset. Table
25 describes the CLRFLAG format. The defined bits correspond to
the same bit positions in Status Register Group C.
The CLRAUX command clears Auxiliary Register Group A through
Auxiliary Register Group D, the Redundant Auxiliary Register
Group A through Redundant Auxiliary Register Group D, and Status
Register Group A and Status Register Group B. All bytes in these
registers are set to 0x8000 by the CLRAUX command. Note that
The diagnostic flags in the status register remain set until they are
cleared by the user, or until the ADES1830/ADES1831 enters the
sleep state.
Table 25. CLRFLAG Data Format
Register
RD/WR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CFD0
CFD1
CFD2
CFD3
CFD4
CFD5
WR
WR
WR
WR
WR
WR
CL_CS8FLT
CL_CS16FLT
CL_CS7FLT
CL_CS15FLT
CL_CS6FLT
CL_CS14FLT
CL_CS5FLT
CL_CS13FLT
CL_CS4FLT
CL_CS12FLT
CL_CS3FLT
CL_CS11FLT
CL_CS2FLT
CL_CS10FLT
CL_CS1FLT
CL_CS9FLT
CL_VAOV
CL_VDEL
CL_VAUV
CL_VDE
CL_VDOV
CL_VDUV
CL_SPIFLT
CL_CED
CL_SLEEP
CL_CMED
CL_THSD
CL_SED
CL_TMODE
CL_SMED
CL OSCCHK
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Rev. A | 26 of 79
Data Sheet
ADES1830/ADES1831
SYSTEM DIAGNOSTIC
CLEAR OVERVOLTAGE AND UNDERVOLTAGE
COMMAND
format. The defined bits correspond to the same bit positions in
Status Register Group D.
The CLOVUV command resets the overvoltage and undervoltage
flags in Status Register Group D (STATD register). The CLOVUV
command requires the system to send six additional bytes to
specify which fault flag is reset. Table 26 describes the CLOVUV
The overvoltage and undervoltage flags in the status register remain set until they are cleared by the user, or until the ADES1830/
ADES1831 enters the sleep state.
Table 26. CLOVUV Command Format
Register
STDR0
STDR1
STDR2
STDR3
STDR4
STDR5
RD/WR
WR
WR
WR
WR
WR
WR
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Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CL_C4OV
CL_C8OV
CL_C12OV
CL_C16OV
CL_C4UV
CL_C8UV
CL_C12UV
CL_C16UV
CL_C3OV
CL_C7OV
CL_C11OV
CL_C15OV
CL_C3UV
CL_C7UV
CL_C11UV
CL_C15UV
CL_C2OV
CL_C6OV
CL_C10OV
CL_C14OV
CL_C2UV
CL_C6UV
CL_C10UV
CL_C14UV
CL_C1OV
CL_C5OV
CL_C9OV
CL_C13OV
CL_C1UV
CL_C5UV
CL_C9UV
CL_C13UV
Rev. A | 27 of 79
Data Sheet
ADES1830/ADES1831
CELL DISCHARGE AND PWM FOR DISCHARGE
The ADES1830/ADES1831 includes internal balancing switches for
each of the cell monitoring channels. The balancing switch is a low
RDSOn FET that allows a peak discharge current of 300 mA. To
simplify discharge operation, a PWM function is available to allow
for a variable discharge current on every Sx pin. The PWM runs
at a period of 937 ms and the PWM duty cycle is controlled with
four bits. Due to the two dedicated SxN and SxP pins per channel,
the ADES1830/ADES1831 allows balancing also of neighboring
channels, and therefore, a duty cycle of up to 100%.
The PWM discharge functionality is possible in the standby, REFUP, extended balancing, and in the measure states while the
discharge timeout has not expired (DCTO ≠ 0). The ADES1830/
ADES1831 interrupts the PWM discharge when an S-measurement
is initiated by the ADCV or ADSV commands with DCP = 0. The
cell discharge is not muted when cell measurements are performed
in extended balancing state or in low power cell monitoring(LPCM)
mode. As a result, in these cases, measurements can be affected
by the voltage drop of the discharge current over the cell cable
resistance.
The PWM discharge happens asynchronously to the ADC measurements. Therefore, it is not predictable if a measurement is
altered by the voltage drop. Depending on the cable resistance and
the discharge current, the intended voltage thresholds (VOV, VUV,
CMT_CUV, and CMT_COV) may not be checked accurately.
Table 27 details the discharge priority.
SX PIN MUTING
All Sx pins may be simultaneously disabled by sending the mute
command and reenabled by sending the unmute command. The
mute and unmute commands do not require any subsequent
data and thus the commands propagate quickly through a stack
of ADES1830/ADES1831 devices. After the mute command is received, it takes 65 μs maximum for the internal discharge switches
to stop the discharge. The mute functionality allows the host to
quickly disable and reenable discharging without disturbing Configuration Register Group B contents. The mute status is reported in
the read-only mute bit in Configuration Register Group A.
Table 27. Discharge Priorities
Priority (7 = Highest)
Event or Feature
Behavior
7
Thermal shutdown
6
Mute
5
4
WRCFGB
DCC bits
3
ADC measurement
command
2
1
WRPWM
PWM
The final discharge control selections are gated off when thermal shutdown occurs. Also, the PWM and DCC control
bits are reset.
All discharge is disabled while the mute feature has been activated by the mute command. Note that mute is cleared
upon watchdog timeout.
DCC and PWM and ADC discharge requests are muted during a write to the Configuration Register Group B register.
If any DCC bit is asserted, the DCC configuration takes precedence over ADC or PWM discharge controls. The
DCC discharge request asserts the Sx pins if not prevented by one of the higher priority features. DCC discharge is
allowed during any ADC conversion command. DCC bits are cleared by the watchdog timeout. At that time, the device
transitions to PWM discharge if the DCTO is not 0 and has not expired to 0.
During the measurement time of an ADC conversion that measures the Cx or Sx pins, PWM discharge can be muted.
Some ADC commands allow the DCP bit to stop cell discharge during measurements (see the Discharge During
Measurements section for details). This occurs if not prevented by one of the higher priority features (above).
PWM discharge requests are muted during a write to the PWM register group.
PWM discharge is the lowest priority. When PWM is enabled, by setting any of the PWM register bits to 1, it controls
cell discharge only if not prevented by one of the higher priority features (above).
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Rev. A | 28 of 79
Data Sheet
ADES1830/ADES1831
CELL DISCHARGE AND PWM FOR DISCHARGE
Discharge is immediately restarted, S-ADC does one more
conversion, and then sleeps. C-ADC continues measuring all
the time.
► An open wire check can be done right after the redundant
measurement. In this case, only three ADSVs are required
to make redundant measurement and open wire check, as
follows:
CELL DISCHARGE WITH CELL
MEASUREMENTS AND DIAGNOSTICS
►
When the internal balancing switch between two Sx pins switches
on, the S-ADC results differ from the C-ADC measurement result
and their results cannot be compared for diagnostic purposes.
To get continuous measurement with diagnostic coverage while
discharging, the following procedure can be used.
ADSV with DCP = 0, CONT = 1, OW = 0 (redundant check)
ADSV with DCP = 0, CONT = 0, OW = 1 (even open wire
check)
► ADSV with DCP = 0, CONT = 0, OW = 2 (odd open wire
check)
► Note: discharge is enabled again automatically after the
last single shot S-ADC conversion.
►
C-ADC conversions are usually started once during initialization:
►
►
ADCV with RD = 0, DCP = 0, CONT = 1.
►
C-ADCs run in continuous mode, deliver measurement results, and feed the IIR filter. No comparison between C-ADC
and S-ADC results is performed. PWM discharge is ongoing
and is not affected.
While in continuous measurement mode, conversion results are
read, and balancing is controlled, as follows:
The timing of the redundant and open-wire measurement is as
follows:
Program desired PWM values.
► Program desired CTHx thresholds.
► Every FTTI, ADSV with DCP = 0, CONT = 1.
Redundant measurement of S-ADC and C-ADC: 8 ms to 16 ms
► Odd channels open wire check: 8 ms
► Even channels open wire check: 8 ms
S-ADCs are switched on additionally, discharge is interrupted,
and C-ADC and S-ADC results are compared.
► Synchronous C-ADC and S-ADC conversion results are available 8 ms to 16 ms after the ADSV as it takes maximum 8 ms
for the SADC to synchronize to the CADC, and an additional
fixed 8 ms for the synchronous conversions.
► After getting results: ADSV with DCP = 1, CONT = 0.
Thus, the whole redundant and open wire diagnostic takes 24
ms to 32 ms and limits the maximum discharge duty cycle. In
average, the discharge is inhibited for 0.5 × (32 ms + 24 ms) =
28 ms. Assuming an FTTI of 100 ms, the maximum discharge duty
cycle of the ADES1830/ADES1831 are limited to 72% (even if the
PWM is configured to 100%, it is limited to 72% by the diagnostic
measurements).
►
►
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►
Rev. A | 29 of 79
Data Sheet
ADES1830/ADES1831
WATCHDOG AND DISCHARGE TIMER
When there is no valid command for more than two seconds, the
watchdog timer expires. If the DCTO is zero when this occurs, the
ADES1830/ADES1831 transitions to the sleep state and resets all
register locations to their default values. If the DCTO is non-zero
when this occurs, the ADES1830/ADES1831 transitions to the
extended balancing state and resets the mute function. Only the
PWM discharge can continue in the extended balancing state and
the DCC bits must be cleared by the host controller before entering
this state. If the DCC bits are not cleared, the static discharge is
disabled during extended balancing, but enabled again upon returning to the standby state. The watchdog timer is always enabled,
and it resets after every valid command with matching command
PEC.
When the discharge timer is enabled, the discharge controls enabled in the PWM register group continue to run for the duration
programmed by the DCTO bits. To enable the discharge timer,
write the DCTO value in the Configuration Register Group B to
a non-zero value. The discharge timer can operate in two time
ranges: 0 minutes to 63 minutes and 0 hours to 16.8 hours. The
range is controlled using the DTRNG bit in the CFGBR3 register.
The bit controls whether the DCTO value uses a bit weight of 1
minute per bit or 16 minutes per bit.
The status of the discharge timer can be determined by reading
Configuration Register Group B using the RDCFGB command.
The DCTO value indicates the time left before the discharge timer
expires.
after writing a valid WRCFGB command to Configuration Register
Group B. The discharge timer may expire in the middle of some
commands.
If the discharge timer expires in the middle of the WRCFGB command, the DCC bits and mute function in Configuration Register
Group B are reset. However, at the end of the valid WRCFGB
command, the new data is copied to the configuration register. The
new data is not lost when the discharge timer fires.
If the discharge timer expires in the middle of the RDCFGB command, the DCC bits and mute function in Configuration Register
Group B reset to their default values. As a result, the readback data
from bytes CFGBR4 and CFGBR5 may be corrupted.
DISCHARGE TIMER MONITOR
When the discharge timer monitor (DTMEN) bit is set in Configuration Register Group B and the ADES1830/ADES1831 has entered
the extended balancing state, the ADES1830/ADES1831 continues
to monitor the cell voltages every 30 seconds by a single C-ADC
conversion and updates the UV flags (CxUV). The ADES1830/
ADES1831 disables the discharge of a cell if its voltage falls below
the UV threshold (VUV) configured in Configuration Register Group
B. Once the input voltage recovers and is above the UV threshold
in subsequent measurements, discharge of the concerned cell
resumes. The ADES1830/ADES1831 disables all discharges if the
DCTO time runs out.
Unlike the watchdog timer, the discharge timer does not reset when
there is a valid command. The discharge timer can only be reset
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Rev. A | 30 of 79
Data Sheet
ADES1830/ADES1831
LOW POWER CELL MONITORING (LPCM)
The ADES1830/ADES1831 has additional monitoring states, commands, and registers that enable monitoring of cell voltages and
sensors (temperature, pressure, gas, and so on) while the battery
management system (BMS) controller is asleep or inactive. In
this LPCM mode, a stack of ADES1830/ADES1831 devices can
be configured to power up periodically, perform measurements,
compare measurements to programmed thresholds, send an isoSPI
packet to the next device in the chain, and then power down. The
device at the far end of the chain controls the sampling period. If
any device in the chain detects an alert condition, that information is
relayed to the next device.
LPCM OPERATION
An LPCM chain consists of a monitor manager (MM), one or more
monitors, and a timeout monitor (TM), as shown in Figure 19.
The ADES1830/ADES1831 can be configured to perform any of
those functions, although in many systems an ADBMS6821 (single)
or ADBMS6822 (dual) isoSPI transceiver is used as the timeout
monitor.
The basic operation steps are as follows:
1. Ensure that no conversions are ongoing.
2. The BMS controller configures the LPCM options in the monitors and then sends the CMEN command to initiate the LPCM
operation. The monitors stop accepting ADC and write commands and begin LPCM operation.
3. At the programmed heartbeat measurement interval, the MM
device wakes up.
4. Cell voltages are measured by C-ADC within 1 ms (typical) and
compared to thresholds.
5. GPIOs are measured by AUX-ADC with 1 ms conversion time
and compared to thresholds.
6. The MM initiates a heartbeat message to the next device in the
chain indicating the monitoring status (see the LPCM Heartbeat
Messages section).
7. When a cell monitor receives a heartbeat message from up the
daisy chain, the following occurs:
► Cell voltages are measured and compared to thresholds.
► GPIOs are measured and compared to thresholds.
► The monitor sends a heartbeat message to the next device
in the chain indicating the monitoring status (see the LPCM
Heartbeat Messages section).
8. If the TM at the bottom of the chain receives a pass heartbeat
message before timeout, the timeout counter is reset.
9. If the TM receives a fail heartbeat message or times out, it
initiates a wake-up signal to the BMS controller or power-up
signal to a regulator.
10. The BMS controller can use a sequence of sending the CMDIS
command to end LPCM operation and resume communication
with the monitors.
Note that the interrupt of the TM asserts as an initial condition when
the LPCM feature is enabled. The LPCM feature assumes that,
until the first heartbeat message has fully propagated through the
daisy chain, there can be a fault in the system in the initial state.
Regardless of the CMC_MPER configuration, the battery monitor
configured as MM starts the first heartbeat sequence 31 ms after
the LPCM is enabled by the CMEN command. This function allows
the LPCM to quickly evaluate the daisy chain when it is enabled.
The host processor can observe this behavior and use it to qualify
its transition to an idle or low power state. The MCU expects
the LPCM interrupt to be asserted immediately after enabling the
feature and then deasserted when the first heartbeat sequence
confirms a passing condition for all battery monitor devices.
Figure 19. Basic LPCM System Configuration
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Rev. A | 31 of 79
Data Sheet
ADES1830/ADES1831
LOW POWER CELL MONITORING (LPCM)
LPCM Thresholds
After taking cell and GPIO voltage measurements, the ADES1830/
ADES1831 compares the results against programmed thresholds to
determine whether a fault condition has occurred. The thresholds
consist of the following:
►
►
►
►
►
►
Cell undervoltage (CMT-CUV)
Cell overvoltage (CMT-COV)
Cell delta voltage (CMT-CDV)
GPIO undervoltage (CMT-GUV)
GPIO overvoltage (CMT-GOV)
GPIO delta voltage (CMT-GDV)
Figure 20 shows the UV, OV, and DV comparisons.
Figure 20. UV, OV, and DV Threshold Comparisons
If a fault is detected, the relevant flags are set and the ADES1830/
ADES1831 transmits a heartbeat message that indicates the failure, as described in the LPCM Heartbeat Messages section.
The DV threshold comparison checks the current measurement
with the previous measurement of the same input. The DV threshold is tripped for either positive or negative transitions so that a
wide variety of analog and digital sensors of different output polarities can be used. Combinations of different types of sensors can
be used if their thresholds are compatible. For example, thermistors
can be used with an analog voltage threshold, which also trips by
the transition of the digital output of a gas sensor. If a threshold type
is not required in the system, the value can be set so that it cannot
trip (for example, UV = 0 V, OV = 6 V, or DV = 6 V). Additionally, cell
and GPIO inputs can be masked so that only the desired inputs are
tested against the thresholds.
LPCM Heartbeat Messages
The LPCM feature uses smart messaging between battery monitor devices to communicate the monitoring status. The heartbeat
message contains device count information about the number of
devices reporting passing conditions, as well as a field of flags
that indicate the types of failing conditions that may be detected.
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The heartbeat message is sent as a command with PEC and data
with data PEC. The usage of PEC values protects communication
against faults. As the ADES1830/ADES1831 receives the heartbeat
message, the command PEC and payload PEC must match, or
else the ADES1830/ADES1831 ignores the command, allowing this
communication fault to be detected by the timeout monitor at the
end of the stack. Table 28 shows the format of the CMHB, which
forms the heartbeat message. Table 29 and Table 30 describe
the contents of the heartbeat message data. Note that the CMHB
command is sent from the ADES1830/ADES1831 devices, not from
the microcontroller.
Unlike other communication, during LPCM operation, this heartbeat
message, consisting of the CMHB command, is initiated by the
ADES1830/ADES1831 at the end of the daisy chain (configured
as the MM) instead of being initiated by the host microprocessor.
The heartbeat message is also unique in that it is not immediately
propagated through the daisy chain. Upon receipt of the CMHB
command, each ADES1830/ADES1831 in the chain performs the
cell and auxiliary pin measurements and comparisons before regenerating the CMHB command to the next device in the chain.
These actions by the ADES1830/ADES1831 create a propagation
delay of approximately 5 ms to 15 ms, depending on the number
of masked GPIO channels per ADES1830/ADES1831 in the daisy
chain. If any of the cell or auxiliary pin measurements cause a
threshold violation, a sticky flag bit is set in the CMF0 register.
In addition to being set by exceeding the corresponding OV/UV/DC
thresholds, CMF0 is set to 0xFF in the event that any of the
following internal diagnostics (reflected in Status Register Group
C) fails during the cell or auxiliary conversions: VA_OV, VA_UV,
VD_OV, VD_UV, VDE, VDEL, SPIFLT, TMODCHK, or OSCCHK.
Issue CLRFLAG of VA_OV, VA_UV, VD_OV, VD_UV, VDE, VDEL,
SPIFLT, TMODCHK, and OSCCHK before entering LPCM to avoid
CMF0 from being set to 0xFF in case any faults are pending.
As part of the configuration, the MM is programmed with a number
equal to the number of cell monitors in the chain. The number of
cell monitors is the initial value used by the MM for the heartbeat
message count. If no threshold flag is asserted on the MM, it
sends a number equal to the number of cell monitors minus 1. If a
threshold flag is asserted, it sends a number equal to the number
of cell monitors and it asserts bits in the flag field of the heartbeat
message to indicate the types of error that are detected. (The code
used for the number of monitors is offset by 0x42 to prevent a pass
count from consisting of all 0s.)
After the MM, each cell monitor receives a count and a flag field
from the previous device. After checking the thresholds, each
monitor either decrements this number if no threshold is violated, or
makes no change to this number if a threshold is violated, and then
sends this number on to the next device. Any fault flags received
from the previous device are also included in the new heartbeat
message generated for the next device.
Rev. A | 32 of 79
Data Sheet
ADES1830/ADES1831
LOW POWER CELL MONITORING (LPCM)
Table 28. CMHB Command
8
8
8
8
8
8
8
8
CMD0
CMD1
PEC0
PEC1
HBD0
HBD1
DPEC0
DPEC1
Table 29. Heartbeat Message Data Format
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HBD0
HBD1
HB_DCNT[7]
HB_GDVP
HB_DCNT[6]
HB_GDVN
HB_DCNT[5]
HB_GOV
HB_DCNT[4]
HB_GUV
HB_DCNT[3]
HB_CDVP
HB_DCNT[2]
HB_CDVN
HB_DCNT[1]
HB_COV
HB_DCNT[0]
HB_CUV
Table 30. Cell Voltage Register Group A Bit Descriptions
Byte
Bits
Bit Name
Description
HBD0
[7:0]
HBD1
7
HB_DCNT[7] to
HB_DCNT[0]
HB_GDVP
HBD1
6
HB_GDVN
HBD1
HBD1
HBD1
5
4
3
HB_GOV
HB_GUV
HB_CDVP
HBD1
2
HB_CDVN
HBD1
HBD1
1
0
HB_COV
HB_CUV
Heartbeat message device count. The MM sets the initial value for this count based on the configured CMC_NDEV value and the
monitoring status of the MM device. Each monitor device in the chain decrements this value only if all monitoring comparisons pass.
This sticky flag bit is asserted if a GPIO delta voltage comparison is violated in the positive direction (voltage increasing) for any device.
Cleared by the CLRCMFLAG command.
This sticky flag bit is asserted if a GPIO delta voltage comparison is violated in the negative direction (voltage decreasing) for any
device. Cleared by the CLRCMFLAG command.
This sticky flag bit is asserted if a GPIO overvoltage comparison is violated for any device. Cleared by the CLRCMFLAG command.
This sticky flag bit is asserted if a GPIO undervoltage comparison is violated for any device. Cleared by the CLRCMFLAG command.
This sticky flag bit is asserted if a cell delta voltage comparison is violated in the positive direction (voltage increasing) for any device.
Cleared by the CLRCMFLAG command.
This sticky flag bit is asserted if a cell delta voltage comparison is violated in the negative direction (voltage decreasing) for any device.
Cleared by the CLRCMFLAG command.
This sticky flag bit is asserted if a cell overvoltage comparison is violated for any device. Cleared by the CLRCMFLAG command.
This sticky flag bit is asserted if a cell undervoltage comparison is violated for any device. Cleared by the CLRCMFLAG command.
Table 31. Final Pass Value for the Heartbeat Message Data
Byte
Pass Value
HBD0
HBD1
0x42
0x00
At the bottom of the chain, the TM must receive the proper heartbeat message count that indicates no failing devices and no flags
asserted. The final pass value of the heartbeat message data is
shown in Table 31. Otherwise, a fault output is asserted.
See the following examples:
►
►
►
►
►
If there are six monitors in the chain, the microcontroller writes
CMC_NDEV = 0x48 (6 devices plus offset of 0x42) before the
microcontroller goes to sleep.
If no threshold is violated at the MM, the MM sends HB_DCNT =
0x47 (CMC_NDEV – 1) to the next device.
If the second device in the chain passes its fault checks, it sends
HB_DCNT = 0x46 (decrement by 1) to the next device.
If the third device in the chain fails its fault checks, it sends
HB_DCNT = 0x46 (does not decrement) and asserts the appropriate flags in HBD1.
If the third device in the chain is the only monitor that fails, the
TM receives 1 as the cell monitor number, and asserts its fault
output.
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LPCM Interrupt Indications
The LPCM feature indicates an interrupt in the following three
conditions:
►
The interrupt asserts as an initial condition when the LPCM
feature is enabled. The LPCM feature assumes that until the first
heartbeat message has fully propagated through the daisy chain,
there can be a fault in the system in the initial state. Regardless
of the CMC_MPER configuration, the battery monitor configured
as MM starts the first heartbeat sequence 31 ms after LPCM
is enabled by the CMEN command. This allows the LPCM to
quickly evaluate the daisy chain when it is enabled. The host
processor can observe this behavior and use it to qualify its
transition to an idle or low power state. The host expects the
LPCM interrupt to be asserted immediately after enabling the
feature and then deasserted when the first heartbeat sequence
confirms a passing condition for all battery monitor devices. Each
ADES1830/ADES1831 in the daisy chain, including the MM,
first performs cell and auxiliary measurements and comparisons
before generating the heartbeat message to the next device in
the daisy chain. The propagation delay is approximately 6 ms
per ADES1830/ADES1831 in the daisy chain. So, for example,
a daisy chain of three ADES1830/ADES1831 devices waits 31
ms after CMEN to begin the heartbeat sequence and requires
an additional 18 ms to propagate the heartbeat message through
the three devices to the TM at the bottom of the chain. The host
can expect the initial interrupt condition to end approximately 49
Rev. A | 33 of 79
Data Sheet
ADES1830/ADES1831
LOW POWER CELL MONITORING (LPCM)
ms after the CMEN command for a daisy chain of three devices,
provided no thresholds are violated.
► The interrupt asserts if there is no heartbeat message for a
configurable period of time. This value can be configured by
CMC_TPER in the ADES1830/ADES1831 if the bridgeless timeout monitor feature is implemented. Otherwise, it is configured
for the TM device that is acting as the watchdog for LPCM
heartbeat messaging.
► The interrupt asserts when the heartbeat message contains an
incorrect data payload. In this case, there is no need to wait
for the configured timeout period. When the heartbeat message
payload indicates wrong number of devices or a fault flag, the
interrupt immediately asserts.
Clear CM Flag Command
The CLRCMFLAG command resets the flags in the CMF0 register
of the CMFx register group. The CLRCMFLAG command requires
the system to send two additional bytes. These two bytes must both
be set to 0xFF to reset all flags.
Because the bits in CMF0 are also set to FF if any of the
following internal diagnostics (reflected in Status Register Group
C) fails during the cell or auxiliary conversions (VA_OV, VA_UV,
VD_OV, VD_UV, VDE, VDEL, SPIFLT, TMODCHK, or OSCCHK), a
CLRFLAG command must be issued before entering LPCM to clear
CMF0.
LPCM BRIDGELESS TIMEOUT MONITOR
The ADES1830/ADES1831 can be set up as an LPCM TM when
an isoSPI bridge transceiver is not used. In that configuration,
system faults are indicated on GPIO3 and/or GPIO4. See Figure
21. The bridgeless timeout monitor settings include a timeout period
for receiving a pass heartbeat message from the stack. In this
configuration, the TM also checks its cell and GPIO inputs against
the thresholds and uses that information along with the received
heartbeat message to determine the fault status.
Note that GPIO3 and GPIO4 are pull-downs only. Therefore, external pull-up resistors are required for monitor outputs.
Figure 21. Bridgeless Timeout Monitor System Configuration
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Rev. A | 34 of 79
Data Sheet
ADES1830/ADES1831
LOW POWER CELL MONITORING (LPCM)
LPCM WITH REVERSIBLE ISOSPI
In a system that implements a reversible isoSPI, the LPCM can
be used in the forward direction, the reverse direction, or both
directions simultaneously. Operating in both directions requires that
two adjacent ADES1830/ADES1831 devices be programmed to
function as MMs, and the proper port must be specified using the
CMC_DIR configuration bit. Two TMs must be used, one on each
end. See Figure 22.
Figure 22. LPCM with Reversible isoSPI
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Rev. A | 35 of 79
Data Sheet
ADES1830/ADES1831
LOW POWER CELL MONITORING (LPCM)
USING THE LPCM AND DISCHARGE TIMER
Once the BMS controller sends the CMEN command, the monitors stop accepting some commands, such as ADC and write
commands. However, it is possible to enable the discharge timer
feature and the LPCM feature to operate simultaneously. To do
so, the BMS controller must configure the discharge timer configuration and the LPCM configuration before sending the CMEN
command. The DCC bits must be cleared before sending the
CMEN command, as described in the Extended Balancing and
DTM Measure States and Watchdog and Discharge Timer sections.
After the CMEN command, the monitors quickly transition to the
extended balancing state to begin discharge and LPCM operation.
If the discharge timer monitor feature is enabled (DTMEN = 1),
the heartbeat conversions are used to monitor the cell voltages for
discharging, rather than using the 30 second monitor period. The
VUV undervoltage threshold stored in the configuration register is
used to halt discharge if DTMEN = 1. The CMT_CUV undervoltage
threshold is used to determine whether an LPCM violation occurs.
These two undervoltage thresholds can be programmed to different
values to allow the discharge to terminate without waking the BMS
controller. The cell discharge is not muted when cell measurements
are performed in the LPCM and extended balancing modes. The
measurements are affected by the voltage drop over the cell cable
resistance due to the discharge current. The PWM discharge happens asynchronously to the ADC measurements. Therefore, it is
not predictable if a measurement is altered by the cable drop.
Depending on the cable resistance and the discharge current, the
intended voltage thresholds may not be checked accurately.
LPCM EXPANDED STATE DIAGRAM
Figure 23 shows the standard ADES1830/ADES1831 state diagram
to the left (in black), with the added ADES1830/ADES1831 states
and paths to the right (in red).
Figure 23. State Diagram with Low Power Cell Monitoring
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Rev. A | 36 of 79
Data Sheet
ADES1830/ADES1831
LOW POWER CELL MONITORING (LPCM)
LPCM POWER CONSUMPTION
During LPCM operation, the ADES1830/ADES1831 consumes a
quiescent current of about 10 μA during most of the measurement
period. The device takes about 6.7 ms to power up, take measurements, check thresholds, send the heartbeat message over isoSPI, and power down. During this burst of activity, the ADES1830/
ADES1831 uses approximately 70 µC of charge additionally. The
measurement period (MPER) can be configured to be 1 sec, 2 sec,
4 sec, 8 sec, 12 sec, 16 sec, or 32 sec. Therefore, the average
LPCM current is:
ILPCM(AVG) ≈ 70 µC/MPER + 10 µA
1 sec ≈ 80 µA 2 sec ≈ 45 µA 4 sec ≈ 28 µA 8 sec ≈ 19 µA 12 sec ≈
16 µA 16 sec ≈ 14 µA 32 sec ≈ 12 µA
LPCM SYSTEM DIAGNOSTICS
The heartbeat message allows the system microcontroller to perform diagnostics before the controller goes to sleep. The controller
can configure the monitors in such a way that one or more monitors
are expected to detect a fault condition. The controller can then
monitor the fault outputs and the heartbeat message to confirm
that the expected faults are detected. In this way, the system can
confirm proper cell voltage fault detection, GPIO fault detection,
monitoring period, timeout detection, and fault output assertion.
For the available measurement periods, the approximate average
currents are:
LPCM Configuration Example
The following is an example pseudo code for configuring a stack of ADES1830/ADES1831 devices for low power cell monitoring.
//Wake up
repeat(NUMDEV) begin
CSB low;
CSB high;
wait(500us); // 500us