ADF4002SRU-EP

Phase Detector/Frequency Synthesizer ADF4002-EP Enhanced Product FEATURES GENERAL DESCRIPTION 400 MHz bandwidth 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode 104 MHz phase frequency detector The ADF4002-EP frequency synthesizer is used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and a programmable N divider. The 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the part can be used as a standalone PFD and charge pump. ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Military temperature range: −55°C to +125°C Controlled manufacturing baseline One assembly/test site One fabrication site Product change notification Qualification data available on request Additional application and technical information can be found in the ADF4002 data sheet. APPLICATIONS Clock conditioning Clock generation IF LO generation FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP RSET CPGND REFERENCE 14-BIT R COUNTER REFIN PHASE FREQUENCY DETECTOR CHARGE PUMP CP 14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER 22 LOCK DETECT FUNCTION LATCH CURRENT SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 HIGH-Z N COUNTER LATCH SDOUT CURRENT SETTING 1 AVDD MUXOUT MUX SDOUT RFINA RFINB 13-BIT N COUNTER M3 M2 M1 CE AGND 09187-001 ADF4002-EP DGND Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADF4002-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................5 Enhanced Product Features ............................................................ 1 Thermal Characteristics ...............................................................5 Applications ....................................................................................... 1 ESD Caution...................................................................................5 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................6 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................7 Revision History ............................................................................... 2 Outline Dimensions ..........................................................................8 Specifications..................................................................................... 3 Ordering Guide .............................................................................8 Timing Characteristics ................................................................ 4 REVISION HISTORY 9/2018—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Added Enhanced Product Features Section.................................. 1 Changes to Figure 4 and Figure 5 ................................................... 7 Changes to Ordering Guide ............................................................ 9 11/2010—Revision 0: Initial Version Rev. A | Page 2 of 8 Enhanced Product ADF4002-EP SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Operating temperature range is −55°C to +125°C. Table 1. Parameter RF CHARACTERISTICS RF Input Sensitivity RF Input Frequency (RFIN) REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity1 REFIN Input Capacitance REFIN Input Current PHASE FREQUENCY DETECTOR (PFD) Phase Detector Frequency2 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage ICP vs. VCP Sink and Source Current Matching ICP vs. Temperature LOGIC INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IINH, IINL Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output High Current, IOH Output Low Voltage, VOL POWER SUPPLIES AVDD DVDD VP IDD3 (AIDD + DIDD) IP Power-Down Mode NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH)4, 5 Normalized 1/f Noise (PN1_f)4, 6 Min Typ Max Unit Test Conditions/Comments −10 5 0 400 dBm MHz For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/µs 20 0.8 300 AVDD 10 ±100 MHz V p-p pF µA For REFIN < 20 MHz, ensure SR > 50 V/µs Biased at AVDD/2 (ac coupling ensures AVDD/2 bias) 104 MHz ABP[2:1] = 00 (2.9 ns antibacklash pulse width) Programmable mA µA % kΩ nA % % % RSET = 5.1 kΩ 5 625 2.5 3.0 11 1 1.5 2 2 1.4 0.6 ±1 10 V V µA pF 100 0.4 V V µA V 1.4 DVDD − 0.4 2.7 AVDD AVDD 3.3 1 V V V mA mA µA −222 −119 dBc/Hz dBc/Hz 5.0 5.5 6.0 0.4 RSET = 5.1 kΩ TA = 25°C 0.5 V ≤ VCP ≤ (VP − 0.5 V) 0.5 V ≤ VCP ≤ (VP − 0.5 V) VCP = VP/2 Open-drain output, 1 kΩ pull-up resistor to 1.8 V CMOS output IOL = 500 µA AVDD ≤ VP ≤ 5.5 V TA = 25°C AIDD + DIDD PLL loop bandwidth = 500 kHz Measured at 10 kHz offset; normalized to 1 GHz AVDD = DVDD = 3 V. Guaranteed by design. Sample tested to ensure compliance. TA = 25°C; AVDD = DVDD = 3 V; RFIN = 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF); RF frequency and REFIN frequency in MHz. 4 All phase noise measurements were performed with a Rohde & Schwarz FSUP26 phase noise test system using the EVAL-ADF4002EBZ1 evaluation board and the ultralow noise, 100 MHz OCXO from Wenzel (Part No. 501-16843) as the PLL reference. 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value) and 10logfPFD. PNSYNTH = PNTOT − 10logfPFD − 20logN. 6 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF) and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and the flicker noise are modeled in ADIsimPLL. 1 2 3 Rev. A | Page 3 of 8 ADF4002-EP Enhanced Product TIMING CHARACTERISTICS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Operating temperature range is −55°C to +125°C. Table 2. Parameter t1 t2 t3 t4 t5 t6 1 Limit1 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min Description DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Guaranteed by design, but not production tested. Timing Diagram t3 t4 CLK t1 DATA DB23 (MSB) t2 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE 09187-022 t5 LE Figure 2. Timing Diagram Rev. A | Page 4 of 8 Enhanced Product ADF4002-EP ABSOLUTE MAXIMUM RATINGS This device is a high performance RF integrated circuit with an ESD rating of