ADF4007BCPZ

High Frequency Divider/PLL Synthesizer ADF4007 Data Sheet FEATURES GENERAL DESCRIPTION 7.5 GHz bandwidth Maximum PFD frequency of 120 MHz Divide ratios of 8, 16, 32, or 64 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems RSET control of charge pump current Hardware power-down mode The ADF4007 is a high frequency divider/PLL synthesizer that can be used in a variety of communications applications. It can operate to 7.5 GHz on the RF side and to 120 MHz at the PFD. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, and a divider/prescaler. The divider/ prescaler value can be set by two external control pins to one of four values (8, 16, 32, or 64). The reference divider is permanently set to 2, allowing an external REFIN frequency of up to 240 MHz. APPLICATIONS A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and a VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. Satellite communications Broadband wireless access CATV Instrumentation Wireless LANs FUNCTIONAL BLOCK DIAGRAM VP VDD ADF4007 CPGND REFERENCE R COUNTER ÷2 RFINA N COUNTER ÷ 8, ÷ 16, ÷ 32, ÷ 64 PHASE FREQUENCY DETECTOR CHARGE PUMP MUXOUT MUX N2 N1 GND M2 CP M1 04537-001 REFIN RFINB RSET Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved. ADF4007 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RF Input Stage ................................................................................9 Applications ....................................................................................... 1 Prescaler P ......................................................................................9 General Description ......................................................................... 1 R Counter .......................................................................................9 Functional Block Diagram .............................................................. 1 Phase Frequency Detector (PFD) and Charge Pump...............9 Revision History ............................................................................... 2 MUXOUT ................................................................................... 10 Specifications..................................................................................... 3 Applications Information .............................................................. 11 Absolute Maximum Ratings ............................................................ 4 Fixed High Frequency Local Oscillator................................... 11 ESD Caution .................................................................................. 4 Using the ADF4007 as a Divider .............................................. 12 Pin Configuration and Function Descriptions ............................. 5 PCB Design Guidelines for Chip Scale Package......................... 13 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 14 Theory of Operation ........................................................................ 9 Ordering Guide .......................................................................... 14 Reference Input Section ............................................................... 9 REVISION HISTORY 7/12—Rev. A to Rev. B Changes to Figure 2 .......................................................................... 5 Changed Applications Section to Applications Information Section .............................................................................................. 11 Updated Outline Dimensions (Changed CP-20-1 to CP-20-6)...... 14 Changes to Ordering Guide .......................................................... 14 12/09—Rev. 0 to Rev. A Added Exposed Pad Notation to Figure 2 and Table 3.................5 Changes to Table 5.............................................................................6 Changes to Ordering Guide .......................................................... 14 2/04—Revision 0: Initial Version Rev. B | Page 2 of 16 Data Sheet ADF4007 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) RF Input Frequency REFIN CHARACTERISTICS REFIN Input Sensitivity REFIN Input Frequency REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 3 MUXOUT MUXOUT Frequency3 CHARGE PUMP ICP Sink/Source Absolute Accuracy RSET Range ICP Three-State Leakage Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD 4 (AIDD + DIDD) IP NOISE CHARACTERISTICS Normalized Phase Noise Floor 5 B Version 1 Unit Test Conditions/Comments 1.0/7.0 0.5/7.5 GHz min/max GHz min/max RF input level: +5 dBm to −10 dBm RF input level: +5 dBm to −5 dBm, for lower frequencies, ensure that slew rate (SR) > 560 V/µs 0.8/VDD 20/240 10 ±100 V p-p min/max MHz min/max pF max µA max Biased at AVDD/2 2 For f < 20 MHz, use square wave (slew rate > 50 V/µs) 120 MHz max 200 MHz max CL = 15 pF 5.0 2.5 3.0/11 10 2 1.5 2 mA typ % typ kΩ typ nA max % typ % typ % typ With RSET = 5.1 kΩ With RSET = 5.1 kΩ 1.4 0.6 ±1 10 V min V max µA max pF max VDD − 0.4 0.4 V min V max 2.7/3.3 AVDD AVDD/5.5 17 2.0 V min/max −219 dBc/Hz typ V min/max mA max mA max 1 TA = 85°C 0.5 V ≤ VCP ≤ VP − 0.5 V 0.5 V ≤ VCP ≤ VP − 0.5 V VCP = VP/2 TA = 25°C IOH = 100 µA IOL = 500 µA AVDD ≤ VP ≤ 5.5 V 15 mA typ TA = 25°C Operating temperature range (B version) is −40°C to +85°C. AC coupling ensures AVDD/2 bias. See Figure 13 for typical circuit. Guaranteed by design. Characterized to ensure compliance. 4 TA = 25°C; AVDD = DVDD = 3 V; N = 64; RFIN = 7.5 GHz. 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider value) and 10logFPFD. PNSYNTH = PNTOT − 10logFPFD − 20logN. The in-band phase noise (PNTOT) is measured using the HP8562E Spectrum Analyzer from Agilent. 2 3 Rev. B | Page 3 of 16 ADF4007 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter AVDD to GND1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature CSP θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 s) Infrared (15 s) Transistor Count CMOS Bipolar 1 Rating −0.3 V to +3.6 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VP + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 122°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of