ADF4106

a FEATURES 6.0 GHz Bandwidth 2.7 V to 3.3 V Power Supply Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 3 V Systems Programmable Dual Modulus Prescaler 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents Programmable Anti-Backlash Pulsewidth 3-Wire Serial Interface Analog and Digital Lock Detect Hardware and Software Power-Down Mode APPLICATIONS Broadband Wireless Access Instrumentation Wireless LANS Base Stations For Wireless Radio PLL Frequency Synthesizer ADF4106 GENERAL DESCRIPTION The ADF4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high-frequency systems, simplifying system architecture and lowering cost. FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP CPGND RSET REFERENCE REFIN 14-BIT R COUNTER PHASE FREQUENCY DETECTOR CHARGE PUMP CP 14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER 22 FUNCTION LATCH CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 LOCK DETECT CURRENT SETTING 1 CURRENT SETTING 2 FROM FUNCTION LATCH AB COUNTER LATCH HIGH Z 19 13 AVDD MUX MUXOUT N = BP + A 13-BIT B COUNTER LOAD RFINA RFINB PRESCALER P/P + 1 LOAD 6-BIT A COUNTER SDOUT M3 M2 M1 ADF4106 6 R EV. 0 CE AGND DGND Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 (AV V 10%; ≤ CPGND = V; ADF4106–SPECIFICATIONS1 R ==5D.1Vk =; 3dBm referredAVto 50V ≤T5.5 V; AGNDT = DGND = otherwise 0noted.) ; = T to unless DD DD DD P SET A MIN MAX 1 Parameter RF CHARACTERISTICS RF Input Frequency (RFIN)3 RF Input Sensitivity Maximum Allowable Prescaler Output Frequency4 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity5 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency6 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD7 (AIDD + DIDD) IP Power-Down Mode8 (AIDD + DIDD) B Version 0.5/6.0 –10/0 300 20/250 0.8/AVDD 10 ± 100 56 BChips2 (typ) 0.5/6.0 –10/0 300 20/250 0.8/AVDD 10 ± 100 56 Unit GHz min/max dBm min/max MHz max MHz min/max V p-p min/max pF max µA max MHz max Test Conditions/Comments See Figure 3 for Input Circuit For f < 20 MHz, Use DC-Coupled Square Wave, (0 to VDD) AC-Coupled; When DC-Coupled, 0 to VDD max (CMOS Compatible) 5 625 2.5 2.7/10 1 2 1.5 2 1.4 0.6 ±1 10 1.4 1.4 100 0.4 2.7/3.3 AVDD AVDD/5.5 15 0.4 10 5 625 2.5 2.7/10 1 2 1.5 2 1.4 0.6 ±1 10 1.4 1.4 100 0.4 2.7/3.3 AVDD AVDD/5.5 13 0.4 10 mA typ µA typ % typ kΩ typ nA typ % typ % typ % typ V min V max µA max pF max V min V min µA max V max V min/V max V min/V max mA max mA max µA typ Programmable, See Table V With RSET = 5.1 kΩ With RSET = 5.1 kΩ See Table V 0.5 V VCP 0.5 V VCP VCP = VP/2 VP – 0.5 V VP – 0.5 V Open Drain Output Chosen 1 kΩ Pull-up to 1.8 V CMOS Output Chosen IOL = 500 µA AVDD VP 13 mA typ TA = 25°C 5.5 V –2– REV. 0 ADF4106 Parameter NOISE CHARACTERISTICS ADF4106 Phase Noise Floor9 Phase Noise Performance10 900 MHz Output11 5800 MHz Output12 5800 MHz Output13 Spurious Signals 900 MHz Output11 5800 MHz Output12 5800 MHz Output13 B Version –174 –166 –159 –93 –74 –84 –90/–92 –65/–70 –70/–75 1 BChips2 (typ) –174 –166 –159 –93 –74 –84 –90/–92 –65/–70 –70/–75 Unit dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc typ dBc typ dBc typ Test Conditions/Comments @ 25 kHz PFD Frequency @ 200 kHz PFD Frequency @ 1 MHz PFD Frequency @ VCO Output @ 1 kHz Offset and 200 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 1 kHz Offset and 1 MHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 1 MHz/2 MHz and 1 MHz PFD Frequency NOTES 1 Operating temperature range (B Version) is –40 °C to +85°C. 2 The BChip specifications are given as typical values. 3 Use a square wave for lower frequencies, below the mimimum stated. 4 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 5 AVDD = DVDD = 3 V 6 Guaranteed by design. Sample tested to ensure compliance. 7 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RF IN = 6.0 GHz 8 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RF IN = 6.0 GHz 9 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). 10 The phase noise is measured with the EVAL-ADF4106EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 11 fREFIN = 10 MHz; f PFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz 12 fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 5800 MHz; N = 29000; Loop B/W = 20 kHz 13 fREFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; f RF = 5800 MHz; N = 5800; Loop B/W = 100 kHz Specifications subject to change without notice. TIMING CHARACTERISTICS Parameter t1 t2 t3 t4 t5 t6 (AVDD = DVDD = 3 V 10%; AVDD ≤ VP ≤ 5.5 V; AGND = DGND = CPGND = 0 V; RSET = 5.1 k ; TA = TMIN to TMAX unless otherwise noted.) Limit at TMIN to TMAX (B Version) 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min Test Conditions/Comments DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulsewidth Guaranteed by design but not production tested. t3 CLOCK t4 t1 DATA DB23 (MSB) DB22 t2 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE t5 LE Figure 1. Timing Diagram REV. 0 – 3– ADF4106 ABSOLUTE MAXIMUM RATINGS 1, 2 ORDERING GUIDE AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.3 V VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V REFIN, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C TSSOP JA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W CSP JA Thermal Impedance . . . . . . . . . . . . . . . . . . 122°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high-performance RF integrated circuit with an ESD rating of