ADF4107BCP-REEL

PLL Frequency Synthesizer ADF4107 FEATURES GENERAL DESCRIPTION 7.0 GHz bandwidth 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode The ADF4107 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. APPLICATIONS Broadband wireless access Satellite systems Instrumentation Wireless LANs Base stations for wireless radio FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP RSET CPGND REFERENCE 14-BIT R COUNTER REFIN PHASE FREQUENCY DETECTOR CHARGE PUMP CP 14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER SDOUT FUNCTION LATCH 22 FROM FUNCTION LATCH A, B COUNTER LATCH CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 HIGH Z 19 AVDD MUXOUT MUX 13-BIT B COUNTER SDOUT LOAD M3 M2 M1 6-BIT A COUNTER 03338-001 ADF4107 6 AGND CURRENT SETTING 2 LOAD PRESCALER P/P + 1 CE CURRENT SETTING 1 13 N = BP + A RFINA RFINB LOCK DETECT DGND Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved. ADF4107 TABLE OF CONTENTS Features .............................................................................................. 1 Phase Frequency Detector and Charge Pump...........................9 Applications....................................................................................... 1 MUXOUT and Lock Detect...................................................... 10 General Description ......................................................................... 1 Input Shift Register .................................................................... 10 Functional Block Diagram .............................................................. 1 Latch Summary........................................................................... 11 Revision History ............................................................................... 2 Reference Counter Latch Map.................................................. 12 Specifications..................................................................................... 3 AB Counter Latch Map ............................................................. 13 Timing Characteristics ................................................................ 4 Function Latch Map................................................................... 14 Absolute Maximum Ratings............................................................ 5 Initialization Latch Map ............................................................ 15 ESD Caution.................................................................................. 5 Function Latch............................................................................ 16 Pin Configurations and Function Descriptions ........................... 6 Initialization Latch ..................................................................... 17 Typical Performance Characteristics ............................................. 7 Applications..................................................................................... 18 Functional Description .................................................................... 9 Local Oscillator for LMDS Base Station Transmitter............ 18 Reference Input Stage................................................................... 9 Interfacing ................................................................................... 19 RF Input Stage............................................................................... 9 PCB Design Guidelines for Chip Scale Package .................... 19 Prescaler (P/P + 1)........................................................................ 9 Outline Dimensions ....................................................................... 20 A and B Counters ......................................................................... 9 Ordering Guide .......................................................................... 20 R Counter ...................................................................................... 9 REVISION HISTORY 4/07—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to REFIN Characteristics Section..................................... 3 Changes to Noise Characteristics Section..................................... 4 Changes to Absolute Maximum Ratings Section......................... 5 Changes to Figure 23...................................................................... 12 Changes to Ordering Guide .......................................................... 20 5/03—Revision 0: Initial Version Rev. A | Page 2 of 20 ADF4107 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) 3 RF Input Sensitivity Maximum Allowable Prescaler Output Frequency 4 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity 5 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 7 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD 8 (AIDD + DIDD) IP Power-Down Mode 9 (AIDD + DIDD) B Version 1 B Chips 2 (Typ) Unit Test Conditions/Comments 1.0/7.0 –5/+5 300 1.0/7.0 –5/+5 300 GHz min/max dBm min/max MHz max See Figure 18 for input circuit 20/250 0.8/VDD 10 ±100 20/250 0.8/VDD 10 ±100 MHz min/max V p-p min/max pF max μA max For f < 20 MHz, ensure slew rate >50 V/μs Biased at AVDD/2 6 104 104 MHz max ABP = 0,0 (2.9 ns antibacklash pulse width) Programmable; see Figure 25 5 625 2.5 3.0 to 11 1 2 1.5 2 5 625 2.5 3.0 to 11 1 2 1.5 2 mA typ μA typ % typ kΩ typ nA typ % typ % typ % typ With RSET = 5.1 kΩ 1.4 0.6 ±1 10 1.4 0.6 ±1 10 V min V max μA max pF max 1.4 VDD − 0.4 100 0.4 1.4 VDD − 0.4 100 0.4 V min V min μA max V max 2.7/3.3 AVDD AVDD/5.5 17 0.4 10 2.7/3.3 AVDD AVDD/5.5 15 0.4 10 V min/V max V min/V max mA max mA max μA typ Rev. A | Page 3 of 20 With RSET = 5.1 kΩ See Figure 25 0.5 V ≤ VCP ≤ VP − 0.5 V 0.5 V ≤ VCP ≤ VP − 0.5 V VCP = VP/2 Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V CMOS output chosen IOL = 500 μA AVDD ≤ VP ≤ 5.5 V 15 mA typ TA = 25°C ADF4107 Parameter NOISE CHARACTERISTICS ADF4107 Normalized Phase Noise Floor10 Phase Noise Performance11 900 MHz Output12 6400 MHz Output13 6400 MHz Output14 Spurious Signals 900 MHz Output12 6400 MHz Output13 6400 MHz Output14 B Version1 B Chips2 (Typ) Unit −219 −219 dBc/Hz typ −93 −76 −83 −93 −76 −83 dBc/Hz typ dBc/Hz typ dBc/Hz typ @ VCO output @ 1 kHz offset and 200 kHz PFD frequency @ 1 kHz offset and 200 kHz PFD frequency @ 1 kHz offset and 1 MHz PFD frequency −90/−92 −65/−70 −70/−75 −90/−92 −65/−70 −70/−75 dBc typ dBc typ dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency @ 200 kHz/400 kHz and 200 kHz PFD frequency @ 1 MHz/2 MHz and 1 MHz PFD frequency Test Conditions/Comments 1 Operating temperature range (B version) is −40°C to +85°C. The B chip specifications are given as typical values. 3 Use a square wave for lower frequencies, below the minimum stated. 4 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 5 AVDD = DVDD = 3 V. 6 AC-coupling ensures AVDD/2 bias. 7 Guaranteed by design. Sample tested to ensure compliance. 8 TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 7.0 GHz. 9 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz. 10 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value) and 10log(FPFD). PNSYNTH = PNTOT − 20logN −10logFPFD. 11 The phase noise is measured with the EVAL-ADF4107EB1 evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 12 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop BW = 20 kHz. 13 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 6400 MHz; N = 32,000; loop BW = 20 kHz. 14 fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 6400 MHz; N = 6400; loop BW = 100 kHz. 2 TIMING CHARACTERISTICS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. 1 Table 2. Limit2 (B Version) 10 10 25 25 10 20 Parameter t1 t2 t3 t4 t5 t6 2 Test Conditions/Comments DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width Guaranteed by design but not production tested. Operating temperature range (B Version) is −40°C to +85°C. t3 t4 CLOCK t1 DATA DB23 (MSB) t2 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE t5 03338-002 1 Unit ns min ns min ns min ns min ns min ns min LE Figure 2. Timing Diagram Rev. A | Page 4 of 20 ADF4107 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND 1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance LFCSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Transistor Count CMOS Bipolar 1 Rating −0.3 V to +3.6 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to Vp + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 112°C/W 30.4°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of