ADF4108

PLL Frequency Synthesizer ADF4108 FEATURES 8.0 GHz bandwidth 3.2 V to 3.6 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3.3 V systems Programmable, dual modulus prescaler 8/9, 16/17, 32/33, or 64/65 Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode Loop filter design possible with ADIsimPLL GENERAL DESCRIPTION The ADF4108 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dualmodulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. APPLICATIONS Broadband wireless access Satellite systems Instrumentation Wireless LANs Base stations for wireless radio AVDD DVDD FUNCTIONAL BLOCK DIAGRAM VP CPGND REFERENCE REFIN 14-BIT R COUNTER 14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER FUNCTION LATCH A, B COUNTER LATCH 13 13-BIT B COUNTER LOAD LOAD 6-BIT A COUNTER M3 M2 M1 SDOUT LOCK DETECT CURRENT SETTING 1 CPI3 CPI2 CPI1 CURRENT SETTING 2 CPI6 CPI5 CPI4 HIGH Z 19 AVDD MUX MUXOUT PHASE FREQUENCY DETECTOR RSET CHARGE PUMP CP 22 FROM SDOUT FUNCTION LATCH N = BP + A RFINA RFINB PRESCALER P/P + 1 ADF4108 06015-001 6 CE AGND DGND Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADF4108 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Rating ............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ........................................................................ 9 Reference Input Stage................................................................... 9 RF Input Stage............................................................................... 9 Prescaler (P/P + 1)........................................................................ 9 A and B Counters ......................................................................... 9 R Counter ...................................................................................... 9 Phase Frequency Detector and Charge Pump...........................9 MUXOUT and Lock Detect...................................................... 10 Input Shift Register .................................................................... 10 Latch Summary........................................................................... 11 Reference Counter Latch Map.................................................. 12 AB Counter Latch Map ............................................................. 13 Function Latch Map................................................................... 14 Initialization Latch Map ............................................................ 15 Function Latch............................................................................ 16 Initialization Latch ..................................................................... 17 Power Supply Considerations................................................... 17 Interfacing ....................................................................................... 18 ADuC812 Interface .................................................................... 18 ADSP-2181 Interface ................................................................. 18 PCB Design Guidelines for Chip Scale Package......................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20 REVISION HISTORY 4/06—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADF4108 SPECIFICATIONS AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) RF Input Sensitivity Maximum Allowable Prescaler Output Frequency 3 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity 4 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 6 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD (AIDD + DIDD) 7 IP Power-Down Mode (AIDD + DIDD) 8 B Version 1 1.0/8.0 −5/+5 300 325 20/250 0.8/VDD 10 ±100 104 B Chips 2 (Typ) 1.0/8.0 −5/+5 300 325 20/250 0.8/VDD 10 ±100 104 Unit GHz min/max dBm min/max MHz max MHz max MHz min/max V p-p min/max pF max μA max MHz max Programmable; see Figure 19 5 625 2.5 3.0/11 1 2 1.5 2 1.4 0.6 ±1 10 1.4 VDD − 0.4 100 0.4 3.2/3.6 AVDD AVDD/5.5 17 0.4 10 5 625 2.5 3.0/11 1 2 1.5 2 1.4 0.6 ±1 10 1.4 VDD − 0.4 100 0.4 3.2/3.6 AVDD AVDD/5.5 17 0.4 10 mA typ μA typ % typ kΩ typ nA typ % typ % typ % typ V min V max μA max pF max V min V min μA max V max V min/V max V min/V max mA max mA max μA typ AVDD ≤ VP ≤ 5.5 V 15 mA typ TA = 25°C Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V CMOS output chosen IOL = 500 μA With RSET = 5.1 kΩ With RSET = 5.1 kΩ See Figure 19 1 nA typical; TA = 25°C 0.5 V ≤ VCP ≤ VP – 0.5 V 0.5 V ≤ VCP ≤ VP – 0.5 V VCP = VP/2 Test Conditions/Comments See Figure 12 for input circuit For lower frequencies ensure slew rate (SR) > 320 V/μs P=8 P = 16 For f < 20 MHz, ensure SR > 50 V/μs Biased at AVDD/2 5 Rev. 0 | Page 3 of 20 ADF4108 Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor 9 Phase Noise Performance 10 7900 MHz Output 11 Spurious Signals 7900 MHz Output11 1 2 B Version 1 −219 −81 –61 B Chips 2 (Typ) −219 −81 –61 Unit dBc/Hz typ dBc/Hz typ dBc typ Test Conditions/Comments @ VCO output @ 1 kHz offset and 1 MHz PFD frequency @ 1 MHz offset and 1 MHz PFD frequency Operating temperature range (B version) is –40°C to +85°C. The B chip specifications are given as typical values. 3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 AVDD = DVDD = 3.3 V. 5 AC coupling ensures AVDD/2 bias. 6 Guaranteed by design. Sample tested to ensure compliance. 7 TA = 25°C; AVDD = DVDD = 3.3 V; P = 32; RFIN = 8 GHz, fPFD = 200 kHz, REFIN = 10 MHz. 8 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz. 9 This value can be used to calculate phase noise for any application. Use the formula –219 + 10 log(fPFD) + 20 logN to calculate in-band phase noise performance as seen at the VCO output. The value given is the lowest noise mode. 10 The phase noise is measured with the EVAL-ADF4108EB1 evaluation board, with the Hittite HMC506LP4 VCO. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 11 fREFIN = 10 MHz; fPFD = 1 MHz; fRF = 7900 MHz; N = 7900; loop B/W = 50 kHz, VCO = HMC506LP4, spurs are dominated by the leakage current on the tuning port of the HMC506LP4 VCO. Rev. 0 | Page 4 of 20 ADF4108 TIMING CHARACTERISTICS AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 t1 t2 t3 t4 t5 t6 1 2 Limit 2 (B Version) 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min Test Conditions/Comments DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width Guaranteed by design but not production tested. Operating temperature range (B Version) is –40°C to +85°C. t3 CLOCK t4 t1 DATA DB23 (MSB) DB22 t2 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE t5 LE 06015-002 Figure 2. Timing Diagram Rev. 0 | Page 5 of 20 ADF4108 ABSOLUTE MAXIMUM RATING TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND 1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance CSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature (60 sec) Time at Peak Temperature Transistor Count CMOS Bipolar 1 Rating –0.3 V to +3.9 V –0.3 V to +0.3 V –0.3 V to +5.8 V –0.3 V to +5.8 V –0.3 V to VDD + 0.3 V –0.3 V to VP + 0.3 V –0.3 V to VDD + 0.3 V –40°C to +85°C –65°C to +125°C 150°C 112°C/W 30.4°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of