RF PLL Frequency Synthesizers
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
FEATURES
GENERAL DESCRIPTION
ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz;
ADF4113: 4.0 GHz
2.7 V to 5.5 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler 8/9, 16/17, 32/33,
64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
The ADF4110 family of frequency synthesizers can be used to
implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. They
consist of a low noise digital PFD (phase frequency detector), a
precision charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
(P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO).
APPLICATIONS
Base stations for wireless radio (GSM, PCS, DCS, CDMA,
WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications test equipment
CATV equipment
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD
VP
DVDD
RSET
CPGND
REFERENCE
14-BIT
R COUNTER
REFIN
PHASE
FREQUENCY
DETECTOR
14
CHARGE
PUMP
CP
R COUNTER
LATCH
24-BIT
INPUT REGISTER
FUNCTION
LATCH
22
A, B COUNTER
LATCH
SDOUT
LOCK
DETECT
HIGH Z
13
AVDD
MUX
N = BP + A
RFINA
PRESCALER
P/P +1
RFINB
13-BIT
B COUNTER
LOAD
AGND
MUXOUT
SDOUT
LOAD
6-BIT
A COUNTER
6
CE
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
19
FROM
FUNCTION
LATCH
CURRENT
SETTING 1
M3
ADF4110/ADF4111
ADF4112/ADF4113
DGND
M2 M1
03496-0-001
CLK
DATA
LE
Figure 1. Functional Block Diagram
Rev. F
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ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Phase Frequency Detector (PFD) and Charge Pump............ 13
Applications ....................................................................................... 1
Muxout and Lock Detect ........................................................... 13
General Description ......................................................................... 1
Input Shift Register .................................................................... 13
Functional Block Diagram .............................................................. 1
Function Latch ............................................................................ 19
Revision History ............................................................................... 2
Initialization Latch ..................................................................... 20
Specifications..................................................................................... 3
Device Programming after Initial Power-Up ......................... 20
Timing Characteristics ..................................................................... 5
Resynchronizing the Prescaler Output .................................... 21
Absolute Maximum Ratings ............................................................ 6
Applications..................................................................................... 22
Transistor Count ........................................................................... 6
Local Oscillator for GSM Base Station Transmitter .............. 22
ESD Caution .................................................................................. 6
Using a D/A Converter to Drive the RSET Pin ......................... 23
Pin Configurations and Function Descriptions ........................... 7
Shutdown Circuit ....................................................................... 23
Typical Performance Characteristics ............................................. 8
Wideband PLL ............................................................................ 23
Circuit Description ......................................................................... 12
Direct Conversion Modulator .................................................. 25
Reference Input Section ............................................................. 12
Interfacing ................................................................................... 26
RF Input Stage ............................................................................. 12
PCB Design Guidelines for Chip Scale Package .................... 26
Prescaler (P/P + 1) ...................................................................... 12
Outline Dimensions ....................................................................... 27
A and B Counters ....................................................................... 12
Ordering Guide ............................................................................... 28
R Counter .................................................................................... 12
REVISION HISTORY
1/13—Rev. E to Rev. F
Changes to Table 1 ............................................................................. 4
Changes to Ordering Guide ...........................................................28
3/03—Data sheet changed from Rev. A to Rev. B.
Edits to Specifications ....................................................................... 2
Updated OUTLINE DIMENSIONS ............................................. 24
8/12—Rev. D to Rev. E
Changed CP-20-1 to CP-20-6 ........................................... Universal
Updated Outline Dimensions ........................................................28
Changes to Ordering Guide ...........................................................28
1/01—Data sheet changed from Rev. 0 to Rev. A.
Changes to DC Specifications in B Version, B Chips,
Unit, and Test Conditions/Comments Columns ..................... 2
Changes to Absolute Maximum Rating ......................................... 4
Changes to FRINA Function Test ..................................................... 5
Changes to Figure 8 ........................................................................... 7
New Graph Added—TPC 22 ........................................................... 9
Change to PD Polarity Box in Table V ......................................... 15
Change to PD Polarity Box in Table VI ........................................ 16
Change to PD Polarity Paragraph ................................................. 17
Addition of New Material
(PCB Design Guidelines for Chip–Scale package) ................ 23
Replacement of CP-20 Outline with CP-20 [2] Outline ............ 24
5/12—Rev. C to Rev. D
Changes to Figure 2 ........................................................................... 5
Changes to Figure 4 and Table 4 ...................................................... 7
Updated Outline Dimensions ........................................................28
Changes to Ordering Guide ...........................................................28
3/04—Data sheet changed from Rev. B to Rev. C.
Updated Format .................................................................. Universal
Changes to Specifications ................................................................. 2
Changes to Figure 32 .......................................................................22
Changes to the Ordering Guide.....................................................28
Rev. F | Page 2 of 28
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; dBm referred to 50 Ω;
TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is as follows: B Version: −40°C to +85°C.
Table 1.
Parameter
RF CHARACTERISTICS (3 V)
RF Input Sensitivity
RF Input Frequency
ADF4110
ADF4110
ADF4111
ADF4112
ADF4112
ADF4113
Maximum Allowable Prescaler Output
Frequency 2
RF CHARACTERISTICS (5 V)
RF Input Sensitivity
RF Input Frequency
ADF4110
ADF4111
ADF4112
ADF4113
ADF4113
Maximum Allowable Prescaler Output
Frequency2
REFIN CHARACTERISTICS
REFIN Input Frequency
Reference Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR FREQUENCY 4
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP 3-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
B Version
B Chips 1
Unit
−15/0
−15/0
dBm min/max
80/550
80/550
MHz min/max
50/550
0.08/1.2
0.2/3.0
0.1/3.0
0.2/3.7
50/550
0.08/1.2
0.2/3.0
0.1/3.0
0.2/3.7
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
165
165
MHz max
−10/0
−10/0
dBm min/max
80/550
0.08/1.4
0.1/3.0
0.2/3.7
0.2/4.0
80/550
0.08/1.4
0.1/3.0
0.2/3.7
0.2/4.0
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
200
200
MHz max
5/104
0.4/AVDD
3.0/AVDD
10
±100
55
5/104
0.4/AVDD
3.0/AVDD
10
±100
55
MHz min/max
V p-p min/max
V p-p min/max
pF max
µA max
MHz max
5
625
2.5
2.7/10
1
2
1.5
2
5
625
2.5
2.7/10
1
2
1.5
2
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
0.8 × DVDD
0.2 × DVDD
±1
10
0.8 × DVDD
0.2 × DVDD
±1
10
V min
V max
µA max
pF max
DVDD – 0.4
0.4
DVDD – 0.4
0.4
V min
V max
Rev. F | Page 3 of 28
Test Conditions/Comments
See Figure 29 for input circuit.
For lower frequencies, ensure slew rate
(SR) > 30 V/µs.
Input level = −10 dBm.
For lower frequencies, ensure SR > 30 V/µs.
For lower frequencies, ensure SR > 75 V/µs.
Input level = −10 dBm.
Input level = −10 dBm. For lower frequencies,
ensure SR > 130 V/µs.
For lower frequencies, ensure SR > 50 V/µs.
For lower frequencies, ensure SR > 50 V/µs.
For lower frequencies, ensure SR > 75 V/µs.
For lower frequencies, ensure SR > 130 V/µs.
Input level = −5 dBm.
For f < 5 MHz, ensure SR > 100 V/µs.
AVDD = 3.3 V, biased at AVDD/2. See Note 3.
AVDD = 5 V, biased at AVDD/2. See Note 3.
Programmable (see Table 9).
With RSET = 4.7 kΩ.
With RSET = 4.7 kΩ.
See Table 9.
0.5 V ≤ VCP ≤ VP – 0.5 V.
0.5 V ≤ VCP ≤ VP – 0.5 V.
VCP = VP/2.
IOH = 500 µA.
IOL = 500 µA.
ADF4110/ADF4111/ADF4112/ADF4113
Parameter
POWER SUPPLIES
AVDD
DVDD
VP
IDD 5 (AIDD + DIDD)
ADF4110
ADF4111
ADF4112
ADF4113
IP
Low Power Sleep Mode
NOISE CHARACTERISTICS
ADF4113 Normalized Phase Noise Floor 6
Phase Noise Performance 7
ADF4110: 540 MHz Output 8
ADF4111: 900 MHz Output 9
ADF4112: 900 MHz Output9
ADF4113: 900 MHz Output9
ADF4111: 836 MHz Output 10
ADF4112: 1750 MHz Output 11
ADF4112: 1750 MHz Output 12
ADF4112: 1960 MHz Output 13
ADF4113: 1960 MHz Output13
ADF4113: 3100 MHz Output 14
Spurious Signals
ADF4110: 540 MHz Output9
ADF4111: 900 MHz Output9
ADF4112: 900 MHz Output9
ADF4113: 900 MHz Output9
ADF4111: 836 MHz Output10
ADF4112: 1750 MHz Output11
ADF4112: 1750 MHz Output12
ADF4112: 1960 MHz Output13
ADF4113: 1960 MHz Output13
ADF4113: 3100 MHz Output14
Data Sheet
B Version
B Chips 1
Unit
Test Conditions/Comments
2.7/5.5
AVDD
AVDD/6.0
2.7/5.5
AVDD
AVDD/6.0
V min/V max
V min/V max
AVDD ≤ VP ≤ 6.0 V. See Figure 25 and Figure 26.
5.5
5.5
7.5
11
0.5
1
4.5
4.5
6.5
8.5
0.5
1
mA max
mA max
mA max
mA max
mA max
µA typ
4.5 mA typical.
4.5 mA typical.
6.5 mA typical.
8.5 mA typical.
TA = 25°C.
−215
−215
dBc/Hz typ
−91
−87
−90
−91
−78
−86
−66
−84
−85
−86
−91
−87
−90
−91
−78
−86
−66
−84
−85
−86
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ VCO output.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 300 Hz offset and 30 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 200 Hz offset and 10 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 200 kHz PFD frequency.
@ 1 kHz offset and 1 MHz PFD frequency.
−97/−106
−98/−110
−91/−100
−100/−110
−81/−84
−88/−90
−65/−73
−80/−84
−80/−84
−80/−82
−97/−106
−98/−110
−91/−100
−100/−110
−81/−84
−88/−90
−65/−73
−80/−84
−80/−84
−82/−82
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 30 kHz/60 kHz and 30 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 10 kHz/20 kHz and 10 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 200 kHz/400 kHz and 200 kHz PFD frequency.
@ 1 MHz/2 MHz and 1 MHz PFD frequency.
The B chip specifications are given as typical values.
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3
AC coupling ensures AVDD/2 bias. See Figure 33 for a typical circuit.
4
Guaranteed by design.
5
TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz.
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN.
7
The phase noise is measured with the EV-ADF411XSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the
synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (Table 7).
8
fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop B/W = 20 kHz.
9
fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz.
10
fREFIN = 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop B/W = 3 kHz.
11
fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop B/W = 20 kHz
12
fREFIN = 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop B/W = 1 kHz.
13
fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop B/W = 20 kHz.
14
fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; loop B/W = 20 kHz.
1
2
Rev. F | Page 4 of 28
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
TIMING CHARACTERISTICS
Guaranteed by design but not production tested. AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP ≤ 6 V;
AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
Limit at TMIN to TMAX (B Version)
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
t3
Test Conditions/Comments
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
t4
CLOCK
t1
DATA
DB23 (MSB)
t2
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
LE
03496-002
t5
LE
Figure 2. Timing Diagram
Rev. F | Page 5 of 28
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted
Table 3.
Parameter
AVDD to GND 1
AVDD to DVDD
VP to GND
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFINA, RFINB to GND
RFINA to RFINB
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
LFCSP θJA Thermal Impedance
(Paddle Soldered)
LFCSP θJA Thermal Impedance
(Paddle Not Soldered)
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
1
Rating
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +7 V
−0.3 V to +5.5 V
−0.3 V to VDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to VDD + 0.3 V
±320 mV
−40°C to +85°C
−65°C to +150°C
150°C
150.4°C/W
122°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of