ADF4113HVBRUZ-RL7

High Voltage Charge Pump, PLL Synthesizer ADF4113HV Data Sheet FEATURES GENERAL DESCRIPTION High voltage charge pump (15 V) 2.7 V to 5.5 V power supply 200 MHz to 4.0 GHz frequency range Pin compatible with ADF4110, ADF4111, ADF4112, ADF4113 ADF4106, and ADF4002 synthesizers Two selectable charge pump currents Digital lock detect Power-down mode Loop filter design possible with ADIsimPLL™ The ADF4113HV is an integer-N frequency synthesizer with a high voltage charge pump (15 V). The synthesizer is designed for use with voltage controlled oscillators (VCOs) that have high tuning voltages (up to 15 V). Active loop filters are often used to achieve high tuning voltages, but the ADF4113HV charge pump can drive a high voltage VCO directly with a passive-loop filter. The ADF4113HV can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision high voltage charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). APPLICATIONS Applications using high voltage VCOs IF/RF local oscillator (LO) generation in base stations Point-to-point radio LO generation Clock for analog-to-digital and digital-to-analog converters Wireless LANs, PMR Communications test equipment A simple 3-wire interface controls all of the on-chip registers. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM AVDD VP DVDD RSET CPGND REFERENCE 14-BIT R COUNTER REFIN PHASE FREQUENCY DETECTOR CHARGE PUMP LOCK DETECT CURRENT SETTING CP 14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER FUNCTION LATCH 22 A, B COUNTER LATCH SDOUT FROM FUNCTION LATCH RFINB AVDD 13 N = BP + A RFINA HIGH Z 19 MUX MUXOUT SDOUT 13-BIT B COUNTER LOAD PRESCALER P/P + 1 M3 M2 M1 LOAD 6-BIT A COUNTER ADF4113HV CE AGND 06223-001 6 DGND Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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Technical Support www.analog.com ADF4113HV Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Prescaler (P/P + 1) ........................................................................9 Applications ....................................................................................... 1 A and B Counters ..........................................................................9 Functional Block Diagram .............................................................. 1 R Counter .......................................................................................9 Revision History ............................................................................... 2 Phase Frequency Detector (PFD) and Charge Pump............ 10 Specifications..................................................................................... 3 Muxout and Lock Detect ........................................................... 10 Timing Characteristics ................................................................ 4 Input Shift Register .................................................................... 10 Absolute Maximum Ratings ............................................................ 5 Function Latch ............................................................................ 13 Transistor Count ........................................................................... 5 Applications..................................................................................... 15 Thermal Resistance ...................................................................... 5 Using a Digitial-to-Analog Converter to Drive the RSET Pin .................................................................................. 15 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Circuit Description ........................................................................... 9 Reference Input Section ............................................................... 9 Interfacing ................................................................................... 15 PCB Design Guidelines for Chip Scale Package .................... 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17 RF Input Stage ............................................................................... 9 REVISION HISTORY 10/12—Rev. A to Rev. B Changed CP-20-1 Package to CP-20-6 Package ............. Universal Changes to Table 3 and Table 4 ....................................................... 5 Added EPAD Notation..................................................................... 6 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 9/08—Rev. 0 to Rev. A Changes to Figure 22 ...................................................................... 13 1/07—Revision 0: Initial Version Rev. B | Page 2 of 20 Data Sheet ADF4113HV SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; 13.5 V < VP ≤ 16.5 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range for B version: −40°C to +85°C. Table 1. Parameter RF CHARACTERISTICS (3 V) RF Input Sensitivity RF Input Frequency Prescaler Output Frequency 2 RF CHARACTERISTICS (5 V) RF Input Sensitivity RF Input Frequency Prescaler Output Frequency REFIN CHARACTERISTICS REFIN Input Frequency Reference Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR FREQUENCY CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD 5 (AIDD + DIDD) IP Low Power Sleep Mode NOISE CHARACTERISTICS Normalized Phase Noise Floor 6 B Version B Chips 1 Unit Test Conditions/Comments −15/0 0.2/3.7 165 −15/0 0.2/3.7 165 dBm min/max GHz min/max MHz max For lower frequencies, ensure SR > 130 V/μs −10/0 0.2/3.7 0.2/4.0 200 −10/0 0.2/3.7 0.2/4.0 200 dBm min/max GHz min/max GHz min/max MHz max For lower frequencies, ensure SR > 130 V/µs Input level = −5 dBm 5/150 0.4/AVDD 1.0/AVDD 10 ±100 5 5/150 0.4/AVDD 1.0/AVDD 10 ±100 5 MHz min/max V p-p min/max V p-p min/max pF max µA max MHz max 640 80 2.5 3.9/10 5 3 1.5 2 640 80 2.5 3.9/10 5 3 1.5 2 μA typ µA typ % typ kΩ typ nA max % typ % typ % typ 0.8 × DVDD 0.2 × DVDD ±1 10 0.8 × DVDD 0.2 × DVDD ±1 10 V min V max µA max pF max DVDD − 0.4 0.4 DVDD − 0.4 0.4 V min V max 2.7/5.5 AVDD 13.5/16.5 16 0.25 1 2.7/5.5 AVDD 13.5/16.5 11 0.25 1 V min/V max V min/V max mA max mA max µA typ −212 −212 dBc/Hz typ For f < 5 MHz, ensure SR > 100 V/µs AVDD = 3.3 V, biased at AVDD/2 3 For f ≥ 10 MHz, AVDD = 5 V, biased at AVDD/23, 4 RSET = 4.7 kΩ 1 1 V ≤ VCP ≤ VP – 1 V 1 V ≤ VCP ≤ VP – 1 V VCP = VP/2 IOH = 500 µA IOL = 500 µA 11 mA typical TA = 25°C The B chip specifications are given as typical values. This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 3 AC coupling ensures AVDD/2 bias. 4 Guaranteed by characterization. 5 TA = 25oC; AVDD = DVDD = 5.5 V; P = 16; RFIN = 900 MHz. 6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider value) and 10logfPFD: PNSYNTH = PNTOT − 10logfPFD − 20logN. 2 Rev. B | Page 3 of 20 ADF4113HV Data Sheet TIMING CHARACTERISTICS Guaranteed by design but not production tested. AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; 13.5 V ≤ VP ≤ 16.5 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Timing Diagram t4 t5 CLK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 06223-002 t6 LE Figure 2. Timing Diagram Rev. B | Page 4 of 20 Data Sheet ADF4113HV ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. TRANSISTOR COUNT Table 3. Parameter AVDD to GND1 AVDD to DVDD VP to GND Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND RFINA to RFINB Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature Reflow, Soldering Peak Temperature Time at Peak Temperature 1 The transistor count is 12,150 (CMOS) and 348 (bipolar). Rating −0.3 V to +7 V −0.3 V to +0.3 V −0.3 V to +18 V −0.3 V to VDD + 0.3 V −0.3 V to VP + 0.3 V −0.3 V to VDD + 0.3 V ±320 mV THERMAL RESISTANCE Table 4. Thermal Resistance Package Type TSSOP LFCSP (Paddle Soldered)1 1 Unit °C/W °C/W Two signal planes (that is, on top and bottom surfaces), two buried planes, and four thermal vias. ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C θJA 150.4 62.82 260°C 40 sec GND = AGND = DGND = 0 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of