Integer-N/Fractional-N PLL Synthesizer
ADF4155
Data Sheet
FEATURES
GENERAL DESCRIPTION
Input frequency range: 500 MHz to 8000 MHz
Fractional-N synthesizer and integer-N synthesizer
Phase frequency detector (PFD) up to 125 MHz
High resolution 38-bit modulus
Separate charge pump supply (VP) allows extended tuning
voltage in 5 V systems
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Differential and single-ended reference inputs
Power supply: 3.3 V ± 5%
Logic compatibility: 1.8 V
Programmable dual-modulus prescaler (P) of 4/5 or 8/9
Programmable output power level
3-wire serial interface
Analog and digital lock detect
The ADF4155 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
when used with an external loop filter, external voltage
controlled oscillator (VCO), and external reference frequency.
The ADF4155 is for use with external VCO parts up to an
8 GHz operating frequency. The high resolution programmable
modulus allows synthesis of exact frequencies with 0 Hz error.
The VCO frequency can be divided by 1, 2, 4, 8, 16, 32, or 64 to
allow the user to generate RF output frequencies as low as
7.8125 MHz.
Control of all on-chip registers is through a simple 3-wire
interface. The device operates with a nominal power supply of
3.3 V ± 5% and can be powered down when not in use.
APPLICATIONS
The ADF4155 is available in a 24-lead, 4 mm × 4 mm LFCSP
package.
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM,
PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Test equipment
Wireless LANs, CATV equipment
Clock generation
FUNCTIONAL BLOCK DIAGRAM
AVDD
REFIN +
REFIN –
CLK
DATA
LE
DVDD
10-BIT R
COUNTER
×2
DOUBLER
RFVDD
VP
RSET
MULTIPLEXER
÷2
DIVIDER
MUXOUT
LOCK
DETECT
DATA REGISTER
FUNCTION
LATCH
CHARGE
PUMP
CPOUT
PHASE
COMPARATOR
CE
CREG1
CREG2
INTEGER
REG
FRACTION
REG
ADF4155
MODULUS
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
÷ 1/2/4/8/16/32/64
OUTPUT
STAGE
RFOUT +
RFOUT –
PDBRF
N COUNTER
AGND
DGND
CPGND
RFGND
RFIN +
RFIN –
12262-001
INPUT
STAGE
Figure 1.
Rev. 0
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ADF4155
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register Maps .................................................................................. 15
Applications ....................................................................................... 1
Register 0 ..................................................................................... 17
General Description ......................................................................... 1
Register 1 ..................................................................................... 18
Functional Block Diagram .............................................................. 1
Register 2 ..................................................................................... 19
Revision History ............................................................................... 2
Register 3 ..................................................................................... 19
Specifications..................................................................................... 3
Register 4 ..................................................................................... 20
Timing Characteristics ................................................................ 5
Register 5 ..................................................................................... 22
Absolute Maximum Ratings ............................................................ 6
Register 6 ..................................................................................... 23
Transistor Count ........................................................................... 6
Register 7 ..................................................................................... 24
ESD Caution .................................................................................. 6
Register 8 ..................................................................................... 25
Pin Configuration and Function Descriptions ............................. 7
Register Initialization Sequence ............................................... 26
Typical Performance Characteristics ............................................. 9
RF Synthesizer—A Worked Example ...................................... 26
Circuit Description ......................................................................... 12
Reference Doubler and Reference Divider ............................. 27
Reference Input Section ............................................................. 12
Cycle Slip Reduction for Faster Lock Times ........................... 27
RF N Counter .............................................................................. 12
Spurious Optimization .............................................................. 27
Phase Frequency Detector and Charge Pump ........................... 13
Spur Mechanisms ....................................................................... 27
MUXOUT and Lock Detect ...................................................... 13
Applications Information .............................................................. 28
Input Shift Registers ................................................................... 13
Local Oscillator with RF Buffer ................................................ 28
Program Modes .......................................................................... 13
Outline Dimensions ....................................................................... 29
Output Stage ................................................................................ 14
Ordering Guide .......................................................................... 29
REVISION HISTORY
4/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
ADF4155
SPECIFICATIONS
AVDD = DVDD = RFVDD = 3.3 V ± 5%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = RFGND = CPGND = 0 V, and TA = TMIN to TMAX, unless otherwise
noted. Operating temperature range is −40°C to +85°C.
Table 1.
Parameter
REFIN+\REFIN− CHARACTERISTICS
Input Frequency
Single-Ended Mode
Differential Mode
Input Sensitivity
Single-Ended Mode
Differential Mode
Min
Typ
Max
Unit
10
10
250
600
MHz
MHz
0.7
AVDD
V p-p
0.4
1.8
V p-p
±60
pF
pF
µA
125
100
125
75
MHz
MHz
MHz
MHz
6.0
8.0
1.5
GHz
GHz
GHz
For f < 10 MHz, ensure slew rate > 21 V/µs
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
PHASE DETECTOR
Phase Detector Frequency
6.9
1.4
RFIN+\RFIN− CHARACTERISTICS
RF Input Frequency
Prescaler Output Frequency
CHARGE PUMP (CP)
ICP Sink/Source
High Value
Low Value
RSET Range
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output High Current, IOH
Output Low Voltage, VOL
POWER SUPPLIES
AVDD
DVDD
RFVDD
VP
IP
Output Dividers
Test Conditions/Comments
0.5
REFIN+ biased at AVDD/2; ac coupling ensures
AVDD/2 bias
LVDS and LVPECL compatible, REFIN+\REFIN−
biased at 2.1 V; ac coupling ensures 2.1 V bias
Negative bleed on
Pulsed bleed on
Negative bleed off and pulsed bleed off
CSR enabled
For lower frequencies, ensure that the slew
rate > 400 V/µs
−10 dBm minimum/0 dBm maximum
−5 dBm minimum/0 dBm maximum
RSET = 4.7 kΩ
2.7
5
0.31
4.7
3
3
1.5
10
1.5
0.6
±1
3.0
DVDD − 0.4
500
0.4
3.135
3.465
AVDD
AVDD
AVDD
5.5
4.1
6 to 36
Rev. 0 | Page 3 of 32
mA
mA
kΩ
%
%
%
0.5 V ≤ VCP ≤ VP − 0.5 V
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = 2.5 V
V
V
µA
pF
Compatible with 1.8 V and 3 V logic
V
µA
V
CMOS output selected
V
V
V
V
mA
mA
IOL = 500 µA
Voltage must equal AVDD
Voltage must equal AVDD
Each output divide by 2 consumes 6 mA; see
Table 6 for details on the current consumption
as a function of the output power and divider
ADF4155
Parameter
Total IDD (DIDD + AIDD + RFIDD)
Data Sheet
Min
Low Power Sleep Mode
RFOUT+/RFOUT− CHARACTERISTICS
Maximum Output Frequency
Minimum Output Frequency Using
Dividers
Harmonic Content (Second)
Harmonic Content (Third)
Minimum RF Output Power 1
Maximum RF Output Power1
NOISE CHARACTERISTICS
Normalized Phase Noise Floor, PNSYNTH 2
Integer-N Mode
Fractional-N-Mode
Normalized 1/f Noise, PN1_f 3
In-Band Phase Noise 4
Spurious Signals due to PFD
Frequency
Level of Signal with RF Mute Enabled
Typ
38
Max
47
Unit
mA
105
131
mA
10
500
22
530
µA
µA
4000
MHz
MHz
7.8125
−16
−26
−22
−7
−4
5
dBc
dBc
dBc
dBc
dBm
dBm
−223
−218
−116
−98
−110
−112
−40
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBm
Test Conditions/Comments
RF output (Bit DB6, Register 6) disabled,
3.6 GHz at VCO output
RFOUT+/RFOUT− = 1800 MHz, divide by 2 enabled,
5 dBm
Hardware powered down using CE
Software powered down, serial peripheral
interface (SPI) powered up in low power sleep
mode
500 MHz fundamental output and
divide by 64 selected
RFOUT+/RFOUT− = 2.9 GHz, fundamental mode
RFOUT+/RFOUT− = 2.9 GHz, divide by 2 enabled
RFOUT+/RFOUT− = 2.9 GHz, fundamental mode
RFOUT+/RFOUT− = 2.9 GHz, divide by 2 enabled
Programmable in 3 dB steps
Negative bleed enabled
PLL bandwidth = 500 kHz
FRAC = 0
10 kHz offset; normalized to 1 GHz
10 kHz offset from 5.8 GHz carrier
At 5.8 GHz VCO output, fPFD = 61.44 MHz
At 5.8 GHz VCO output, fPFD = 30.72 MHz
Using an external 18 nH pull-up inductor to RFVDD into a 50 Ω load.
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N counter
value) and 10 logfPFD. PNSYNTH = PNTOT − 10 log fPFD − 20 logN.
3
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at a frequency offset (f) is given by PN = P1_f + 10log(10kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the
ADIsimPLL design tool.
4
fREFIN = 122.88 MHz, fPFD = 61.44 MHz, frequency offset = 10 kHz, VCO frequency = 5.8 GHz, RFOUT = 5.8 GHz, N = 94.40104167, loop bandwidth = 60 kHz, ICP =0. 938 mA,
and IBLEED = 60 µA.
1
2
Rev. 0 | Page 4 of 32
Data Sheet
ADF4155
TIMING CHARACTERISTICS
AVDD = DVDD = RFVDD = 3.3 V ± 5%, AVDD ≤ VP ≤ 5.5V, AGND = DGND = RFGND = CPGND = 0 V, 1.8 V and 3 V logic levels used, and TA =
TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Timing Diagram
t4
t5
CLK
t2
DATA
DB31 (MSB)
t3
DB30
DB3
(CONTROL BIT C4)
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
t1
t6
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 32
12262-002
LE
ADF4155
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to GND1
AVDD to DVDD
RFVDD to AVDD
RFVDD to DVDD
VP to GND 1
VP to AVDD
Digital I/O Voltage to GND1
Analog I/O Voltage to GND1
REFIN+, REFIN− to GND1
REFIN+ to REFIN−
RFIN+ to RFIN−
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
LFCSP θJA, Thermal Impedance (Pad
Soldered to GND)
Reflow Soldering
Peak Temperature
Time at Peak Temperature
ESD
Charged Device Model
Human Body Model
1
Rating
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +2.5 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to VDD + 0.3 V
±2.1 V
±700 mV
−40°C to +85°C
−65°C to +125°C
150°C
47.3°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
TRANSISTOR COUNT
The transistor count for the ADF4155 is 31,190 (CMOS) and
1652 (bipolar).
ESD CAUTION
260°C
40 sec
1250 V
4000 V
GND = AGND = DGND = RFGND = CPGND = 0 V.
Rev. 0 | Page 6 of 32
Data Sheet
ADF4155
19 REFIN+
21 MUXOUT
20 REFIN–
22 CREG2
24 RSET
23 DGND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 DVDD
CLK 1
DATA 2
LE 3
ADF4155
CE 4
TOP VIEW
17 PDBRF
16 RFVDD
15 RFOUT+
CREG 1 5
14 RFOUT–
VP 6
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO GROUND.
12262-003
AGND 12
RFIN– 11
AVDD 9
RFIN+ 10
CPOUT 7
CPGND 8
13 RFGND
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
CLK
2
DATA
3
LE
4
CE
5
CREG1
6
VP
7
CPOUT
8
9
CPGND
AVDD
10
11
RFIN+
RFIN−
12
13
14
AGND
RFGND
RFOUT−
15
RFOUT+
16
RFVDD
17
18
PDBRF
DVDD
19
20
21
REFIN+
REFIN−
MUXOUT
Description
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This input is a high
impedance CMOS input.
Load Enable Input. When LE goes high, the data stored in the shift register is loaded into the register that is
selected by the four LSBs. This input is a high impedance CMOS input.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
A logic high on this pin powers up the device, depending on the status of the power-down bits.
Output of Internal Low Dropout (LDO) Regulator. Supply voltage to digital circuits. Nominal voltage of 1.8 V.
100 nF decoupling capacitors to ground required.
Charge Pump Power Supply. VP must have the same or greater value than AVDD up to 5.5 V. Connect
decoupling capacitors, as close to this pin as possible, to the analog ground plane.
Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the
loop filter is connected to the VTUNE pin of the external VCO.
Charge Pump Ground. This output is the ground return pin for the CPOUT pin.
Analog Power Supply. This pin ranges from 3.135 V to 3.465 V. Connect decoupling capacitors, as close to this
pin as possible, to the analog ground plane. AVDD must have the same value as DVDD and RFVDD.
RF Input. This small signal input must be ac-coupled to the external VCO.
Complementary RF Input. Decouple this pin to the ground plane with a small bypass capacitor, typically
100 pF. If driven differentially, connect this input similar to RFIN+.
Analog Ground. Ground return pins for the analog circuitry.
RF Ground. This output is the ground return pin for the RFVDD pin.
Complementary RF Output. The output level is programmable. The VCO fundamental output or a divideddown version is available.
RF Output. The output level is programmable. The VCO fundamental output or a divided-down version is
available.
Analog Power Supply for RF Outputs. This pin ranges from 3.135 V to 3.465 V. Connect decoupling capacitors,
as close to this pin as possible, to the analog ground plane. RFVDD must have the same value as AVDD and DVDD.
RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
Digital Power Supply. This pin must be at the same voltage as AVDD and RFVDD. Connect decoupling capacitors,
as close to this pin as possible, to the ground plane.
Reference Input.
Complementary Reference Input.
Multiplexer Output. The multiplexer output allows the lock detect, the scaled RF, or the scaled reference
frequency to be externally accessed.
Rev. 0 | Page 7 of 32
ADF4155
Pin No.
22
Mnemonic
CREG2
23
24
DGND
RSET
EPAD
Data Sheet
Description
Output of Internal LDO. Supply voltage to digital circuits. Nominal voltage of 1.8 V. 100 nF decoupling
capacitors to ground required.
Digital Ground. Ground return pins for the digital circuitry.
Connect a resistor between this pin and ground to set the charge pump output current. The nominal voltage
bias at the RSET pin is 0.55 V. The relationship between ICP_MAX and RSET is as follows:
ICP_MAX = 23.5/RSET
where:
RSET = 4.7 kΩ.
ICP = 5 mA.
Exposed Pad. The exposed pad must be connected to ground.
Rev. 0 | Page 8 of 32
Data Sheet
ADF4155
TYPICAL PERFORMANCE CHARACTERISTICS
10
PRESCALER 4/5
PRESCALER 8/9
8
–15
4
CURRENT (mA)
–10
6
–25
–30
–2
–35
–4
–40
–6
–45
–8
–50
–10
0
2G
4G
6G
8G
10G
RF INPUT FREQUENCY (Hz)
Figure 4. RF Input Sensitivity vs. RF Input Frequency, RF Output Disabled
0
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10
8
–15
4
MISMATCH (%)
6
–20
–25
–30
2
0
–2
–35
–4
–40
–6
–8
–50
–10
4G
6G
8G
10G
RF INPUT FREQUENCY (Hz)
12262-005
–45
2G
1.0
Figure 7. Charge Pump Output Characteristics, VP = 5 V, Selected ICP Values
Between 0.312 mA (Minimum) and 5.000 mA (Maximum), RSET = 4.7 kΩ
–10
0
0.5
5.000mA UP
5.000mA DOWN
2.500mA UP
2.500mA DOWN
3.125mA UP
3.125mA DOWN
4.062mA UP
4.062mA DOWN
0.312mA UP
0.312mA DOWN
0.937mA UP
0.937mA DOWN
1.562mA UP
1.562mA DOWN
VCP (V)
PRESCALER 4/5
PRESCALER 8/9
–5
RF INPUT SENSITIVITY (dBm)
2
0
12262-007
–20
12262-004
RF INPUT SENSITIVITY (dBm)
–5
Figure 5. RF Input Sensitivity vs. RF Input Frequency, RF Output Enabled,
RF Divide-by-2 Selected
2.812mA
3.125mA
3.437mA
3.750mA
4.062mA
4.375mA
4.687mA
5.000mA
0.312mA
0.625mA
0.937mA
1.250mA
1.562mA
1.875mA
2.187mA
2.500mA
0.5
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOLTAGE (V)
12262-008
0
Figure 8. Charge Pump Output Mismatch vs. VCP, Selected ICP Values Between
0.312 mA (Minimum) and 5.000 mA (Maximum), RSET = 4.7 kΩ
10
10
5
+2dBm POWER SETTING
–10
IBS SPUR LEVEL (dBc)
–1dBm POWER SETTING
0
–4dBm POWER SETTING
–5
–10
–15
–50
FIRST-ORDER
FIRST-ORDER
–70
SECOND-ORDER
THIRD-ORDER
THIRD-ORDER
–90
550
1050
1550
2050
2550
3050
FREQUENCY (MHz)
3550
4050
–130
2270
Figure .6. Single-Ended RF Output Power Level vs. Frequency and
Power Setting, RF Output Pins Pulled Up to 3.3 V via 18 nH Inductors
2280
2290
2300
2310
2320
VCO OUTPUT FREQUENCY (MHz)
2330
12262-009
–20
50
–30
–110
12262-006
RF OUTPUT POWER LEVEL (dBm)
+5dBm POWER SETTING
Figure 9. Integer Boundary Spurs (IBS) Spur Level vs. VCO Output Frequency,
fPFD = 61.44 MHz, Sweep Resolution = 80 kHz
Rev. 0 | Page 9 of 32
ADF4155
Data Sheet
3.66
0
PFD SPUR
REFERENCE SPUR
FREQUENCY (GHz)
–60
–80
3.63
3.62
3.61
–100
3.60
–120
3.59
2550
3050
3550
3.58
–1.0
12262-010
2050
4050
CARRIER FREQUENCY (MHz)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Figure 13. PLL Lock Time with Cycle Sleep Reduction (CSR) On/Off,
Locking over 50 MHz Range (Jump from 3.648 GHz to 3.6 GHz),
fPFD = 61.44 MHz, Loop Bandwidth = 15 kHz, ICP = 0.31 mA
–80
PFD SPUR (PFD = 61.44MHz)
PFD SPUR (PFD = 30.72MHz)
PFD SPUR (PFD = 15.36MHz)
–90
PHASE NOISE (dBc/Hz)
SPUR LEVEL (dBc)
–20
0
TIME (ms)
Figure 10. PFD and Reference Spur Level vs. Carrier Frequency
Measured at VCO Output, fPFD = 61.44 MHz, REFIN+/REFIN− = 122.88 MHz
0
–0.5
12262-113
SPUR LEVEL (dBc)
3.64
–40
–140
1550
CSR ENABLED
CSR DISABLED
3.65
–20
–40
–60
–80
–100
–100
–110
–120
–130
–140
–120
2200
2700
3200
3700
4200
CARRIER FREQUENCY (MHz)
–160
1M
10M
–80
REFERENCE SPUR (PFD = 61.44MHz)
REFERENCE SPUR (PFD = 30.72MHz)
REFERENCE SPUR (PFD = 15.36MHz)
–90
–40
–60
–80
–100
–120
–100
–110
–120
–130
–140
1700
2200
2700
3200
CARRIER FREQUENCY (MHz)
3700
4200
Figure 12. Reference Spur Level vs. Carrier Frequency Measured at RF Output,
REFIN+/REFIN− = 122.88 MHz (Note the improvement in the PFD spurs when
the PFD frequency is lowered.)
Rev. 0 | Page 10 of 32
–160
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
Figure 15. Fractional-N Phase Noise and Spur Performance,
VCOOUT = 5800 MHz, REFIN+/REFIN− = 122.88 MHz,
fPFD = 61.44 MHz, Loop Filter Bandwidth = 60 kHz
12262-014
–150
12262-012
–140
1200
100k
Figure 14. Integer-N Phase Noise and Spur Performance;
VCOOUT = 5775.36 MHz, REFIN+/REFIN− = 122.88 MHz,
fPFD = 61.44 MHz, Loop Filter Bandwidth= 60 kHz
PHASE NOISE (dBc/Hz)
SPUR LEVEL (dBc)
–20
10k
FREQUENCY OFFSET (Hz)
Figure 11. PFD Spur Level vs. Carrier Frequency Measured at RF Output,
REFIN+/REFIN− = 122.88 MHz (Note the improvement in the PFD spurs when
the PFD frequency is lower.)
0
1k
12262-013
1700
12262-011
–140
1200
–150
Data Sheet
ADF4155
–80
PHASE NOISE (dBc/Hz)
–90
–100
–110
–120
–130
–140
–160
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
12262-015
–150
Figure 16. RF Output Phase Noise, RF Divider = 2 Enabled, Fractional-N,
RFOUT+ = 2900 MHz, REFIN+/REFIN− = 122.88 MHz, fPFD = 61.44 MHz,
Loop Filter Bandwidth = 60 kHz
Rev. 0 | Page 11 of 32
ADF4155
Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
INT, FRAC, MOD, and R Counter Relationship
The reference input stage is shown in Figure 17. The reference
input can accept both single-ended and differential signals, and
the choice is controlled by the reference input mode bit (Bit DB30,
Register 6). To use a differential signal for the reference input,
this bit must be programmed high. In this case, the SW1 and
SW2 switches are opened, the SW3 and SW4 switches are
closed, and the current source driving the differential pair of the
transistors is switched on. The differential signal is buffered,
before it is fed to the emitter-coupled logic (ECL) to a CMOS
converter. When a single-ended signal is used as the reference,
Bit DB30 in Register 6 must be programmed to 0. In this case,
the SW1 and SW2 switches are closed, the SW3 and SW4
switches are opened, and the current source driving the
differential pair of transistors is switched off.
The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in
conjunction with the R counter, make it possible to generate
output frequencies that are spaced by fractions of the PFD
frequency (fPFD). For more information, see the RF Synthesizer—
A Worked Example section.
Calculate the RF VCO frequency (RFOUT) by the following:
RFOUT = fPFD × N
where:
RFOUT is the output frequency of the external VCO voltage
controlled oscillator (without using the output divider).
fPFD is a frequency of phase frequency detector.
N is the desired value of the feedback counter N.
Calculate the fPFD by the following equation:
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
REFERENCE
INPUT MODE
SW2
BUFFER
SW1
TO
R COUNTER
MULTIPLEXER
AVDD
ECL TO CMOS
BUFFER
N = INT +
REFIN+
2.5kΩ
12262-016
SW4
BIAS
GENERATOR
Figure 17. Reference Input Stage
RF N COUNTER
The RF N counter allows a division ratio in the PLL feedback
path. The division ratio is determined by the INT, FRAC1,
MOD1, FRAC2, and MOD2 values, which build up this divider
(see Figure 18). Note that MOD1 is a fixed nonprogrammable
value equal to 224.
RF N COUNTER
FRAC1 +
FRAC2
MOD1
TO PFD
N COUNTER
1.
2.
3.
4.
5.
6.
INT
REG
FRAC1
REG
FRAC2
VALUE
Calculate N by dividing RFOUT/fPFD.
The integer value of this number forms INT.
Subtract this value from the full N value.
Multiply the remainder by 224.
The integer value of this number forms FRAC1.
Calculate the MOD2 basis on the channel spacing (fCHSP) by
MOD2 = fPFD/GCD(fPFD, fCHSP)
(4)
where:
fCHSP is the desired channel spacing frequency.
GCD(fPFD, fCHSP) is a greatest common divider of the PFD
frequency and the channel spacing frequency.
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
MOD2
VALUE
12262-017
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
(3)
This results in a very fine frequency resolution with no residual
frequency error. To apply this formula, take the following steps:
MOD2
N = INT +
FRAC2
MOD2
MOD1
FRAC1 +
where:
INT is the 16-bit integer value (23 to 32,767 for 4/5 prescaler, 75
to 65,535 for 8/9 prescaler).
FRAC1 is the numerator of the primary modulus (1 − 16,777,215).
FRAC2 is the numerator of the 14-bit auxiliary modulus (1 − 16,383).
MOD2 is the programmable, 14-bit auxiliary fractional
modulus (2 − 16,383).
MOD1 is a 24-bit primary modulus with a fixed value of 224
(16,777,216).
REFIN–
2.5kΩ
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
T is the REFIN divide by 2 bit (0 or 1)
N comprises
85kΩ
SW3
(1)
7.
Figure 18. RF N Counter
Rev. 0 | Page 12 of 32
Calculate FRAC2 by the following equation:
FRAC2 = [(N − INT) × 224 − FRAC1)] × MOD2
(5)
Data Sheet
ADF4155
INT N Mode
INPUT SHIFT REGISTERS
If FRAC1 and FRAC2 = 0, the synthesizer operates in integer-N
mode.
Data is clocked into the 32-bit shift register on each rising edge
of CLK. The data is clocked in MSB first. Data is transferred
from the shift register to one of the nine latches on the rising
edge of LE.
R Counter
The 10-bit R counter allows the input reference frequency, REFIN,
to be divided down to produce the reference clock to the PFD.
Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR AND CHARGE PUMP
The phase frequency detector takes inputs from the R counter
and N counter and produces an output proportional to the
phase and frequency difference between them. Figure 19 is a
simplified schematic of the phase frequency detector. The PFD
includes a fixed delay element that sets the width of the
antibacklash pulse (ABP), which is typically 2.6 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
and provides a consistent reference spur level.
HIGH
D1
Q1
UP
U1
+IN
CLR1
CHARGE
PUMP
DELAY
CP
The destination latch is determined by the state of the four
control bits (C4, C3, C2, and C1) in the shift register. These are
the four LSBs: DB3, DB2, DB1, and DB0, as shown in Figure 2.
The truth table for these bits is shown in Table 5. Figure 22 and
Figure 23 summarize how the latches are programmed.
Table 5. Truth Table for the C4, C3, C2, and C1 Control Bits
C4
0
0
0
0
0
0
0
0
1
Control Bits
C3
C2
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
C1
0
1
0
1
0
1
0
1
0
Register
Register 0 (R0)
Register 1 (R1)
Register 2 (R2)
Register 3 (R3)
Register 4 (R4)
Register 5 (R5)
Register 6 (R6)
Register 7 (R7)
Register 8 (R8)
U3
PROGRAM MODES
HIGH
D2
Q2
DOWN
Table 5 and Figure 24 through Figure 32 show how the program
modes must be set up in the ADF4155.
12262-018
U2
–IN
Figure 19. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4155 allows the user to access
various internal points on the chip. The state of MUXOUT is
controlled by the M3, M2, and M1 bits in Register 4 (for further
details, see Figure 28). Figure 20 shows the MUXOUT section
in block diagram form.
DVDD
The following ADF4155 settings are double buffered: the
fractional value (FRAC1/FRAC2), the modulus value (MOD2),
the reference doubler, the reference divide by 2 (RDIV2), the
R counter value, the charge pump current setting, and the
R divider select. This means that two events must occur before
the device can use a new value for any of the double buffered
settings. First, the new value must be latched into the device by
writing to the appropriate register. Second, a new write must be
performed on Register R0.
For example, any time that the modulus value is updated,
Register 0 (R0) must be written to, to ensure that the modulus
value is loaded correctly.
THREE-STATE OUTPUT
DVDD
DGND
R COUNTER OUTPUT
MUX
CONTROL
MUXOUT
N COUNTER OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
DGND
12262-019
RESERVED
Figure 20. MUXOUT Schematic
Rev. 0 | Page 13 of 32
ADF4155
Data Sheet
OUTPUT STAGE
RFVDD
50Ω
For best spur performance, it is recommended to use the VCO
output and disable the RF output (Bit DB6, Register 6) stage.
RFOUT–
RF INPUT
STAGE
The output stage uses an internal 50 Ω resistor to RFVDD. An
external pull-up inductor to RFVDD is necessary prior to ac
coupling into a 50 Ω load. Alternatively, the output can be
combined in a 1 + 1:1 transformer or a 180° microstrip coupler.
If the outputs are used individually, the unused complimentary
output must be terminated with a similar circuit to the used
output.
BUFFER/
DIVIDE-BY1/2/4/8/16/32/64
12262-020
The RFOUT+ and RFOUT− pins of the ADF4155 are connected to
the collectors of an NPN differential pair driven by a signal
from the RF divider block, as shown in Figure 21.
The current consumption as a function of the output power and
the RF divider is shown in Table 6.
50Ω
RFOUT+
The RF output stage is used where lower frequency operation is
required by enabling one of the output dividers.
To optimize the output power requirements, the tail current of
the differential pair is programmable using Bits[DB5:DB4] in
Register 6 (R6). Four current levels can be set. These levels give
output power levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm.
RFVDD
Figure 21. Output Stage
Another feature of the ADF4155 is that the supply current to the
RF output stage can be shut down until the device achieves lock
as measured by the digital lock detect circuitry. This shutdown
is enabled by using the mute till lock detect (MTLD) bit (DB11)
in Register 6 (R6).
Table 6. Total IDD (DIDD + AIDD + RFIDD)
Divide By
1
2
4
8
16
32
64
RFOUT Off
37.4
46.5
53.1
61.3
66.3
70.4
72.9
RFOUT = −4 dBm
55.3
64.4
70.9
79.1
84.2
88.2
90.8
RFOUT = −1 dBm
67.5
76.6
83.2
91.4
96.4
100.5
103.0
RFOUT = +2 dBm
83.9
93.0
99.6
107.8
112.8
116.9
119.4
Rev. 0 | Page 14 of 32
RFOUT = +5 dBm
96.0
105.1
111.7
119.8
124.9
129.0
131.5
Data Sheet
ADF4155
REGISTER MAPS
PRESCALER
REGISTER 0
RESERVED
16-BIT INTEGER VALUE (INT)
CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
0
0
0
PR1
N16
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
DB7 DB6
N5
N4
N3
DB5 DB4
DB3
N2
C4(0) C3(0) C2(0) C1(0)
N1
DB2
DB1
DB0
REGISTER 1
DBR 1
24-BIT MAIN FRACTIONAL VALUE (FRAC1)
RESERVED
CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
DB7 DB6
F5
F4
F3
DB5 DB4
DB3
F2
C4(0) C3(0) C2(0) C1(1)
F1
DB2
DB1
DB0
REGISTER 2
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
DBR 1
14-BIT AUXILIARY MODULUS VALUE (MOD2)
RESERVED
0
0
0
0
0
0
M14
M13
M12
M11
M10
M9
M8
M7
M6
M5
DB7 DB6
M4
CONTROL BITS
DB5 DB4
M3
M2
DB3
DB2
DB1
DB0
M1 C4(0) C3(0) C2(1) C1(0)
REGISTER 3
1
0
0
0
0
0
0
0
0
0
0
0
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
RESERVED
0
MUXOUT
LEVEL SELECT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
DBR 1
14-BIT AUXILIARY FRACTIONAL WORD (FRAC2)
RESERVED
DB7 DB6
P4
P3
CONTROL BITS
DB5 DB4
DB3
P2
C4(0) C3(0) C2(1) C1(1)
P1
DB2
DB1
DB0
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
L2
M3
M2
M1
RD2
RD1
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
D1
CP4
CP3
CP2
CP1
0
LVS
COUNTER
RESET
CHARGE PUMP
CURRENT
SETTING DBR 1
CHARGE PUMP
THREE-STATE
DBR 1
PD
10-BIT R COUNTER
PHASE
DETECTOR
POLARITY
DBR1
DOUBLE BUFFER
MUXOUT
RDIV2
REFERENCE
DOUBLER DBR1
DITHER 2
RESERVED
REGISTER 4
DB7
DB6
DB5
DB4
U4
U3
U2
U1
CONTROL BITS
DB3
DB2
DB1
DB0
C4(0) C3(1) C2(0) C1(0)
RESERVED
CONTROL BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
1 DBR
0
0
0
PB2
PB1
PB
0
ABP
0
0
0
CSR
0
0
0
0
0
0
0
0
= DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 22. Register Summary (Register 0 to Register 5)
Rev. 0 | Page 15 of 32
0
0
0
DB7 DB6
0
0
DB5 DB4
0
0
DB3
DB2
DB1
DB0
C4(0) C3(1) C2(0) C1(1)
12262-021
CSR
ABP SELECT
RESERVED
RESERVED
PB
PULSE BLEED
DELAY
REGISTER 5
ADF4155
Data Sheet
REGISTER 6
RM1
1
0
0
1
1
1
D12
D11
BLEED CURRENT SETTINGS
D10
BL8
BL7
BL6
BL5
BL4
BL3
BL2
BL1
BLE
D8
0
0
0
0
OUTPUT
POWER
CONTROL BITS
DB5 DB4
DB3
D2
D1
C4(0) C3(1) C2(1) C1(0)
LD MODE
1
RF
DIVIDER
SELECT
RESERVED
MTLD
DB7 DB6
REF IN
MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
RESERVED
RESERVED
RF OUTPUT
ENABLE
NEG BLEED
DBB 1
CONTROL BITS
D3
DB2
DB1
DB0
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LD5
LOL MODE
LOCK
DETECT
CYCLE
COUNT
RESERVED
REGISTER 7
DB7 DB6
LD4 LOL
1
DB5 DB4
1
DB3
DB2
DB1
DB0
LD1 C4(0) C3(1) C2(1) C1(1)
RESERVED
PHASE WORD
CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
L1
1
1
1
0
1
0
1
0
0
1
0
1
1
1
1
1
1
1
1 DBB = DOUBLE BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0 IF, AND ONLY IF, DB14 OF REGISTER 4 IS HIGH.
Figure 23. Register Summary (Register 6 to Register 8)
Rev. 0 | Page 16 of 32
1
0
DB7 DB6
0
0
DB5 DB4
0
1
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(0) C1(0)
12262-022
DITHER 1
REGISTER 8
Data Sheet
ADF4155
REGISTER 0
Prescaler (P) Value
Register 0 Control Bits
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC1, MOD1, FRAC2, and MOD2 counters, determines the
overall division ratio from the VCO output to the PFD input.
With Bits[C4:C1] set to 0000, Register 0 is programmed. Figure 24
shows the input data format for programming this register.
Operating at CML levels, the prescaler takes the clock from the
VCO output and divides it down for the counters. It is based on
a synchronous 4/5 core. When the prescaler is set to 4/5, the
maximum RF frequency allowed is 6 GHz. Therefore, when
operating the ADF4155 above 6 GHz, set the prescaler to 8/9.
The prescaler limits the INT value to the following:
16-Bit Integer Value (INT)
The 16 bits [DB19:DB4] set the INT value, which determines
the integer part of the feedback division factor. The INT value is
used in Equation 3 (see the INT, FRAC, MOD, and R Counter
Relationship section). All integer values from 23 to 32,767 are
allowed for 4/5 prescaler. For prescaler 8/9, the minimum
integer value is 75, and the maximum integer value value is
65,535.
•
•
P = 4/5, INTMIN = 23, INTMAX = 32,767
P = 8/9, INTMIN = 75, INTMAX = 65,535
RESERVED
16-BIT INTEGER VALUE (INT)
CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
0
0
0
PR1
N16
PR1
PRESCALER
0
4/5
1
8/9
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
DB7 DB6
N5
N16
N15
...
N5
N4
N3
N2
N1
0
0
...
0
0
0
0
0
N4
N3
DB5 DB4
DB3
N2
C4(0) C3(0) C2(0) C1(0)
N1
DB0
INTEGER VALUE (INT)
0
0
...
0
0
0
0
1
NOT ALLOWED
0
...
0
0
0
1
0
NOT ALLOWED
.
.
...
.
.
.
.
.
...
0
0
...
1
0
1
1
0
NOT ALLOWED
0
0
...
1
0
1
1
1
23
0
0
...
1
1
0
0
0
24
.
.
...
.
.
.
.
.
...
1
1
...
1
1
1
0
1
65533
1
1
...
1
1
1
1
0
65534
1
1
...
1
1
1
1
1
65535
INTMIN = 75 WITH PRESCALER = 8/9
Rev. 0 | Page 17 of 32
DB1
NOT ALLOWED
0
Figure 24. Register 0 (R0)
DB2
12262-023
PRESCALER
In the ADF4155, the PR1 bit (DB20) in Register 0 sets the
prescaler value.
ADF4155
Data Sheet
REGISTER 1
modulator. This fraction, along with the INT value, specifies the
new frequency channel that the synthesizer locks to, as shown
in the RF Synthesizer—A Worked Example section. FRAC1
values from 0 to (224 − 1) cover channels over a frequency range
equal to the PFD reference frequency.
Register 1 Control Bits
With Bits[C4:C1] set to 0001, Register 1 is programmed. Figure 25
shows the input data format for programming this register.
24-Bit Main Fractional Value (FRAC1)
The 24 FRAC1 bits [DB27:DB4] together with FRAC2 and
MOD2 set the numerator of the fraction that is input to the Σ-Δ
DBR 1
CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
1
0
0
0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F11
F12
F13
F14
F10
F9
F8
F7
F24
F23
..........
F2
F1
MAIN FRACTIONAL VALUE (FRAC1)
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
16777212
1
1
..........
0
1
16777213
1
1
..........
1
0
16777214
1
1
.........
1
1
16777215
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 25. Register 1 (R1)
Rev. 0 | Page 18 of 32
F6
F5
DB7 DB6
F4
F3
DB0
DB3
F2
C4(0) C3(0) C2(0) C1(1)
F1
DB2
DB1
DB5 DB4
12262-024
24-BIT MAIN FRACTIONAL VALUE (FRAC1)
RESERVED
Data Sheet
ADF4155
REGISTER 2
REGISTER 3
Register 2 Control Bits
Register 3 Control Bits
With Bits[C4:C1] set to 0010, Register 2 is programmed. Figure 26
shows the input data format for programming this register.
With Bits[C4:C1] set to 0011, Register 3 is programmed. Figure 27
shows the input data format for programming this register.
14-Bit Auxiliary Modulus Value (MOD2)
14-Bit Auxiliary Fractional Value (FRAC2)
The 14 MOD2 bits [DB17:DB4] set the auxiliary fractional
modulus. The auxiliary fractional modulus is used to correct
any residual error due to the main fractional modulus. For more
information, see the RF Synthesizer—A Worked Example section.
The auxiliary fractional value bits [DB17:DB4] control the
auxiliary fractional word. The word must be less than the
MOD2 value programmed in Register 2.
DBR 1
14-BIT AUXILIARY MODULUS VALUE (MOD2)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M14
M13
M12
M11
M10
M9
M8
M7
M6
CONTROL BITS
DB7 DB6
M5
M4
M3
DB5 DB4
M2
DB3
DB2
DB1
DB0
M1 C4(0) C3(0) C2(1) C1(0)
M14
M13
..........
M2
M1
AUXILIARY MODULUS VALUE (MOD2)
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
16380
1
1
..........
0
1
16381
1
1
..........
1
0
16382
1
1
.........
1
1
16383
12262-025
RESERVED
1 DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 26. Register 2 (R2)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
P14
P13
P12
P11
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 27. Register 3 (R3)
Rev. 0 | Page 19 of 32
P10
P7
P6
P5
DBR 1
DB7 DB6
P4
P3
CONTROL BITS
DB5 DB4
DB3
P2
C4(0) C3(0) C2(1) C1(1)
P1
DB2
DB1
DB0
P9
P8
P14
P13
..........
P2
P1
AUXILIARY FRACTIONAL VALUE (FRAC2)
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
16380
1
1
..........
0
1
16381
1
1
..........
1
0
16382
1
1
.........
1
1
16383
12262-026
14-BIT AUXILIARY FRACTIONAL WORD (FRAC2)
RESERVED
ADF4155
Data Sheet
REGISTER 4
Charge Pump Current Setting
Register 4 Control Bits
With Bits[C4:C1] set to 0100, Register 4 is programmed. Figure 28
shows the input data format for programming this register.
Bits[DB13:DB10] set the charge pump current. Set this value to
the charge pump current that the loop filter is designed with
(see Figure 28).
Dither 2
MUXOUT Level Select
Dither to the second stage of the main Σ-Δ modulator can be
activated on the ADF4155 by setting Bit DB30 in Register 4
(see Figure 28) to 1. This feature allows the user to optimize a
design for improved spurious performance.
The DB8 bit sets the voltage level used on the MUXOUT
output. If the bit is programmed to 0, the MUXOUT uses a
value of 1.8 V as the high level. When this bit is set to 1, the
high level on the MUXOUT output is equal to DVDD (3.3 V ± 5%).
Dither randomizes the fractional quantization noise so that it
resembles white noise rather than spurious noise. As a result,
the device is optimized for improved spurious performance.
This operation is normally used for fast locking applications
when the PLL closed-loop bandwidth is wide.
Phase Detector Polarity
MUXOUT
Power-Down (PD) Mode
The on-chip multiplexer is controlled by Bits[DB29:DB27]
(see Figure 28).
DB6 provides the programmable power-down mode. Setting this
bit to 1 performs a power-down. Setting this bit to 0 returns the
synthesizer to normal operation. In software power-down mode,
the device retains all information in its registers. The register
contents are only lost if the supply voltages are removed.
Reference Doubler
Setting DB26 to 0 feeds the reference frequency input (REFIN)
directly to the 10-bit R counter, disabling the doubler. Setting
this bit to 1 multiplies the REFIN by a factor of 2 before feeding it
into the 10-bit R counter. When the doubler is disabled, the REFIN
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising and
falling edges of REFIN become active edges at the PFD input.
When the doubler is enabled and the dither is enabled, the in-band
phase noise performance is sensitive to the REFIN duty cycle.
The phase noise degradation can be as much as 5 dB for REFIN
duty cycles outside a 45% to 55% range. The phase noise is
insensitive to the REFIN duty cycle when the dither is switched
off and when the doubler is disabled.
The maximum allowable REFIN frequency when the reference
doubler is enabled is 80 MHz.
RDIV2
Setting the DB25 bit to 1 inserts a divide by 2 toggle flip-flop
between the R counter and PFD, which extends the maximum
REFIN input rate. This function allows a 50% duty cycle signal to
appear at the PFD input, which is necessary for cycle slip reduction.
The DB7 bit sets the phase detector polarity. When a passive
loop filter or a noninverting active loop filter is used, set this bit
to 1. If an active filter with an inverting characteristic is used,
set this bit to 0.
Note that the software power-down issue requires a software
workaround by using the following write sequence until fixed.
To perform a power-down, take the following steps:
1.
2.
Write INT = 65535 (0xFFFF) and prescaler = 1 in
Register 0 (R0).
Write DB6 = 1 in Register 4 (R4).
To exit from a power-down, take the following steps:
1.
2.
Write the correct INT value and prescaler value in
Register 0 (R0).
Write DB6 = 0 in Register 4 (R4).
When power-down is activated, the following events occur:
•
•
•
•
•
10-Bit R Counter
Synthesizer counters are forced to their load state
conditions.
Charge pump is forced into three-state mode.
Digital lock detect circuitry is reset.
RF output buffers are disabled.
Input registers remain active and capable of loading and
latching data.
Charge Pump (CP) Three-State
The 10-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 1023 are allowed.
Setting the DB5 bit to 1 puts the charge pump into three-state
mode. Set this bit to 0 for normal operation.
Double Buffer
Counter Reset
The DB14 bit enables or disables double buffering of
Bits[DB23:DB21] in Register 6. The Program Modes section
explains how double buffering works.
The DB4 bit is the reset bit for the R counter and the N counter
of the ADF4155. When this bit is set to 1, the RF synthesizer
N counter and R counter are held in reset. For normal
operation, set this bit to 0.
Rev. 0 | Page 20 of 32
0
L2
L2
DITHER 2
0
OFF
1
M3
M2
M1
RD2
RD1
R8
R7
R6
R5
R4
R3
R2
R1
D1
CP4
CP3
CP2
CP1
0
LVS
DB7
U4
COUNTER
RESET
CHARGE PUMP
THREE-STATE
PD
DB6 DB5 DB4
U3
U2
U1
DB3
DB2
DOUBLE BUFFER
R6, DB23 TO DB21
MUXOUT
LOGIC LEVEL
U1
0
DISABLED
0
1.8 V
0
DISABLED
1
ENABLED
1
ENABLED
1
3.3 V (DVDD)
1
ENABLED
0
1
REFERENCE DIVIDE BY 2
DISABLED
ENABLED
R9
..........
R2
R1
0
0
..........
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
1020
1
1
..........
0
1
1021
1
1
..........
1
0
1022
1
1
..........
1
1
1023
M3
M2
M1
OUTPUT
0
0
0
THREE-STATE OUTPUT
0
0
1
DVDD
0
1
0
DGND
0
1
1
R COUNTER OUTPUT
1
0
0
N COUNTER OUTPUT
1
0
1
ANALOG LOCK DETECT
1
1
0
DIGITAL LOCK DETECT
1
1
1
RESERVED
R DIVIDER (R)
CP4
CP3
CP2
CP1
ICP (mA)
4.7kΩ
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.31
0.63
0.94
1.25
1.56
1.88
2.19
2.50
2.81
3.13
3.44
3.75
4.06
4.38
4.69
5.00
1 DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 28. Register 4 (R4)
Rev. 0 | Page 21 of 32
U2
DB0
COUNTER
RESET
D1
DISABLED
LVS
DB1
C4(0) C3(1) C2(0) C1(0)
REFERENCE
DOUBLER
RD1
R10
R9
0
RD2
ON
R10
CONTROL BITS
CHARGE PUMP
THREE-STATE
0
DISABLED
1
ENABLED
U3
POWER-DOWN
0
DISABLED
1
ENABLED
U4
0
NEGATIVE
1
POSITIVE
12262-027
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
PHASE
DETECTOR
POLARITY
CHARGE PUMP
CURRENT
SETTING DBR 1
MUXOUT
LEVEL SELECT
DBR 1
10-BIT R COUNTER
RESERVED
DBR 1
DOUBLE
BUFFER
MUXOUT
RDIV2
REFERENCE
ADF4155
DOUBLER DBR 1
DITHER 2
RESERVED
Data Sheet
ADF4155
Data Sheet
REGISTER 5
Antibacklash Pulse (ABP) Select
Register 5 Control Bits
Set DB23 to 0 to select the pulsed bleed delay, Bits[DB27:DB26]
as the antibacklash pulse width. The recommended default
setting is pulse bleed delay (2.6 ns). The pulse bleed delay bits
(DB27:DB26) function as the antibacklash pulse width
irrespective of whether the pulse bleed is enabled or disabled.
With Bits[C4:C1] set to 0101, Register 5 is programmed. Figure 29
shows the input data format for programming this register.
Pulse Bleed Delay
In some cases, pulsed bleed (DB25) can improve spurious
performance compared to constant negative bleed. If enabling
pulsed bleed, disable the constant negative bleed bit (Register 6,
Bit DB12). Pulsed bleed works by adding a programmable delay
to the charge pump down pulse, thereby introducing a phase
offset in the loop and improving the linearity of the charge
pump. The advantage over the constant negative bleed is that
the programmable delay is only on for a short time within one
PFD period compared to the constant negative bleed which is
constantly on. This pulsed bleed can improve the spurious
performance. The downside of a pulsed bleed is that there is less
resolution to program the amount of bleed compared to the
constant negative bleed.
Set DB23 to 1 to use a narrow antibacklash pulse width of
1.6 ns. For PFD frequencies greater than 80 MHz, it is
recommended to use the 1.6 ns pulse width.
Cycle Slip Reduction (CSR)
Setting DB19 to 1 enables cycle slip reduction. When using
cycle slip reduction, the signal at the PFD must have a 50% duty
cycle for the cycle slip reduction to work. The charge pump
current setting must also be set to a minimum. Refer to the
Cycle Slip Reduction for Faster Lock Times section for more
information.
The pulsed bleed delay is programmed using Bits[DB27:DB26].
Selecting the pulsed bleed delay so that the phase offset is
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