6 GHz Fractional-N Frequency Synthesizer ADF4156
FEATURES
RF bandwidth to 6 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable fractional modulus Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113/ADF4106/ ADF4153 and ADF4154 frequency synthesizers Programmable RF output phase Loop filter design possible with ADISimPLL Cycle slip reduction for faster lock times
GENERAL DESCRIPTION
The ADF4156 is a 6 GHz fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a sigma-delta (Σ-Δ) based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry leading to faster lock times without the need for modifications to the loop filter. Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.
APPLICATIONS
CATV equipment Base stations for mobile radio (WiMAX, GSM, PCS, DCS, SuperCell 3G, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs, PMR Communications test equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP RSET
ADF4156
REFIN ×2 DOUBLER 5-BIT R COUNTER /2 DIVIDER VDD DGND LOCK DETECT MUXOUT OUTPUT MUX SDOUT VDD RDIV NDIV THIRD ORDER FRACTIONAL INTERPOLATOR FRACTION REG MODULUS REG INTEGER REG N COUNTER CURRENT SETTING RFCP4 RFCP3 RFCP2 RFCP1 RFINA RFINB + PHASE FREQUENCY DETECTOR – REFERENCE
CHARGE PUMP CSR
CP
HIGH Z
CE CLOCK DATA LE
32-BIT DATA REGISTER
AGND
DGND
CPGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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05863-001
ADF4156 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings............................................................ 5 Thermal Impedance ..................................................................... 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Circuit Description........................................................................... 8 Reference Input Section............................................................... 8 RF Input Stage............................................................................... 8 RF INT Divider............................................................................. 8 INT, FRAC, MOD, and R Relationship ..................................... 8 RF R Counter ................................................................................ 8 Phase Frequency Detector (PFD) and Charge Pump.............. 9 MUXOUT and LOCK Detect..................................................... 9 Input Shift Registers ..................................................................... 9 Program Modes ............................................................................ 9 Register Maps.................................................................................. 10 FRAC/INT Register, R0............................................................. 11 PHASE REGISTER, R1.............................................................. 12 MOD/R Register, R2 .................................................................. 13 Function Register, R3................................................................. 15 CLK Div Register, R4 ................................................................. 16 Reserved Bits............................................................................... 16 Initialization Sequence .............................................................. 16 RF Synthesizer: A Worked Example ........................................ 17 Modulus....................................................................................... 17 Reference Doubler and Reference Divider ............................. 17 12-Bit Programmable Modulus................................................ 17 Cycle Slip Reduction for Faster Lock Times........................... 17 Spur Mechanisms ....................................................................... 18 Spur Consistency and Fractional Spur Optimization ........... 18 PHASE RESYNC ........................................................................ 19 Low Frequency Applications .................................................... 19 Filter Design—ADIsimPLL....................................................... 19 Interfacing ................................................................................... 20 PCB Design Guidelines for Chip Scale Package .................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 22
REVISION HISTORY
5/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADF4156 SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω, unless otherwise noted. Table 1.
Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 3 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD NOISE CHARACTERISTICS Normalized Phase Noise Floor 4 Phase Noise Performance 5 5800 MHz Output 6
1 2
B Version 0.5/6.0
Unit GHz min/max
Test Conditions/Comments 1 −10 dBm min to 0 dBm max; for lower frequencies, ensure slew rate (SR) > 400 V/μs For f < 10 MHz, use a dc-coupled CMOS-compatible square wave, slew rate > 25 V/μs Biased at AVDD/2 2
10/250 0.4/AVDD 10 ±100 32
MHz min/max V p-p min/max pF max μA max MHz max
5 312.5 2.5 2.7/10 1 2 2 2 1.4 0.6 ±1 10 1.4 VDD – 0.4 100 0.4 2.7/3.3 AVDD AVDD/5.5 32 −211 −89
mA typ μA typ % typ kΩ min/max nA typ % typ % typ % typ V min V max μA max pF max V min V min μA max V max V min/V max V min/V max mA max dBc/Hz typ dBc/Hz typ
Programmable With RSET = 5.1 kΩ With RSET = 5.1 kΩ Sink and source current 0.5 V < VCP < VP – 0.5 0.5 V < VCP < VP – 0.5 VCP = VP/2
Open-drain output chosen; 1 kΩ pull-up to 1.8 V CMOS output chosen IOL = 500 μA
26 mA typical
@ VCO output @ 5 kHz offset, 25 MHz PFD frequency
Operating temperature for B version: −40°C to +85°C. AC coupling ensures AVDD/2 bias. 3 Guaranteed by design. Sample tested to ensure compliance. 4 This figure can be used to calculate phase noise for any application. Use the formula –213 + 10log(fPFD) + 20logN to calculate in-band phase noise performance as seen at the VCO output. The value given is the lowest noise mode. 5 The phase noise is measured with the EVAL-ADF4156EB1 evaluation board and the Agilent E5500 phase noise system. 6 fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 5800 MHz; N = 232; loop B/W = 20 kHz, ICP = 313 μA; lowest noise mode.
Rev. 0 | Page 3 of 24
ADF4156
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω, unless otherwise noted. Table 2.
Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width
Timing Diagram
t4
CLOCK
t5
t2
DATA DB23 (MSB) DB22
t3
DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t7
LE
t1
LE
t6
05863-002
Figure 2. Timing Diagram
Rev. 0 | Page 4 of 24
ADF4156 ABSOLUTE MAXIMUM RATINGS
TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD, unless otherwise noted. Table 3.
Parameter VDD to GND VDD to VDD VP to GND VP to VDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature Reflow Soldering Peak Temperature Time at Peak Temperature Maximum Junction Temperature Rating −0.3 V to +4 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 260°C 40 sec 150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of 200:1. This is to attenuate the SDM noise.
Rev. 0 | Page 19 of 24
ADF4156
INTERFACING
The ADF4156 has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When latch enable (LE) is high, the 29 bits that have been clocked into the input register on each rising edge of SCLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 6 for the latch truth table. The maximum allowable serial clock rate is 20 MHz. than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 ounce of copper to plug the via. The user should connect the printed circuit board thermal pad to AGND.
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the lead frame chip scale package (CP-20-1) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider
Rev. 0 | Page 20 of 24
ADF4156 OUTLINE DIMENSIONS
5.10 5.00 4.90
16 9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8° 0°
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 3.75 BCS SQ 0.75 0.55 0.35 0.05 MAX 0.02 NOM
0.60 MAX
16 15
PIN 1 INDICATOR
20 1
2.25 2.10 SQ 1.95
6 5
11 10
0.25 MIN 0.30 0.23 0.18
1.00 0.85 0.80 SEATING PLANE
12° MAX
0.80 MAX 0.65 TYP
0.50 BSC
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 24. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters
Rev. 0 | Page 21 of 24
ADF4156
ORDERING GUIDE
Model ADF4156BRUZ 1 ADF4156BRUZ-RL1 ADF4156BRUZ-RL71 ADF4156BCPZ1 ADF4156BCPZ-RL1 ADF4156BCPZ-RL71 EVAL-ADF4156EB1
1
Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C
Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option RU-16 RU-16 RU-16 CP-20-1 CP-20-1 CP-20-1
Z = Pb-free part.
Rev. 0 | Page 22 of 24
ADF4156 NOTES
Rev. 0 | Page 23 of 24
ADF4156 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05863-0-5/06(0)
Rev. 0 | Page 24 of 24
