ADF4193WCCPZ-RL7

Low Phase Noise, Fast Settling PLL Frequency Synthesizer ADF4193 Data Sheet FEATURES GENERAL DESCRIPTION New, fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 µs with phase settled by 20 µs 0.5° rms phase error at 2 GHz RF output Digitally programmable output phase RF input range up to 3.5 GHz 3-wire serial interface On-chip, low noise differential amplifier Phase noise figure of merit: −216 dBc/Hz Loop filter design possible using ADIsimPLL™ Qualified for automotive applications The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO). The Σ-Δ based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases cost, complexity, PCB area, shielding, and characterization on previous ping-pong GSM PLL architectures. APPLICATIONS GSM/EDGE base stations PHS base stations Instrumentation and test equipment FUNCTIONAL BLOCK DIAGRAM SDVDD DVDD1 DVDD2 DVDD3 AVDD1 VP1 VP2 VP3 RSET REFERENCE 4-BIT R COUNTER ×2 DOUBLER REFIN HIGH Z MUXOUT OUTPUT MUX ÷2 DIVIDER SW1 + PHASE FREQUENCY DETECTOR – CPOUT+ CHARGE + PUMP – CPOUT– VDD SW2 DGND CMR LOCK DETECT DIFFERENTIAL AMPLIFIER – AIN– + AIN+ RDIV NDIV AOUT N COUNTER SW3 FRACTIONAL INTERPOLATOR CLK DATA LE 24-BIT DATA REGISTER RFIN+ RFIN– FRACTION REG MODULUS REG INTEGER REG AGND1 AGND2 DGND1 DGND2 DGND3 SDGND SWGND 05328-001 ADF4193 Figure 1. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADF4193 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Function Register (R3) .............................................................. 19 Applications ....................................................................................... 1 Charge Pump Register (R4) ...................................................... 20 General Description ......................................................................... 1 Power-Down Register (R5) ....................................................... 21 Functional Block Diagram .............................................................. 1 Mux Register (R6) ...................................................................... 22 Revision History ............................................................................... 3 Programming .................................................................................. 23 Specifications..................................................................................... 4 Worked Example ........................................................................ 23 Timing Characteristics ................................................................ 5 Spur Mechanisms ....................................................................... 23 Absolute Maximum Ratings ............................................................ 6 Power-Up Initialization ............................................................. 24 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Changing the Frequency of the PLL and the Phase Look-Up Table ............................................................................................. 24 Typical Performance Characteristics ............................................. 9 Applications Information .............................................................. 26 Theory of Operation ...................................................................... 12 Local Oscillator for A GSM Base Station ................................ 26 Reference Input Section ............................................................. 12 Interfacing ................................................................................... 28 RF Input Stage ............................................................................. 12 PCB Design Guidelines for Chip Scale Package .................... 28 Register Map.................................................................................... 15 Outline Dimensions ....................................................................... 29 FRAC/INT Register (R0) ........................................................... 16 Ordering Guide .......................................................................... 29 MOD/R Register (R1) ................................................................ 17 Automotive Products ................................................................. 29 Phase Register (R2) .................................................................... 18 Rev. G | Page 2 of 29 Data Sheet ADF4193 REVISION HISTORY 1/15—Rev. F to Rev. G Moved Revision History Section ..................................................... 3 Changes to Figure 3........................................................................... 7 Changes to PCB Design Guidelines for Chip Scale Package Section ...............................................................................28 Deleted CP-32-2, Figure 40 ............................................................29 Updated Outline Dimensions ........................................................29 Changes to Ordering Guide ...........................................................29 3/13—Rev. E to Rev. F Added CP-32-2 Package .................................................... Universal Added Figure 40 ..............................................................................28 Changes to Ordering Guide ...........................................................28 2/13—Rev. D to Rev. E Changes to Phase Detector Frequency Parameter, Version C, Table 1 ................................................................................................. 3 Changes to Worked Example Section ...........................................22 Changes to Avoid Integer Boundary Channels Section .............24 3/12—Rev. C to Rev. D Changes to Noise Characteristics Parameter, Table 1 .................. 4 Change to Table 4 .............................................................................. 6 Updated Outline Dimensions ........................................................28 Changes to Ordering Guide ...........................................................28 1/11—Rev. B to Rev. C Changes to Features Section ............................................................ 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Ordering Guide ...........................................................28 Added Automotive Products Paragraph ......................................28 6/06—Rev A. to Rev. B Changes to Table 1 ............................................................................ 3 Changes to Figure 32 ...................................................................... 18 Changes to Power-Up Initialization Section ............................... 23 Changes to Timer Values for Tx Section and Timer Values for Rx Section ........................................................................................ 25 11/05—Rev 0. to Rev. A Updated Format ................................................................. Universal Changes to Features Section ............................................................ 1 Changes to Table 1 ............................................................................ 3 Changes to Reference Input Section ............................................. 11 Changes to RF N Divider Section ................................................. 11 Changes to the Lock Detect Section ............................................. 13 Changes to Figure 29 ...................................................................... 15 Changes to the 8-Bit INT Value Section ...................................... 15 Changes to Figure 33 ...................................................................... 19 Replaced Figure 35 .......................................................................... 21 Changes to the Σ-Δ and Lock Detect Modes Section ................ 21 Changes to the Power-Up Initialization Section ......................... 23 Changes to Table 8 .......................................................................... 23 Changes to the Local Oscillator for a GSM Base Station Section ........................................................................ 25 Changes to the Timer Values for Rx Section ............................... 25 Changes to Figure 36 ...................................................................... 26 Updates to the Outline Dimensions ............................................. 28 Changes to the Ordering Guide .................................................... 28 4/05—Revision 0: Initial Version Rev. G | Page 3 of 29 ADF4193 Data Sheet SPECIFICATIONS AVDD = DVDD = SDVDD = 3 V ± 10%, VP1, VP2 = 5 V ± 10%, VP3 = 5.35 V ± 5%, AGND = DGND = GND = 0 V, RSET = 2.4 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) RF Input Sensitivity Maximum Allowable Prescaler Output Frequency 3 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Edge Slew Rate REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency CHARGE PUMP ICP Up/Down High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage ICP Up vs. Down Matching ICP vs. VCP ICP vs. Temperature DIFFERENTIAL AMPLIFIER Input Current Output Voltage Range VCO Tuning Range Output Noise LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP1, VP2 VP3 IDD (AVDD + DVDD + SDVDD) IDD (VP1 + VP2) IDD (VP3) IDD Power-Down B Version 1 C Version 2 Unit Test Conditions/Comments 0.4/3.5 −10/0 470 0.4/3.5 −10/0 470 GHz min/max dBm min/max MHz max See Figure 21 for input circuit 10/300 10/300 MHz min/max For f > 120 MHz, set REF/2 bit = 1. For f < 10 MHz, use a dc-coupled square wave 300 0.7/VDD 0 to VDD 10 ±100 300 0.7/VDD 0 to VDD 10 ±100 V/µs min V p-p min/max V max pF max µA max 26 30 MHz max 6.6 104 5 1/4 1 0.1 1 1 6.6 104 5 1/4 1 0.1 1 1 mA typ µA typ % typ kΩ min/max nA typ % typ % typ % typ 1 1.4/(VP3 − 0.3) 1.8/(VP3 − 0.8) 7 1 1.4/(VP3 − 0.3) 1.8/(VP3 − 0.8) 7 nA typ V min/max V min/max nV/√Hz typ 1.4 0.7 ±1 10 1.4 0.7 ±2 10 V min V max µA max pF max VDD − 0.4 0.4 VDD − 0.4 0.4 V min V max 2.7/3.3 AVDD 4.5/5.5 5.0/5.65 27 27 30 10 2.7/3.3 AVDD 4.5/5.5 5.0/5.65 35 30 35 10 V min/V max V min/V max V min/V max mA max mA max mA max µA typ Rev. G | Page 4 of 29 AC-coupled CMOS-compatible With RSET = 2.4 kΩ With RSET = 2.4 kΩ Nominally RSET = 2.4 kΩ 0.75 V ≤ VCP ≤ VP – 1.5 V 0.75 V ≤ VCP ≤ VP – 1.5 V 0.75 V ≤ VCP ≤ VP – 1.5 V At 20 kHz offset IOH = 500 µA IOL = 500 µA AVDD ≤ VP1, VP2 ≤ 5.5 V VP1, VP2 ≤ VP3 ≤ 5.65 V 22 mA typ 22 mA typ 24 mA typ Data Sheet ADF4193 Parameter SW1, SW2, and SW3 RON (SW1 and SW2) RON SW3 NOISE CHARACTERISTICS Output 900 MHz 4 1800 MHz 5 Phase Noise Normalized Phase Noise Floor (PNSYNTH) 6 Normalized 1/f Noise (PN1_f) 7 B Version 1 C Version 2 Unit Test Conditions/Comments 65 75 65 75 Ω typ Ω typ −108 −102 −108 −102 dBc/Hz typ dBc/Hz typ At 5 kHz offset and 26 MHz PFD frequency At 5 kHz offset and 13 MHz PFD frequency −216 −216 dBc/Hz typ −110 −110 dBc/Hz typ At VCO output with dither off, PLL loop bandwidth = 500 kHz Measured at 10 kHz offset, normalized to 1 GHz Operating temperature range is from −40°C to +85°C. Operating temperature range is from −40°C to +105°C The prescaler value is chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 fREFIN = 26 MHz; fSTEP = 200 kHz; fRF = 900 MHz; loop bandwidth = 40 kHz. 5 fREFIN = 13 MHz; fSTEP = 200 kHz; fRF = 1800 MHz; loop bandwidth = 60 kHz. 6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider value) and 10 log(fPFD). PNSYNTH = PNTOT − 10 log(fPFD) − 20 log(N). 7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 1 2 3 TIMING CHARACTERISTICS AVDD = DVDD = 3 V ± 10%, VP1, VP2 = 5 V ± 10%, VP3 = 5.35 V ± 5%, AGND = DGND = GND = 0 V, RSET = 2.4 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 2 Limit (C Version) 2 10 10 10 15 15 10 15 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width Operating temperature is from −40°C to +85°C. Operating temperature is from −40°C to +105°C. t4 t5 CLK t3 t2 DATA DB23 (MSB) DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 LE 05238-002 1 Limit (B Version) 1 10 10 10 15 15 10 15 Figure 2. Timing Diagram Rev. G | Page 5 of 29 ADF4193 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND AVDD to DVDD, SDVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN+, RFIN− to GND Operating Temperature Range Industrial (B Version) Operating Temperature Range Automotive (W Version) Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Rating −0.3 V to +3.6 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VP + 0.3 V −0.3 V to VDD + 0.3 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. This device is a high performance RF integrated circuit with an ESD rating of 20 kHz, the 1/f noise has a negligible effect on the PLL output phase noise. Outside the loop bandwidth, the differential amplifier’s noise FM modulates the VCO. The passive filter network following the differential amplifier, shown in Figure 36, suppresses this noise contribution to below the VCO noise from offsets of 400 kHz and above. This network has a negligible effect on lock time because it is bypassed when SW3 is closed while the loop is locking. AIN– 500Ω AOUT VP3 500Ω 30kΩ Figure 27. MUXOUT Circuit Lock Detect MUXOUT can be programmed to provide a digital lock detect signal. Digital lock detect is active high. Its output goes high if there are 40 successive PFD cycles with an input error of less than 3 ns. For reliable lock detect operation with RF frequencies