ADF4196BCPZ

Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer ADF4196 Data Sheet FEATURES GENERAL DESCRIPTION Fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 μs with phase settled within 20 μs 1 degree rms phase error at 4 GHz RF output Digitally programmable output phase RF input range up to 6 GHz 3-wire serial interface On-chip, low noise differential amplifier Phase noise figure of merit: −216 dBc/Hz The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations, and the fast settling feature makes the ADF4196 suitable for pulse Doppler radar applications. The ADF4196 consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump. A differential amplifier converts the differential charge pump output to a single-ended voltage for the external voltage controlled oscillator (VCO). The sigma-delta (Σ-Δ) based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input. APPLICATIONS GSM/EDGE base stations PHS base stations Pulse Doppler radar Instrumentation and test equipment Beam-forming/phased array systems A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles within the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases the cost, complexity, PCB area, shielding, and characterization found on previous ping-pong GSM PLL architectures. FUNCTIONAL BLOCK DIAGRAM SDVDD DVDD1 DVDD2 DVDD3 AVDD VP1 VP2 VP3 RSET REFERENCE 4-BIT R COUNTER ×2 DOUBLER REFIN SW1 + PHASE FREQUENCY DETECTOR – CPOUT+ CHARGE + PUMP – CPOUT– SW2 VDD HIGH-Z MUXOUT /2 DIVIDER DGND OUTPUT MUX CMR LOCK DETECT DIFFERENTIAL AMPLIFIER – AIN– + AIN+ RDIV NDIV AOUT N COUNTER SW3 FRACTIONAL INTERPOLATOR CLK DATA LE 24-BIT DATA REGISTER RFIN+ RFIN– FRACTION REG MODULUS REG INTEGER REG AGND1 AGND2 DGND1 DGND2 DGND3 SDGND SWGND 09450-001 ADF4196 Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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Technical Support www.analog.com ADF4196 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Shift Register .................................................................... 13 Applications ....................................................................................... 1 Register Map ................................................................................... 14 General Description ......................................................................... 1 FRAC/INT Register (R0) Latch Map ....................................... 15 Functional Block Diagram .............................................................. 1 MOD/R Register (R1) Latch Map ............................................ 16 Revision History ............................................................................... 2 Phase Register (R2) Bit Latch Map .......................................... 17 Specifications..................................................................................... 3 Function Register (R3) Latch Map........................................... 18 Timing Characteristics ................................................................ 4 Charge Pump Register (R4) Latch Map .................................. 19 Absolute Maximum Ratings............................................................ 5 Power-Down Register (R5) Bit Map ........................................ 20 Thermal Resistance ...................................................................... 5 Mux Register (R6) Latch Map and Truth Table ..................... 21 Transistor Count ........................................................................... 5 Programming the ADF4196 .......................................................... 22 ESD Caution .................................................................................. 5 Worked Example ........................................................................ 22 Pin Configuration and Function Descriptions ............................. 6 Spur Mechanisms ....................................................................... 22 Typical Performance Characteristics ............................................. 8 Power-Up Initialization ............................................................. 23 Theory of Operation ...................................................................... 11 General Description ................................................................... 11 Changing the Frequency of the PLL and the Phase Lookup Table ............................................................................................. 23 Reference Input ........................................................................... 11 Applications Information .............................................................. 25 RF Input Stage ............................................................................. 11 Local Oscillator for a GSM Base Station ................................. 25 PFD and Charge Pump .............................................................. 12 Interfacing ................................................................................... 27 Differential Charge Pump ......................................................... 12 PCB Design Guidelines ............................................................. 27 Fast Lock Timeout Counters..................................................... 12 Outline Dimensions ....................................................................... 28 Differential Amplifier ................................................................ 13 Ordering Guide .......................................................................... 28 MUXOUT and Lock Detect ......................................................... 13 REVISION HISTORY 5/15—Rev. C to Rev. D Changed LFCSP_VQ to LFCSP_WQ ......................... Throughout Changes to Figure 3 .......................................................................... 6 Changed ADuC70xx Interface Section to Analog Microcontroller Interface Section ................................................ 27 Changes to Analog Microcontroller Interface Section and Figure 38 .......................................................................................... 27 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 1/13—Rev. B to Rev. C Change to Power-Up Initialization Section ................................ 23 Changes to Ordering Guide .......................................................... 28 12/11—Rev. A to Rev. B Changes to Figure 10, Figure 11, Figure 13, and Figure 14 ............................................................................................ 9 Change to Figure 31 ....................................................................... 17 10/11—Revision A: Initial Version Rev. D | Page 2 of 28 Data Sheet ADF4196 SPECIFICATIONS AVDD = DVDD1, DVDD2, DVDD3 = SDVDD = 3 V ± 10%; VP1, VP2 = 5 V ± 10%; VP3 = 5.35 V ± 5%; AGND1, AGND2 = DGND1, DGND2, DGND3 = 0 V; RSET = 2.4 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range = −40°C to +85°C. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RFIN±) RF Input Sensitivity Maximum Allowable Prescaler Output Frequency1 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Edge Slew Rate REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency CHARGE PUMP ICP Up/Down High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage ICP Up vs. Down Matching ICP vs. VCP ICP vs. Temperature DIFFERENTIAL AMPLIFIER Input Current Output Voltage Range VCO Tuning Range Output Noise LOGIC INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IINH, IINL Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLIES AVDD DVDD1, DVDD2, DVDD3 VP1, VP2 VP3 IDD (AVDD + DVDD1, DVDD2, DVDD3 + SDVDD) IDD (VP1 + VP2) IDD (VP3) IDD Power-Down Min Typ 0.4 −10 300 0.7 Max Unit Test Conditions/Comments 6 0 750 GHz dBm MHz See Figure 21 for input circuit 300 For f > 120 MHz, set REF/2 bit = 1 (Register R1) VDD 0 to VDD 10 ±100 MHz V/µs V p-p V pF µA 26 MHz 6.6 104 5 1 4 1 0.1 1 1 1 1.4 1.8 VP3 − 0.3 VP3 − 0.8 7 1.4 0.7 ±1 10 0.4 V V 3.3 AVDD 4.5 5.0 22 22 24 10 nA V V nV/√Hz V V µA pF VDD − 0.4 2.7 mA µA % kΩ nA % % % 5.5 5.65 27 27 30 Rev. D | Page 3 of 28 V V V V mA mA mA µA AC-coupled CMOS compatible RSET = 2.4 kΩ RSET = 2.4 kΩ Nominally RSET = 2.4 kΩ 0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V 0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V 0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V At 20 kHz offset IOH = 500 µA IOL = 500 µA AVDD ≤ VP1, VP2 ≤ 5.5 V VP1, VP2 ≤ VP3 ≤ 5.65 V ADF4196 Data Sheet Parameter SW1, SW2, AND SW3 On Resistance SW1 and SW2 SW3 NOISE CHARACTERISTICS Output 900 MHz2 1800 MHz3 Phase Noise Normalized Phase Noise Floor (PNSYNTH)4 Normalized 1/f Noise (PN1_f)5 Min Typ Max Unit Test Conditions/Comments 65 75 Ω Ω −108 −102 dBc/Hz dBc/Hz At 5 kHz offset and 26 MHz PFD frequency At 5 kHz offset and 13 MHz PFD frequency −216 dBc/Hz −110 dBc/Hz At VCO output with dither off, PLL loop bandwidth = 500 kHz Measured at 10 kHz offset, normalized to 1 GHz 1 Choose a prescaler value that ensures that the frequency on the RF input is less than the maximum allowable prescaler frequency (750 MHz). fREFIN = 26 MHz; fSTEP = 200 kHz; fRF = 900 MHz; loop bandwidth = 40 kHz. fREFIN = 13 MHz; fSTEP = 200 kHz; fRF = 1800 MHz; loop bandwidth = 60 kHz. 4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider value) and 10 log(fPFD). PNSYNTH = PNTOT − 10 log(fPFD) − 20 log(N). 5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL™. 2 3 TIMING CHARACTERISTICS AVDD = DVDD1, DVDD2, DVDD3 = 3 V ± 10%; VP1, VP2 = 5 V ± 10%; VP3 = 5.35 V ± 5%; AGND1, AGND2 = DGND1, DGND2, DGND3 = 0 V; RSET = 2.4 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature = −40°C to +85°C. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Limit 10 ns min 10 ns min 10 ns min 15 ns min 15 ns min 10 ns min 15 ns min Description LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Timing Diagram t4 t5 CLK t3 t2 DATA DB23 (MSB) DB22 DB2 (LSB) (CONTROL BIT C3) DB1 (LSB) (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 09450-002 LE Figure 2. Timing Diagram Rev. D | Page 4 of 28 Data Sheet ADF4196 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter AVDD to Ground AVDD to DVDD1, DVDD2, DVDD3, SDVDD VP1, VP2, VP3 to Ground VP1, VP2, VP3 to AVDD Digital I/O Voltage to Ground Analog I/O Voltage to Ground REFIN, RFIN+, RFIN− to Ground Operating Temperature Range Industrial Storage Temperature Range Maximum Junction Temperature Reflow Soldering Peak Temperature Time at Peak Temperature Rating −0.3 V to +3.6 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VP1, VP2, VP3 + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C Table 4. Thermal Resistance Package Type 32-Lead LFCSP (Paddle Soldered) θJA 27.3 Unit °C/W TRANSISTOR COUNT This device includes 75,800 metal oxide semiconductors (MOS) and 545 bipolar junction transistors (BJT). ESD CAUTION 260°C 40 sec Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. This device is a high performance RF integrated circuit with an ESD rating of