ADF4216BRU

a Dual RF PLL Frequency Synthesizers ADF4216/ADF4217/ADF4218 GENERAL DESCRIPTION FEATURES ADF4216: 550 MHz/1.2 GHz ADF4217: 550 MHz/2.0 GHz ADF4218: 550 MHz/2.5 GHz 2.7 V to 5.5 V Power Supply Selectable Charge Pump Currents Selectable Dual Modulus Prescaler IF: 8/9 or 16/17 RF: 32/33 or 64/65 3-Wire Serial Interface Power-Down Mode The ADF4216/ADF4217/ADF4218 are dual frequency synthesizers that can be used to implement local oscillators (LOs) in the upconversion and downconversion sections of wireless receivers and transmitters. They can provide the LO for both the RF and IF sections. They consist of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P+1). The A (6-bit) and B (11-bit) counters, in conjunction with the dual modulus prescaler (P/P+1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (PhaseLocked Loop) can be implemented if the synthesizers are used with an external loop filter and VCOs (Voltage Controlled Oscillators). APPLICATIONS Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Base Stations for Wireless Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Communications Test Equipment CATV Equipment Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 11-BIT IF B-COUNTER IFINB VP2 ADF4216/ADF4217/ADF4218 N = BP + A IFINA VP1 PHASE COMPARATOR IF PRESCALER CHARGE PUMP 6-BIT IF A-COUNTER REFIN CLOCK DATA LE CPIF IF LOCK DETECT OSCILLATOR 14-BIT IF R-COUNTER OUTPUT MUX 22-BIT DATA REGISTER MUXOUT SDOUT 14-BIT IF R-COUNTER RF LOCK DETECT N = BP + A 11-BIT RF B-COUNTER RFINA RFINB RF PRESCALER CHARGE PUMP 6-BIT RF A-COUNTER CPRF PHASE COMPARATOR DGNDRF AGNDRF DGNDIF DGNDIF AGNDIF REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1 (V 1 = V 2 = 3 V ⴞ 10%, 5 V ⴞ 10%; ADF4216/ADF4217/ADF4218–SPECIFICATIONS V 1, V 2 ⱕ V 1, V 2 ⱕ 6.0 V ; AGND = DGND = AGND = DGND = 0 V; T = T to T unless otherwise noted.) DD DD DD P P RF RF IF IF A MIN Parameter B Version B Chips2 Unit RF/IF CHARACTERISTICS (3 V) RF Input Frequency (RFIN) ADF4216 ADF4217 ADF4218 IF Input Frequency (IFIN) RF Input Sensitivity IF Input Sensitivity Maximum Allowable Prescaler Output Frequency3 0.2/1.2 0.2/2.0 0.5/2.5 45/550 –15/+4 –10/+4 0.2/1.2 0.2/2.0 0.5/2.5 45/550 –15/+4 –10/+4 GHz min/max GHz min/max GHz min/max MHz min/max dBm min/max dBm min/max 165 165 MHz max RF/IF CHARACTERISTICS (5 V) RF Input Frequency (RFIN) ADF4216 ADF4217 ADF4218 IF Input Frequency (IFIN) RF Input Sensitivity IF Input Sensitivity Maximum Allowable Prescaler Output Frequency3 0.2/1.2 0.2/2.0 0.5/2.5 25/550 –15/+4 –10/+4 0.2/1.2 0.2/2.0 0.5/2.5 25/550 –15/+4 –10/+4 GHz min/max GHz min/max GHz min/max MHz min/max dBm min/max dBm min/max 200 200 MHz max REFIN CHARACTERISTICS REFIN Input Frequency 5/40 5/40 MHz min/max REFIN Input Sensitivity4 0.5 0.5 V p-p min REFIN Input Capacitance REFIN Input Current 10 ± 100 10 ± 100 pF max µA max PHASE DETECTOR Phase Detector Frequency5 40 40 MHz max CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature 4.5 1.125 1 1 1 10 10 4.5 1.125 1 1 1 10 10 mA typ mA typ % typ nA typ % typ % max % typ LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance Oscillator Input Current 0.8 × VDD 0.2 × VDD ±1 10 ± 100 0.8 × VDD 0.2 × VDD ±1 10 ± 100 V min V max µA max pF max µA max LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage VDD – 0.4 0.4 VDD – 0.4 0.4 V min V max POWER SUPPLIES VDD1 VDD2 VP 2.7/5.5 VDD1 VDD1/6.0 2.7/5.5 VDD1 VDD1/6.0 V min/V max V min/V max –2– DD MAX Test Conditions/Comments See Figure 3 for Input Circuit. For lower frequency operation (below the minimum stated) use a square wave source. See Figure 3 for Input Circuit. For lower frequency operation (below the minimum stated) use a square wave source. For f < 5 MHz, use dc-coupled square wave (0 to VDD). AC-Coupled. When DC-Coupled: 0 to VDD max (CMOS-Compatible) 0.5 V ⱕ VCP ⱕ VP – 0.5 V VCP = VP /2 IOH = 500 µA IOL = 500 µA AVDD ⱕ VP ⱕ 6.0 V REV. 0 ADF4216/ADF4217/ADF4218 Parameter POWER SUPPLIES (Continued) IDD (RF + IF)6 ADF4216 ADF4217 ADF4218 IDD (RF Only) ADF4216 ADF4217 ADF4218 IDD (IF Only) ADF4216 ADF4217 ADF4218 IP (IP1 + IP2) Low-Power Sleep Mode NOISE CHARACTERISTICS Phase Noise Floor7 Phase Noise Performance8 ADF4216, ADF4217, ADF4218 (IF)9 ADF4216 (RF): 900 MHz Output10 ADF4217 (RF): 900 MHz Output10 ADF4218 (RF): 900 MHz Output10 ADF4216 (RF): 836 MHz Output11 ADF4217 (RF): 1750 MHz Output12 ADF4217 (RF): 1750 MHz Output13 ADF4218 (RF): 1960 MHz Output14 Spurious Signals ADF4216 ADF4217, ADF4218 (IF)9 ADF4216 (RF): 900 MHz Output10 ADF4217 (RF): 900 MHz Output10 ADF4218 (RF): 900 MHz Output10 ADF4216 (RF): 836 MHz Output11 ADF4217 (RF): 1750 MHz Output12 ADF4217 (RF): 1750 MHz Output13 ADF4218 (RF): 1960 MHz Output14 B Version B Chips2 Unit Test Conditions/Comments 18 21 25 9 12 14 mA max mA max mA max See TPC 22 and TPC 23 9.0 mA typical at VDD = 3 V and TA = 25°C 12 mA typical at VDD = 3 V and TA = 25°C 14 mA typical at VDD = 3 V and TA = 25°C 10 14 18 5 7 9 mA max mA max mA max 5.0 mA typical at VDD = 3 V and TA = 25°C 7.0 mA typical at VDD = 3 V and TA = 25°C 9.0 mA typical at VDD = 3 V and TA = 25°C 9 9 9 0.6 5 4.5 4.5 4.5 0.6 5 mA max mA max mA max mA max µA max 4.5 mA typical at VDD = 3 V and TA = 25°C 4.5 mA typical at VDD = 3 V and TA = 25°C 4.5 mA typical at VDD = 3 V and TA = 25°C TA = 25°C 0.5 µA typical –171 –164 –171 –164 dBc/Hz typ dBc/Hz typ –91 –87 –88 –90 –78 –85 –66 –84 –91 –87 –88 –90 –78 –85 –66 –84 dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ @ 25 kHz PFD Frequency @ 200 kHz PFD Frequency @ VCO Output @ 1 kHz Offset and 200 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 300 Hz Offset and 30 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 200 Hz Offset and 10 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency –97/–106 –98/–106 –91/–100 –80/–84 –80/–84 –88/–90 –65/–73 –80/–84 –97/–106 –98/–106 –91/–100 –80/–84 –80/–84 –88/–90 –65/–73 –80/–84 dB typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 30 kHz/60 kHz and 30 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 10 kHz/20 kHz and 10 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency NOTES 1 Operating temperature range is as follows: B Version: –40°C to +85°C. 2 The B Chip specifications are given as typical values. 3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is less than this value. 4 VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels. 5 Guaranteed by design. Sample tested to ensure compliance. 6 P = 16; RFIN = 900 MHz; IFIN = 540 MHz. 7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). 8 The phase noise is measured with the EVAL-ADF421XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (f REFOUT = 10 MHz @ 0 dBm). 9 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fIF = 540 MHz; N = 2700; Loop B/W = 20 kHz. 10 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz. 11 fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop B/W = 3 kHz. 12 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz. 13 fREFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz. 14 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz. Specifications subject to change without notice. REV. 0 –3– ADF4216/ADF4217/ADF4218 TIMING CHARACTERISTICS (VDD1 = VDD2 = 3 V ⴞ 10%, 5 V ⴞ 10%; VP1, VP2 = VDD , 5 V ⴞ 10%; AGND = DGND = 0 V; TA = TMIN to TMAX unless otherwise noted.) Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 t2 t3 t4 t5 t6 10 10 25 25 10 20 ns min ns min ns min ns min ns min ns min DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulsewidth NOTES Guaranteed by design but not production tested. Specification subject to change without notice. t3 t4 CLOCK t1 DATA DB21 (MSB) t2 DB20 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE t5 LE Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS 1, 2 Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C (TA = 25°C unless otherwise noted) VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V Digital I/O Voltage to GND . . . . . . –0.3 V to DVDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V REFIN, RFINA, RFINB, IFINA, IFINB to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C TSSOP θJA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high-performance RF integrated circuit with an ESD rating of < 2 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = AGND = DGND = 0 V. TRANSISTOR COUNT 11749 (CMOS) and 522 (Bipolar). ORDERING GUIDE Model Temperature Range Package Description Package Option* ADF4216BRU ADF4217BRU ADF4218BRU –40°C to +85°C –40°C to +85°C –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) RU-20 RU-20 RU-20 *Contact the factory for chip availability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4216/ADF4217/ADF4218 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 ADF4216/ADF4217/ADF4218 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 VDD1 2 3 V P1 CPRF 4 5 6 DGNDRF RFINA RFINB 7 8 AGNDRF REFIN 9 10 DGNDIF MUXOUT 11 CLK 12 DATA 13 LE 14 15 AGNDIF IFINB 16 17 18 IFINA DGNDIF CPIF 19 20 V P2 VDD2 Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VDD1 should have a value of between 2.7 V and 5.5 V. VDD1 must have the same potential as VDD2. Power Supply for the RF Charge Pump. This should be greater than or equal to VDD. Output from the RF Charge Pump. When enabled this provides ± ICP to the external loop filter, which in turn drives the external VCO. Ground Pin for the RF Digital Circuitry. Input to the RF Prescaler. This low-level input signal is normally ac-coupled to the external VCO. Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. Ground Pin for the RF Analog Circuitry. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. Ground Pin for the IF Digital (Interface and Control Circuitry). This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled Reference Frequency to be accessed externally. See Table V. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. Ground Pin for the IF Analog Circuitry. Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. Input to the IF Prescaler. This low-level input signal is normally ac-coupled to the external VCO. Ground Pin for the IF Digital, Interface, and Control Circuitry. Output from the IF Charge Pump. When enabled this provides ± ICP to the external loop filter, which in turn drives the external VCO. Power Supply for the IF Charge Pump. This should be greater than or equal to VDD. Positive Power Supply for the IF, Interface, and Oscillator Sections. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VDD2 should have a value of between 2.7 V and 5.5 V. VDD2 must have the same potential as VDD1. PIN CONFIGURATION VDD1 1 20 VDD2 VP 1 2 19 VP2 3 18 CPIF DGNDRF 4 17 DGNDIF 16 IFINA CPRF RFINA 5 RFINB 6 AGNDRF 7 TSSOP ADF4216/ ADF4217/ ADF4218 REFIN 8 REV. 0 15 IFINB 14 AGNDIF 13 LE DGNDIF 9 12 DATA MUXOUT 10 11 CLK –5– ADF4216/ADF4217/ADF4218 –Typical Performance Characteristics 0 FREQ 0.0 0.15 0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95 1.05 1.15 1.25 MAGS11 0.957111193 0.963546793 0.953621785 0.953757706 0.929831379 0.908459709 0.897303634 0.876862863 0.849338092 0.858403269 0.841888714 0.840354983 0.822165839 ANGS11 –3.130429321 –6.686426265 –11.19913586 –15.35637483 –20.3793432 –22.69144845 –27.07001443 –31.32240763 –33.68058163 –38.57674885 –41.48606772 –45.97597958 –49.19163116 FREQ 1.35 1.45 1.55 1.65 1.75 1.85 1.95 2.05 2.15 2.25 2.35 2.45 2.55 IMPEDANCE – OHMS 50 MAGS11 0.816886959 0.825983016 0.791737125 0.770543186 0.793897072 0.745765233 0.7517547 0.745594889 0.713387801 0.711578577 0.698487131 0.669871818 0.668353367 REFERENCE LEVEL = –4.2dBm –10 VDD = 3V, VP = 5V ICP = 4.375mA ANGS11 –51.80711782 –56.20373378 –61.21554647 –61.88187496 –65.39516615 –69.24884474 –71.21608147 –75.93169947 –78.8391674 –81.71934806 –85.49067481 –88.41958754 –91.70921678 –20 OUTPUT POWER – dB FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD GHz S MA R PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz –30 RES. BANDWIDTH = 1kHz –40 VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS –50 AVERAGES = 30 –60 –70 –90dBc –80 –90 –100 –400kHz TPC 1. S-Parameter Data for the AD4218 RF Input (Up to 2.5 GHz) 900MHz +200kHz +400kHz TPC 4. ADF4218 RF Reference Spurs (900 MHz, 200 kHz, 20 kHz) 10dB/DIVISION –40 0 VDD = 3.3V VP = 3.3V –5 –200kHz RL = –40dBc/Hz RMS NOISE = 0.55ⴗ –50 PHASE NOISE – dBc/Hz RF INPUT POWER – dBm –60 –10 TA = +85ⴗC –15 TA = –40ⴗC –20 –25 0.55ⴗ rms –70 –80 –90 –100 –110 –120 –30 –35 –130 TA = +25ⴗC 0 0.5 1.5 2 1 RF INPUT FREQUENCY – GHz 2.5 –140 100Hz 3 TPC 2. Input Sensitivity for the ADF4218 (RF) 10dB/DIVISION –40 REFERENCE LEVEL = –4.2dBm VDD = 3V, VP = 5V LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz –40 VIDEO BANDWIDTH = 10Hz –50 SWEEP = 1.9 SECONDS AVERAGES = 19 –60 –90dBc/Hz –70 0.65ⴗ rms –70 –80 –90 –100 –110 –80 –120 –90 –130 –100 –2kHz –1kHz 900MHz +1kHz RMS NOISE = 0.65ⴗ –60 PFD FREQUENCY = 200kHz –30 RL = –40dBc/Hz –50 ICP = 4.375mA PHASE NOISE – dBc/Hz OUTPUT POWER – dB –20 1MHz TPC 5. ADF4218 RF Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz) 0 –10 FREQUENCY OFFSET FROM 900MHz CARRIER –140 100Hz +2kHz TPC 3. ADF4218 RF Phase Noise (900 MHz, 200 kHz, 20 kHz) FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz TPC 6. ADF4218 RF Integrated Phase Noise (900 MHz, 200 kHz, 35 kHz) –6– REV. 0 ADF4216/ADF4217/ADF4218 0 0 REFERENCE LEVEL = –4.2dBm –10 –20 VDD = 3V, VP = 5V ICP = 4.375mA –10 PFD FREQUENCY = 200kHz –20 POWER OUTPUT – dB OUTPUT POWER – dB RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz –40 SWEEP = 2.5 SECONDS –50 AVERAGES = 30 –60 –70 –89dBc –80 PFD FREQUENCY = 30kHz –30 RES. BANDWIDTH = 3Hz –40 VIDEO BANDWIDTH = 3Hz SWEEP = 255 SECONDS –50 POSITIVE PEAK DETECT MODE –60 –78dBc/Hz –70 –90 –100 –400kHz –200kHz 900MHz +200kHz +400kHz –80kHz TPC 7. ADF4218 RF Reference Spurs (900 MHz, 200 kHz, 35 kHz) –40kHz 1750MHz +40kHz +80kHz TPC 10. ADF4218 RF Reference Spurs (1750 MHz, 30 kHz, 3 kHz) –120 0 REFERENCE LEVEL = –8.0dBm –10 VDD = 3V, VP = 5V VDD = 3V VP = 5V ICP = 4.375mA –130 PFD FREQUENCY = 30kHz –20 –30 PHASE NOISE – dBc/Hz LOOP BANDWIDTH = 3kHz OUTPUT POWER – dB ICP = 4.375mA –80 –90 –100 VDD = 3V, VP = 5V LOOP BANDWIDTH = 3kHz LOOP BANDWIDTH = 35kHz –30 REFERENCE LEVEL = –5.7dBm RES. BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10kHz –40 SWEEP = 477ms –50 AVERAGES = 10 –60 –70 –80 –140 –150 –160 –74dBc/Hz –170 –90 –100 –180 –400Hz –200Hz 1750MHz +200Hz +400Hz TPC 8. ADF4218 RF Phase Noise (1750 MHz, 30 kHz, 3 kHz) 10dB/DIVISION –40 RL = –40dBc/Hz 10 100 1000 PHASE DETECTOR FREQUENCY – kHz 1 TPC 11. ADF4218 RF Phase Noise vs. PFD Frequency RMS NOISE = 1.8ⴗ –60 –50 VDD = 3V VP = 3V PHASE NOISE – dBc/Hz –60 PHASE NOISE – dBc/Hz 10000 –70 1.8ⴗ rms –80 –90 –100 –110 –70 –80 –90 –120 –130 –140 100Hz FREQUENCY OFFSET FROM 1750MHz CARRIER –100 –40 1MHz TPC 9. ADF4218 RF Integrated Phase Noise (1750 MHz, 30 kHz, 3 kHz) REV. 0 –20 0 20 40 TEMPERATURE – ⴗC 60 80 100 TPC 12. ADF4218 RF Phase Noise vs. Temperature (900 MHz, 200 kHz, 20 kHz) –7– ADF4216/ADF4217/ADF4218 10dB/DIVISION –40 –60 RMS NOISE = 0.52ⴗ –50 VDD = 3V VP = 5V FIRST REFERENCE SPUR – dBc RL = –40dBc/Hz –60 PHASE NOISE – dBc/Hz –70 –80 –90 0.60ⴗ rms –70 –80 –90 –100 –110 –120 –130 –100 –40 0 –20 20 40 TEMPERATURE – ⴗC 60 80 –140 100Hz 100 TPC 13. ADF4218 RF Reference Spurs vs. Temperature (900 MHz, 200 kHz, 20 kHz) 0 FIRST REFERENCE SPUR – dBc –15 OUTPUT POWER – dB –35 –45 –55 –65 –75 PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz –40 VIDEO BANDWIDTH = 10Hz –50 SWEEP = 2.5 SECONDS AVERAGES = 30 –60 –70 –80 –90 2 3 TUNING VOLTAGE – Volts 4 ICP = 5mA –30 –95 1 VDD = 3V, VP = 5V –20 –85 0 REFERENCE LEVEL = –4.2dBm –10 VDD = 3V VP = 5V –25 –88.0dBc –100 5 –400kHz TPC 14. ADF4218 RF Reference Spurs vs. VTUNE (900 MHz, 200 kHz, 20 kHz) –200kHz 900MHz +200kHz +400kHz TPC 17. ADF4218 IF Reference Spurs (540 MHz, 200 kHz, 20 kHz) –120 0 VDD = 3V VP = 5V VDD = 3V, VP = 5V ICP = 4.375mA –130 –20 PFD FREQUENCY = 200kHz –30 LOOP BANDWIDTH = 20kHz PHASE NOISE – dBc/Hz REFERENCE LEVEL = –4.2dBm –10 OUTPUT POWER – dB 1MHz TPC 16. ADF4218 IF Integrated Phase Noise (540 MHz, 200 kHz, 20 kHz) –5 –105 FREQUENCY OFFSET FROM 900MHz CARRIER RES. BANDWIDTH = 10Hz –40 VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS –50 AVERAGES = 19 –60 –89dBc/Hz –70 –80 –140 –150 –160 –170 –90 –100 –180 –2kHz –1kHz 900MHz +1kHz +2kHz TPC 15. ADF4218 IF Phase Noise (540 MHz, 200 kHz, 20 kHz) 1 10 100 1000 PHASE DETECTOR FREQUENCY – kHz 10000 TPC 18. ADF4218 IF Phase Noise vs. PFD Frequency –8– REV. 0 ADF4216/ADF4217/ADF4218 –60 3.0 VDD = 3V VP = 3V VDD = 3V VP = 3V 2.5 PHASE NOISE – dBc/Hz –70 DIDD – mA 2.0 –80 1.5 1.0 –90 0.5 –100 –40 0 –20 20 40 TEMPERATURE – ⴗC 60 80 0 100 TPC 19. ADF4218 IF Phase Noise vs. Temperature (540 MHz, 200 kHz, 20 kHz) 50 100 150 PRESCALER OUTPUT FREQUENCY – MHz 200 TPC 22. DIDD vs. Prescaler Output Frequency (ADF4218, RF Only) 10 –60 9 VDD = 3V VP = 5V FIRST REFERENCE SPUR – dBc 0 ADF4218 8 –70 AIDD – mA 7 –80 6 ADF4217 5 4 ADF4216 3 –90 2 1 –100 –40 0 –20 20 40 TEMPERATURE – ⴗC 60 80 0 100 TPC 20. ADF4218 IF Reference Spurs vs. Temperature (540 MHz, 200 kHz, 20 kHz) FIRST REFERENCE SPUR – dBc VDD = 3V VP = 5V –25 –35 –45 –55 –65 –75 –85 –95 –105 0 1 2 3 TUNING VOLTAGE – Volts 4 5 TPC 21. ADF4218 IF Reference Spurs vs. VTUNE (900 MHz, 200 kHz, 20 kHz) REV. 0 64/65 TPC 23. ADF4218 AIDD vs. Prescaler Value (RF) –5 –15 32/33 PRESCALER VALUE –9– ADF4216/ADF4217/ADF4218 CIRCUIT DESCRIPTION Pulse Swallow Function REFERENCE INPUT SECTION The A and B counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows: The reference input stage is shown below in Figure 2. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. POWER-DOWN CONTROL NC 100k⍀ fVCO = [(P × B) + A] × fREFIN/R fVCO = Output frequency of external voltage controlled oscillator (VCO). P = Preset modulus of dual modulus prescaler (8/9, 16/17, etc.). B = Preset Divide Ratio of binary 11-bit counter (1 to 2047). A = Preset Divide Ratio of binary 6-bit A counter (0 to 63). SW2 REFIN TO R COUNTER NC BUFFER SW1 fREFIN = Output frequency of the external reference frequency oscillator. SW3 NO R = Preset divide ratio of binary 14-bit programmable reference counter (1 to 16383). Figure 2. Reference Input Stage R COUNTER IF/RF INPUT STAGE The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. The IF/RF input stage is shown in Figure 3. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler. BIAS GENERATOR AVDD 2k⍀ N = BP+A 2k⍀ TO PFD 11-BIT B COUNTER RFINA FROM IF/RF INPUT STAGE PRESCALER P/P+1 LOAD 6-BIT A COUNTER MODULUS CONTROL RFINB LOAD N DIVIDER AGND Figure 3. IF/RF Input Stage Figure 4. A and B Counters PRESCALER The dual modulus prescaler (P/P+1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). This prescaler, operating at CML levels, takes the clock from the IF/RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. It is based on a synchronous 4/5 core. PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 5 is a simplified schematic. The prescaler is selectable. On the IF side it can be set to either 8/9 (DB20 of the IF AB Counter Latch set to 0) or 16/17 (DB20 set to 1). On the RF side it can be set to 64/65 (DB20 of the RF AB Counter Latch set to 0) or 32/33 (DB20 set to 1). See Tables IV and VI. HI D1 Q1 UP U1 ⴙ IN CLR1 DELAY ELEMENT U3 CHARGE PUMP CP A AND B COUNTERS The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The devices are guaranteed to work when the prescaler output is 165 MHz or less. Typically they will work with 200 MHz output from the prescaler. –10– HI CLR2 DOWN D1 Q1 U1 – IN Figure 5. PFD Simplified Schematic REV. 0 ADF4216/ADF4217/ADF4218 MUXOUT AND LOCK DETECT The output multiplexer on the ADF4216 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by P3, P4, P11 and P12. See Tables III and V. Figure 6 shows the MUXOUT section in block diagram form. 2. The IF Counter Reset mode resets the R and N counters in the IF section and also puts the IF charge pump into threestate. The RF Counter Reset mode resets the R and N counters in the RF section and also puts the RF charge pump into three-state. The IF and RF Counter Reset mode does both of the above. Upon removal of the reset bits, the N counter resumes counting in close alignment with the R counter (maximum error is one prescaler output cycle). DVDO IF ANALOG LOCK DETECT IF R COUNTER OUTPUT IF N COUNTER OUTPUT IF/RF ANALOG LOCK DETECT MUX CONTROL MUXOUT 3. The Fastlock mode uses MUXOUT to switch a second loop filter damping resistor to ground during Fastlock operation. Activation of Fastlock occurs whenever RF CP Gain in the RF Reference counter is set to one. RF R COUNTER OUTPUT RF N COUNTER OUTPUT POWER-DOWN RF ANALOG LOCK DETECT It is possible to program the ADF4216 family for either synchronous or asynchronous power-down on either the IF or RF side. DGND Figure 6. MUXOUT Circuit Lock Detect MUXOUT can be programmed for analog lock detect. The Nchannel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected it is high with narrow low-going pulses. INPUT SHIFT REGISTER The functional block diagram for the ADF4216 family is shown on Page 1. The main blocks include a 22-bit input shift register, a 14-bit R counter and an 17-bit N counter, comprising a 6-bit A counter and an 11-bit B counter. Data is clocked into the 22bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs DB1, DB0 as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table I. Table I. C2, C1 Truth Table Control Bits C2 C1 Data Latch 0 0 1 1 IF R Counter IF AB Counter (and Prescaler Select) RF R Counter RF AB Counter (and Prescaler Select) 0 1 0 1 PROGRAM MODES Synchronous IF Power-Down Programming a “1” to P7 of the ADF4216 family will initiate a power-down. If P2 of the ADF4216 family has been set to “0” (normal operation), a synchronous power-down is conducted. The device will automatically put the charge pump into threeState and then complete the power-down. Asynchronous IF Power-Down If P2 of the ADF4216 family has been set to “1” (three-state the IF charge pump), and P7 is subsequently set to “1,” then an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the “1” to the IF power-down bit (P7). Synchronous RF Power-Down Programming a “1” to P16 of the ADF4216 family will initiate a power-down. If P10 of the ADF4216 family has been set to “0” (normal operation), a synchronous power-down is conducted. The device will automatically put the charge pump into three-state and then complete the power-down. Asynchronous RF Power-Down If P10 of the ADF4216 families has been set to “1” (three-state the RF charge pump), and P16 is subsequently set to “1,” an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the “1” to the RF power-down bit (P16). Activation of either synchronous or asynchronous power-down forces the IF/RF loop’s R and N dividers to their load state conditions and the IF/RF input section is debiased to a high impedance state. The REFIN oscillator circuit is only disabled if both the IF and RF power-downs are set. Table III and Table V show how to set up the Program Modes in the ADF4216 family. The following should be noted: The input register and latches remain active and are capable of loading and latching data during all the power-down modes. 1. IF and RF Analog Lock Detect indicate when the PLL is in lock. When the loop is locked and either IF or RF Analog Lock Detect is selected, the MUXOUT pin will show a logic high with narrow low-going pulses. When the IF/RF Analog Lock Detect is chosen, the locked condition is indicated only when both IF and RF loops are locked. The IF/RF section of the devices will return to normal powered up operation immediately upon LE latching a “0” to the appropriate power-down bit. REV. 0 –11– ADF4216/ADF4217/ADF4218 Table II. ADF4216 Family Latch Summary IF FO IF LOCK DETECT THREE-STATE CPIF IF CP GAIN IF PD POLARITY NOT USED IF REFERENCE COUNTER LATCH DB21 DB20 DB19 DB18 DB17 DB16 P4 P3 P2 P5 P1 CONTROL BITS 14-BIT REFERENCE COUNTER, R DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) IF PRESCALER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 NOT USED IF POWER-DOWN IF AB COUNTER LATCH 11-BIT B COUNTER DB8 CONTROL BITS 6-BIT A COUNTER DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1) RE FO RF LOCK DETECT THREE-STATE CPRF RF CP GAIN RF PD POLARITY NOT USED RF REFERENCE COUNTER LATCH DB21 DB20 DB19 DB18 DB17 DB16 P4 P3 P2 P5 P1 CONTROL BITS 14-BIT REFERENCE COUNTER, R DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (1) C1 (0) RF PRESCALER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 NOT USED RF POWER-DOWN RF AB COUNTER LATCH 11-BIT B COUNTER –12– DB8 CONTROL BITS 6-BIT A COUNTER DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A6 A5 A4 A3 A2 A1 C2 (1) C1 (1) REV. 0 ADF4216/ADF4217/ADF4218 IF FO IF LOCK DETECT THREE-STATE CPIF IF CP GAIN IF PD POLARITY Table III. IF Reference Counter Latch Map DB21 DB20 DB19 DB18 DB17 P4 P3 P2 P5 P1 REV. 0 CONTROL BITS 14-BIT REFERENCE COUNTER, R DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 0 1 . . . 1 1 1 1 0 1 1 0 . . . 0 0 1 1 1 0 1 0 . . . 0 1 0 1 1 2 3 4 . . . 16380 16381 16382 16383 P1 PHASE DETECTOR POLARITY 0 1 NEGATIVE POSITIVE P5 ICP 0 1 1.25mA 4.375mA P2 CHARGE PUMP 0 1 OUTPUT NORMAL THREE-STATE FROM RFR LATCH P12 P11 P4 P3 MUXOUT 0 0 0 0 LOGIC LOW STATE 0 0 0 0 0 1 1 1 0 X X 1 1 X X 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 1 IF ANALOG LOCK DETECT IF REFERENCE DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT RF/IF ANALOG LOCK DETECT RF REFERENCE DIVIDER RF N DIVIDER FASTLOCK OUTPUT SWITCH ON AND CONNECTED TO MUXOUT IF COUNTER RESET RF COUNTER RESET IF AND RF COUNTER RESET –13– ADF4216/ADF4217/ADF4218 IF POWER-DOWN IF PRESCALER Table IV. IF AB Counter Latch Map DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 11-BIT B COUNTER B11 B10 B9 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 P6 IF PRESCALER 0 1 8/9 16/17 P7 IF SECTION 0 1 NORMAL OPERATION POWER-DOWN .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... CONTROL BITS 6-BIT A COUNTER DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1) A6 A5 A4 A3 A2 A1 X X X X . . . X X X X X X . . . X X 0 0 0 0 . . . 1 1 0 0 0 0 . . . 1 1 0 0 1 1 . . . 1 1 0 1 0 1 . . . 0 1 B3 B2 B1 B COUNTER DIVIDER RATIO 0 0 0 0 . . . 1 1 1 1 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 NOT ALLOWED NOT ALLOWED NOT ALLOWED 3 . . . 2044 2045 2046 2047 A COUNTER DIVIDE RATIO 0 1 2 3 14 15 N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER THAN OR EQUAL TO A. TO ENSURE CONTINUOUSLY ADJACENT VALUES OF N, NMIN IS (P2 – P). –14– REV. 0 ADF4216/ADF4217/ADF4218 RF FO RF LOCK DETECT THREE-STATE CPRF RF CP GAIN RF PD POLARITY Table V. RF Reference Counter Latch Map DB21 DB20 DB19 DB18 DB17 P12 P11 P10 P13 P9 DB16 P9 0 1 REV. 0 CONTROL BITS 14-BIT REFERENCE COUNTER, R ICP 0 1 1.25mA 4.375mA CHARGE PUMP 0 1 OUTPUT NORMAL THREE-STATE DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (1) C1 (0) R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 0 1 . . . 1 1 1 1 0 1 1 0 . . . 0 0 1 1 1 0 1 0 . . . 0 1 0 1 1 2 3 4 . . . 16380 16381 16382 16383 PHASE DETECTOR POLARITY NEGATIVE POSITIVE P13 P10 DB15 P12 P11 FROM IFR LATCH P4 P3 MUXOUT 0 0 0 0 0 X 0 0 1 0 1 0 LOGIC LOW STATE IF ANALOG LOCK DETECT IF REFERENCE DIVIDER OUTPUT 0 0 0 X 1 1 1 0 0 1 0 1 IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT RF/IF ANALOG LOCK DETECT 1 1 1 X X 0 0 0 1 0 1 0 RF REFERENCE DIVIDER RF N DIVIDER FASTLOCK OUTPUT SWITCH ON AND CONNECTED TO MUXOUT 1 1 1 0 1 1 1 1 1 1 0 1 IF COUNTER RESET RF COUNTER RESET IF AND RF COUNTER RESET –15– ADF4216/ADF4217/ADF4218 RF POWER-DOWN RF PRESCALER Table VI. RF AB Counter Latch Map DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P16 P14 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 11-BIT B COUNTER B11 B10 B9 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 P14 RF PRESCALER 0 1 64/65 32/33 P16 RF SECTION 0 1 NORMAL OPERATION POWER-DOWN .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... CONTROL BITS 6-BIT A COUNTER DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A6 A5 A4 A3 A2 A1 C2 (1) C1 (1) A6 A5 A4 A3 A2 A1 X X X X . . . X X X X X X . . . X X 0 0 0 0 . . . 1 1 0 0 0 0 . . . 1 1 0 0 1 1 . . . 1 1 0 1 0 1 . . . 0 1 B3 B2 B1 B COUNTER DIVIDE RATIO 0 0 0 0 . . . 1 1 1 1 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 NOT ALLOWED NOT ALLOWED NOT ALLOWED 3 . . . 2044 2045 2046 2047 A COUNTER DIVIDE RATIO 0 1 2 3 14 15 N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER THAN OR EQUAL TO A. FOR ENSURE CONTINUOUSLY ADJACENT VALUES OF N, NMIN IS (P2 – P). –16– REV. 0 ADF4216/ADF4217/ADF4218 IF SECTION Programmable IF Reference (R) Counter If control bits C2, C1 are 0, 0 then the data is transferred from the input shift register to the 14 Bit IF R counter. Table III shows the input shift register data format for the IF R counter and the divide ratios possible. IF Phase Detector Polarity P1 sets the IF Phase Detector Polarity. When the IF VCO characteristics are positive, this should be set to “1.” When they are negative, it should be set to “0.” See Table III. IF Charge Pump Three-State P2 puts the IF charge pump into three-state mode when programmed to a “1.” It should be set to “0” for normal operation. See Table III. IF Charge Pump Currents P5 sets the IF Charge Pump current. With P5 set to “0,” ICP is 1.25 mA. With P5 set to “1,” ICP is 4.375 mA. See Table III. Programmable IF AB Counter If control bits C2, C1 are 0, 1, the data in the input register is used to program the IF AB counter. The AB counter consists of a 6-bit swallow counter (A counter) and 11-bit programmable counter (B counter). Table IV shows the input register data format for programming the IF AB counter and the divide ratios possible. IF Prescaler Value P6 in the IF AB Counter Latch sets the IF prescaler value. Either 8/9 or 16/17 is available. See Table IV. IF Power-Down Table III and Table V show the power-down bits in the ADF4216 family. See Power-Down section for functional description. RF SECTION Programmable RF Reference (R) Counter If control bits C2, C1 are 1, 0, the data is transferred from the input shift register to the 14-bit RFR counter. Table V shows the input shift register data format for the RFR counter and the divide ratios possible. RF Phase Detector Polarity P9 sets the IF Phase Detector Polarity. When the RF VCO characteristics are positive this should be set to “1.” When they are negative it should be set to “0.” See Table V. RF Charge Pump Three-State P10 puts the RF charge pump into three-state mode when programmed to a “1.” It should be set to “0” for normal operation. See Table V. RF Program Modes Table III and Table V show how to set up the Program Modes in the ADF4216 family. RF Charge Pump Currents programmable counter (B Counter). Table VI shows the input register data format for programming the RF N counter and the divide ratios possible. RF Prescaler Value P14 in the RF AB Counter Latch sets the RF prescaler value. Either 32/33 or 64/65 is available. See Table VI. RF Power-Down Table IV and Table VI show the power-down bits in the ADF4216 family. See Power-Down section for functional description. RF Fastlock The RF CP Gain bit (P17) of the RF N register in the ADF4210 family is the Fastlock Enable Bit. Only when this is “1” is IF Fastlock enabled. When Fastlock is enabled, the RF CP current is set to its maximum value. Also an extra loop filter damping resistor to ground is switched in using the FLO pin, thus compensating for the change in loop characteristics while in Fastlock. Since the RF CP Gain bit is contained in the RF N Counter, only one write is needed both to program a new output frequency and to initiate Fastlock. To come out of Fastlock, the RF CP Gain bit on the RF N register must be set to “0.” See Table VI. APPLICATIONS SECTION Local Oscillator for GSM Handset Receiver Figure 7 shows the ADF4216 being used in a classic superheterodyne receiver to provide the required LOs (Local Oscillators). In this circuit, the reference input signal is applied to the circuit at REFIN and is being generated by a 13 MHz TCXO (Temperature Controlled Crystal Oscillator). In order to have a channel spacing of 200 kHz (the GSM standard), the reference input must be divided by 65, using the on-chip reference counter. The RF output frequency range is 1050 MHz to 1085 MHz. Loop filter component values are chosen so that the loop bandwidth is 20 kHz. The synthesizer is set up for a charge pump current of 4.375 mA and the VCO sensitivity is 15.6 MHz/V. The IF output is fixed at 125 MHz. The IF loop bandwidth is chosen to be 20 kHz with a channel spacing of 200 kHz. Loop filter component values are chosen accordingly. Local Oscillator for WCDMA Receiver Figure 8 shows the ADF4217 being used to generate the local oscillator frequencies for a Wideband CDMA (WCDMA) system. The RF output range needed is 1720 MHz to 1780 MHz. The VCO190–1750T will accomplish this. Channel spacing is 200 kHz with a 20 kHz loop bandwidth. VCO sensitivity is 32 MHz/V. Charge pump current of 4.375 mA is used and the desired phase margin for the loop is 45°. The IF output is fixed at 200 MHz. The VCO190–200T is used. It has a sensitivity of 11.5 MHz/V. Channel spacing and loop bandwidth is chosen to be the same as the RF side. P13 sets the RF Charge Pump current. With P13 set to “0,” ICP is 1.25 mA. With P5 set to “1,” ICP is 4.375 mA. See Table V. Programmable RF AB Counter If control bits C2, C1 are 1, 1, the data in the input register is used to program the RF N (AB) counter. The AB counter consists of a 6-bit swallow counter (A Counter) and an 11-bit REV. 0 –17– ADF4216/ADF4217/ADF4218 RFOUT IFOUT VP 100pF VDD VP VDD2 VDD1 VP1 100pF 18⍀ 18⍀ 18⍀ 100pF VCC 3.3k⍀ VCO190-125T 620pF VP2 CPIF 9k⍀ VCC 3.3k⍀ CPRF 400pF 620pF 18⍀ 620pF 100pF 18⍀ VCO190-1068U 18⍀ 5.8k⍀ ADF4216 3.9nF 6nF MUXOUT LOCK DETECT 1nF 100pF IFIN CLK DATA LE SPI-COMPATIBLE SERIAL BUS AGNDIF 51⍀ DGNDIF REFIN DGNDRF VDD AGNDRF 51⍀ RFIN 13MHz TCXO DECOUPLING CAPACITORS (22␮F/10pF) ON VDD1, VP, OF THE ADF4216, THE TCXO, AND ON VCC OF THE VCOs, HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4216 RFOUT IFOUT 100pF VP VDD VP VP2 VDD2 VDD1 VP1 100pF 18⍀ 18⍀ 18⍀ 100pF VCC 3.3k⍀ VCO190-200T 450pF 1.5k⍀ VCC 3.3k⍀ CPRF CPIF 2.4nF 690pF 760pF 18⍀ 100pF 18⍀ VCO190-1750T 18⍀ 4.7k⍀ ADF4217 24nF 7.5nF MUXOUT LOCK DETECT 1nF 100pF RFIN 10MHz TCXO DECOUPLING CAPACITORS (22␮F/10pF) ON VDD1, VP, OF THE ADF4217, THE TCXO, AND CLK DATA LE SPI-COMPATIBLE SERIAL BUS 51⍀ AGNDIF REFIN DGNDIF VDD DGNDRF 51⍀ AGNDRF IFIN ON VCC OF THE VCOs, HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. Figure 8. Local Oscillator for WCDMA Receiver Using the ADF4217 –18– REV. 0 ADF4216/ADF4217/ADF4218 INTERFACING ADSP-2181 Interface The ADF4216/ADF4217/ADF4218 family has a simple SPIcompatible serial interface for writing to the device. SCLK, SDATA, and LE (Latch Enable) control the data transfer. When LE goes high, the 22 bits that have been clocked into the input register on each rising edge of SCLK will be transferred to the appropriate latch. See Figure 1 for the Timing Diagram and Table I for the Latch Truth Table. Figure 10 shows the interface between the ADF421x family and the ADSP-21xx Digital Signal Processor. As previously noted, the ADF421x family needs a 22-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the Autobuffered Transmit Mode of operation with Alternate Framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 22-bit word. To program each 22-bit latch, store the three 8-bit bytes, enable the Autobuffered mode and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 909 kHz or one update every 1.1 ms. This is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds. ADuC812 Interface Figure 9 shows the interface between the ADF421x family and the ADuC812 microconverter. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The microconverter is set up for SPI Master Mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF421x family needs a 22-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. SCLK DT ADSP-21xx I/O FLAG When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will be about 180 kHz. MOSI ADuC812 I/O PORTS SCLK SDATA LE ADF4216/ ADF4217/ ADF4218 MUXOUT (LOCK DETECT) Figure 9. ADuC812 to ADF421x Family Interface REV. 0 SDATA LE ADF4216/ ADF4217/ ADF4218 MUXOUT (LOCK DETECT) Figure 10. ADSP-21xx to ADF421x Family Interface On first applying power to the ADF421x family, it requires four writes (one each to the R counter latch and the AB counter latch for both RF1 and RF2 side) for the output to become active. SCLOCK TFS SCLK –19– ADF4216/ADF4217/ADF4218 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C01028–2.5–10/00 (rev. 0) Thin Shrink Small Outline Package (TSSOP) (RU-20) 0.260 (6.60) 0.252 (6.40) 20 11 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 10 PIN 1 SEATING PLANE 0.0433 (1.10) MAX 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8ⴗ 0ⴗ 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. 0.006 (0.15) 0.002 (0.05) –20– REV. 0