ADF4252BCPZ-R7

Dual Fractional-N/Integer-N Frequency Synthesizer ADF4252 Data Sheet FEATURES GENERAL DESCRIPTION 3.0 GHz fractional-N/1.2 GHz integer-N 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage to 5 V Programmable dual modulus prescaler RF: 4/5, 8/9 IF: 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Programmable modulus on fractional-N synthesizer Trade off noise vs. spurious performance The ADF4252 is a dual fractional-N/integer-N frequency synthesizer that can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Both the RF and IF synthesizers consist of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. The RF synthesizer has a Σ-Δ-based fractional interpolator that allows programmable fractional-N division. The IF synthesizer has programmable integer-N counters. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Control of all the on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. APPLICATIONS Base stations for mobile radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications test equipment CATV equipment FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 VDD3 DVDD VP1 VP2 RSET ADF4252 REFERENCE REFIN 2 DOUBLER 4-BIT R COUNTER PHASE FREQUENCY DETECTOR CHARGE PUMP CPRF REFOUT OUTPUT MUX LOCK DETECT RFINA FRACTIONAL-N RF DIVIDER CLK DATA LE RFINB 24-BIT DATA REGISTER IFINB INTEGER-N IF DIVIDER 2 DOUBLER 15-BIT R COUNTER PHASE FREQUENCY DETECTOR AGND1 AGND2 DGND IFINA CHARGE PUMP CPGND1 CPGND2 CPIF 02946-001 MUXOUT Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2002–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADF4252 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  RF N Divider Register (Address R0) ....................................... 23  Applications ....................................................................................... 1  RF R Divider Register (Address R1) ........................................ 23  General Description ......................................................................... 1  RF Control Register (Address R2) ........................................... 23  Functional Block Diagram .............................................................. 1  Master Register (Address R3) ................................................... 24  Revision History ............................................................................... 3  IF N Divider Register (Address R4) ......................................... 24  Specifications..................................................................................... 4  IF R Divider Register (Address R5) ......................................... 25  Timing Characteristics ................................................................ 5  IF Control Register (Address R6)............................................. 25  Absolute Maximum Ratings............................................................ 6  Device Programming after Initial Power-Up.............................. 26  ESD Caution .................................................................................. 6  RF and IF Synthesizers Operational ........................................ 26  Pin Configuration and Function Descriptions ............................. 7  RF Synthesizer Operational, IF Power-Down .......................... 26  Typical Performance Characteristics ............................................. 8  IF Synthesizer Operational, RF Power-Down .......................... 26  Detailed Functional Block Diagram ............................................ 12  RF Synthesizer: An Example..................................................... 26  Theory of Operation ...................................................................... 13  IF Synthesizer: An Example ...................................................... 26  Reference Input Section ............................................................. 13  Modulus ....................................................................................... 26  RF and IF Input Stage ................................................................ 13  Reference Doubler and Reference Divider ............................. 26  RF INT Divider ........................................................................... 13  12-Bit Programmable Modulus ................................................ 26  INT, FRAC, MOD, and R Relationship ................................... 13  Spurious Optimization and Fastlock ....................................... 27  RF R Counter .............................................................................. 13  Spurious Signals—Predicting Where They Appear............... 27  IF R Counter ............................................................................... 13  Prescaler....................................................................................... 27  IF Prescaler (P/P + 1) ................................................................. 14  Filter Design—ADIsimPLL....................................................... 27  IF A and B Counters .................................................................. 14  Interfacing ....................................................................................... 28  Pulse Swallow Function ............................................................. 14  ADuC812 Interface .................................................................... 28  Phase Frequency Detector (PFD) and Charge Pump ............ 14  ADSP-2181 Interface ................................................................. 28  MUXOUT and Lock Detect ...................................................... 14  PCB Design Guidelines for Chip Scale Package......................... 29  Lock Detect ................................................................................. 14  Outline Dimensions ....................................................................... 30  Input Shift Register..................................................................... 14  Ordering Guide .......................................................................... 30  Register Maps .................................................................................. 15  Register Descriptions ..................................................................... 23  Rev. E | Page 2 of 30 Data Sheet ADF4252 REVISION HISTORY 8/2019—Rev. D to Rev. E Changes to RF Phase Resync Section ...........................................25 Changes to RF Synthesizer Operational, IF Power-Down Section and IF Synthesizer Operational, RF Power-Down Section ..............................................................................................26 3/2019—Rev. C to Rev. D Changes to RF Synthesizer Operational, IF Power-Down Section and IF Synthesizer Operational, RF Power-Down Section .......26 Updated Outline Dimensions ........................................................30 Changes to Ordering Guide ...........................................................30 9/2015—Rev. B to Rev. C Updated Layout .................................................................. Universal Changed CP-24 to CP-24-10 ............................................ Universal Changes to Table 1 ............................................................................ 4 Changes to Table 3 ............................................................................ 6 Changes to Figure 3 and Table 4 ..................................................... 7 Added Detailed Functional Block Diagram Section ..................12 Changed Circuit Description Section to Theory of Operation Section ..............................................................................................13 Changes to INT, FRAC, MOD, and R Relationship Section .....13 Added Register Maps Section ........................................................15 Changed Table II to Figure 34 .......................................................15 Changed Table III to Figure 35 ......................................................16 Changed Table IV to Figure 36...................................................... 17 Changed Table V to Figure 37 ....................................................... 18 Changed Table VI to Figure 38...................................................... 19 Changed Table VII to Figure 39 .................................................... 20 Changed Table VIII to Figure 40................................................... 21 Changed Table IX to Figure 41 ...................................................... 22 Deleted Note 1 and Note 2, Noise and Spur Setting Section ..... 23 Changes to ADSP-2181 Interface Section and Figure 43 .......... 28 Updated Outline Dimensions........................................................ 30 Changes to Ordering Guide ........................................................... 30 10/2003—Rev. A to Rev. B Change to Specifications .................................................................. 2 Change to Timing Characteristics .................................................. 3 Change to Absolute Maximum Ratings ......................................... 4 Change to Ordering Guide .............................................................. 4 Inserted Lock Detect section ......................................................... 22 Change to Outline Dimensions ..................................................... 27 Rev. E | Page 3 of 30 ADF4252 Data Sheet SPECIFICATIONS VDD1 = VDD2 = VDD3 = DVDD = 3 V ± 10%, DVDD < VP1, VP2 < 5.5 V, GND = 0 V, RSET = 2.7 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter1 RF CHARACTERISTICS RF Input Frequency (RFINA, RFINB)2 RF Input Sensitivity RF Input Frequency (RFINA, RFINB)2 RF Phase Detector Frequency Allowable Prescaler Output Frequency IF CHARACTERISTICS IF Input Frequency (IFINA, IFINB)2 IF Input Sensitivity IF Phase Detector Frequency Allowable Prescaler Output Frequency REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Current REFIN Input Capacitance CHARGE PUMP RF ICP Sink/Source High Value Low Value IF ICP Sink/Source High Value Low Value ICP Three-State Leakage Current RF Sink and Source Current Matching RSET Range IF Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage Min Typ 0.25 −10 0.1 50 −10 0.5 Max Unit 3.0 0 3.0 GHz dBm GHz 30 375 MHz MHz 1200 0 55 150 MHz dBm MHz MHz 250 MHz VDD1 V p-p ±100 10 μA pF Test Conditions/Comments Input level = −8 dBm minimum, 0 dBm maximum Guaranteed by design Guaranteed by design For f < 10 MHz, use dc-coupled square wave (0 V to VDD) AC-coupled; when dc-coupled, use 0 V to VDD max (CMOS-compatible) See Figure 37 4.375 625 mA μA 5 625 1 2 2.7 2 2 2 mA μA nA % kΩ % % % See Figure 41 1.5 5.6 1.35 0.6 ±1 10 V V μA pF 0.4 V V VDD − 0.4 Rev. E | Page 4 of 30 0.5 V < VCP < VP − 0.5 See Figure 37 0.5 V < VCP < VP − 0.5 VCP = VP/2 IOH = 0.2 mA IOL = 0.2 mA Data Sheet ADF4252 Parameter1 POWER SUPPLIES VDD1, VDD2, VDD3 DVDD VP1, VP2 IDD3 RF + IF RF Only IF Only Power-Down Mode RF NOISE AND SPURIOUS CHARACTERISTICS Noise Floor In-Band Phase Noise Performance4 Lowest Spur Mode Low Noise and Spur Mode Lowest Noise Mode Spurious Signals Min Typ 2.7 VDD1 VDD1 Max Unit 3.3 V V V 5.5 13 10 4 1 16 13 5.5 Test Conditions/Comments mA mA mA μA −141 dBc/Hz −90 −95 −103 dBc/Hz dBc/Hz dBc/Hz At 20 MHz PFD frequency At VCO output RFOUT = 1.8 GHz, PFD = 20 MHz RFOUT = 1.8 GHz, PFD = 20 MHz RFOUT = 1.8 GHz, PFD = 20 MHz See the Typical Performance Characteristics section 1 Operating temperature range = −40°C to +85°C. Use a square wave for frequencies less than fMIN. RF = 1 GHz, RF PFD = 10 MHz, MOD = 4095, IF = 500 MHz, IF PFD = 200 kHz, REF = 10 MHz, VDD = 3 V, VP1 = 5 V, and VP2 = 3 V. 4 The in-band phase noise is measured with the EVAL-ADF4252EB2 evaluation board and the HP5500E phase noise test system. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz at 0 dBm). fOUT = 1.74 GHz, fREF = 20 MHz, N = 87, MOD = 100, Channel Spacing = 200 kHz, VDD = 3.3 V, and VP = 5 V. 2 3 TIMING CHARACTERISTICS VDD1 = VDD2 = VDD3 = DVDD = 3 V ± 10%, DVDD < VP1, VP2 < 5.5 V, GND = 0 V, unless otherwise noted. Table 2. Parameter1 t1 t2 t3 t4 t5 t6 t7 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width Guaranteed by design, but not production tested. t4 t5 CLOCK t3 t2 DATA LE DB23 (MSB) DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 t1 t7 02946-002 1 Limit at TMIN to TMAX 10 10 10 25 25 10 20 LE Figure 2. Timing Diagram Rev. E | Page 5 of 30 ADF4252 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 3. Parameter1 VDD1, VDD2, VDD3, DVDD to GND2 REFIN, RFINA, RFINB to GND RFINA to RFINB VP1, VP2 to GND VP1, VP2 to VDD1 Digital Input/Output Voltage to GND Analog Input/Output Voltage to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature Rating −0.3 V to +4 V −0.3 V to VDD + 0.3 V ±600 mV −0.3 V to +5.8 V −3.3 V to +3.5 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +150°C 150°C 122°C/W ESD CAUTION 260°C 40 sec 1 This device is a high performance RF integrated circuit with an ESD rating of 91, use P = 8/9 for optimum noise performance. SPURIOUS OPTIMIZATION AND FASTLOCK FILTER DESIGN—ADISIMPLL As mentioned in the Noise and Spur Setting section, the device can be optimized for spurious performance. However, in fast locking applications, the loop bandwidth needs to be wide. Therefore, the filter does not provide much attenuation of the spurious outputs. The programmable charge pump can be used to avoid this issue. The filter is designed for a narrow-loop bandwidth so that steady-state spurious specifications are met. This is designed using the lowest charge pump current setting. To implement fast lock during a frequency jump, the charge pump current is set to the maximum setting for the duration of the jump. This has the effect of widening the loop bandwidth, which improves lock time. When the PLL has locked to the new frequency, the charge pump is again programmed to the lowest charge pump current setting. This narrows the loop bandwidth to its original cutoff frequency to allow better attenuation of the spurious outputs than the wide-loop bandwidth. A filter design and analysis program is available to help users implement their PLL design. Visit www.analog.com/ADIsimPLL for a free download of the ADIsimPLL™ software. The software designs, simulates, and analyzes the entire PLL frequency domain and time domain response. Various passive and active filter architectures are allowed. Rev. E | Page 27 of 30 ADF4252 Data Sheet INTERFACING The ADF4252 has a simple SPI-compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that were clocked into the input register on each rising edge of SCLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the control bit truth table. ADuC812 INTERFACE Figure 42 shows the interface between the ADF4252 and the ADuC812 microconverter. Because the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The microconverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the input/output port driving LE is brought low. Each latch of the ADF4252 needs (at most) a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written, the LE input must be brought high to complete the transfer. MOSI SCLK SDATA LE I/O PORTS CE ADuC812 ADF4252 02946-042 MUXOUT (LOCK DETECT) Figure 42. ADuC812 to ADF4252 Interface ADSP-2181 INTERFACE Figure 43 shows the interface between the ADF4252 and the ADSP-2181 digital signal processor. Each latch of the ADF4252 needs (at most) a 24-bit word. The easiest way to accomplish this using the ADSP-2181 is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. The input/output port lines on the ADuC812 are also used to control power-down (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 166 kHz. SCLK DT TFS SCLK SDATA LE CE I/O FLAGS ADSP-2181 MUXOUT (LOCK DETECT) ADF4252 Figure 43. ADSP-2181 to ADF4252 Interface Rev. E | Page 28 of 30 02946-044 The maximum allowable serial clock rate is 20 MHz, which means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 μs. This is more than adequate for systems that have typical lock times in hundreds of microseconds. SCLOCK Data Sheet ADF4252 PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE pad and the inner edges of the pad pattern. This ensures that shorting is avoided. The leads on the chip scale package (CP-24-10) are rectangular. The printed circuit board pad for these must be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land must be centered on the pad. This ensures that the solder joint size is maximized. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they must be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter must be between 0.3 mm and 0.33 mm, and the via barrel must be plated with 1 oz copper to plug the via. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board must be at least as large as this exposed pad. On the printed circuit board, there must be a clearance of at least 0.25 mm between the thermal VVCO VDD VP R48 0Ω 6.3V 6.3V The user must connect the printed circuit board to AGND. R44 0Ω VP R1 20Ω 6.3V VVCO R49 0Ω 6.3V 6.3V C7 22µF C11 22µF C29 22µF C8 10pF C12 10pF C30 10pF 6.3V VDD’ C10 10pF C6 10pF C15 100pF 14 VCC R12 18Ω R13 C16 18Ω 100pF R14 18Ω 10 RF OUT VIN 2 VP1 VP2 R17 13kΩ C20 82pF VCO2 VCO190–540T C19 2.2nF C18 270pF U1 ADF4252BCP R16 7.5kΩ R20 470Ω CPRF CPIF C23 10nF 14 VCC 2 V IN C25 3.3nF C24 100nF IFINA R19 270Ω REFIN T13 J5 C13 1nF R45 0Ω R47 0Ω 3V R27 2.7kΩ R11 51Ω 3 R46 0Ω O/P 4 B+ C45 10pF 2 GND C26 R21 100pF 18Ω R23 18Ω C28 100pF C44 100pF MUXOUT AGND1 LE DGND DATA AGND2 R27 10kΩ T16 R28 10kΩ VDD R29 10kΩ D4 CPGND2 CLK Y3 R22 18Ω RFINA C43 100pF 5V C27 100pF R24 51Ω RFINB C14 1nF RFOUT J7 T14 C32 33pF Y2 10MHz REFOUT J8 R26 1kΩ R4 1MΩ C31 33pF 4 R38 0Ω R39 0Ω 1 U6 2 VCC 3V R34 0Ω 5V 02946-043 C17 100pF RFOUT 10 VCO1 VCO190–1730T CPGND1 R15 51Ω C46 22µF DVDD C4 10pF R43 0Ω VDD3 C5 22µF VDD2 C9 22µF VDD1 IFOUT J6 C3 22µF R35 0Ω Figure 44. Typical PLL Circuit Schematic Rev. E | Page 29 of 30 ADF4252 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.20 1 0.50 BSC 2.20 2.10 SQ 2.00 EXPOSED PAD 13 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-004714 SEATING PLANE 0.50 0.40 0.30 P IN 1 IN D IC AT O R AR E A OP T IO N S (SEE DETAIL A) 24 19 18 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8 09-07-2018-B PIN 1 INDICATOR AREA DETAIL A (JEDEC 95) 4.10 4.00 SQ 3.90 Figure 45. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-24-10) Dimensions shown in millimeters ORDERING GUIDE Model1 ADF4252BCPZ ADF4252BCPZ-RL ADF4252BCPZ-R7 EVAL-ADF4252EBZ2 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. ©2002–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02946-0-8/19(E) Rev. E | Page 30 of 30 Package Option CP-24-10 CP-24-10 CP-24-10