ADF4360-8BCPZRL

Integrated Synthesizer and VCO ADF4360-8 Data Sheet FEATURES GENERAL DESCRIPTION Output frequency range: 65 MHz to 400 MHz 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable output power level 3-wire serial interface Digital lock detect Hardware and software power-down mode The ADF4360-8 is an integrated integer-N synthesizer and voltage-controlled oscillator (VCO). The ADF4360-8 center frequency is set by external inductors. This allows a frequency range of between 65 MHz to 400 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. APPLICATIONS System clock generation Test equipment Wireless LANs CATV equipment FUNCTIONAL BLOCK DIAGRAM AVDD DVDD RSET CE ADF4360-8 MUXOUT MULTIPLEXER REFIN 14-BIT R COUNTER LOCK DETECT CLK DATA 24-BIT DATA REGISTER LE MUTE 24-BIT FUNCTION LATCH CHARGE PUMP CP PHASE COMPARATOR VVCO VTUNE L1 L2 CC CN RFOUTA VCO CORE 13-BIT B COUNTER OUTPUT STAGE RFOUTB 04763-001 N=B AGND DGND CPGND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004-2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADF4360-8 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 MUXOUT and Lock Detect...................................................... 10 Applications ....................................................................................... 1 Input Shift Register .................................................................... 11 General Description ......................................................................... 1 VCO ............................................................................................. 11 Functional Block Diagram .............................................................. 1 Output Stage................................................................................ 12 Revision History ............................................................................... 2 Latch Structure ........................................................................... 13 Specifications..................................................................................... 3 Power-Up ..................................................................................... 17 Timing Characteristics ................................................................ 5 Control Latch .............................................................................. 19 Absolute Maximum Ratings............................................................ 6 N Counter Latch ......................................................................... 20 Transistor Count ........................................................................... 6 R Counter Latch ......................................................................... 20 ESD Caution .................................................................................. 6 Applications Information .............................................................. 21 Pin Configuration and Function Descriptions ............................. 7 Choosing the Correct Inductance Value ................................. 21 Typical Performance Characteristics ............................................. 8 Fixed Frequency LO ................................................................... 21 Circuit Description ......................................................................... 10 Interfacing ................................................................................... 22 Reference Input Section ............................................................. 10 PCB Design Guidelines for Chip Scale Package........................... 22 N Counter .................................................................................... 10 Output Matching ........................................................................ 23 R Counter .................................................................................... 10 Outline Dimensions ....................................................................... 24 PFD and Charge Pump .............................................................. 10 Ordering Guide .......................................................................... 24 REVISION HISTORY 5/2016—Rev. C to Rev. D Changed ADF4360 Family to ADF4360-8 and ADSP-21xx to ADSP-2181 ........................................... Throughout Changes to Figure 3 .......................................................................... 7 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 11/2012—Rev. B to Rev. C Changes to Table 1 ............................................................................ 4 Changes to Table 3 ............................................................................ 6 Updated Outline Dimensions ....................................................... 24 2/2012—Rev. A to Rev. B Changes to Figure 3 and Table 4 ..................................................... 7 Changes to Output Matching Section .......................................... 23 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 01/2005—Rev. 0 to Rev. A Changes to Table 1.............................................................................3 Changes to Table 2.............................................................................5 Changes to Figure 20...................................................................... 12 Added Power-Up Section .............................................................. 17 Deleted Power-Up Section ............................................................ 22 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 10/2004—Revision 0: Initial Version Rev. D | Page 2 of 24 Data Sheet ADF4360-8 SPECIFICATIONS 1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter REFIN CHARACTERISTICS REFIN Input Frequency B Version Unit Test Conditions/Comments 10/250 MHz min/max 0.7/AVDD 0 to AVDD 5.0 ±60 V p-p min/max V max pF max µA max For f < 10 MHz, use a dc-coupled CMOS-compatible square wave, slew rate > 21 V/µs. AC-coupled. CMOS-compatible. 8 MHz max 2.5 0.312 2.7/10 0.2 mA typ mA typ kΩ nA typ 2 % typ 1.25 V ≤ VCP ≤ 2.5 V. 1.5 2 % typ % typ 1.25 V ≤ VCP ≤ 2.5 V. VCP = 2.0 V. 1.5 0.6 ±1 3.0 V min V max µA max pF max DVDD − 0.4 500 0.4 V min µA max V max 3.0/3.6 AVDD AVDD 5 2.5 12.0 3.5 to 11.0 7 V min/V max mA typ mA typ mA typ mA typ µA typ 400 MHz Minimum VCO Output Frequency VCO Output Frequency 65 88/108 MHz MHz min/max VCO Frequency Range VCO Sensitivity 1.2 2 Ratio MHz/V typ Lock Time 6 Frequency Pushing (Open Loop) 400 0.24 µs typ MHz/V typ REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 2 CHARGE PUMP ICP Sink/Source 3 High Value Low Value RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage IOH, Output High Current VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VVCO AIDD 4 DIDD4 IVCO4, 5 IRFOUT4 Low Power Sleep Mode4 RF OUTPUT CHARACTERISTICS5 Maximum VCO Output Frequency With RSET = 4.7 kΩ. CMOS output chosen. IOL = 500 µA. ICORE = 5 mA. RF output stage is programmable. ICORE = 5 mA. Depending on L. See the Choosing the Correct Inductance Value section. L1, L2 = 270 nH. See the Choosing the Correct Inductance Value section for other frequency values. FMAX/FMIN L1, L2 = 270 nH. See the Choosing the Correct Inductance Value section for other sensitivity values. To within 10 Hz of final frequency. Rev. D | Page 3 of 24 ADF4360-8 Parameter Frequency Pulling (Open Loop) Harmonic Content (Second) Harmonic Content (Third) Output Power5, 7 Output Power5, 8 Output Power Variation VCO Tuning Range NOISE CHARACTERISTICS5 VCO Phase Noise Performance 9 Synthesizer Phase Noise Floor 10 Phase Noise Figure of Merit10 In-Band Phase Noise 11, 12 RMS Integrated Phase Error 13 Spurious Signals due to PFD Frequency12, 14 Level of Unlocked Signal with MTLD Enabled Data Sheet B Version 10 −16 −21 −9/0 −14/−9 ±3 1.25/2.5 Unit Hz typ dBc typ dBc typ dBm typ dBm typ dB typ V min/max Test Conditions/Comments Into 2.00 VSWR load. −120 −139 −140 −142 −160 −150 −142 −215 −102 0.09 −75 dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ Degrees typ dBc typ At 100 kHz offset from carrier. At 800 kHz offset from carrier. At 3 MHz offset from carrier. At 10 MHz offset from carrier. At 200 kHz PFD frequency. At 1 MHz PFD frequency. At 8 MHz PFD frequency. −70 dBm typ Using tuned load, programmable in 3 dB steps; see Table 7. Using 50 Ω resistors to VVCO, programmable in 3 dB steps; see Table 7. At 1 kHz offset from carrier. 100 Hz to 100 kHz. Operating temperature range is –40°C to +85°C. Guaranteed by design. Sample tested to ensure compliance. ICP is internally modified to maintain constant loop gain over the frequency range. 4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V. 5 Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2. 6 Jumping from 88 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz. 7 For more detail on using tuned loads, see the Output Matching section. 8 Using 50 Ω resistors to VVCO, into a 50 Ω load. 9 The noise of the VCO is measured in open-loop conditions. 10 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). The phase noise figure of merit subtracts 10 log (PFD frequency). 11 The phase noise is measured with the EV-ADF4360-8EB1Z evaluation board and the HP 8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer; offset frequency = 1 kHz. 12 fREFIN = 10 MHz; fPFD = 200 kHz; N = 1000; loop bandwidth = 10 kHz. 13 fREFIN = 10 MHz; fPFD = 1 MHz; N = 120; loop bandwidth = 100 kHz. 14 The spurious signals are measured with the EV-ADF4360-8EB1Z evaluation board and the HP 8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer; fREFOUT = 10 MHz at 0 dBm. 1 2 3 Rev. D | Page 4 of 24 Data Sheet ADF4360-8 TIMING CHARACTERISTICS1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width Refer to the Power-Up section for the recommended power-up procedure for this device. t4 t5 CLOCK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 04763-002 1 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 LE Figure 2. Timing Diagram Rev. D | Page 5 of 24 ADF4360-8 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VVCO to GND VVCO to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature CSP θJA Thermal Impedance Paddle Soldered Paddle Not Soldered Lead Temperature, Soldering Reflow 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to + 85°C −65°C to +150°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. This device is a high performance RF integrated circuit with an ESD rating of