Microwave Wideband Synthesizer
with Integrated VCO
ADF4371
Data Sheet
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 62.5 MHz to 32,000 MHz
Fractional-N synthesizer and Integer N synthesizer
High resolution 39-bit fractional modulus
Typical spurious PFD: −90 dBc
Integrated rms jitter: 38 fs (1 kHz to 100 MHz)
Normalized phase noise floor: −234 dBc/Hz
PFD operation to 250 MHz
Reference frequency operation to 600 MHz
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
62.5 MHz to 8,000 MHz output at RF8x and RFAUX8x
8,000 MHz to 16,000 MHz output at RF16x
16,000 MHz to 32,000 MHz output at RF32x
Lock time approximately 3 ms with automatic calibration
Lock time 1228.8 (19)
VCO_ALC_TIMEOUT × 1024 + TIMEOUT > 3072
(20)
There are several suitable values that meet these criteria. By
considering the minimum specifications, the following values
are the most suitable:
•
•
•
SYNTH_LOCK_TIMEOUT = 2 (minimum value)
VCO_ALC_TIMEOUT = 3
TIMEOUT = 2
Much faster lock times than those detailed in this data sheet are
possible by bypassing the calibration processes. Contact Analog
Devices, Inc., for more information.
Rev. A | Page 19 of 50
ADF4371
Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT
RF N COUNTER
When a single-ended signal is used as the reference, connect the
reference signal to REFP and program Bit 6 in REG0022 to 0. In
this case, SW1 and SW2 are closed, SW3 and SW4 are open, and
the current source that drives the differential pair of transistors
switches off.
For optimum integer boundary spur and phase noise performance,
use the single-ended setting for all references up to 500 MHz
(even if using a differential signal). Use the differential setting
for reference frequencies greater than 500 MHz.
FROM
VCO OUTPUT OR
OUTPUT DIVIDERS
TO PFD
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
VALUE
FRAC1
VALUE
FRAC2
VALUE
MOD2
VALUE
16982-030
Figure 35 shows the reference input stage. The reference input
can accept both single-ended and differential signals. Use the
reference mode bit (Bit 6 in REG0022) to select the signal. To
use a differential signal on the reference input, program this bit
high. In this case, SW1 and SW2 are open, SW3 and SW4 are
closed, and the current source that drives the differential pair of
transistors switches on. The differential signal is buffered, and it is
provided to an emitter coupled logic (ECL) to the CMOS converter.
Figure 36. RF N Divider
INT, FRAC, MOD, and R Counter Relationship
The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in
conjunction with the R counter, make it possible to generate
output frequencies that are spaced by fractions of fPFD. For more
information, see the RF Synthesizer, a Worked Example section.
Calculate fVCO_OUT using the following equation:
fVCO_OUT = fPFD × N
(21)
Calculate fPFD using the following equation:
REFERENCE
INPUT MODE
=
f PFD REFIN ×
85kΩ
SW2
BUFFER
(22)
where:
REFIN is the reference frequency input.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 5-bit programmable
reference counter.
T is the REFIN divide by 2 bit (0 or 1)
SW1
SW3
1+ D
R × (1 + T )
TO
R COUNTER
MULTIPLEXER
AV DD
ECL TO CMOS
BUFFER
Calculate the desired value of the feedback counter N using the
following equation:
REFP
REFN
=
N INT +
50Ω
SW4
BIAS
GENERATOR
16982-029
50Ω
Figure 35. Reference Input Stage, Differential Mode
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. Determine the division ratio by the INT, FRAC1, FRAC2,
and MOD2 values that this divider comprises.
FRAC2
MOD2
MOD1
FRAC1 +
(23)
where:
INT is the 16-bit integer value. In integer mode, INT = 20 to
32,767 for the 4/5 prescaler, and 64 to 65,535 for the 8/9
prescaler. In fractional mode, INT= = 23 to 32,767 for the 4/5
prescaler, and 75 to 65,535 for the 8/9 prescaler.
FRAC1 is the numerator of the primary modulus (0 to 33,554,431).
FRAC2 is the numerator of the 14-bit auxiliary modulus
(0 to 16,383).
MOD2 is the programmable, 14-bit auxiliary fractional
modulus (2 to 16,383).
MOD1 is a 25-bit primary modulus with a fixed value of
225 = 33,554,432.
Rev. A | Page 20 of 50
Data Sheet
ADF4371
2.
3.
4.
(24)
where:
fCHSP is the desired channel spacing frequency.
GCD(fPFD, fCHSP) is the greatest common divisor of the PFD
frequency and the channel spacing frequency.
5.
Calculate FRAC2 using the following equation:
FRAC2 = ((N – INT) × 225 – FRAC1) × MOD2
UP
CLR1
DELAY
HIGH
CHARGE
PUMP
U3
U2
–IN
Figure 37. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4371 allows the user to
access various internal points on the chip. Figure 38 shows the
MUXOUT section in block diagram form.
AVDD
THREE-STATE OUTPUT
AVDD
(26)
If zero frequency error is not required, the MOD1 and
MOD2 denominators operate together to create a 39-bit
resolution modulus.
CP
CLR2
DOWN
D2
Q2
(25)
The FRAC2 and MOD2 fraction result in outputs with zero
frequency error for channel spacing when
fPFD/GCD(fPFD, fCHSP) = MOD2 < 16,383
Q1
U1
+IN
Calculate N by dividing VCOOUT/fPFD. The integer value of
this number forms INT.
Subtract INT from the full N value.
Multiply the remainder by 225. The integer value of this
number forms FRAC1.
Calculate MOD2 based on the channel spacing (fCHSP)
using the following equation:
MOD2 = fPFD/GCD(fPFD, fCHSP)
D1
R DIVIDER OUTPUT
N DIVIDER OUTPUT
MUX
CONTROL
MUXOUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
RESERVED
INT N Mode
When FRAC1 and FRAC2 are equal to 0, the synthesizer
operates in integer N mode. It is recommended that the
SD_EN_FRAC0 bit in REG002B be set to 1 to disable the
SDMs, which gives an improvement in the inband phase noise,
and reduces any additional ΣΔ noise.
R Counter
The 5-bit R counter allows the input reference frequency (input
to REFP and REFN) to be divided down to produce the reference
clock to the PFD. Division ratios from 1 to 32 are allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 37 is a simplified schematic of
the phase frequency detector. The PFD includes a fixed delay
element that sets the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and provides a consistent reference spur level. Set the phase
detector polarity to positive on this device because of the
positive tuning of the VCO.
DIGITAL
GROUND
16982-032
1.
HIGH
16982-031
These calculations result in a very low frequency resolution
with no residual frequency error. To apply Equation 23, perform
the following steps:
Figure 38. MUXOUT Schematic
DOUBLE BUFFERS
The main fractional value (FRAC1), auxiliary modulus value
(MOD2), auxiliary fractional value (FRAC2), reference doubler,
reference divide by 2 (RDIV2), R counter value, and charge
pump current setting are double buffered in the ADF4371. Two
events must occur before the ADF4371 uses a new value for any
of the double buffered settings. First, the new value must latch
into the device by writing to the appropriate register, and
second, a new write to REG0010 must be performed.
For example, to ensure that the modulus value loads correctly,
every time that the modulus value updates, REG0010 must be
written to.
VCO
The VCO in the ADF4371 consists of four separate VCO cores:
Core A, Core B, Core C, and Core D, each of which uses 256
overlapping bands, which allows the device to cover a wide
frequency range without large VCO sensitivity (KV) and without
resultant poor phase noise and spurious performance.
Rev. A | Page 21 of 50
ADF4371
Data Sheet
The correct VCO and band are chosen automatically by the
VCO and band select logic whenever REG0010 is updated, and
automatic calibration is enabled. The VTUNE is disconnected from
the output of the loop filter and is connected to an internal
reference voltage.
The R counter output is used as the clock for the band select
logic. After band selection, normal PLL action resumes. The
nominal value of KV is 50 MHz/V when the N divider is driven
from the VCO output, or the KV value is divided by D. D is
the output divider value if the N divider is driven from the
RF output divider.
The VCO shows variation of KV as the tuning voltage, VTUNE,
varies within the band and from band to band. For wideband
applications covering a wide frequency range (and changing
output dividers), a value of 50 MHz/V provides the most accurate
KV, because this value is closest to the average value. Figure 39
and Figure 40 shows how KV varies with fundamental VCO
frequency along with an average value for the frequency band.
Users may prefer Figure 39 and Figure 40 when using narrowband designs.
150
140
VCO SENSITIVITY, KV (MHz/V)
130
120
110
100
90
80
70
60
50
40
30
20
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
FREQUENCY (GHz)
16982-033
10
Figure 39. VCO Sensitivity, KV vs. Frequency VCC_VCO = 5 V
VCO ALC THRESHOLD
Different VCO ALC threshold values are used for different
device revisions for the best performance. The device revision is
checked by reading the DEVICE_REVISION bits in Address 0x06.
The default register values for the latest device revision
(DEVICE_REVISION = 0x0A) are given in the register tables.
When using the older device revision (DEVICE_REVISION =
0x09), the following settings are recommended:
•
•
For 3.3 V VCO operation, Address 0x2D, Bits[2:0] = 0x1
For 5 V VCO operation, Address 0x2E, Bits[2:0] = 0x2 and
Address 0x2F, Bits[2:0] = 0x4
All other register settings are the same, and there is no difference in
performance specifications between the two revisions.
OUTPUT STAGE
The RF8P and RF8N pins of the ADF4371 connect to
the collectors of a bipolar negative positive negative (NPN)
differential pair driven by buffered outputs of the VCO, as
shown in Figure 41. The ADF4371 contains internal 50 Ω
resistors connected to the VCC_X1 pin. To optimize the power
dissipation vs. the output power requirements, the tail current
of the differential pair is programmable using Bits[1:0] in
REG0025. Four current levels can be set. These levels give
approximate output power levels of −4 dBm, −1 dBm, 2 dBm,
and 5 dBm. Levels of −4 dBm and −1 dBm can be achieved by
ac coupling into a 50 Ω load. Levels of 2 dBm and 5 dBm
require an external shunt inductor connected to the VCC_X1
pin. Do not use these two higher levels without an inductor
because not using an inductor can cause the compression of the
output stage. An inductor has a narrower operating frequency
than a 50 Ω resistor. For accurate power levels, refer to the
Typical Performance Characteristics section. Add an external
shunt inductor to provide higher power levels, which is less
wideband than the internal bias only. Terminate the unused
complementary output with a circuit similar to the used output.
100
VCC_X1
50Ω
RF8P
80
70
VCO
60
VCC_X1
50Ω
RF8N
BUFFER,
DIVIDE BY
1, 2, 4, 8,
16, 32, 64
16982-035
50
40
30
Figure 41. Output Stage
20
10
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
FREQUENCY (GHz)
Figure 40. VCO Sensitivity, KV vs. Frequency VCC_VCO = 3.3 V
16982-034
VCO SENSITIVITY, KV (MHz/V)
90
RFAUX8P and RFAUX8N provides the same functionality as
the RF8P and RF8N output, but can also output the divided
RF8x frequency or the VCO frequency if desired.
These outputs can be powered down when not in use, and the
pins can be left open if unused.
Rev. A | Page 22 of 50
Data Sheet
ADF4371
The doubled VCO output (8 GHz to 16 GHz) is available on the
RF16 pin, which can be directly connected to the next circuit.
The quadrupled output is available on the RF32P and RF32N
pins, which can also be directly connected to the next circuit.
DOUBLER
The VCO frequency multiplied by 2 is available at the RF16P
and RF16N pins. This output can be powered down when not in
use, and the pins RF16P and RF16N can be left open if unused.
RF16P
RF16N
Table 8. Filter and Bias Settings for Quadrupled Output
Frequency (GHz)
26
Filter
7
3
1
0
0
Bias
3
3
0
0
1
Automatic tracking mode (Bit 1 in REG0023) is common for
doubler and quadrupler outputs. When they are enabled
together, load the filter and bias coefficients for both outputs
manually for optimum performance.
16982-036
×2
mode (Bit 1 in REG0023) and manually load the settings in
Table 8 to REG0071.
Figure 42. Doubler Output Stage
An automatic tracking filter on the ADF4371 that suppresses
the VCO and other unwanted frequency products ensures the
doubled output is maximized and that the VCO and 3 × VCO
frequencies are suppressed regardless of the output frequency.
Suppression of
125 MHz:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
REG001F (with doubled R_WORD[4:0] for halved fPFD)
REG001A (MOD2WORD[13:8] for halved fPFD)
REG0019 (MOD2WORD[7:0] for halved fPFD)
REG0018 (FRAC2WORD[13:7] for halved fPFD)
REG0017 (FRAC2WORD[6:0] for halved fPFD)
REG0016 (FRAC1WORD[23:16] for halved fPFD)
REG0015 (FRAC1WORD[15:8] for halved fPFD)
REG0014 (FRAC1WORD[7:0] for halved fPFD)
REG0012 (enable autocalibration: EN_AUTOCAL = 1)
REG0011 (BIT_INTEGER_WORD[15:8] for halved fPFD)
REG0010 (BIT_INTEGER_WORD[7:0] for halved fPFD)
Ensure the device is locked by checking lock detect.
REG001F (R_WORD[4:0] for desired fPFD)
REG001A (MOD2WORD[13:8] for desired fPFD)
REG0019 (MOD2WORD[7:0] for desired fPFD)
REG0018 (FRAC2WORD[13:7] for desired fPFD)
REG0017 (FRAC2WORD[6:0] for desired fPFD)
REG0016 (FRAC1WORD[23:16] for desired fPFD)
REG0015 (FRAC1WORD[15:8] for desired fPFD)
REG0014 (FRAC1WORD[7:0] for desired fPFD)
REG0012 (disable autocalibration: EN_AUTOCAL = 0)
REG0011 (BIT_INTEGER_WORD[15:8] for desired fPFD)
REG0010 (BIT_INTEGER_WORD[7:0] for desired fPFD)
The frequency change occurs on the second write to REG0010.
Because halved fPFD is used with autocalibration, use the half of
the fPFD value in the calculation of the timeout values explained
in Lock Time section.
The unchanged registers do not need to be updated. For
example, for an integer-N PLL configuration (fractional devices
are not used), skip Step 1 to Step 8. In this case, the only
required updates are REG0011 and REG0010.
Rev. A | Page 25 of 50
ADF4371
Data Sheet
POWER SUPPLIES
The ADF4371 contains four multiband VCOs that together
cover an octave range of frequencies. To achieve optimal VCO
phase noise performance, it is recommended to connect a low
noise regulator, such as the ADM7150 or LT3045 to the
VCC_VCO pin. Connect the same regulator to the VCC_VCO
and VCC_LDO pins. 1 μF decoupling capacitors connected to
the 5 V VCO supply are recommended.
Take care with the RF output traces to minimize discontinuities
and ensure the best signal integrity. Via placement and
grounding are critical.
OUTPUT MATCHING
The low frequency output can be ac-coupled to the next circuit,
if desired. However, if higher output power is required, use a
pull-up inductor to increase the output power level.
VDD_X1
For all other the 3.3 V supply pins, use one ADM7150 or one
LT3045 regulator. 1 μF is also recommended for the VDD_VP
pin. Additional decoupling to other supply pins is not required.
7.5nH
10pF
RF8P
50Ω
PCB DESIGN GUIDELINES FOR AN LGA PACKAGE
The bottom of the chip scale package has a central exposed
thermal pad. The thermal pad on the PCB must be at least as
large as the exposed pad. On the PCB, there must be a minimum
clearance of 0.25 mm between the thermal pad and the inner
edges of the pad pattern. This clearance ensures the avoidance
of shorting.
To improve the thermal performance of the package, use thermal
vias on the PCB thermal pad. If vias are used, incorporate them
into the thermal pad at the 1.2 mm pitch grid. The via diameter
must be between 0.3 mm and 0.33 mm, and the via barrel must
be plated with 1 oz. of copper to plug the via.
For a microwave PLL and VCO synthesizer, such as the
ADF4371, take care with the board stackup and layout. Do not
consider using FR4 material because it causes an amplitude
decrease in signals greater than 3 GHz. Instead, Rogers 4350,
Rogers 4003, or Rogers 3003 dielectric material is suitable.
16982-041
APPLICATIONS INFORMATION
Figure 44. Optimum Output Stage
When differential outputs are not needed, terminate the unused
output or combine it with both outputs using a balun.
For lower frequencies less than 1 GHz, it is recommended to
use a 100 nH inductor on the RF8P and RF8N pins.
The RF8P and RF8N pins form a differential circuit. Provide
each output with the same (or similar) components where
possible, including the same shunt inductor value, bypass
capacitor, and termination.
The RFAUX8P and RFAUX8N pins are effectively the same as
RF8P and RF8N and must be treated in the manner as outlined
for RF8P and RF8N.
The RF16P and RF16N pins and the RF32P and RF32N pins
can be directly connected to the next circuit stage. These pins
are internally matched to 50 Ω and do not require additional
decoupling.
Rev. A | Page 26 of 50
Data Sheet
ADF4371
REGISTER SUMMARY
Table 10. ADF4371 Register Summary
Reg
0x00
Bits
[7:0]
0x01
[7:0]
0x03
0x04
0x05
0x06
0x10
0x11
0x12
0x14
0x15
0x16
0x17
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x22
0x23
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
0x24
0x25
[7:0]
[7:0]
0x26
0x27
0x28
0x2A
0x2B
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
0x2C
[7:0]
0x2D
[7:0]
0x2E
[7:0]
0x2F
[7:0]
0x30
0x31
0x32
[7:0]
[7:0]
[7:0]
0x33
0x34
0x35
0x36
0x37
0x38
0x39
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit 7
SOFT_
RESET_R
SINGLE_
INSTRUCTION
Bit 6
LSB_FIRST_R
Bit 5
ADDRESS_
ASCENSION_R
STALLING
MASTER_
READBACK_
CONTROL
RESERVED
Bit 4
SDO_ACTIVE_
R
Bit 3
SDO_ACTIVE
Bit 2
ADDRESS_
ASCENSION
RESERVED
Bit 1
LSB_FIRST
Bit 0
SOFT_RESET
CHIP_TYPE
PRODUCT_ID[7:0]
PRODUCT_ID[15:8]
PRODUCT_GRADE
DEVICE_REVISION
BIT_INTEGER_WORD[7:0]
BIT_INTEGER_WORD[15:8]
RESERVED
EN_AUTOCAL
PRE_SEL
RESERVED
FRAC1WORD[7:0]
FRAC1WORD[15:8]
FRAC1WORD[23:16]
FRAC2WORD[6:0]
RESERVED
FRAC1WORD
[24]
FRAC2WORD[13:7]
MOD2WORD[7:0]
RESERVED
PHASE_ADJ
MOD2WORD[13:8]
PHASE_WORD[7:0]
PHASE_WORD[15:8]
PHASE_WORD[23:16]
CP_CURRENT
PD_POL
PD
RESERVED
CNTR_RESET
RESERVED
R_WORD
MUXOUT
MUXOUT_EN
LEV_SEL
RESERVED
RESERVED
REFIN_MODE
REF_DOUB
RDIV2
RESERVED
TRACKING_FIL
RESERVED
CLK_DIV_MODE
RESERVED
RESERVED
TER_MUX_SEL
FB_SEL
DIV_SEL
RESERVED
RF_DIVSEL_
MUTE_LD
RESERVED
X4_EN
X2_EN
RF_EN
RF_OUT_POWER
DB
BLEED_ICP
LD_BIAS
LDP
BLEED_GATE
BLEED_EN
VCOLDO_PD
RF_PBS
RESERVED
LD_COUNT
LOL_EN
RESERVED
BLEED_POL
RESERVED
LE_SEL
RESERVED
READ_SEL
SD_LOAD_
RESERVED
LSB_P1
VAR_MOD_EN
RESERVED
RESERVED
SD_EN_FRAC0
ENB
RESERVED
ALC_RECT_
ALC_REF_
ALC_REF_DAC_NOM_VCO1
VTUNE_
DISABLE_ALC
SELECT_
DAC_LO_
CALSET_EN
VCO1
VCO1
RESERVED
ALC_RECT_
ALC_REF_
ALC_REF_DAC_NOM_VCO2
DAC_
SELECT_VCO2
LO_VCO2
RESERVED
ALC_RECT_
ALC_REF_
ALC_REF_DAC_NOM_VCO3
DAC_
SELECT_VCO3
LO_VCO3
SWITCH_
RESERVED
ALC_RECT_
ALC_REF_
ALC_REF_DAC_NOM_VCO4
LDO_
DAC_
SELECT_VCO4
3P3V_5V
LO_VCO4
VCO_BAND_DIV
TIMEOUT[7:0]
ADC_MUX_
ADC_FAST_
ADC_CTS_
ADC_
RESERVED
ADC_ENABLE
TIMEOUT[9:8]
SEL
CONV
CONV
CONVERSION
RESERVED
SYNTH_LOCK_TIMEOUT
VCO_FSM_TEST_MODES
VCO_ALC_TIMEOUT
ADC_CLK_DIVIDER
ICP_ADJUST_OFFSET
SI_BAND_SEL
SI_VCO_SEL
SI_VCO_BIAS_CODE
RESERVED
VCO_FSM_TEST_MUX_SEL
SI_VTUNE_CAL_SET
Rev. A | Page 27 of 50
Default
0x18
RW
R/W
0x00
R/W
0x0X
0xXX
0xXX
0xXX
0x32
0x00
0x40
0x00
0x00
0x00
0x00
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0xE8
0x03
0x00
0x00
0x00
0x48
0x01
0x14
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x80
0x07
R/W
R/W
0x32
0xC5
0x03
0x00
0x01
R/W
R/W
R/W
R/W
R/W
0x44
R/W
0x11
R/W
0x10
R/W
0x92
R/W
0x3F
0xA7
0x04
R/W
R/W
R/W
0x0C
0x9E
0x4C
0x30
0x00
0x00
0x07
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADF4371
Reg
0x3A
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x47
0x52
0x6E
0x6F
0x70
0x71
0x72
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
0x73
[7:0]
0x7C
[7:0]
Data Sheet
Bit 7
Bit 6
RESERVED
SD_RESET
Bit 5
Bit 4
Bit 3
ADC_OFFSET
Bit 2
Bit 1
RESERVED
CP_TMODE
RESERVED
Bit 0
RESERVED
CLK1_DIV[7:0]
RESERVED
TRM_IB_VCO_BUF
CLK1_DIV[11:8]
CLK2_DIVIDER_1[7:0]
CLK2_DIVIDER_2[3:0]
TRM_RESD_VCO_MUX
TRM_RESD_VCO_BUF
RESERVED
BAND_SEL_X2
BAND_SEL_X4
AUX_FREQ_
SEL
CLK2_DIVIDER_1[11:8]
RESERVED
TRM_RESCI_VCO_BUF
VCO_DATA_READBACK[7:0]
VCO_DATA_READBACK[15:8]
RESERVED
RESERVED
POUT_AUX
PDB_AUX
RESERVED
ADC_CLK_
DISABLE
RESERVED
RESERVED
Rev. A | Page 28 of 50
RESERVED
BIAS_SEL_X2
BIAS_SEL_X4
COUPLED_
RESERVED
VCO
PD_NDIV
LD_DIV
LOCK_
DETECT_
READBACK
Default
0x55
0x00
0x0C
0x80
0x50
0x28
0x00
0xC0
0xF4
0x00
0x00
0x03
0x60
0x32
RW
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
0x00
R/W
0x00
R
Data Sheet
ADF4371
REGISTER DETAILS
Address: 0x00, Default: 0x18, Name: REG0000
7
6
5
4
3
2
1
0
0 0 0 1 1 0 0 0
[7] SOFT_RESET_R (R/W)
Copy of Bit-0.
[0] SOFT_RESET (R/W)
Soft Reset.
[6] LSB_FIRST_R (R/W)
Copy of Bit-1.
[1] LSB_FIRST (R/W)
Reads LSB first when Active.
[5] ADDRESS_ASCENSION_R (R/W)
Copy of Bit-2.
[2] ADDRESS_ASCENSION (R/W)
Set Address in Ascending Order (Default
is Ascending).
[4] SDO_ACTIVE_R (R/W)
Copy of Bit-3.
[3] SDO_ACTIVE (R/W)
Choose Between 3-Pin or 4-Pin Operation.
Table 11. Bit Descriptions for REG0000
Bit(s)
7
6
5
4
3
Bit Name
SOFT_RESET_R
LSB_FIRST_R
ADDRESS_ASCENSION_R
SDO_ACTIVE_R
SDO_ACTIVE
2
ADDRESS_ASCENSION
1
0
LSB_FIRST
SOFT_RESET
Description
Copy of Bit 0.
Copy of Bit 1.
Copy of Bit 2.
Copy of Bit 3.
Choose Between 3-Pin or 4-Pin Operation.
0: 3-pin.
1: 4-pin. Enables SDIO pin and the SDIO pin becomes an input only.
Set Address in Ascending Order (Default Is Ascending).
0: descending.
1: ascending.
Reads LSB First when Active.
Soft Reset.
0: normal operation.
1: soft reset.
Default
0x0
0x0
0x0
0x1
0x1
Access
R/W
R/W
R/W
R/W
R/W
0x0
R/W
0x0
0x0
R/W
R/W
Address: 0x01, Default: 0x00, Name: REG0001
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
[7] SINGLE_INSTRUCTION (R/W)
Single Instruction.
[6] STALLING (R/W)
Stalling.
[4:0] RESERVED
[5] MASTER_READBACK_CONTROL (R/W)
Master Readback Control.
Table 12. Bit Descriptions for REG0001
Bit(s)
7
Bit Name
SINGLE_INSTRUCTION
6
5
[4:0]
STALLING
MASTER_READBACK_CONTROL
RESERVED
Description
Single Instruction. SPI stream mode is
disabled if this bit is set to 1.
Stalling.
Master Readback Control.
Reserved.
Rev. A | Page 29 of 50
Default
0x0
Access
R/W
0x0
0x0
0x0
R/W
R/W
R
ADF4371
Data Sheet
Address: 0x03, Default: 0x0X, Name: REG0003
7
6
5
4
3
0
0
0
0
X X X X
2
1
0
[7:4] RESERVED
[3:0] CHIP_TYPE (RP)
Chip Type.
Table 13. Bit Descriptions for REG0003
Bit(s)
[7:4]
[3:0]
Bit Name
RESERVED
CHIP_TYPE
Description
Reserved.
Chip Type.
Default
0x0
Prog
Access
R
RP
Address: 0x04, Default: 0xXX, Name: REG0004
7
6
5
4
3
2
1
0
X X X X X X X X
[7:0] PRODUCT_ID[7:0] (R/WP)
Product ID.
Table 14. Bit Descriptions for REG0004
Bit(s)
[7:0]
Bit Name
PRODUCT_ID[7:0]
Description
Product ID.
Default
Prog
Access
R/WP
Address: 0x05, Default: 0xXX, Name: REG0005
7
6
5
4
3
2
1
0
X X X X X X X X
[7:0] PRODUCT_ID[15:8] (R/WP)
Product ID.
Table 15. Bit Descriptions for REG0005
Bit(s)
[7:0]
Bit Name
PRODUCT_ID[15:8]
Description
Product ID.
Default
Prog
Access
R/WP
Address: 0x06, Default: 0xXX, Name: REG0006
7
6
5
4
3
2
1
0
X X X X X X X X
[7:4] PRODUCT_GRADE (RP)
Product Grade.
[3:0] DEVICE_REVISION (RP)
Device Revision.
Table 16. Bit Descriptions for REG0006
Bit(s)
[7:4]
[3:0]
Bit Name
PRODUCT_GRADE
DEVICE_REVISION
Description
Product Grade.
Device Revision.
Default
Prog
Prog
Access
RP
RP
Address: 0x10, Default: 0x32, Name: REG0010
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
0
[7:0] BIT_INTEGER_WORD[7:0] (R/W)
16-Bit Integer Word.
Table 17. Bit Descriptions for REG0010
Bit(s)
[7:0]
Bit Name
BIT_INTEGER_WORD[7:0]
Description
16-Bit Integer Word. Sets the integer value of N. Updates to the PLL N counter,
including FRAC1, FRAC2, and MOD2, are double buffered by this bitfield.
Rev. A | Page 30 of 50
Default
0x32
Access
R/W
Data Sheet
ADF4371
Address: 0x11, Default: 0x00, Name: REG0011
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] BIT_INTEGER_WORD[15:8] (R/W)
16-Bit Integer Word.
Table 18. Bit Descriptions for REG0011
Bit(s)
[7:0]
Bit Name
BIT_INTEGER_WORD[15:8]
Description
16-Bit Integer Word. Sets the integer value of N.
Default
0x0
Access
R/W
Default
0x0
0x1
Access
R
R/W
0x0
R/W
0x0
R
Address: 0x12, Default: 0x40, Name: REG0012
7
6
5
4
0
1
2
3
0 1 0 0 0 0 0 0
[7] RESERVED
[4:0] RESERVED
[6] EN_AUTOCAL (R/W)
Enables Autocalibration.
[5] PRE_SEL (R/W)
Prescaler Select.
Table 19. Bit Descriptions for REG0012
Bit(s)
7
6
Bit Name
RESERVED
EN_AUTOCAL
5
PRE_SEL
[4:0]
RESERVED
Description
Reserved.
Enables Autocalibration.
0: VCO autocalibration disabled.
1: VCO autocalibration enabled.
Prescaler Select. The dual modulus prescaler is set by this bit. The prescaler, at the input to
the N divider, divides down the VCO signal so the N divider can handle it. The prescaler
setting affects the RF frequency and the minimum and maximum INT value.
0: 4/5 prescaler.
1: 8/9 prescaler.
Reserved.
Address: 0x14, Default: 0x00, Name: REG0014
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] FRAC1WORD[7:0] (R/W)
25-Bit FRAC1 Value.
Table 20. Bit Descriptions for REG0014
Bit(s)
[7:0]
Bit Name
FRAC1WORD[7:0]
Description
25-Bit FRAC1 Value. Sets the FRAC1 value.
Default
0x0
Access
R/W
Default
0x0
Access
R/W
Address: 0x15, Default: 0x00, Name: REG0015
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] FRAC1WORD[15:8] (R/W)
25-Bit FRAC1 Value.
Table 21. Bit Descriptions for REG0015
Bit(s)
[7:0]
Bit Name
FRAC1WORD[15:8]
Description
25-Bit FRAC1 Value. Sets the FRAC1 value.
Rev. A | Page 31 of 50
ADF4371
Data Sheet
Address: 0x16, Default: 0x00, Name: REG0016
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] FRAC1WORD[23:16] (R/W)
25-Bit FRAC1 Value.
Table 22. Bit Descriptions for REG0016
Bit(s)
[7:0]
Bit Name
FRAC1WORD[23:16]
Description
25-Bit FRAC1 Value. Sets the FRAC1 value.
Default
0x0
Access
R/W
Default
0x0
0x0
Access
R/W
R/W
Address: 0x17, Default: 0x00, Name: REG0017
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] FRAC2WORD[6:0] (R/W)
14-Bit FRAC2 Value.
[0] FRAC1WORD[24] (R/W)
25-Bit FRAC1 Value.
Table 23. Bit Descriptions for REG0017
Bit(s)
[7:1]
0
Bit Name
FRAC2WORD[6:0]
FRAC1WORD[24:24]
Description
14-Bit FRAC2 Value. Sets the FRAC2 value.
25-Bit FRAC1 Value. Sets the FRAC1 value.
Address: 0x18, Default: 0x00, Name: REG0018
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] RESERVED
[6:0] FRAC2WORD[13:7] (R/W)
14-Bit FRAC2 Value.
Table 24. Bit Descriptions for REG0018
Bit(s)
7
[6:0]
Bit Name
RESERVED
FRAC2WORD[13:7]
Description
Reserved.
14-Bit FRAC2 Value. Sets the FRAC2 value.
Default
0x0
0x0
Access
R
R/W
Address: 0x19, Default: 0xE8, Name: REG0019
7
6
5
4
3
2
1
0
1
1
1
0
1
0
0
0
[7:0] MOD2WORD[7:0] (R/W)
14-Bit MOD2 Value.
Table 25. Bit Descriptions for REG0019
Bit(s)
[7:0]
Bit Name
MOD2WORD[7:0]
Description
14-Bit MOD2 Value. Sets the MOD2 value.
Rev. A | Page 32 of 50
Default
0xE8
Access
R/W
Data Sheet
ADF4371
Address: 0x1A, Default: 0x03, Name: REG001A
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
[7] RESERVED
[5:0] MOD2WORD[13:8] (R/W)
14-Bit MOD2 Value.
[6] PHASE_ADJ (R/W)
Phase Adjust Enable.
Table 26. Bit Descriptions for REG001A
Bit(s)
7
6
Bit Name
RESERVED
PHASE_ADJ
[5:0]
MOD2WORD[13:8]
Description
Reserved.
Phase Adjust Enable. Set to 1 to enable phase adjust. Phase adjust increases the phase
of the output relative to the current phase.
0: phase adjust disabled.
1: phase adjust enabled.
14-Bit MOD2 Value. Sets the MOD2 value.
Default
0x0
0x0
Access
R
R/W
0x3
R/W
Default
0x0
Access
R/W
Default
0x0
Access
R/W
Default
0x0
Access
R/W
Address: 0x1B, Default: 0x00, Name: REG001B
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE_WORD[7:0] (R/W)
24-Bit Phase Value.
Table 27. Bit Descriptions for REG001B
Bit(s)
[7:0]
Bit Name
PHASE_WORD[7:0]
Description
24-Bit Phase Value. Sets the phase word for phase adjust. The phase of the RF output
frequency can be adjusted in 24-bit steps. Phase Step = Phase Word ÷ 16,777,216 × 360°.
Address: 0x1C, Default: 0x00, Name: REG001C
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE_WORD[15:8] (R/W)
24-Bit Phase Value.
Table 28. Bit Descriptions for REG001C
Bit(s)
[7:0]
Bit Name
PHASE_WORD[15:8]
Description
24-Bit Phase Value. Sets the phase word for phase adjust. The phase of the RF output
frequency can be adjusted in 24-bit steps. Phase Step = Phase Word ÷ 16,777,216 × 360°.
Address: 0x1D, Default: 0x00, Name: REG001D
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE_WORD[23:16] (R/W)
24-Bit Phase Value.
Table 29. Bit Descriptions for REG001D
Bit(s)
[7:0]
Bit Name
PHASE_WORD[23:16]
Description
24-Bit Phase Value. Sets the phase word for phase adjust. The phase of the RF output
frequency can be adjusted in 24-bit steps. Phase Step = Phase Word ÷ 16,777,216 × 360°.
Rev. A | Page 33 of 50
ADF4371
Data Sheet
Address: 0x1E, Default: 0x48, Name: REG001E
7
6
5
4
3
2
1
0
0 1 0 0 1 0 0 0
[7:4] CP_CURRENT (R/W)
Charge Pum p Current Setting.
[0] CNTR_RESET (R/W)
Counter Reset.
[3] PD_POL (R/W)
Phase Detector Polarity.
[1] RESERVED
[2] PD (R/W)
Power-Down.
Table 30. Bit Descriptions for REG001E
Bit(s)
[7:4]
Bit Name
CP_CURRENT
3
PD_POL
2
PD
1
0
RESERVED
CNTR_RESET
Description
Charge Pump Current Setting. Sets the charge pump current. Set these bits to the charge
pump current that the loop filter is designed for.
0: 0.35 mA.
1: 0.70 mA.
10: 1.05 mA.
11: 1.4 mA.
100: 1.75 mA.
101: 2.1 mA.
110: 2.45 mA.
111: 2.8 mA.
1000: 3.15 mA.
1001: 3.5 mA.
1010: 3.85 mA.
1011: 4.2 mA.
1100: 4.55 mA.
1101: 4.9 mA.
1110: 5.25 mA.
1111: 5.6 mA.
Phase Detector Polarity. If using a noninverting loop filter and a VCO with positive tuning
slope, set phase detector polarity to positive. If using an inverting loop filter and a VCO with a
negative tuning slope, set phase detector polarity to positive. If using a noninverting loop
filter and a VCO with a negative tuning slope, set phase detector polarity to negative. If using
an inverting loop filter and a VCO with a positive tuning slope, set phase detector polarity to
negative.
0: negative phase detector polarity.
1: positive phase detector polarity.
Power-Down. Setting to 1 powers down all internal PLL blocks of the ADF4371. The VCO and
multipliers remain powered up. The registers do not lose their values. After bringing the
ADF4371 out of power-down (setting to 0) a write to REG0010 is required to relock the loop.
0: normal operation.
1: power-down.
Reserved.
Counter Reset. Setting to 1 holds the N divider and R counter in reset. There are no signals
entering the PFD.
0: normal operation.
1: counter reset.
Rev. A | Page 34 of 50
Default
0x4
Access
R/W
0x1
R/W
0x0
R/W
0x0
0x0
R
R/W
Data Sheet
ADF4371
Address: 0x1F, Default: 0x01, Name: REG001F
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:5] RESERVED
[4:0] R_WORD (R/W)
5-Bit R Counter.
Table 31. Bit Descriptions for REG001F
Bit(s)
[7:5]
[4:0]
Bit Name
RESERVED
R_WORD
Description
Reserved.
5-Bit R Counter.
0: 32
1: 1
10: 2
11: 3
…
11111: 31
Default
0x0
0x1
Access
R
R/W
Address: 0x20, Default: 0x14, Name: REG0020
7
6
5
4
3
2
1
0
0
0
0
1
0
1
0
0
[7:4] MUXOUT (R/W)
Mux Out.
[1:0] RESERVED
[2] LEV_SEL (R/W)
Mux Out Level Select.
[3] MUXOUT_EN (R/W)
Mux Out Enable.
Table 32. Bit Descriptions for REG0020
Bit(s)
[7:4]
Bit Name
MUXOUT
3
MUXOUT_EN
2
LEV_SEL
[1:0]
RESERVED
Description
Mux Out. Is used to set the mux out signal when MUXOUT_EN = 1.
0: tristate, high impedance output (only works when MUXOUT_EN = 0).
1: digital lock detect.
10: charge pump up.
11: charge pump down.
100: R divider/2.
101: N divider/2.
110: VCO test modes.
111: Reserved.
1000: high.
1001: VCO calibration R band/2.
1010: VCO calibration N band/2.
Mux Out Enable. Set to 0 if using 4-wire SPI.
0: MUXOUT pin is configured as the serial data output for 4-wire SPI. Mux out
functionality is disabled.
1: MUXOUT pin is configured for mux out functionality.
Mux Out Level Select. Select the voltage level of the logic at the mux out.
0: 1.8 V logic.
1: 3.3 V logic.
Reserved.
Rev. A | Page 35 of 50
Default
0x1
Access
R/W
0x0
R/W
0x1
R/W
0x0
R
ADF4371
Data Sheet
Address: 0x22, Default: 0x00, Name: REG0022
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
[7] RESERVED
[3:0] RESERVED
[6] REFIN_MODE (R/W)
Choose Between Single-Ended or
Differential REFin.
[4] RDIV2 (R/W)
RDIV2.
[5] REF_DOUB (R/W)
Reference Doubler.
Table 33. Bit Descriptions for REG0022
Bit(s)
7
6
Bit Name
RESERVED
REFIN_MODE
5
REF_DOUB
4
RDIV2
[3:0]
RESERVED
Description
Reserved.
Choose Between Single-Ended or Differential REFIN.
0: single-ended REFIN.
1: differential REFIN.
Reference Doubler. Controls the reference doubler block.
0: doubler disabled.
1: doubler enabled.
RDIV2. Controls the reference divide by 2 clock. This feature can be used to provide a 50%
duty cycle signal to the PFD.
0: RDIV2 disabled.
1: RDIV2 enabled.
Reserved.
Default
0x0
0x0
Access
R
R/W
0x0
R/W
0x0
R/W
0x0
R
Default
0x0
0x0
0x0
0x0
Access
R
R/W
R
R/W
0x0
R
Address: 0x23, Default: 0x00, Name: REG0023
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
[7:6] RESERVED
[0] RESERVED
[5:4] CLK_DIV_MODE (R/W)
Reserved.
[1] TRACKING_FILTER_MUX_SEL (R/W)
Tracking Filter Mux Select.
[3:2] RESERVED
Table 34. Bit Descriptions for REG0023
Bit(s)
[7:6]
[5:4]
[3:2]
1
Bit Name
RESERVED
CLK_DIV_MODE
RESERVED
TRACKING_FILTER_MUX_SEL
0
RESERVED
Description
Reserved.
Reserved.
Reserved.
Tracking Filter Mux Select.
0: normal, tracking filter coefficients set automatically.
1: tracking filter coefficients set manually from SPI (REG0070 and REG0071).
Reserved.
Rev. A | Page 36 of 50
Data Sheet
ADF4371
Address: 0x24, Default: 0x80, Name: REG0024
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7] FB_SEL (R/W)
Feedback.
[3:0] RESERVED
[6:4] DIV_SEL (R/W)
Division Selection.
Table 35. Bit Descriptions for REG0024
Bit(s)
7
Bit Name
FB_SEL
[6:4]
DIV_SEL
[3:0]
RESERVED
Description
Feedback.
0: divider feedback to N counter.
1: fundamental feedback to N counter.
Division Selection.
0: divide 1.
1: divide 2.
10: divide 4.
11: divide 8.
100: divide 16.
101: divide 32.
110: divide 64.
111: reserved.
Reserved.
Default
0x1
Access
R/W
0x0
R/W
0x0
R
Address: 0x25, Default: 0x07, Name: REG0025
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
[7] MUTE_LD (R/W)
Reserved.
[1:0] RF_OUT_POWER (R/W)
Select Output Power Level.
[6] RESERVED
[2] RF_EN (R/W)
RFOUT Enable.
[5] RF_DIVSEL_DB (R/W)
Select if DIV_SEL is Double Buffered.
[4] X4_EN (R/W)
Quadrupler Path Enable.
[3] X2_EN (R/W)
Doubler Path Enable.
Table 36. Bit Descriptions for REG0025
Bit(s)
7
6
5
4
Bit Name
MUTE_LD
RESERVED
RF_DIVSEL_DB
X4_EN
3
X2_EN
2
RF_EN
[1:0]
RF_OUT_POWER
Description
Reserved.
Reserved.
Select if DIV_SEL is Double Buffered.
Quadrupler Path Enable.
0: RF quadrupler off.
1: RF quadrupler on.
Doubler Path Enable.
0: RF doubler off.
1: RF doubler on.
RFOUT Enable.
0: RF8P and RF8N are disabled.
1: RF8P and RF8N are enabled.
Select Output Power Level.
0: −4 dBm.
1: −1 dBm.
10: 2 dBm.
11: 5 dBm.
Rev. A | Page 37 of 50
Default
0x0
0x0
0x0
0x0
Access
R/W
R
R/W
R/W
0x0
R/W
0x1
R/W
0x3
R/W
ADF4371
Data Sheet
Address: 0x26, Default: 0x32, Name: REG0026
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
0
[7:0] BLEED_ICP (R/W)
Bleed Current.
Table 37. Bit Descriptions for REG0026
Bit(s)
[7:0]
Bit Name
BLEED_ICP
Description
Bleed Current. Sets the bleed current. The optimum bleed current is set by ((4/N) × ICP)/3.75,
where ICP is the charge pump current in μA.
Default
0x32
Access
R/W
Default
0x3
Access
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x1
R/W
Address: 0x27, Default: 0xC5, Name: REG0027
7
6
5
4
3
2
1
0
1 1 0 0 0 1 0 1
[7:6] LD_BIAS (R/W)
Lock Detect Bias.
[1:0] RF_PBS (R/W)
Reserved.
[5] LDP (R/W)
Lock Detect Precision.
[2] VCOLDO_PD (R/W)
VCO LDO Enable.
[4] BLEED_GATE (R/W)
Gated Bleed.
[3] BLEED_EN (R/W)
Bleed Enable.
Table 38. Bit Descriptions for REG0027
Bit(s)
[7:6]
Bit Name
LD_BIAS
5
LDP
4
BLEED_GATE
3
BLEED_EN
2
VCOLDO_PD
[1:0]
RF_PBS
Description
Lock Detect Bias. The lock detector window size is set by adjusting the lock detector bias in
conjunction with the lock detector precision.
0: 5 ns lock detect delay if LDP = 0.
1: 6 ns.
10: 8 ns.
11: 12 ns lock detect delay (for large values of bleed)
Lock Detect Precision. Controls the sensitivity of the digital lock detector, depending on INT or
FRAC operation selected.
0: FRAC Mode (5 ns).
1: INT Mode (2.4 ns).
Gated Bleed.
0: gate bleed disabled.
1: gate bleed on, digital lock detect (digital lock detect must be enabled)
Bleed Enable. Bleed current applies to a current inside the charge pump to improve the
linearity of the charge pump. This current leads to lower phase noise and improved spurious
performance. Set to 1 to enable negative bleed.
0: negative bleed disabled.
1: negative bleed enabled.
VCO LDO Enable. For optimal spurious and phase noise performance, disable VCO LDO.
0:VCO LDO enabled.
1: VCO LDO disabled.
Reserved.
Rev. A | Page 38 of 50
Data Sheet
ADF4371
Address: 0x28, Default: 0x03, Name: REG0028
7
6
5
4
3
2
1
0
0 0 0 0 0 0 1 1
[7:3] RESERVED
[0] LOL_EN (R/W)
Loss of Lock Enable.
[2:1] LD_COUNT (R/W)
Lock Detector Count.
Table 39. Bit Descriptions for REG0028
Bit(s)
[7:3]
[2:1]
Bit Name
RESERVED
LD_COUNT
0
LOL_EN
Description
Reserved.
Lock Detector Count. Initial value of the lock detector. This field sets the number of counts
of PFD within lock window before asserting digital lock detect high.
0: 1024 cycles.
1: 2048 cycles.
10: 4096 cycles.
11: 8192 cycles.
Loss of Lock Enable. When loss of lock is enabled, if digital lock detect is asserted, and the
reference signal is removed, digital lock detect goes low. It is recommended to set to 1 to
enable loss of lock.
0: disabled.
1: loss of lock enabled.
Default
0x0
0x1
Access
R
R/W
0x1
R/W
Default
0x0
0x0
Access
R
R/W
0x0
0x0
0x0
0x0
R
R/W
R
R/W
Address: 0x2A, Default: 0x00, Name: REG002A
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
[7:6] RESERVED
[0] READ_SEL (R/W)
Readback Select.
[5] BLEED_POL (R/W)
Bleed Polarity.
[2:1] RESERVED
[4] RESERVED
[3] LE_SEL (R/W)
Reserved.
Table 40. Bit Descriptions for REG002A
Bit(s)
[7:6]
5
Bit Name
RESERVED
BLEED_POL
4
3
[2:1]
0
RESERVED
LE_SEL
RESERVED
READ_SEL
Description
Reserved.
Bleed Polarity. Controls the polarity of the bleed current. Negative is typical usage.
0: negative bleed.
1: positive bleed (not recommended).
Reserved.
Reserved.
Reserved.
Readback Select. Selects the value to be read back.
0: readback VCO, band, and bias compensation data.
1: readback device version ID.
Rev. A | Page 39 of 50
ADF4371
Data Sheet
Address: 0x2B, Default: 0x01, Name: REG002B
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:6] RESERVED
[0] SD_EN_FRAC0 (R/W)
ΣΔ Enable.
[5] LSB_P1 (R/W)
Adds 1/2 bit to FRAC1 when auxiliary
SDM is off (VAR_MOD_EN=0) .
[1] RESERVED
[2] SD_LOAD_ENB (R/W)
Mask ΣΔ Reset when REG0010 is
updated.
[4] VAR_MOD_EN (R/W)
Enable Auxiliary SDM.
[3] RESERVED
Table 41. Bit Descriptions for REG002B
Bit(s)
[7:6]
5
Bit Name
RESERVED
LSB_P1
4
VAR_MOD_EN
3
2
RESERVED
SD_LOAD_ENB
1
0
RESERVED
SD_EN_FRAC0
Description
Reserved.
Adds a half bit to FRAC1 when auxiliary SDM is off (VAR_MOD_EN = 0). Set to 0 for normal
operation.
Enable Auxiliary SDM. If FRAC2 is different than 0, programmed this bit to 1.
0: normal operation.
1: enable auxiliary SDM.
Reserved.
Mask ΣΔ Reset when REG0010 is updated.
0: reset ΣΔ when REG0010 is updated.
1: do not reset ΣΔ when REG0010 is updated.
Reserved.
ΣΔ Enable. Set to 1 when in INT mode (when FRAC1 = FRAC2 = 0), and set to 0 when in
FRAC mode.
0: ΣΔ enabled (for fractional mode).
1: ΣΔ disabled (for integer mode).
Default
0x0
0x0
Access
R
R/W
0x0
R/W
0x0
0x0
R
R/W
0x0
0x1
R
R/W
Address: 0x2C, Default: 0x44, Name: REG002C
7
6
5
4
3
2
1
0
0
1
0
0
0
1
0
0
[7] RESERVED
[6] ALC_RECT_SELECT_VCO1 (R/W)
Select ALC Rectifier DC Bias (Core
D).
[5] ALC_REF_DAC_LO_VCO1 (R/W)
Select ALC Threshold Voltage (Core
D).
[0] DISABLE_ALC (R/W)
Autom atic VCO Bias Control (ALC).
[1] VTUNE_CALSET_EN (R/W)
Tem perature Dependent VCO Calibration
Voltage.
[4:2] ALC_REF_DAC_NOM_VCO1 (R/W)
Select VCO ALC Threshold (Core
D).
Table 42. Bit Descriptions for REG002C
Bit(s)
7
6
Bit Name
RESERVED
ALC_RECT_SELECT_VCO1
5
ALC_REF_DAC_LO_VCO1
[4:2]
ALC_REF_DAC_NOM_VCO1
1
VTUNE_CALSET_EN
0
DISABLE_ALC
Description
Reserved.
Select ALC Rectifier DC Bias (Core D).
0: 3.3 V VCO operation.
1: 5 V VCO operation.
Select ALC Threshold Voltage (Core D).
0: 5 V VCO operation.
1: 3.3 V VCO operation.
Select VCO ALC Threshold (Core D).
001: 3.3 V and 5 V VCO operation.
Temperature Dependent VCO Calibration Voltage.
0: disable temperature dependent VCO calibration voltage.
1: enable temperature dependent VCO calibration voltage.
Automatic VCO Bias Control (ALC).
0: ALC enabled.
1: ALC disabled.
Rev. A | Page 40 of 50
Default
0x0
0x1
Access
R
R/W
0x0
R/W
0x1
R/W
0x0
R/W
0x0
R/W
Data Sheet
ADF4371
Address: 0x2D, Default: 0x11, Name: REG002D
7
6
5
4
3
2
1
0
0 0 0 1 0 0 0 1
[7:5] RESERVED
[2:0] ALC_REF_DAC_NOM_VCO2 (R/W)
Select VCO ALC Threshold (Core
C).
[4] ALC_RECT_SELECT_VCO2 (R/W)
Sets ALC Rectifier DC Bias (Core
C).
[3] ALC_REF_DAC_LO_VCO2 (R/W)
Select ALC Threshold Voltage (Core
C).
Table 43. Bit Descriptions for REG002D
Bit(s)
[7:5]
4
Bit Name
RESERVED
ALC_RECT_SELECT_VCO2
3
ALC_REF_DAC_LO_VCO2
[2:0]
ALC_REF_DAC_NOM_VCO2
Description
Reserved.
Sets ALC Rectifier DC Bias (Core C).
0: 3.3 V VCO operation.
1: 5 V VCO operation.
Select ALC Threshold Voltage (Core C).
0: 5 V VCO operation.
1: 3.3 V VCO operation.
Select VCO ALC Threshold (Core C).
001: 5 V VCO operation.
010: 3.3 V VCO operation.
Default
0x0
0x1
Access
R
R/W
0x0
R/W
0x1
R/W
Default
0x0
0x1
Access
R
R/W
0x0
R/W
0x0
R/W
Address: 0x2E, Default: 0x10, Name: REG002E
7
6
5
4
3
2
1
0
0 0 0 1 0 0 0 0
[7:5] RESERVED
[4] ALC_RECT_SELECT_VCO3 (R/W)
Sets ALC Rectifier DC Bias (Core
B).
[2:0] ALC_REF_DAC_NOM_VCO3 (R/W)
Select VCO ALC Threshold (Core
B).
[3] ALC_REF_DAC_LO_VCO3 (R/W)
Sets ALC Threshold Voltage (Core
B).
Table 44. Bit Descriptions for REG002E
Bit(s)
[7:5]
4
Bit Name
RESERVED
ALC_RECT_SELECT_VCO3
3
ALC_REF_DAC_LO_VCO3
[2:0]
ALC_REF_DAC_NOM_VCO3
Description
Reserved.
Sets ALC Rectifier DC Bias (Core B).
0: 3.3 V VCO operation.
1: 5 V VCO operation.
Sets ALC Threshold Voltage (Core B).
0: 5 V VCO operation.
1: 3.3 V VCO operation.
Select VCO ALC Threshold (Core B).
000: 5 V VCO operation.
010: 3.3 V VCO operation.
Rev. A | Page 41 of 50
ADF4371
Data Sheet
Address: 0x2F, Default: 0x92, Name: REG002F
7
6
5
4
3
2
1
0
1 0 0 1 0 0 1 0
[7] SWITCH_LDO_3P3V_5V (R/W)
Switch LDO Operation Between 3.3
V and 5 V.
[2:0] ALC_REF_DAC_NOM_VCO4 (R/W)
Select VCO ALC Threshold (Core
A).
[6:5] RESERVED
[3] ALC_REF_DAC_LO_VCO4 (R/W)
Select ALC Lower Threshold Voltage
Range (Core A).
[4] ALC_RECT_SELECT_VCO4 (R/W)
Sets ALC Rectifier DC Bias (Core
A).
Table 45. Bit Descriptions for REG002F
Bit(s)
7
Bit Name
SWITCH_LDO_3P3V_5V
[6:5]
4
RESERVED
ALC_RECT_SELECT_VCO4
3
ALC_REF_DAC_LO_VCO4
[2:0]
ALC_REF_DAC_NOM_VCO4
Description
Switch LDO Operation Between 3.3 V and 5 V.
0: 3.3 V VCO operation.
1: 5 V VCO operation.
Reserved.
Sets ALC Rectifier DC Bias (Core A).
0: 3.3 V VCO operation.
1: 5 V VCO operation.
Select ALC Lower Threshold Voltage Range (Core A).
0: 5 V VCO operation.
1: 3.3 V VCO operation.
Select VCO ALC Threshold (Core A).
010: 3.3 V and 5 V VCO operation.
Default
0x1
Access
R/W
0x0
0x1
R
R/W
0x0
R/W
0x2
R/W
Address: 0x30, Default: 0x3F, Name: REG0030
7
6
5
4
3
2
1
0
0 0 1 1 1 1 1 1
[7:0] VCO_BAND_DIV (R/W)
Sets the Autocalibration Tim e per
Stage.
Table 46. Bit Descriptions for REG0030
Bit(s)
[7:0]
Bit Name
VCO_BAND_DIV
Description
Sets the Autocalibration Time per Stage. See the Lock Time section for details.
Default
0x3F
Access
R/W
Address: 0x31, Default: 0xA7, Name: REG0031
7
6
5
4
3
2
1
0
1 0 1 0 0 1 1 1
[7:0] TIMEOUT[7:0] (R/W)
Used as Part of the ALC Wait Tim e
and Synthetic Lock Tim e.
Table 47. Bit Descriptions for REG0031
Bit(s)
[7:0]
Bit Name
TIMEOUT[7:0]
Description
Used as Part of the ALC Wait Time and Synthetic Lock Time. See the Lock Time section for details.
Rev. A | Page 42 of 50
Default
0xA7
Access
R/W
Data Sheet
ADF4371
Address: 0x32, Default: 0x04, Name: REG0032
3
4
5
6
7
1
2
0
0 0 0 0 0 1 0 0
[7] ADC_MUX_SEL (R/W)
ADC Mux Select.
[1:0] TIMEOUT[9:8] (R/W)
Used as Part of the ALC Wait Tim e
and Synthetic Lock Tim e.
[6] RESERVED
[2] ADC_ENABLE (R/W)
ADC Enable.
[5] ADC_FAST_CONV (R/W)
ADC Fast Conversion.
[3] ADC_CONVERSION (R/W)
Enables ADC Conversion.
[4] ADC_CTS_CONV (R/W)
ADC Continuous Conversion.
Table 48. Bit Descriptions for REG0032
Bit(s)
7
Bit Name
ADC_MUX_SEL
6
5
RESERVED
ADC_FAST_CONV
4
ADC_CTS_CONV
3
ADC_CONVERSION
2
ADC_ENABLE
[1:0]
TIMEOUT[9:8]
Description
Analog-to-Digital Converter (ADC) Mux Select.
0: proportional to absolute temperature (PTAT) voltage muxed to ADC input.
1: scaled VTUNE voltage muxed to ADC input.
Reserved.
ADC Fast Conversion.
0: disabled.
1: enabled.
ADC Continuous Conversion.
0: disabled.
1: enabled.
Enables ADC Conversion.
0: no ADC conversion.
1: perform ADC conversion on REG0000 write if ADC is enabled.
ADC Enable.
0: disabled.
1: enabled.
Used as Part of the ALC Wait Time and Synthetic Lock Time. See the Lock Time section
for details.
Default
0x0
Access
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x0
R/W
Address: 0x33, Default: 0x0C, Name: REG0033
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
0
[7:5] RESERVED
[4:0] SYNTH_LOCK_TIMEOUT (R/W)
Part of VCO Calibration Routine.
Table 49. Bit Descriptions for REG0033
Bit(s)
[7:5]
[4:0]
Bit Name
RESERVED
SYNTH_LOCK_TIMEOUT
Description
Reserved.
Part of VCO Calibration Routine. See the Lock Time section for details.
Default
0x0
0xC
Access
R
R/W
Address: 0x34, Default: 0x9E, Name: REG0034
7
6
5
4
3
2
1
0
1
0
0
1
1
1
1
0
[7:5] VCO_FSM_TEST_MODES (R/W)
Reserved.
[4:0] VCO_ALC_TIMEOUT (R/W)
Wait Tim e for ALC Loop to Settle.
Table 50. Bit Descriptions for REG0034
Bit(s)
[7:5]
[4:0]
Bit Name
VCO_FSM_TEST_MODES
VCO_ALC_TIMEOUT
Description
Reserved.
Wait Time for ALC Loop to Settle. See the Lock Time section for details.
Rev. A | Page 43 of 50
Default
0x4
0x1E
Access
R/W
R/W
ADF4371
Data Sheet
Address: 0x35, Default: 0x4C, Name: REG0035
7
6
5
4
3
2
1
0
0
1
0
0
1
1
0
0
[7:0] ADC_CLK_DIVIDER (R/W)
ADC Clock Divider.
Table 51. Bit Descriptions for REG0035
Bit(s)
[7:0]
Bit Name
ADC_CLK_DIVIDER
Description
ADC Clock Divider. ADC_CLK = fPFD/((ADC_CLK_DIV × 4) + 2). Target 100 kHz
for ADC_CLK. Refer to AN-2005 for more details.
Default
0x4C
Access
R/W
Address: 0x36, Default: 0x30, Name: REG0036
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
0
[7:0] ICP_ADJUST_OFFSET (R/W)
Reserved.
Table 52. Bit Descriptions for REG0036
Bit(s)
[7:0]
Bit Name
ICP_ADJUST_OFFSET
Description
Reserved.
Default
0x30
Access
R/W
Address: 0x37, Default: 0x00, Name: REG0037
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
[7:0] SI_BAND_SEL (R/W)
Selects Band in Core when Test Mode
is Enabled.
Table 53. Bit Descriptions for REG0037
Bit(s)
[7:0]
Bit Name
SI_BAND_SEL
Description
Selects Band in Core when Test Mode is Enabled.
Default
0x0
Access
R/W
Address: 0x38, Default: 0x00, Name: REG0038
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
[7:4] SI_VCO_SEL (R/W)
Selects Core when Test Mode is
Enabled.
[3:0] SI_VCO_BIAS_CODE (R/W)
Sets VCO Bias when Test Mode is
Enabled.
Table 54. Bit Descriptions for REG0038
Bit(s)
[7:4]
Bit Name
SI_VCO_SEL
[3:0]
SI_VCO_BIAS_CODE
Description
Selects Core when Test Mode is Enabled.
0: all cores off.
1: VCO Core D.
10: VCO Core C.
100: VCO Core B.
1000: VCO Core A.
Sets VCO Bias when Test Mode is Enabled.
0000: maximum VCO bias (approximately 3.2 V).
1111: minimum VCO bias (approximately 1.8 V).
Rev. A | Page 44 of 50
Default
0x0
Access
R/W
0x0
R/W
Data Sheet
ADF4371
Address: 0x39, Default: 0x07, Name: REG0039
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
[7] RESERVED
[3:0] SI_VTUNE_CAL_SET (R/W)
Select VCO VTUNE Target Voltage
when Test Mode is Enabled.
[6:4] VCO_FSM_TEST_MUX_SEL (R/W)
VCO Test Mux Select.
Table 55. Bit Descriptions for REG0039
Bit(s)
7
[6:4]
Bit Name
RESERVED
VCO_FSM_TEST_MUX_SEL
[3:0]
SI_VTUNE_CAL_SET
Description
Reserved.
VCO Test Mux Select.
0: busy.
1: N band.
10: R band.
11: reserved.
100: timeout clock.
101: bias minimum.
110: ADC busy.
111: logic low.
Select VCO VTUNE Target Voltage when Test Mode is Enabled.
0: 1.18 V.
1: 1.18 V.
10: 1.18 V.
11: 1.18 V.
100: 1.33 V.
101: 1.48 V.
110: 1.63 V.
111: 1.78 V.
1000: 1.93 V.
1001: 2.08 V.
1010: 2.23 V.
1011: 2.38 V.
1100: 2.53 V.
1101: 2.53 V.
1110: 2.53 V.
1111: 2.53 V.
Default
0x0
0x0
Access
R
R/W
0x7
R/W
Address: 0x3A, Default: 0x55, Name: REG003A
7
6
5
4
3
2
1
0
0
1
0
1
0
1
0
1
[7:0] ADC_OFFSET (R/W)
VCO Calibration ADC Offset Correction.
Table 56. Bit Descriptions for REG003A
Bit(s)
[7:0]
Bit Name
ADC_OFFSET
Description
VCO Calibration ADC Offset Correction.
Rev. A | Page 45 of 50
Default
0x55
Access
R/W
ADF4371
Data Sheet
Address: 0x3D, Default: 0x00, Name: REG003D
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
[7] RESERVED
[5:0] RESERVED
[6] SD_RESET (R/W)
Reserved.
Table 57. Bit Descriptions for REG003D
Bit(s)
7
6
[5:0]
Bit Name
RESERVED
SD_RESET
RESERVED
Description
Reserved.
Reserved.
Reserved.
Default
0x0
0x0
0x0
Access
R
R/W
R
Address: 0x3E, Default: 0x0C, Name: REG003E
7
6
5
4
3
2
1
0
0 0 0 0 1 1 0 0
[7:4] RESERVED
[1:0] RESERVED
[3:2] CP_TMODE (R/W)
Charge Pum p Test Modes.
Table 58. Bit Descriptions for REG003E
Bit(s)
[7:4]
[3:2]
Bit Name
RESERVED
CP_TMODE
[1:0]
RESERVED
Description
Reserved.
Charge Pump (CP) Test Modes
0: CP tristate
11: normal operation
Reserved.
Default
0x0
0x3
Access
R
R/W
0x0
R
Address: 0x3F, Default: 0x80, Name: REG003F
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7:0] CLK1_DIV[7:0] (R/W)
Reserved.
Table 59. Bit Descriptions for REG003F
Bit(s)
[7:0]
Bit Name
CLK1_DIV[7:0]
Description
Reserved.
Default
0x80
Access
R/W
Address: 0x40, Default: 0x50, Name: REG0040
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
0
[7] RESERVED
[3:0] CLK1_DIV[11:8] (R/W)
Reserved.
[6:4] TRM_IB_VCO_BUF (R/W)
Reserved.
Table 60. Bit Descriptions for REG0040
Bit(s)
7
[6:4]
[3:0]
Bit Name
RESERVED
TRM_IB_VCO_BUF
CLK1_DIV[11:8]
Description
Reserved.
Reserved.
Reserved.
Rev. A | Page 46 of 50
Default
0x0
0x5
0x0
Access
R
R/W
R/W
Data Sheet
ADF4371
Address: 0x41, Default: 0x28, Name: REG0041
7
6
5
4
3
2
1
0
0
0
1
0
1
0
0
0
[7:0] CLK2_DIVIDER_1[7:0] (R/W)
Reserved.
Table 61. Bit Descriptions for REG0041
Bit(s)
[7:0]
Bit Name
CLK2_DIVIDER_1[7:0]
Description
Reserved.
Default
0x28
Access
R/W
Address: 0x42, Default: 0x00, Name: REG0042
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] CLK2_DIVIDER_2[3:0] (R/W)
Reserved.
[3:0] CLK2_DIVIDER_1[11:8] (R/W)
Reserved.
Table 62. Bit Descriptions for REG0042
Bit(s)
[7:4]
[3:0]
Bit Name
CLK2_DIVIDER_2
CLK2_DIVIDER_1[11:8]
Description
Reserved.
Reserved.
Default
0x0
0x0
Access
R/W
R/W
Address: 0x47, Default: 0xC0, Name: REG0047
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
0
[7:5] TRM_RESD_VCO_MUX (R/W)
Reserved.
[4:0] RESERVED
Table 63. Bit Descriptions for REG0047
Bit(s)
[7:5]
[4:0]
Bit Name
TRM_RESD_VCO_MUX
RESERVED
Description
Reserved.
Reserved.
Default
0x6
0x0
Access
R/W
R
Address: 0x52, Default: 0xF4, Name: REG0052
7
6
5
4
3
2
1
0
1 1 1 1 0 1 0 0
[7:5] TRM_RESD_VCO_BUF (R/W)
Reserved.
[1:0] RESERVED
[4:2] TRM_RESCI_VCO_BUF (R/W)
Reserved.
Table 64. Bit Descriptions for REG0052
Bit(s)
[7:5]
[4:2]
[1:0]
Bit Name
TRM_RESD_VCO_BUF
TRM_RESCI_VCO_BUF
RESERVED
Description
Reserved. VCO buffer trim.
Reserved.
Reserved.
Rev. A | Page 47 of 50
Default
0x7
0x5
0x0
Access
R/W
R/W
R
ADF4371
Data Sheet
Address: 0x6E, Default: 0x00, Name: REG006E
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] VCO_DATA_READBACK[7:0] (R)
Open-Loop VCO Counter Readback.
Table 65. Bit Descriptions for REG006E
Bit(s)
[7:0]
Bit Name
VCO_DATA_READBACK[7:0]
Description
Open-Loop VCO Counter Readback.
Default
0x0
Access
R
Default
0x0
Access
R
Address: 0x6F, Default: 0x00, Name: REG006F
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] VCO_DATA_READBACK[15:8] (R)
Open-Loop VCO Counter Readback.
Table 66. Bit Descriptions for REG006F
Bit(s)
[7:0]
Bit Name
VCO_DATA_READBACK[15:8]
Description
Open-Loop VCO Counter Readback.
Address: 0x70, Default: 0x03, Name: REG0070
7
6
5
4
3
2
1
0
0 0 0 0 0 0 1 1
[7:5] BAND_SEL_X2 (R/W)
Filter Select for Doubler Output Tracking
Filter.
[1:0] BIAS_SEL_X2 (R/W)
Bias Select for Doubler Output Tracking
Filter.
[4:2] RESERVED
Table 67. Bit Descriptions for REG0070
Bit(s)
[7:5]
[4:2]
[1:0]
Bit Name
BAND_SEL_X2
RESERVED
BIAS_SEL_X2
Description
Filter Select for Doubler Output Tracking Filter.
Reserved.
Bias Select for Doubler Output Tracking Bias.
Default
0x0
0x0
0x3
Access
R/W
R
R/W
Address: 0x71, Default: 0x60, Name: REG0071
7
6
5
4
3
2
1
0
0 1 1 0 0 0 0 0
[7:5] BAND_SEL_X4 (R/W)
Filter Select for Quadrupler Output
Tracking Filter.
[1:0] BIAS_SEL_X4 (R/W)
Bias Select for Quadrupler Output
Tracking Filter.
[4:2] RESERVED
Table 68. Bit Descriptions for REG0071
Bit(s)
[7:5]
[4:2]
[1:0]
Bit Name
BAND_SEL_X4
RESERVED
BIAS_SEL_X4
Description
Filter Select for Quadrupler Output Tracking Filter.
Reserved.
Bias Select for Quadrupler Output Tracking Bias.
Rev. A | Page 48 of 50
Default
0x3
0x0
0x0
Access
R/W
R
R/W
Data Sheet
ADF4371
Address: 0x72, Default: 0x32, Name: REG0072
6
7
2
3
4
5
1
0
0 0 1 1 0 0 1 0
[7] RESERVED
[0] RESERVED
[6] AUX_FREQ_SEL (R/W)
Auxillary RF Output Frequency Select.
[1] COUPLED_VCO (R/W)
Reserved.
[5:4] POUT_AUX (R/W)
Auxiliary RF Output Power.
[2] RESERVED
[3] PDB_AUX (R/W)
Power-Down Auxiliary RF Output.
Table 69. Bit Descriptions for REG0072
Bit(s)
7
6
Bit Name
RESERVED
AUX_FREQ_SEL
[5:4]
POUT_AUX
3
PDB_AUX
2
1
0
RESERVED
COUPLED_VCO
RESERVED
Description
Reserved.
Auxiliary RF Output Frequency Select.
0: divided output.
1: VCO output.
Auxiliary RF Output Power. Sets the output power at the auxiliary RF output ports.
0: −4.5 dBm single-ended ÷ −1.5 dBm differential.
1: 1 dBm single-ended ÷ 4 dBm differential.
10: 4 dBm single-ended ÷ 7 dBm differential.
11: 6 dBm single-ended ÷ 9 dBm differential.
Power-Down Auxiliary RF Output.
0: auxiliary RF off.
1: auxiliary RF on.
Reserved.
Reserved.
Reserved.
Default
0x0
0x0
Access
R
R/W
0x3
R/W
0x0
R/W
0x0
0x1
0x0
R
R/W
R
Address: 0x73, Default: 0x00, Name: REG0073
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0
[7:3] RESERVED
[0] LD_DIV (R/W)
Lock Detector Count Divider.
[2] ADC_CLK_DISABLE (R/W)
Disable ADC clock.
[1] PD_NDIV (R/W)
Power-Down N divider.
Table 70. Bit Descriptions for REG0073
Bits
[7:3]
2
1
0
Bit Name
RESERVED
ADC_CLK_DISABLE
PD_NDIV
LD_DIV
Description
Reserved.
Disable ADC Clock. ADC_ENABLE setting overwrites this bit.
Power-Down N Divider.
Lock Detector Count Divider. Divides the lock detector count cycles by 32 so that the
LD_COUNT bits in REG0028 can be selected as 32, 64, 128, and 256.
Default
0x0
0x0
0x0
0x0
Access
R
R/W
R/W
R/W
Address: 0x7C, Default: 0x00, Name: REG007C
[7:1] RESERVED
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[0] LOCK_DETECT_READBACK (R)
Readback of the Lock Detect Bit.
Table 71. Bit Descriptions for REG007C
Bit(s)
[7:1]
0
Bit Name
RESERVED
LOCK_DETECT_READBACK
Description
Reserved.
Readback of the Lock Detect Bit.
Rev. A | Page 49 of 50
Default
0x0
0x0
Access
R
R
ADF4371
Data Sheet
OUTLINE DIMENSIONS
7.10
7.00
6.90
PIN 1
INDICATOR
AREA
0.30
0.25
0.20
PIN 1
INDICATOR
C 0.30 × 0.45°
48
37
1
36
5.50 REF
SQ
25
SIDE VIEW
SEATING
PLANE
0.10
BSC
0.70 REF
0.398
0.358
0.318
13
BOTTOM VIEW
0.45
0.40
0.30
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
10-29-2018-A
PKG-005474
1.158
1.058
0.958
12
24
0.50
BSC
TOP VIEW
5.00 BSC
SQ
EXPOSED
PAD
Figure 45. 48-Terminal Land Grid Array [LGA]
(CC-48-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADF4371BCCZ
ADF4371BCCZ-RL7
EV-ADF4371SD2Z
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
48-Terminal Land Grid Array [LGA]
48-Terminal Land Grid Array [LGA]
Evaluation Board
Z = RoHS Compliant Part.
©2019–2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16982-9/21(A)
Rev. A | Page 50 of 50
Package Option
CC-48-4
CC-48-4
