ADF4602

Single-Chip, Multiband 3G Femtocell Transceiver ADF4602 FEATURES Single-chip multiband 3G transceiver 3GPP 25.104 release 6 WCDMA/HSPA compatible UMTS band coverage Local area Class BS in Band 1 to Band 6 and Band 8 to Band 10 Direct conversion transmitter and receiver Minimal external components Integrated multiband multimode monitoring No Tx SAW or Rx interstage SAW filters Integrated power management (3.1 V to 3.6 V supply) Integrated synthesizers including PLL loop filters Integrated PA bias control DACs/GPOs WCDMA and GSM receive baseband filter options Easy to use with minimal calibration Automatic Rx DC offset control Simple gain, frequency, mode programming Low supply current 50 mA typical Rx current 50 mA to 100 mA Tx current (varies with output power) 6 mm × 6 mm 40-pin LFCSP package FUNCTIONAL BLOCK DIAGRAM GPO[4:1] GPO 1 TO 4 DAC1 DAC2 DAC1 DAC2 ADF4602 Tx_PWR_CONTROL TXBBIB TXBBI TXLBRF Tx_PWR_ CONTROL TXHBRF Tx_PWR_ CONTROL LO GENERATOR Tx PLL LOOP FILTER FRAC N SYNTHESIZER VSUP7 TXBBQ TXBBQB Tx_PWR_CONTROL Rx PLL LO GENERATOR LOOP FILTER FRAC N SYNTHESIZER VSUP6 Rx_LO_LB SELECTABLE BANDWIDTH BASEBAND FILTERS RXHB1RF I CHANNEL RXBBI RXBBIB DC OFFSET CORRECTION RXBBQ Q CHANNEL Rx_LO_LB REFIN 26MHz 19.2MHz SERIAL INTERFACE VDD VSUP8 RXBBQB DC OFFSET CORRECTION APPLICATIONS 3G home basestations (femtocells) 3G repeaters RXHB2RF RXLBRF LDO1 LDO2 LDO3 LDO4 LDO5 VINT REFCLK SEN SCLK SDATA VSUP1 VSUP2 VSUP3 VSUP4 VSUP5 CHIPCLK Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. 07092-001 ADF4602 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Timing Characteristics..................................................................... 8 Absolute Maximum Ratings............................................................ 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 Theory of Operation ...................................................................... 17 Transmitter Description ............................................................ 17 DACs ............................................................................................ 18 General Purpose Outputs .......................................................... 18 Receiver Description .................................................................. 18 Power Management ................................................................... 21 Frequency Synthesis ................................................................... 22 Serial Port Interface (SPI) .............................................................. 23 Operation and Timing ............................................................... 23 Registers ........................................................................................... 24 Register Map ............................................................................... 24 Register Description .................................................................. 25 Software Initialization Procedure ................................................. 29 Initialization Sequence .............................................................. 29 Applications Information .............................................................. 31 Interfacing the ADF4602 to the AD9863 ................................ 31 Outline Dimensions ....................................................................... 33 Ordering Guide .......................................................................... 33 REVISION HISTORY 10/09—Revision 0: Initial Version Rev. 0 | Page 2 of 36 ADF4602 GENERAL DESCRIPTION The ADF4602 is a 3G transceiver integrated circuit (IC) offering unparalleled integration and feature set. The IC is ideally suited to high performance 3G femtocells providing cellular fixed mobile converged (FMC) services. With only a handful of external components, a full multiband transceiver is implemented. UMTS Band 1 through Band 6 and Band 8 through Band 10 are supported in a single device. The receiver is based on a direct conversion architecture. This architecture is the ideal choice for highly integrated wideband CDMA (WCDMA) receivers, reducing the bill of materials by fully integrating all interstage filtering. The front end includes three high performance, single-ended low noise amplifiers (LNAs), allowing the device to support tri-band applications. The single-ended input structure eases interface and reduces the matching components required for small footprint singleended duplexers. The excellent device linearity achieves good performance with a large range of SAW and ceramic filter duplexers. The integrated receive baseband filters offer selectable bandwidth, enabling the device to receive both WCDMA and GSM-EDGE radio signals. The selectable bandwidth filter, coupled with the multiband LNA input structure, allows GSM-EDGE signals to be monitored as part of a UMTS home basestation. The transmitter uses an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise, eliminating the need for external transmit SAW filters. The fully integrated phase lock loops (PLLs) provide high performance and low power fractional-N frequency synthesis for both receive and transmit sections. Special precautions have been taken to provide the isolation demanded by frequency division duplex (FDD) systems. All VCO and loop filter components are fully integrated. The ADF4602 also contains on-chip low dropout voltage regulators (LDOs) to deliver regulated supply voltages to the functions on chip, with an input voltage of between 3.1 V and 3.6 V. The IC is controlled via a standard 3-wire serial interface with advanced internal features allowing simple software programming. Comprehensive power-down modes are included to minimize power consumption in normal use. Rev. 0 | Page 3 of 36 ADF4602 SPECIFICATIONS VDD = 3.1 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3.3 V and TA = 25°C, 26 MHz reference input level = 0.7 V p-p. Table 1. Parameter REFERENCE SECTION Reference Input Reference Input Frequency Reference Input Amplitude REFCLK Output (26 MHz) Output Load Capacitance Output Swing Output Slew Rate Output Duty Cycle Variation CHIPCLK Output (19.2 MHz) Output Load Capacitance Frequency Multiplication Ratio Output Swing Output Duty Cycle Variation Output Jitter Lock Time TRANSMIT SECTION I/Q Input Input Resistance Input Capacitance Differential Peak Input Voltage Input Common-Mode Voltage Baseband Filter 3 dB Bandwidth TX Gain Control Maximum Gain Gain Control Range Gain Control Resolution Gain Control Accuracy Gain Settling Time RF Specifications (High Band) Carrier Frequency Output Impedance Output Power (POUT) Output Noise Spectral Density Min Typ Max Unit Test Conditions 0.1 26 0.7 10 1.5 200 2 10 2.0 40 MHz V p-p pF V p-p V/μs % pF N/A V p-p % ps rms μs Single-ended operation, dc-coupled 1 10 pF load 10 pF load Input duty cycle = 50% 48/65 1.5 2 36 50 40 48/65 10 pF load Input duty cycle = 50% 1.05 100 2 500 1.2 4.0 5 60 1/32 1.0 10 1 550 1.4 kΩ pF mV pd V MHz dB dB dB dB dB μs Single-ended Single-ended 1 V p-p differential baseband input Average of LSB steps Any 1 dB step Any 10 dB step POUT within 0.1 dB of final value 1710 50 −8 −155 −161 −161 −163 −35 5 55 70 2170 Carrier Leakage FDD EVM FDD ACLR MHz Ω dBm dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc % dB dB TM1 signal 64 DPCH 40 MHz offset 80 MHz offset 95 MHz offset 190 MHz offset POUT = −8 dBm POUT = −8 dBm ±5 MHz, POUT = −8 dBm ±10 MHz, POUT = −8 dBm Rev. 0 | Page 4 of 36 ADF4602 Parameter RF Specifications (Low Band) Carrier Frequency Output Impedance Output Power (POUT) Output Noise Spectral Density Carrier Leakage FDD EVM FDD ACLR RECEIVE SECTION Baseband I/Q Output Output Common Mode Voltage Differential Output Range Output DC Offset Quadrature Gain Error Quadrature Phase Error In-Band Gain Ripple Low-Pass Filter Rejection WCDMA (Seventh Order) Min 824 50 −6 −158 −35 5 55 70 Typ Max 960 Unit MHz Ω dBm dBc/Hz dBc % dB dB Test Conditions TM1 signal 64 DPCH 45 MHz offset POUT = −6 dBm POUT = −6 dBm ±5 MHz, POUT = −6 dBm ±10 MHz, POUT = −6 dBm 1.15 1.35 1.2 1.4 4 ±5 ±100 0.3 1 0.2 30 45 84 110 14 31 55 80 12 47 90 250 200 102 90 1 ±1 ±2 1.35 1.55 0.7 V V V p-p d mV mV dB °rms dB dB dB dB dB dB dB dB dB dB dB dB ns ns dB dB dB dB dB Mode 1 Mode 2 WCDMA HPF mode GSM servo loop mode WCDMA (Fifth Order) GSM @2.7 MHz @3.5 MHz @5.9 MHz @10 MHz @2.7 MHz @3.5 MHz @5.9 MHz @10 MHz @200 kHz @400 kHz @800 kHz 1.92 MHz band 100 kHz band WCDMA mode Differential Group Delay WCDMA GSM Receiver Gain Control Maximum Voltage Gain Gain Control Range Gain Control Resolution Gain Control Step Error RF Specifications (High Band) Input Frequency Input Impedance Input Return Loss Noise Figure Maximum Input Power 3 Input IP3 Input IP2 EVM 1 dB step 10 dB step 1710 50 −20 4.0 2170 MHz Ω dB dB dBm dBm dBm dBm dBm % −20 −2 −7 0 53 65 8 Rev. 0 | Page 5 of 36 TX power of −8 dBm, spur-free measurement 2 Maximum LNA gain Minimum LNA gain ±10 MHz and ±20 MHz Offset, 59 dB gain 85 MHz and 190 MHz Offset, 59 dB gain 80 MHz offset 190 MHz offset −60 dBm input ADF4602 Parameter RF Specifications (Low Band) Input Frequency Input Impedance Input Return Loss Noise Figure Maximum Input Power3 Input IP3 Input IP2 EVM Synthesizer Section Channel Resolution Lock Time3 DAC/GPO CONTROL DAC1 Resolution Output Range Absolute Accuracy Output LSB Step Output Capacitive Load Output Current Output Impedance DAC2 Resolution Output Range DNL INL Output Capacitive Load Output Current Output Impedance GPO1 to GPO4 Output Current Output High Voltage Output Low Voltage Switching Time LOGIC INPUTS Input High Voltage, VINH Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS (SDATA) Output High Voltage, VOH Output Low Voltage, VOL CLKOUT Rise/Fall CLKOUT Load TEMPERATURE RANGE (TA) Min 824 50 −20 4.0 −20 −2 2 5 40 7 50 200 Typ Max 960 Unit MHz Ω dB dB dBm dBm dBm dBm dBm % kHz μs Test Conditions 80 dB gain, TX power of −8 dBm Maximum LNA gain Minimum LNA gain ±10 MHz and ±20 MHz offset, 59 dB gain 45 MHz and 90 MHz offset, 59 dB gain 45 MHz offset −60 dBm input 5 2.3 ±50 25 −10 1 6 0 ±0.5 ±1.0 −5 5 2 10 2.6 0.2 1 1.2 1.2 2.1 3.3 0.6 ±1 10 1 +5 2.85 1 +10 3.15 bits V mV mV nF mA Ω bits V LSB LSB nF mA Ω mA mA V V μs V V V μA pF V V ns pF °C VDD > 3.15 V Any code, VDD > 3.2 V No load No load GPO1, GPO2, GPO3 GPO4 Maximum output current Maximum output current 5 pF load 1.8 V readback mode 4 2.8 V readback mode4 VX − 0.45 0.45 5 10 85 VX = VINT or VSUP8, IOH = 500 μA IOL = 500 μA 0 Rev. 0 | Page 6 of 36 ADF4602 Parameter POWER SUPPLIES Voltage Supply VDD VSUP1 VSUP2 Min Typ Max Unit Test Conditions 3.1 3.3 2.6 2.8 3.6 V V V VSUP3 VSUP4 VSUP5 1.9 2.6 2.8 V V V VSUP6 VSUP7 VSUP8 VINT CURRENT CONSUMPTION Transmit Current Consumption −8 dBm Output Level −28 dBm Output Level Receive Current Consumption 1 2 1.9 1.9 2.8 1.6 1.8 2.0 V V V V Main supply input Output from internal LDO1, 10 mA rating, supply for RX VCO Output from Internal LDO2, 30 mA rating, supply for RX baseband and RX downconverter Output from internal LDO3, 10 mA rating, supply for RX LNAs Output from internal LDO4, 10 mA rating, supply for TX VCO Output from internal LDO5, 100 mA rating, supply for TX modulator, TX baseband, PA control DACs Supply input for RX synthesizer, connect to VSUP3 Supply input for TX synthesizer, connect to VSUP3 Supply input for reference section, connect to VSUP2 Supply input for serial interface control logic VDD = 3.6 V, output is matched into 50 Ω FRF = 2170 MHz FRF = 2170 MHz 100 50 50 mA mA mA The reference frequency should be dc coupled to the REFIN pin. It is ac-coupled internally. The noise figure measurement does not include spurious due to harmonics of the 26 MHz reference frequency. Spurs appear at integer multiples of the reference frequency (every 26 MHz), degrading the receive sensitivity by about 6 dB. 3 Guaranteed by design, not production tested. 4 Bit sif_vsup8 in Register 2 controls whether 1.8 V readback mode or 2.8 V readback mode is selected. See the Serial Port Interface (SPI) section for more details. Rev. 0 | Page 7 of 36 ADF4602 TIMING CHARACTERISTICS VDD = 3.1 V to 3.6 V, VGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design but not production tested. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Limit at TMIN to TMAX 62 10 10 10 31 31 10 20 20 20 Unit ns min ns min ns min ns min ns min ns min ns min ns max ns max ns max Test Conditions/Comments SEN high to write time SEN to SCLK setup time SDATA to SCLK setup time SDATA to SCLK hold time SCLK high duration SCLK low duration SEN to SCLK hold time SEN to SDATA valid delay SCLK to SDATA valid delay SEN to SDATA disabled delay WRITE t5 SCLK t6 t3 SDATA W[25] t4 W[1] W[0] W[24] SEN t1 Figure 2. Serial Interface Write Diagram READ REQUEST READ SCLK t9 SDATA Q[25] Q[24] Q[1] Q[0] R[25] R[24] R[1] R[0] 07092-002 t2 t7 t10 SEN t8 3 or more 3 OR MORE SYSCLK periods SCLK PERIODS ADF4602 selected device DRIVES RSDATA drives SDATA DB B releases HOST RELEASES RSDATA SDATA Figure 3. Serial Interface Read/Write Diagram Rev. 0 | Page 8 of 36 07092-003 ADF4602 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VSUP1, VSUP2 to GND VSUP4, VSUP5, VSUP6, VSUP7, VSUP8, VSUP9 to GND VSUP3 to GND VINT to GND Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Commercial (B Version) Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature Rating −0.3 V to +4 V −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V 0°C to +85°C −65°C to +125°C 150°C 32°C/W 240°C 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of 2100 MHz (Band 1) the buffer state should be set to 1, and the corresponding VCO buffer value in R0.174 should be set to 0x5F. This ensures correct device operation for frequencies > 2100 MHz. For operation below 2100 MHz (Band 2). the buffer state should be set to 0, and the corresponding VCO buffer value in R0.174 should be set to 0x50. This ensures correct device operation for frequencies < 2100 MHz. These bits should be set to 0x5F for transmit frequencies >2100 MHz, and 0x50 for transmit frequencies 2100 MHz If transmit synthesizer frequency is 2100 MHz If transmit synthesizer frequency is