ADF5002

4 GHz to 18 GHz Divide-by-8 Prescaler ADF5002 FEATURES Divide-by-8 prescaler High frequency operation: 4 GHz to 18 GHz Integrated RF decoupling capacitors Low power consumption Active mode: 30 mA Power-down mode: 7 mA Low phase noise: −153 dBc/Hz Single dc supply: 3.3 V compatible with ADF4xxx PLLs Temperature range: −40°C to +105°C Small package: 3 mm × 3 mm LFCSP FUNCTIONAL BLOCK DIAGRAM CE BIAS ADF5002 VDDx 100Ω 100Ω 1pF RFOUT RFOUT 1pF 3pF RFIN DIVIDE BY 8 50Ω 08753-001 APPLICATIONS PLL frequency range extender Point-to-point radios VSAT radios Communications test equipment GND Figure 1. GENERAL DESCRIPTION The ADF5002 prescaler is a low noise, low power, fixed RF divider block that can be used to divide down frequencies as high as 18 GHz to a lower frequency suitable for input to a PLL IC, such as the ADF4156 or the ADF4106. The ADF5002 provides a divide-by-8 function. The ADF5002 operates from a 3.3 V supply and has differential 100 Ω RF outputs to allow direct interface to the differential RF inputs of PLLs such as the ADF4156 and ADF4106. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADF5002 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Absolute Maximum Ratings............................................................ 4  ESD Caution .................................................................................. 4  Pin Configuration and Function Descriptions..............................5  Typical Performance Characteristics ..............................................6  Evaluation Board PCB ......................................................................7  PCB Material Stack-Up ................................................................7  Bill of Materials ..............................................................................7  Application Circuit ............................................................................8  Outline Dimensions ..........................................................................9  Ordering Guide .............................................................................9  REVISION HISTORY 6/10—Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADF5002 SPECIFICATIONS VDD1 = VDD2 = 3.3 V ± 10%, GND = 0 V; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is −40°C to +105°C. Table 1. Parameter RF CHARACTERISTICS Input Frequency RF Input Sensitivity Output Power Min 4 −10 −10 −7 200 400 Typ Max 18 +10 −5 −2 330 660 1000 Phase Noise Reverse Leakage Second Harmonic Content Third Harmonic Content Fourth Harmonic Content Fifth Harmonic Content CE INPUT Input High Voltage, VIH Input Low Voltage, VIL POWER SUPPLIES Voltage Supply IDD (IDD1 + IDD2) Active Power-Down −153 −60 −38 −12 −20 −19 2.2 0.3 3.0 3.3 30 7 3.6 60 25 Unit GHz dBm dBm dBm mV p-p mV p-p mV p-p dBc/Hz dBm dBc dBc dBc dBc V V V mA mA CE is high CE is low Test Conditions/Comments Output Voltage Swing 4 GHz to 18 GHz Single-ended output connected into a 50 Ω load Differential outputs connected into a 100 Ω differential load Peak-to-peak voltage swing on each single-ended output, connected into a 50 Ω load Peak-to-peak voltage swing on differential output, connected into a 100 Ω differential load Peak-to-peak voltage swing on each single-ended output, no load condition Input frequency (fIN) = 12 GHz, offset = 100 kHz RF input power (PIN) = 0 dBm, RFOUT = 4 GHz Rev. 0 | Page 3 of 12 ADF5002 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDDx to GND RFIN Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature LFCSP Thermal Impedance Junction-to-Ambient (θJA) Junction-to-Case (θJC) Peak Temperature Time at Peak Temperature Rating −0.3 V to +3.9 V 10 dBm −40°C to +105°C −65°C to +150°C 150°C 90°C/W 30°C/W 260°C 40 sec This device is a high performance RF integrated circuit with an ESD rating of 2 kV, human body model (HBM), and is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 4 of 12 ADF5002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 15 VDD1 16 GND 14 VDD2 13 GND GND 1 RFIN 2 GND 3 GND 4 PIN 1 INDICATOR 12 GND 11 RFOUT 10 RFOUT 9 GND ADF5002 TOP VIEW (Not to Scale) GND 5 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 3, 4, 5, 8, 9, 12, 13, 16 2 6 7 Mnemonic GND RFIN NC CE Description RF Ground. All ground pins should be tied together. Single-Ended 50 Ω Input to the RF Prescaler. This pin is ac-coupled internally via a 3 pF capacitor. No Connect. This pin can be left unconnected. Chip Enable. This pin is active high. When CE is brought low, the part enters power-down mode. If this functionality is not required, the pin can be left unconnected because it is pulled up internally through a weak pull-up resistor. Divided-Down Output of the Prescaler. This pin has an internal 100 Ω load resistor tied to VDD2 and an ac-coupling capacitor of 1 pF. Complementary Divided-Down Output of the Prescaler. This pin has an internal 100 Ω load resistor tied to VDD2 and an ac-coupling capacitor of 1 pF. Voltage Supply for the Output Stage. This pin should be decoupled to ground with a 0.1 μF capacitor in parallel with a 10 pF capacitor and can be tied directly to VDD1. Voltage Supply for the Input Stage and Divider Block. This pin should be decoupled to ground with a 0.1 μF capacitor in parallel with a 10 pF capacitor. The LFCSP has an exposed paddle that must be connected to GND. 10 11 14 15 RFOUT RFOUT VDD2 VDD1 EPAD Rev. 0 | Page 5 of 12 08753-002 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE MUST BE CONNECTED TO GND. GND 8 NC 6 CE 7 ADF5002 TYPICAL PERFORMANCE CHARACTERISTICS 0 –5 –10 MINIMUM INPUT POWER (dBm) –10 –20 HARMONIC POWER (dBm) –15 –20 –25 –30 –35 –40 –45 FIRST HARMONIC THIRD HARMONIC FIFTH HARMONIC SEVENTH HARMONIC EIGHTH HARMONIC NINTH HARMONIC ELEVENTH HARMONIC 2.7 3.0 VDDx (V) 3.3 3.6 08753-006 08753-007 –30 VDD = 3.0V VDD = 3.3V VDD = 3.6V –40 –50 0 5 20 10 15 INPUT FREQUENCY (GHz) 25 30 08753-003 –60 –50 2.4 Figure 3. RF Input Sensitivity Figure 6. RF Output Harmonic Content vs. VDDx 40 35 30 25 IDDx (mA) 0 IDD_IN IDD_OUT –1 –2 fIN = 10GHz, VDD = 3.3V OUTPUT POWER (dBm) fIN = 10GHz, PIN = 0dBm 08753-004 –3 –4 –5 –6 –7 –8 –9 20 15 10 5 0 2.5 2.7 2.9 3.1 3.3 VDDx (V) 3.5 3.7 3.9 –10 0 5 10 15 20 INPUT FREQUENCY (GHz) 25 30 Figure 4. IDD1 and IDD2 vs. VDDx, fIN = 10 GHz, PIN = 0 dBm Figure 7. RF Output Power vs. RF Input Frequency, fIN = 10 GHz, VDD = 3.3 V 0 –2 –4 OUTPUT POWER (dBm) –6 –8 –10 –12 –14 –16 –18 –20 2.5 fIN = 10GHz, PIN = 0dBm 2.7 2.9 3.1 3.3 VDDx (V) 3.5 3.7 3.9 08753-005 Figure 5. RF Output Power (Single-Ended) vs. VDDx, fIN = 10 GHz, PIN = 0 dBm Rev. 0 | Page 6 of 12 ADF5002 EVALUATION BOARD PCB The evaluation board has four connectors as shown in Figure 8. The RF input connector (J4) is a high frequency precision SMA connector from Emerson. This connector is mechanically compatible with SMA, 3.5 mm, and 2.92 mm cables. PCB MATERIAL STACK-UP The evaluation board is built using Rogers RO4003C material (0.008 inch). RF track widths are 0.015 inch to achieve a controlled 50 Ω characteristic impedance. The complete PCB stack-up is shown in Figure 9. 1.5oz (53µm) FINISHED COPPER ROGERS RO4003C LAMINATE 0.008” εr = 3.38. STARTING COPPER WEIGHT 0.5oz/0.5oz 0.5oz (18µm) FINISHED COPPER FR4 PREPREG 0.0372” 08753-008 0.062” ± 0.003” COPPER TO COPPER Figure 8. Evaluation Board Silkscreen—Top View The differential RF outputs are brought out on the J2 and J3 SMA connectors. If only one of the outputs is being used, the unused output should be correctly terminated using a 50 Ω SMA termination. The chip enable (CE) pin can be controlled using the T1 test point. If this function is not required, the test point can be left unconnected. 1.5oz (53µm) FINISHED COPPER Figure 9. Evaluation Board PCB Layer Stack-Up BILL OF MATERIALS Table 4. Qty 1 1 3 1 3 1 Reference Designator C1 C2 J1, J2, J3 J4 T1, T2, T3 U1 Description 0.1 μF, 0603 capacitor 10 pF, 0402 capacitor SMA RF connector SMA RF connector Test points ADF5002 RF prescaler Supplier Murata Murata Emerson Emerson Vero Analog Devices, Inc. Part Number GRM188R71H104KA93D GRM1555C1H100JZ01D 142-0701-851 142-0761-801 20-2137 ADF5002BCPZ Rev. 0 | Page 7 of 12 08753-009 The evaluation board is powered from a single 3.0 V to 3.6 V supply, which should be connected to the J1 SMA connector. The power supply can also be connected using the T3 (VDDx) and T2 (GND) test points. 0.5oz (18µm) FINISHED COPPER ROGERS RO4003C LAMINATE 0.008” εr = 3.38. STARTING COPPER WEIGHT 0.5oz/0.5oz ADF5002 APPLICATION CIRCUIT The ADF5002 can be connected either single-ended or differentially to any of the Analog Devices PLL family of ICs. It is recommended that a differential connection be used for best performance and to achieve maximum power transfer. The application circuit shown in Figure 10 shows the ADF5002 used as the RF prescaler in a microwave 16 GHz PLL loop. The ADF5002 divides the 16 GHz RF signal down to 2 GHz, which is input differentially into the ADF4156 PLL. An active filter topology, using the OP184 op amp, is used to provide the wide tuning ranges typically required by microwave VCOs. The positive input pin of the OP184 is biased at half the ADF4156 charge pump supply (VP). This can be easily achieved using a simple resistor divider, ensuring sufficient decoupling close to the +IN A pin of the OP184. This configuration, in turn, allows the use of a single positive supply for the op amp. Alternatively, to optimize performance by ensuring a clean bias voltage, a low noise regulator such as the ADP150 can be used to power the resistor divider network or the +IN A pin directly. 1.8nF 10pF 0.1µF 330Ω 47nF VDD1 VDD2 RFOUT RFOUT GND RFIN ADF5002 PRESCALER DECOUPLING INTEGRATED ADF4156 PLL RFINA RFINB CP 220Ω VP/2 OP AMP OP184 1kΩ 820pF 1µF 1.8nF 6dB ATTENUATION PAD 37Ω 150Ω 150Ω 18Ω MICROWAVE VCO RFOUT VTUNE 18Ω 16GHz OUT Figure 10. ADF5002 Used as the RF Prescaler in a Microwave 16 GHz PLL Loop Rev. 0 | Page 8 of 12 08753-010 ADF5002 OUTLINE DIMENSIONS PIN 1 INDICATOR 3.10 3.00 SQ 2.90 0.50 BSC 0.30 0.25 0.18 13 12 EXPOSED PAD 16 1 PIN 1 INDICATOR 1.60 1.50 SQ 1.40 4 9 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.45 0.40 0.35 8 5 BOTTOM VIEW 0.25 MIN 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 11. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-18) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADF5002BCPZ ADF5002BCPZ-RL7 EVAL-ADF5002EB2Z 1 Temperature Range −40°C to +105°C −40°C to +105°C Package Description 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ), 7” Tape and Reel Evaluation Board Package Option CP-16-18 CP-16-18 111808-A Branding Q1U Q1U Z = RoHS Compliant Part. Rev. 0 | Page 9 of 12 ADF5002 NOTES Rev. 0 | Page 10 of 12 ADF5002 NOTES Rev. 0 | Page 11 of 12 ADF5002 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08753-0-6/10(0) Rev. 0 | Page 12 of 12