Microwave Wideband Synthesizer
with Integrated VCO
ADF5356
Data Sheet
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 53.125 MHz to 13,600 MHz
Noise floor integer channel: −227 dBc/Hz
Noise floor fractional channel: −225 dBc/Hz
Integrated rms jitter (1 kHz to 20 MHz): 97 fs for 6 GHz output
Fractional-N synthesizer and integer N synthesizer
Pin compatible to the ADF5355
High resolution, 52-bit modulus
Phase frequency detector (PFD) operation to 125 MHz
Reference input frequency operation to 600 MHz
Maintains frequency lock over −40°C to +85°C
Low phase noise, voltage controlled oscillator (VCO)
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Analog and digital power supplies: 3.3 V
Charge pump and VCO power supplies: 5.0 V typical
Logic compatibility: 1.8 V
Programmable output power level
RF output mute function
Supported by the ADIsimPLL design tool
The ADF5356 allows implementation of fractional-N or integer N
phase-locked loop (PLL) frequency synthesizers when used with
an external loop filter and an external reference frequency. The
wideband microwave VCO design permits frequency operation
from 6.8 GHz to 13.6 GHz at one radio frequency (RF) output. A
series of frequency dividers at another frequency output permits
operation from 53.125 MHz to 6800 MHz.
The ADF5356 has an integrated VCO with a fundamental
output frequency ranging from 3400 MHz to 6800 MHz. In
addition, the VCO frequency is connected to divide by 1, 2, 4, 8,
16, 32, or 64 circuits that allow the user to generate RF output
frequencies as low as 53.125 MHz. For applications that require
isolation, the RF output stage can be muted. The mute function
is both pin- and software-controllable.
Control of all on-chip registers is through a simple 3-wire interface.
The ADF5356 operates with analog and digital power supplies
ranging from 3.15 V to 3.45 V, with charge pump and VCO
supplies from 4.75 V to 5.25 V. The ADF5356 also contains
hardware and software power-down modes.
APPLICATIONS
Wireless infrastructure (LTE, W-CDMA, TD-SCDMA,
WiMAX, GSM, PCS, DCS)
Point to point and point to multipoint microwave links
Satellites and very small aperture terminals (VSATs)
Test equipment and instrumentation
Clock generation
FUNCTIONAL BLOCK DIAGRAM
REFIN A
REFIN B
CLK
DATA
LE
AVDD
AVDD
CE
10-BIT R
COUNTER
×2
DOUBLER
DATA REGISTER
INTEGER
REG
DVDD
RSET
VVCO
VRF
MULTIPLEXER
÷2
DIVIDER
MUXOUT
CREG1
LOCK
DETECT
FUNCTION
LATCH
FRACTION
REG
VP
CREG2
CHARGE
PUMP
CPOUT
PHASE
COMPARATOR
VTUNE
VREF
VCO
CORE
MODULUS
REG
VBIAS
×2
OUTPUT
STAGE
THIRD-ORDER
FRACTIONAL INTERPOLATOR
VREGVCO
RFOUTB
PDBRF
÷ 1/2/4/8/
16/32/64
ADF5356
MULTIPLEXER
AGND
CPGND
AGNDRF
SDGND
RFOUTA+
RFOUTA–
AGNDVCO
15360-001
N COUNTER
OUTPUT
STAGE
Figure 1.
Rev. 0
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ADF5356
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 3 ..................................................................................... 23
Applications ....................................................................................... 1
Register 4 ..................................................................................... 24
General Description ......................................................................... 1
Register 5 ..................................................................................... 25
Functional Block Diagram .............................................................. 1
Register 6 ..................................................................................... 26
Revision History ............................................................................... 2
Register 7 ..................................................................................... 28
Specifications..................................................................................... 3
Register 8 ..................................................................................... 29
Timing Characteristics ................................................................ 6
Register 9 ..................................................................................... 29
Absolute Maximum Ratings............................................................ 7
Register 10 ................................................................................... 30
Thermal Resistance ...................................................................... 7
Register 11 ................................................................................... 31
Transistor Count ........................................................................... 7
Register 12 ................................................................................... 31
ESD Caution .................................................................................. 7
Register 13 ................................................................................... 32
Pin Configuration and Function Descriptions ............................. 8
Register Initialization Sequence ............................................... 32
Typical Performance Characteristics ........................................... 10
Frequency Update Sequence ..................................................... 33
Theory of Operation ...................................................................... 15
RF Synthesizer—A Worked Example ...................................... 33
Reference Input Section ............................................................. 15
Reference Doubler and Reference Divider ............................. 34
RF N Divider ............................................................................... 15
Spurious Optimization and Fast Lock ..................................... 34
Phase Frequency Detector (PFD) and Charge Pump ............ 16
Optimizing Jitter......................................................................... 34
MUXOUT and Lock Detect ...................................................... 16
Spur Mechanisms ....................................................................... 34
Input Shift Registers ................................................................... 16
PLL Lock Time ........................................................................... 34
Program Modes .......................................................................... 17
Applications Information .............................................................. 36
VCO.............................................................................................. 17
Power Supplies ............................................................................ 36
Output Stage ................................................................................ 17
PCB Design Guidelines for a Chip Scale Package ................. 36
Register Maps .................................................................................. 19
Output Matching ........................................................................ 37
Register 0 ..................................................................................... 21
Outline Dimensions ....................................................................... 38
Register 1 ..................................................................................... 22
Ordering Guide .......................................................................... 38
Register 2 ..................................................................................... 22
REVISION HISTORY
8/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 38
Data Sheet
ADF5356
SPECIFICATIONS
AVDD = DVDD = VRF = 3.3 V ±5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred
to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
REFINA/REFINB CHARACTERISTICS
Input Frequency Range
Single-Ended Mode
Differential Mode
Input Sensitivity
Single-Ended Mode
Symbol
Min
Max
Unit
10
10
250
600
MHz
MHz
0.4
AVDD
V p-p
0.4
1.8
V p-p
±100
±250
125
pF
pF
μA
μA
MHz
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
High Value
Low Value
RSET Range
Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
Input Voltage
High
Low
Input Current, High/Low
Input Capacitance
LOGIC OUTPUTS
Output High Voltage
Output High Current
Output Low Voltage
POWER SUPPLIES
Analog Power
Digital Power and RF Supply
Voltage
CP and VCO Supply Voltage
Total Digital and Analog Current,
DIDD + AIDD3
Output Dividers
CP Supply Power Current
Supply Current
Test Conditions/Comments
For f < 10 MHz, ensure slew rate > 21 V/μs
Differential Mode
PFD
CHARGE PUMP (CP)
CP Current, Sink/Source
Typ
6.9
1.4
ICP
VINH
VINL
IINH/IINL
CIN
1.5
VOH
DVDD − 0.4
1.5
mA
mA
kΩ
%
%
%
DVDD
0.6
±1
3.0
3.15
4.75
Fixed
0.5 V ≤ VCP1 ≤ VP − 0.5 V
0.5 V ≤ VCP1 ≤ VP − 0.5 V
VCP1 = 2.5 V
V
V
μA
pF
500
0.4
V
V
μA
V
3.3
AVDD
3.45
V
5.0
82
5.25
92
6 to 36
8
70
9
90
1.8
IOH
VOL
IP
IVCO
Single-ended reference programmed
Differential reference programmed
RSET = 5.1 kΩ, this resistor is internal in the
ADF5356
4.8
0.3
5.1
3
3
1.5
AVDD
DVDD,
VRF
VP, VVCO
REFINA biased at AVDD/2; ac coupling ensures
AVDD/2 bias
Low voltage differential signaling (LVDS) and
Low voltage positive emitter-coupled logic
(LVPECL) compatible, REFINA/REFINB biased at
2.1 V; ac coupling ensures 2.1 V bias
3.3 V output selected
1.8 V output selected
IOL2 = 500 μA
See Table 7
Voltages must equal AVDD
Rev. 0 | Page 3 of 38
V
mA
VP must equal VVCO
mA
Each output divide by 2 consumes 6 mA
For maximum ICP = 4.8 mA
mA
ADF5356
Parameter
RFOUTA+/RFOUTA− and RFOUTB Supply
Current
Data Sheet
Symbol
IRFOUTx±
Min
Low Power Sleep Mode
RF OUTPUT CHARACTERISTICS
VCO Frequency Range
RFOUTB Output Frequency
Typ
Max
Unit
12
24
35
46
5
20
15
29
42
56
mA
mA
mA
mA
mA
mA
Test Conditions/Comments
RF Output A and RF Output B enabled;
RF Output A is programmable; enabling RF
Output B draws negligible extra current
−4 dBm setting
−1 dBm setting
2 dBm setting
5 dBm setting
Hardware power-down selected
Software power-down selected
6800
13600
12000
6800
MHz
MHz
MHz
MHz
Fundamental VCO range
2× VCO output (RFOUTB), prescaler = 8/9
2× VCO output (RFOUTB), prescaler = 4/5
Prescaler = 8/9
6000
MHz
MHz/V
MHz/V
MHz
Prescaler = 4/5
25
12
0.5
30
MHz
Voltage standing wave ratio (VSWR) = 2:1
RFOUTA/RFOUTA−
VSWR = 2:1 RFOUTB
−26
−29
−32
−14
−10
8
−1
0
2
±1
±1
±5
±3
−53
dBc
dBc
dBc
dBc
dBm
dBm
dBm
dBm
dBm
dB
dB
dB
dB
dBm
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
RFOUTB = 10 GHz
RFOUTA+ = 1 GHz; 7.4 nH inductor to VRF
RFOUTA+ = 6.8 GHz; 7.4 nH inductor to VRF
RFOUTB = 6.8 GHz
RFOUTB = 13.6 GHz
RFOUTA+ = 5 GHz
RFOUTB = 10 GHz
RFOUTA+ = 1 GHz to 6.8 GHz
RFOUTB = 6.8 GHz to 13.6 GHz
RFOUTA+ = 1 GHz
−20
−16
−12
dBm
dBm
dBm
RFOUTA+ = 6.8 GHz
RFOUTB = 6.8 GHz
RFOUTB = 13.6 GHz
3400
6800
6800
53.125
RFOUTA+/RFOUTA− Output
Frequency
53.125
VCO Sensitivity
Frequency Pushing (Open Loop)
Frequency Pulling (Open Loop)
Harmonic Content
Second
Third
Fundamental VCO Feedthrough
RF Output Power4
Variation
Variation over Frequency
Level of Signal with RF Output
Disabled
KV
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise
Performance
VCO noise in open-loop conditions
−115
−135
−137
−155
−113
−133
−135
−153
−110
−130
−132
−150
Rev. 0 | Page 4 of 38
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100 kHz offset from 3.4 GHz carrier
800 kHz offset from 3.4 GHz carrier
1 MHz offset from 3.4 GHz carrier
10 MHz offset from 3.4 GHz carrier
100 kHz offset from 5.0 GHz carrier
800 kHz offset from 5.0 GHz carrier
1 MHz offset from 5.0 GHz carrier
10 MHz offset from 5.0 GHz carrier
100 kHz offset from 6.8 GHz carrier
800 kHz offset from 6.8 GHz carrier
1 MHz offset from 6.8 GHz carrier
10 MHz offset from 6.8 GHz carrier
Data Sheet
Parameter
VCO 2× Phase Noise Performance
Normalized In-Band Phase Noise
Floor
Fractional Channel5
Integer Channel6
Normalized 1/f Noise, PN1_f7
Integrated RMS Jitter (1 kHz to
20 MHz)8
Spurious Signals Due to PFD
Frequency
ADF5356
Symbol
Min
Typ
Max
Unit
−110
−130
−132
−149
−107
−127
−129
−147
−103
−124
−126
−144
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−225
−227
−121
97
dBc/Hz
dBc/Hz
dBc/Hz
fs
−85
dBc
1
Test Conditions/Comments
VCO noise in open-loop conditions
100 kHz offset from 6.8 GHz carrier
800 kHz offset from 6.8 GHz carrier
1 MHz offset from 6.8 GHz carrier
10 MHz offset from 6.8 GHz carrier
100 kHz offset from 10 GHz carrier
800 kHz offset from 10 GHz carrier
1 MHz offset from 10 GHz carrier
10 MHz offset from 10 GHz carrier
100 kHz offset from 13.6 GHz carrier
800 kHz offset from 13.6 GHz carrier
1 MHz offset from 13.6 GHz carrier
10 MHz offset from 13.6 GHz carrier
10 kHz offset; normalized to 1 GHz
VCP is the voltage at the CPOUT pin.
IOL is the output low current.
TA = 25°C; AVDD = DVDD = VRF = 3.3 V; VVCO = VP = 5.0 V; prescaler = 8/9; fREFIN = 122.88 MHz; fPFD = 61.44 MHz; and fRF = 1650 MHz.
4
RF output power using the EV-ADF5356SD1Z evaluation board is measured by a spectrum analyzer, with board and cable losses de-embedded. Unused RF output pins
are terminated into 50 Ω.
5
Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−225 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel.
6
Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−227 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel.
7
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the
ADIsimPLL design tool.
8
Integrated rms jitter using the EV-ADF5356SD1Z evaluation board is measured by a spectrum analyzer. The EV-ADF5356SD1Z evaluation board is configured to accept
a single-ended REFIN signal (SMA 100) = 160 MHz, VCO frequency = 6 GHz, fPFD = 80 MHz, charge pump current = 0.9 mA, with bleed current off. The loop filter is
configured for an 80 kHz loop filter bandwidth. Unused RF output pins are terminated into 50 Ω.
2
3
Rev. 0 | Page 5 of 38
ADF5356
Data Sheet
TIMING CHARACTERISTICS
AVDD = DVDD =VRF = 3.3 V ±5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred
to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Write Timing
Parameter
fCLK
t1
t2
t3
t4
t5
t6
t7
Limit
50
10
5
5
10
10
10
20 or (2/fPFD), whichever is longer
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
Serial peripheral interface (SPI) CLK frequency
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Write Timing Diagram
t4
t5
CLK
t2
DATA
DB31 (MSB)
t3
DB30
DB3
(CONTROL BIT C4)
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
t1
t6
Figure 2. Write Timing Diagram
Rev. 0 | Page 6 of 38
15360-002
LE
Data Sheet
ADF5356
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 3.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required. θJA is the natural convection
junction to ambient thermal resistance measured in a one cubic
foot sealed enclosure.
Parameter
VRF, DVDD, AVDD to GND1
AVDD to DVDD
VP, VVCO to GND1
CPOUT to GND1
Digital Input/Output Voltage to GND1
Analog Input/Output Voltage to GND1
REFINA, REFINB to GND1
REFINA to REFINB
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Electrostatic Discharge (ESD)
Charged Device Model
Human Body Model
1
Rating
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to VP + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
±2.1 V
−40°C to +85°C
−65°C to +125°C
150°C
Table 4. Thermal Resistance
Package Type
CP-32-121
1
θJA
27.3
Unit
°C/W
Thermal impedance simulated values are based on use of a PCB with the
thermal impedance pad soldered to GND (GND = AGND = SDGND = AGNDRF =
AGNDVCO = CPGND = 0 V).
TRANSISTOR COUNT
The transistor count for the ADF5356 is 134,486 (CMOS) and
3874 (bipolar).
260°C
40 sec
ESD CAUTION
500 V
2000 V
GND = AGND = SDGND = AGNDRF = AGNDVCO = CPGND = 0 V.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The ADF5356 is a high performance RF integrated circuit with
an ESD rating of 2 kV and is ESD sensitive. Take proper
precautions for handling and assembly.
Rev. 0 | Page 7 of 38
ADF5356
Data Sheet
32
31
30
29
28
27
26
25
CREG 2
SDGND
MUXOUT
REFINA
REFINB
DVDD
PDBRF
CREG 1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADF5356
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
VBIAS
VREF
NIC
AGNDVCO
VTUNE
VREGVCO
AGNDVCO
VVCO
NOTES
1. NIC = NO INTERNAL CONNECTION. FOR EXISTING DESIGNS THAT CURRENTLY USE THE ADF5355,
TO UPGRADE TO THE ADF5356, THE RSET RESISTOR CAN BE LEFT CONNECTED TO THIS PIN.
2. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
15360-003
AGND
VRF
RFOUTA+
RFOUTA−
AGNDRF
RFOUTB
AGNDRF
AVDD
9
10
11
12
13
14
15
16
CLK
DATA
LE
CE
AVDD
VP
CPOUT
CPGND
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
CLK
2
DATA
3
LE
4
CE
5, 16
AVDD
6
VP
7
CPOUT
8
9
10
CPGND
AGND
VRF
11
RFOUTA+
12
RFOUTA−
13, 15
14
17
AGNDRF
RFOUTB
VVCO
18, 21
19
AGNDVCO
VREGVCO
Description
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four LSBs as the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is
selected by the four LSBs.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A
logic high on this pin powers up the device, depending on the status of the power-down bits.
Analog Power Supplies. These pins range from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog
ground plane as close to these pins as possible. AVDD must have the same value as DVDD.
Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the ground
plane as close to this pin as possible.
Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the loop
filter is connected to VTUNE to drive the internal VCO.
Charge Pump Ground. This output is the ground return pin for CPOUT.
Analog Ground. This pin is the ground return pin for AVDD.
Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin as
possible. VRF must have the same value as AVDD.
VCO Output. The output level is programmable. The VCO fundamental output, or a divided down version, is
available.
Complementary VCO Output. The output level is programmable. The VCO fundamental output, or a divided down
version, is available.
RF Output Stage Ground. This pin is the ground return pin for the RF output stage.
Auxiliary VCO Output. The 2× VCO output is available at this pin.
Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Place decoupling capacitors to the
analog ground plane as close to this pin as possible.
VCO Ground. This pin is the ground return path for the VCO.
VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible.
Connect VREGVCO directly to VVCO.
Rev. 0 | Page 8 of 38
Data Sheet
Pin No.
20
Mnemonic
VTUNE
22
NIC
23
VREF
24
25, 32
VBIAS
CREG1, CREG2
26
PDBRF
27
DVDD
28
29
30
REFINB
REFINA
MUXOUT
31
SDGND
EP
ADF5356
Description
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage. The capacitance at this pin (VTUNE input capacitance) is 9 pF.
No Internal Connection. For existing designs that currently use the ADF5355, to upgrade to the ADF5356, the RSET
resistor can be left connected to this pin.
Internal Compensation Node. This pin is dc biased at half the tuning range. Connect decoupling capacitors to the
ground plane as close to this pin as possible.
Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible.
Outputs from the LDO Regulator. CREG1 and CREG2 are the supply voltages to the digital circuits. These pins have a
nominal voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins.
RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software controllable. Do
not leave this pin floating.
Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground
plane as close to this pin as possible.
Complementary Reference Input. If unused, ac couple this pin to AGND.
Reference Input.
Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the
scaled reference frequency to be externally accessible.
Digital Σ-Δ Modulator Ground. SDGND is the ground return path for the Σ-Δ modulator.
Exposed Pad. The exposed pad must be connected to AGND.
Rev. 0 | Page 9 of 38
ADF5356
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
–50
–80
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
–90
–70
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–100
–90
–110
–130
–110
–120
–130
–140
–150
–150
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 4. Open-Loop VCO Phase Noise, 3.4 GHz
–50
–70
–70
–90
–110
–130
–150
10M
100M
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
–90
–110
–130
100k
1M
10M
100M
–170
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
15360-008
10k
15360-005
1k
Figure 5. Open-Loop VCO Phase Noise, 5.0 GHz
Figure 8. Closed-Loop Phase Noise, RFOUTA+ (100 nH Inductors),
Fundamental VCO and Dividers, VCO = 5.0 GHz, PFD = 61.44 MHz, Loop
Bandwidth = 40 kHz
–50
–70
–70
PHASE NOISE (dBc/Hz)
–50
–90
–110
–130
–150
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
–90
–110
–130
1k
10k
100k
1M
10M
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 6. Open-Loop VCO Phase Noise, 6.8 GHz
100M
–170
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
15360-009
–150
15360-006
PHASE NOISE (dBc/Hz)
1M
–150
FREQUENCY OFFSET FROM CARRIER (Hz)
–170
100k
Figure 7. Closed-Loop Phase Noise, RFOUTA+ (100 nH Inductors),
Fundamental VCO and Dividers, VCO = 3.4 GHz, PFD = 61.44 MHz, Loop
Bandwidth = 40 kHz
–50
–170
10k
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–170
1k
15360-004
–170
15360-007
–160
Figure 9. Closed-Loop Phase Noise, RFOUTA+ (100 nH Inductors),
Fundamental VCO and Dividers, VCO = 6.8 GHz, PFD = 61.44 MHz, Loop
Bandwidth = 40 kHz
Rev. 0 | Page 10 of 38
ADF5356
–60
–60
–80
–80
PHASE NOISE (dBc/Hz)
DIV1
–100
DIV2
–120
–140
–140
–160
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
–180
15360-010
–180
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 13. Closed-Loop Phase Noise, RFOUTB = 6.8 GHz, 2× VCO,
VCO = 3.4 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 10 kHz,
Figure 10. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 3.4 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 10 kHz
–60
–60
–80
–80
DIV1
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–120
15360-013
–160
–100
–100
DIV2
–120
–140
–100
–120
–140
–160
–160
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
–180
15360-011
–180
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
15360-014
PHASE NOISE (dBc/Hz)
Data Sheet
Figure 14. Closed-Loop Phase Noise, RFOUTB = 10 GHz, 2× VCO,
VCO = 5.0 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 10 kHz
Figure 11. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 5.0 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 10 kHz
–60
–60
–70
–80
DIV1
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–80
–100
DIV2
–120
–140
–90
–100
–110
–120
–130
–140
–160
1k
10k
100k
1M
10M
FREQUENCY OFFSET FROM CARRIER (Hz)
100M
Figure 12 Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 6.8 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 10 kHz
Rev. 0 | Page 11 of 38
–160
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 15. Closed-Loop Phase Noise, RFOUTB = 13.6 GHz, 2× VCO,
VCO = 6.8 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 10 kHz
15360-015
–180
15360-012
–150
ADF5356
Data Sheet
15
6800
VCO FREQUENCY (MHz)
Figure 19. VCO Feedthrough at RFOUTB (Board and Cable Losses DeEmbedded) vs. VCO Frequency
Figure 17. Harmonics and RFOUTA+/RFOUTA− Output Power of Carrier vs.
Output Frequency (7.4 nH Inductors, 10 pF AC Coupling Capacitors, Board
and Cable Losses De-Embedded)
15360-020
13.6
–80
13.2
–80
12.8
–70
12.4
–70
12.0
–60
11.6
OUTPUT FREQUENCY (GHz)
–60
11.2
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
–50
10.8
0
15360-017
–60
–60
–50
10.4
–50
–40
10.0
–50
–40
9.6
–40
–30
9.2
–40
–30
8.8
–30
–10
–20
8.4
–30
THIRD HARMONIC (dBc)
FOURTH HARMONIC (dBc)
FIFTH HARMONIC (dBc)
–20
8.0
–20
7.6
–20
–10
7.2
–10
0
CARRIER (dBm)
SECOND HARMONIC (dBc)
6.8
–10
10
0
HARMONICS (dBc)
CARRIER (dBm)
SECOND HARMONIC (dBc)
THIRD HARMONIC (dBc)
FOURTH HARMONIC (dBc)
FIFTH HARMONIC (dBc)
OUTPUT POWER OF CARRIER (dBm)
0
0
HARMONICS (dBc)
10
10
OUTPUT POWER OF CARRIER (dBm)
Figure 16. RFOUTA+/RFOUTA− Output Power vs. Output Frequency, (7.4 nH
Inductors, 10 pF AC Coupling Capacitors, Board and Cable Losses DeEmbedded)
10
15360-019
6600
7.0
6400
6.5
6200
6.0
6000
5.5
5800
5.0
5600
4.5
5400
4.0
5200
3.5
5000
3.0
OUTPUT FREQUENCY (GHz)
4800
2.5
4600
2.0
4400
1.5
4200
1.0
3400
–10
15360-016
–5
4000
0
3800
5
3600
OUTPUT POWER (dBm)
VCO FEEDTHROUGH (dBm)
TA = +85°C
TA = +25°C
TA = –40°C
10
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
–17
–18
–19
OUTPUT FREQUENCY (GHz)
Figure 20. Harmonics and RFOUTB Output Power of Carrier vs. Output
Frequency (10 pF AC Coupling Capacitors, Board and Cable Losses DeEmbedded)
0
3
2
–10
0
–1
POWER (dBm)
OUTPUT POWER (dBm)
1
–2
TA = +85°C
TA = +25°C
TA = –40°C
–3
–4
–20
–30
–40
–5
–6
–50
–60
13.8
13.3
12.8
15360-018
OUTPUT FREQUENCY (GHz)
12.3
11.8
11.3
10.8
9.8
10.3
9.3
8.8
8.3
7.8
7.3
6.8
–8
5
7
9
11
13
15
17
FREQUENCY (GHz)
Figure 18. RFOUTB Output Power vs. Output Frequency (10 pF AC Coupling
Capacitors, Board and Cable Losses De-Embedded)
19
21
23
25
15360-021
–7
Figure 21. Wideband Spectrum, RFOUTB, VCO = 6.8 GHz, RFOUTB Enabled,
RFOUTA+/RFOUTA− Disabled (Board Measurement)
Rev. 0 | Page 12 of 38
Data Sheet
ADF5356
250
–40
13300
12800
OUTPUT FREQUENCY (MHz)
–110
12300
7000
11800
6000
11300
5000
10800
4000
9800
3000
10300
2000
9300
1000
–100
8800
0
–90
8300
0
15360-022
50
–80
7800
100
–70
7300
150
–60
6800
RMS JITTER/NOISE (fs)
200
PFD = 122.88MHz
PFD = 61.44MHz
PFD = 30.72MHz
–50
15360-024
WORST CASE PFD/REFERENCE SPUR (dBc)
1kHz TO 20MHz
12kHz TO 20MHz
OUTPUT FREQUENCY (MHz)
Figure 24. Worst Case PFD/Reference Spur vs. Output Frequency (RFOUTB),
fPFD = 30.72 MHz, 61.44 MHz, and 122.88 MHz, Loop Filter = 3 kHz
Figure 22. RMS Jitter/Noise vs. Output Frequency,
PFD Frequency = 61.44 MHz, Loop Filter = 40 kHz
–60
–60
–70
–80
–90
–100
–110
0
1000
2000
3000
4000
5000
6000
7000
OUTPUT FREQUENCY (MHz)
Figure 23. Worst Case PFD/Reference Spur vs. Output Frequency
(RFOUTA+/RFOUTA−), fPFD = 30.72 MHz, 61.44 MHz, and 122.88 MHz,
Loop Filter = 3 kHz
–80
–100
–120
–140
–160
–180
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
15360-025
–50
NOISE AND SPUR POWER (dBc/Hz)
PFD = 122.88MHz
PFD = 61.44MHz
PFD = 30.72MHz
15360-023
WORST CASE PFD/REFERENCE SPUR (dBc)
–40
Figure 25. Fractional-N Spur Performance, GSM1800 Band, RFOUTA+ =
1550.2 MHz, fREFIN = 122.88 MHz, fPFD = 61.44 MHz, Output Divide by 4
Selected, Loop Filter Bandwidth = 10 kHz, Channel Spacing = 20 kHz
Rev. 0 | Page 13 of 38
ADF5356
Data Sheet
4650
–60
4550
FREQUENCY (MHz)
NOISE AND SPUR POWER (dBc/Hz)
4600
–80
–100
–120
–140
4500
4450
1
4400
4350
4300
4250
–160
100k
1M
10M
100M
FREQUENCY (Hz)
4150
–1
15360-026
10k
Figure 26. Fractional-N Spur Performance, W-CDMA Band, RFOUTA+ =
2113.5 MHz, fREFIN = 122.88 MHz, fPFD = 61.44 MHz, Output Divide by 2
Selected, Loop Filter Bandwidth = 10 kHz, Channel Spacing = 20 kHz
–120
–140
–160
100k
1M
10M
100M
15360-027
NOISE AND SPUR POWER (dBc/Hz)
–100
FREQUENCY (Hz)
2
3
4
Figure 28. Lock Time for 250 MHz Jump from 4150 MHz to 4400 MHz,
Loop Bandwidth = 23 kHz
–80
10k
1
TIME (ms)
–60
–180
1k
0
15360-028
4200
–180
1k
Figure 27. Fractional-N Spur Performance, RFOUTA+ = 2.591 GHz,
fREFIN = 122.88 MHz, fPFD = 61.44 MHz, Output Divide by 2 Selected,
Loop Filter Bandwidth = 10 kHz, Channel Spacing = 20 kHz
Rev. 0 | Page 14 of 38
Data Sheet
ADF5356
THEORY OF OPERATION
REFERENCE INPUT SECTION
INT, FRACx, MODx, and R Counter Relationship
Figure 29 shows the reference input stage. The reference input
can accept both single-ended and differential signals. Use the
reference mode bit (Register 4, Bit DB9) to select the signal. To
use a differential signal on the reference input, program this bit
high. In this case, SW1 and SW2 are open, SW3 and SW4 are
closed, and the current source that drives the differential pair of
transistors switches on. The differential signal buffers and provides
an emitter coupled logic (ECL) to the CMOS converter. When a
single-ended signal is used as the reference, program Bit DB9
in Register 4 to 0. Connect the single-ended reference signal to
REFINA. In this case, SW1 and SW2 are closed, SW3 and SW4
are open, and the current source that drives the differential pair
of transistors switches off.
The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in
conjunction with the R counter, make it possible to generate
output frequencies spaced by fractions of the PFD frequency
(fPFD). For more information, see the RF Synthesizer—A Worked
Example section.
REFERENCE
INPUT MODE
85kΩ
SW2
BUFFER
SW1
SW3
MULTIPLEXER
TO
R COUNTER
AVDD
Calculate the RF VCO frequency (VCOOUT) as follows:
VCOOUT = fPFD × N
where:
VCOOUT is the output frequency of the VCO (without using the
output divider).
fPFD is the frequency of the phase frequency detector.
N is the desired value of the feedback counter, N.
Calculate fPFD as follows:
fPFD = fREFIN × ((1 + D)/(R × (1 + T)))
(2)
where:
fREFIN is the reference input frequency.
D is the fREFIN doubler bit.
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
T is the fREFIN divide by 2 bit (0 or 1).
N comprises
ECL TO CMOS
BUFFER
N INT
REFINA
REFINB
2.5kΩ
2.5kΩ
15360-029
SW4
BIAS
GENERATOR
Figure 29. Reference Input Stage
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. Determine the division ratio by the INT, FRAC1, FRAC2,
and MOD2 values that this divider comprises.
RF N COUNTER
FRAC1 +
N = INT +
MOD2
MOD1
TO PFD
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
REG
FRAC1
REG
FRAC2
VALUE
MOD2
VALUE
15360-030
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
FRAC2
(1)
FRAC2
MOD2
MOD1
FRAC1
(3)
where:
INT is the 16-bit integer value (23 to 32,767 for the 4/5
prescaler, and 75 to 65,535 for the 8/9 prescaler).
FRAC1 is the numerator of the primary modulus (0 to 16,777,215).
FRAC2 is the numerator of the 28-bit auxiliary modulus
(0 to 268,435,455).
MOD2 is the programmable, 28-bit auxiliary fractional
modulus (2 to 268,435,455).
MOD1 is a 24-bit primary modulus with a fixed value of 224 =
16,777,216.
Equation 3 results in a very fine frequency resolution with no
residual frequency error. To apply this formula, take the
following steps:
1. Calculate N by dividing VCOOUT/fPFD. The integer value of
this number forms INT.
2. Subtract the INT value from the full N value.
3. Multiply the remainder by 224. The integer value of this
number forms FRAC1.
4. Calculate MOD2 based on the channel spacing (fCHSP) as
follows:
MOD2 = fPFD/GCD(fPFD, fCHSP)
(4)
Figure 30. RF N Divider
Rev. 0 | Page 15 of 38
where:
GCD(fPFD, fCHSP) is the greatest common divider of the PFD
frequency and the desired channel spacing frequency.
fCHSP is the desired channel spacing frequency.
ADF5356
Calculate FRAC2 as follows:
FRAC2 = ((N − INT) × 224 − FRAC1)) × MOD2
MUXOUT AND LOCK DETECT
(5)
The FRAC2 and MOD2 fraction results in outputs with zero
frequency error for channel spacings when
fPFD/GCD(fPFD/fCHSP) < 268,435,455
(6)
where:
fPFD is the frequency of the phase frequency detector.
GCD is a greatest common denominator function.
fCHSP is the desired channel spacing frequency.
The output multiplexer on the ADF5356 allows the user to access
various internal points on the chip. The M3, M2, and M1 bits in
Register 4 control the state of MUXOUT. Figure 32 shows the
MUXOUT section in block diagram form.
DVDD
THREE-STATE OUTPUT
DVDD
SDGND
If zero frequency error is not required, the MOD1 and MOD2
denominators operate together to create a 52-bit resolution
modulus.
R DIVIDER OUTPUT
N DIVIDER OUTPUT
MUX
CONTROL
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
Integer N Mode
RESERVED
When FRAC1 and FRAC2 are 0, the synthesizer operates in
integer N mode.
SDGND
R Counter
The 10-bit R counter allows the input reference frequency
(fREFIN) to be divided down to produce the reference clock to the
PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 31 is a simplified schematic of
the phase frequency detector. The PFD includes a fixed delay
element that sets the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and provides a consistent reference spur level. Set the phase
detector polarity to positive on this device because of the
positive tuning of the VCO.
HIGH
D1
Q1
CLR1
DELAY
U3
CHARGE
PUMP
CP
CLR2
DOWN
D2
Q2
U2
–IN
Figure 31. PFD Simplified Schematic
15360-031
HIGH
Figure 32. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF5356 digital section includes a 10-bit R counter, a
16-bit RF integer N counter, a 24-bit FRAC1 counter, a 28-bit
auxiliary fractional counter, and a 28-bit auxiliary modulus
counter. Data clocks into the 32-bit shift register on each rising
edge of CLK. The data clocks in MSB first. Data transfers from
the shift register to one of 13 latches on the rising edge of LE.
The state of the four control bits (C4, C3, C2, and C1) in the
shift register determines the destination latch. As shown in
Figure 2, the four least significant bits (LSBs) are DB3, DB2,
DB1, and DB0. The truth table for these bits is shown in Table 6.
Figure 36 and Figure 37 summarize the programming of the
latches.
Table 6. Truth Table for the C4, C3, C2, and C1 Control Bits
UP
U1
+IN
MUXOUT
15360-032
5.
Data Sheet
C4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Rev. 0 | Page 16 of 38
C3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
Control Bits
C2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
C1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
Data Sheet
ADF5356
50
VCO SENSITIVITY, KV (MHz/V)
Table 6 and Figure 38 through Figure 51 show how the program
modes must be set up for the ADF5356.
The following settings in the ADF5356 are double-buffered: main
fractional value (FRAC1), auxiliary modulus value (MOD2),
auxiliary fractional value (FRAC2), reference doubler, reference
divide by 2 (RDIV2), R counter value, and charge pump current
setting. Two events must occur before the ADF5356 uses a new
value for any of the double-buffered settings. First, the new value
must latch into the device by writing to the appropriate register,
and second, a new write to Register 0 must be performed.
VCO
The VCO core in the ADF5356 consists of four separate VCOs,
each of which uses 256 overlapping bands, which allows the
device to cover a wide frequency range without large VCO
sensitivity (KV) and without resulting in poor phase noise and
spurious performance.
The correct VCO and band are chosen automatically by the
VCO and band select logic when Register 0 is updated and
autocalibration is enabled.
The R counter output is the clock for the band select logic. After
band selection, normal PLL action resumes. The nominal value of
KV is 25 MHz/V when the N divider is driven from the VCO
output, or the KV value is divided by D. D is the output divider
value if the N divider is driven from the RF output divider (chosen
by programming Bits[DB23:DB21] in Register 6).
The VCO shows variations of KV as the tuning voltage, VTUNE, varies
within the band and from band to band. For wideband applications
covering a wide frequency range (and changing output dividers), a
value of 25 MHz/V provides the most accurate KV, because this
value is closest to the average value. Figure 33 shows how KV varies
with the fundamental VCO frequency along with an average value
for the frequency band. Users may prefer this KV value shown in
Figure 33 when using narrow-band designs.
LINEAR
TREND LINE
30
20
10
0
3.4
3.8
4.2
4.6
5.0
5.4
5.8
6.2
6.6
FREQUENCY (GHz)
Figure 33. VCO Sensitivity, KV vs. Frequency
OUTPUT STAGE
The RFOUTA+ and RFOUTA− pins of the ADF5356 connect to
the collectors of a negative/positive/negative (NPN) differential
pair driven by buffered outputs of the VCO, as shown in Figure 34.
In this scheme, the ADF5356 contains internal 50 Ω resistors
connected to the VRF pin. To optimize the power dissipation vs.
the output power requirements, the tail current of the differential
pair is programmable using Bits[DB5:DB4] in Register 6. Four
current levels can be set. These levels give approximate output
power levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm,
respectively. Levels of −4 dBm, −1 dBm, and +2 dBm can be
achieved using a 50 Ω resistor connected to VRF and ac coupling
into a 50 Ω load. For accurate power levels, refer to the Typical
Performance Characteristics section. An output power of 5 dBm
requires an external shunt inductor to provide higher power levels;
however, this addition results in less wideband performance
using the internal bias only. Terminate the unused complementary
output with a similar circuit to the used output.
VRF
VRF
50Ω
50Ω
RFOUTA+
VCO
RFOUTA–
BUFFER/
DIVIDE BY
1/2/4/8/
16/32/64
15360-034
For example, to ensure that the modulus value loads correctly,
every time that the modulus value updates, Register 0 must be
written to. The RF divider select in Register 6 is also double
buffered, but only if DB14 of Register 4 is high.
AVERAGE
VCO SENSITIVITY
40
15360-033
PROGRAM MODES
Figure 34. Output Stage
2× VCO
MUX
RFOUTB
Figure 35. Output Stage
Rev. 0 | Page 17 of 38
15360-035
The doubled VCO output (6.8 GHz to 13.6 GHz) is available on
the RFOUTB pin, which can be ac-coupled to the next circuit.
ADF5356
Data Sheet
RFOUTB directly connects to the VCO, and it can be muted but
only by using the RF Output B enable bit (Bit DB10) in Register 6.
Another feature of the ADF5356 is that the supply current to
the RFOUTA+/RFOUTA− output stage can shut down until the
ADF5356 achieves lock as measured by the digital lock detect
circuitry. The mute till lock detect (MTLD) bit (Bit DB11) in
Register 6 enables this function.
Table 7. Total IDD1 (RF Output A Enabled)2
Supply
5 V Supply (IVCO and ICP)
3.3 V Supply (AIDD, DIDD, and
IRFOUTx±)
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
1
2
RFOUTA± Off
(mA)
74
RFOUTA± = −4 dBm
(mA)
74
RFOUTA± = −1 dBm
(mA)
74
RFOUTA± = +2 dBm
(mA)
74
RFOUTA± = +5 dBm
(mA)
74
82.6
91.9
101.7
109.7
114.7
118.7
121.1
103.9
112.6
122.6
130.6
135.7
139.7
142.1
115.1
123.5
134.0
142.1
147.3
151.4
153.8
126.1
134.3
145.2
153.5
158.6
162.7
165.2
136.9
144.5
156.0
164.8
169.8
174.1
176.4
IDD is the total current of IVCO, ICP, AIDD, DIDD, and IRFOUTx±.
RFOUTA± refers to RFOUTA+/RFOUTA−.
Rev. 0 | Page 18 of 38
Data Sheet
ADF5356
REGISTER MAPS
AUTOCAL
PRESCALER
REGISTER 0
RESERVED
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
0
0
0
0
0
0
0
0
0
AC1
PR1
N16
N15
N14
N12
N13
N11
N10
N9
N8
N7
DB8
DB7
DB6
DB5
DB4
N5
N4
N3
N2
N1
N6
DB3
DB2
DB1
DB0
C4(0) C3(0) C2(0) C1(0)
REGISTER 1
RESERVED
CONTROL
BITS
DBR 1
24-BIT MAIN FRACTIONAL VALUE (FRAC1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12
0
0
0
0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
DB11 DB10 DB9
F9
F8
F7
DB8 DB7
F6
F5
F4
DB6 DB5
F3
F2
DB4 DB3
F1
DB2
DB1
DB0
C4(0) C3(0) C2(0) C1(1)
REGISTER 2
14-BIT AUXILIARY FRACTIONAL LSB VALUE (FRAC2_LSB) DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
CONTROL
BITS
14-BIT AUXILIARY MODULUS MSB VALUE (MOD2_LSB) DBR 1
F4
F3
F2
F1
M14
M13
M12
M11
M10
M9
M8
M7
M6
DB8
DB7
DB6
DB5
M5
M4
M3
M2
DB4 DB3
DB2
DB1
DB0
M1 C4(0) C3(0) C2(1) C1(0)
PHASE
ADJUST
PHASE
RESYNC
RESERVED
SD LOAD
RESET
REGISTER 3
CONTROL
BITS
DBR 1
24-BIT PHASE VALUE (PHASE)
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
DB2
DB1
DB0
P5
P4
P3
P2
P1
C4(0) C3(0) C2(1) C1(1)
COUNTER
RESET
PA1
CP THREESTATE
PR1
POWER-DOWN
SD1
PD
POLARITY
0
MUX LOGIC
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
CONTROL
BITS
DBR 1
10-BIT R COUNTER
CURRENT
SETTING
REF MODE
DOUBLE BUFF
MUXOUT
RDIV2 DBR 1
RESERVED
REFERENCE
DOUBLER DBR 1
REGISTER 4
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
M3
M2
M1
RD2
RD1
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
D1
CP4
CP3
CP2
CP1
U6
U5
U4
U3
U2
U1
DB2
DB1
DB0
C4(0) C3(1) C2(0) C1(0)
REGISTER 5
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
DB9
DB8
DB7
DB6
DB5
0
0
0
0
1
0
DB4 DB3
0
DB2
DB1
DB0
C4(0) C3(1) C2(0) C1(1)
BL10
BL9
1
0
1
0
D9
D8
D7
D6
BL8
BL7
BL6
BL5
BL4
BL3
BL2
BL1
0
D5
1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY A WRITE TO REGISTER 0.
2DBB = DOUBLE BUFFERED BITS—BUFFERED BY A WRITE TO REGISTER 0 WHEN BIT DB14 OF REGISTER 4 IS HIGH.
Figure 36. Register Summary (Register 0 to Register 6)
Rev. 0 | Page 19 of 38
D4
RESERVED
RF
OUTPUT A
POWER
DB9 DB8 DB7 DB6 DB5 DB4
0
0
0
D3
D2
D1
CONTROL
BITS
DB3
DB2
DB1
DB0
C4(0) C3(1) C2(1) C1(0)
15360-036
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
BP1
CHARGE PUMP BLEED CURRENT
RF OUTPUT A
ENABLE
RF OUTPUT B
ENABLE
RESERVED
DB31
RESERVED
RF DIVIDER
SELECT 1
MTLD
GATED
BLEED
FEEDBACK
SELECT
BLEED
POLARITY
NEGATIVE
BLEED
REGISTER 6
ADF5356
Data Sheet
LD MODE
LD
CYCLE
COUNT
RESERVED
FRAC-N LD
PRECISION
LOL MODE
LE SYNC
RESERVED
RESERVED
LE SEL
SYNC EDGE
REGISTER 7
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
0
0
0
LE2
1
LE1
0
0
0
0
0
0
0
0
0
0
0
0
0
LD4
LD5
0
0
LOL LD3
CONTROL
BITS
DB3
DB2
DB1
DB0
LD2 LD1 C4(0) C3(1) C2(1) C1(1)
REGISTER 8
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
DB7 DB6
0
1
1
DB5 DB4
1
0
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(0) C1(0)
REGISTER 9
AUTOMATIC
LEVEL CALIBRATION
TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14
VC8
VC7
VC6
VC5
VC4
VC3
VC2
VC1
TL10
TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
DB13 DB12 DB11 DB10
TL1
AL5
AL4
AL3
SYNTHESIZER
LOCK TIMEOUT
CONTROL
BITS
DB9
DB8 DB7 DB6 DB5 DB4
AL1
SL5
AL2
SL4
SL3
DB3
DB2
DB1
DB0
SL2
SL1 C4(1) C3(0) C2(0) C1(1)
ADC ENABLE
TIMEOUT
ADC
CONVERSION
VCO BAND DIVISION
REGISTER 10
ADC
CLOCK DIVIDER
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
CONTROL
BITS
DB13 DB12 DB11 DB10
DB9
DB8 DB7 DB6 DB5 DB4
AD8
AD4
AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)
AD7
AD6
AD5
DB3
DB2
DB1
DB0
VCO BAND HOLD
REGISTER 11
RESERVED
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
VH
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
DB7 DB6
0
0
DB5 DB4
0
0
0
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(1) C1(1)
REGISTER 12
PHASE RESYNC CLOCK VALUE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
CONTROL
BITS
RESERVED
P7
P6
P5
P4
P3
P2
P1
0
1
DB9
DB8
DB7
DB6
DB5
DB4
0
1
1
1
1
1
DB3
DB2
DB1
DB0
C4(1) C3(1) C2(0) C1(0)
REGISTER 13
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
1DBR
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
CONTROL
BITS
14-BIT AUXILIARY MODULUS MSB VALUE (MOD2_MSB) DBR 1
F3
F2
F1
M14
M13
M12
M11
M10
M9
M8
M7
= DOUBLE BUFFERED REGISTER—BUFFERED BY A WRITE TO REGISTER 0.
Figure 37. Register Summary (Register 7 to Register 13)
Rev. 0 | Page 20 of 38
M6
DB8
DB7
DB6
DB5
M5
M4
M3
M2
DB4 DB3
DB2
DB1
DB0
M1 C4(1) C3(1) C2(0) C1(1)
15360-037
14-BIT AUXILIARY FRACTIONAL MSB VALUE (FRAC2_MSB) DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
0
0
0
0
0
0
0
0
0
AC1
PR1
N16
PR1
PRESCALER
0
1
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
N15
N14
4/5
8/9
AC1
VCO
AUTOCAL
0
1
DISABLED
DISABLED
N13
N12
N11
N10
N9
N8
DB8
DB7
DB6
DB5
DB4
N7
N6
N5
N4
N3
N2
N1
N16
N15
....
N5
N4
N3
N2
N1
0
0
0
.
0
0
0
.
1
1
1
0
0
0
.
0
0
0
.
1
1
1
....
....
....
....
....
....
....
....
....
....
....
0
0
0
.
1
1
1
.
1
1
1
0
0
0
.
0
0
1
.
1
1
1
0
0
0
.
1
1
0
.
1
1
1
0
0
1
.
1
1
0
.
0
1
1
0
1
0
.
0
1
0
.
1
0
1
DB1
DB0
C4(0) C3(0) C2(0)
DB3
DB2
C1(0)
INTEGER VALUE (INT)
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
....
NOT ALLOWED
23
24
....
65533
65534
65535
INTMIN = 75 WITH PRESCALER = 8/9
15360-038
RESERVED
PRESCALER
ADF5356
AUTOCAL
Data Sheet
Figure 38. Register 0 Details
REGISTER 0
Prescaler Value
Control Bits
The dual modulus prescaler (P/P + 1), together with the INT,
FRACx, and MODx counters, determines the overall division
ratio from the VCO output to the PFD input. The PR1 bit
(Bit DB20) in Register 0 sets the prescaler value.
With C4 to C1 (Bits[DB3:DB0]) set to 0000, Register 0 is
programmed. Figure 38 shows the input data format for
programming this register.
Reserved
Bits[DB31:DB22] are reserved and must be set to 0.
Automatic Calibration (AUTOCAL)
Write to Register 0 to enact (by default) the VCO automatic
calibration, and to choose the appropriate VCO and VCO subband.
Write 1 to the AC1 bit (Bit DB21) to enable the automatic
calibration, which is the recommended mode of operation.
Set the AC1 bit (Bit DB21) to 0 to disable the automatic calibration,
which leaves the ADF5356 in the same band it is in when
Register 0 updates.
Disable the automatic calibration only for fixed frequency
applications, phase adjust applications, or very small ( (50 μs × fPFD)/Timeout
VCO Band Division
VC8 to VC1 (Bits[DB31:DB24]) set the value of the VCO band
division clock. Determine the value of this clock by
VCO Band Division = ceiling(fPFD/1,600,000)
where ceiling() is a function that rounds up to the nearest
integer.
Synthesizer Lock Timeout
SL5 to SL1 (Bits[DB8:DB4]) set the synthesizer lock timeout
value. This value allows the VTUNE force to settle on the VTUNE pin.
The value must be 20 μs. Calculate the value using the following
equation:
Synthesizer Lock Timeout > (20 μs × fPFD)/Timeout
Rev. 0 | Page 29 of 38
ADC
CLOCK DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
AD8
AD7
AD6
AD5
AD4
AD3 AD2
AD7
..........
AD2
0
0
..........
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
252
1
1
..........
0
1
253
1
1
..........
1
0
254
1
1
..........
1
1
255
DB3
DB2
DB1
DB0
AE2 AE1 C4(1) C3(0) C2(1) C1(0)
AD1
AE2
AD8
CONTROL
BITS
AE1
ADC
0
DISABLED
1
ENABLED
ADC CONVERSION
0
DISABLED
1
ENABLED
AD1 ADC CLK DIV
15360-048
RESERVED
ADC ENABLE
Data Sheet
ADC
CONVERSION
ADF5356
Figure 48. Register 10 Details
AD8 to AD1 (Bits[DB13:DB6]) set the value of this divider. On
power-up, the R counter is not programmed; however, in these
power-up cases, it defaults to R = 1.
REGISTER 10
Control Bits
With C4 to C1 (Bits[DB3:DB0]) set to 1010, Register 10 is
programmed. Figure 48 shows the input data format for
programming this register.
Choose the value such that
ADC_CLK_DIV = ceiling(((fPFD/100,000) − 2)/4)
Reserved
Bits[DB31:DB14] are reserved. Bits[DB23:DB22] must be set to
11, and all other bits in this range must be set to 0.
For example, for fPFD = 61.44 MHz, set ALC_CLK_DIV = 154
so that the ADC clock frequency is 99.417 kHz.
If ADC_CLK_DIV is greater than 255, set it to 255.
ADC Clock Divider (ADC_CLK_DIV)
ADC Conversion Enable
An on-board analog-to-digital converter (ADC) determines the
VTUNE setpoint relative to the ambient temperature of the
ADF5356 environment. The ADC ensures that the initial tuning
voltage in any application is chosen correctly to avoid any
temperature drift issues.
AE2 (Bit DB5) ensures that the ADC performs a conversion
when a write to Register 10 is performed. It is recommended to
enable this mode.
The ADC uses a clock that is equal to the output of the R counter
(or the PFD frequency) divided by ADC_CLK_DIV.
ADC Enable
AE1 (Bit DB4), when set to 1, powers up the ADC for the
temperature dependent VTUNE calibration. It is recommended to
always use this function.
Rev. 0 | Page 30 of 38
ADF5356
VCO BAND HOLD
Data Sheet
RESERVED
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
0
0
0
0
0
VH
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(1) C1(1)
VCO BAND HOLD
VH
0
1
15360-049
0
NORMAL OPERATION
VCO BAND HOLD
Figure 49. Register 11 Details
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P20
P19
...
P5
P4
P3
P2
P1
RESYNC CLOCK
0
0
...
0
0
0
0
0
NOT ALLOWED
0
0
...
0
0
0
0
1
1
0
0
...
0
0
0
1
0
2
.
.
...
.
.
.
.
.
...
0
0
...
1
0
1
1
0
22
0
0
...
1
0
1
1
1
23
0
0
...
1
1
0
0
0
24
.
.
...
.
.
.
.
.
...
1
1
...
1
1
1
0
1
65533
1
1
...
1
1
1
1
0
65534
1
1
...
1
1
1
1
1
1048575
P5
P4
P3
P2
P1
0
1
DB9
DB8
DB7
DB6
DB5
DB4
0
1
1
1
1
1
DB3
DB2
DB1
DB0
C4(1) C3(1) C2(0) C1(0)
15360-050
P20
CONTROL
BITS
RESERVED
PHASE RESYNC CLOCK VALUE
Figure 50. Register 12 Details
REGISTER 11
REGISTER 12
Control Bits
Control Bits
With C4 to C1 (Bits[DB3:DB0]) set to 1011, Register 11 is
programmed. Figure 49 shows the input data format for
programming this register.
With C4 to C1 (Bits[DB3:DB0]) set to 1100, Register 12 is
programmed. Figure 50 shows the input data format for
programming this register.
Reserved
Phase Resynchronization Clock Value
Bits[DB31:DB25] are reserved and must be set to 0. Bit DB22,
Bit DB21, Bit DB16, and Bit DB13 must be set to 1, and all other
bits in this range (Bits[DB23:DB4]) must be set to 0.
P20 to P1 (Bits[DB31:DB12]) set the timeout counter for
activation of the phase resynchronization. This value must be
set such that a resynchronization occurs immediately after (and
not before) the PLL has achieved lock, after reprogramming.
VCO Band Hold
VH (Bit DB24), when set to 1, prevents a reset of the VCO core,
band, and bias during a counter reset. VCO band hold is
required for applications that use external PLLs.
Calculate the timeout value using the following equation:
Timeout Value = Phase Resynchronization Clock Value/fPFD
When not using phase resynchronization, set these bits to 1 for
normal operation.
Reserved
Bits [DB11:DB4] are reserved. Bit DB11 and Bit DB9 must be
set to 0, and all other bits in this range must be set to 1.
Rev. 0 | Page 31 of 38
ADF5356
Data Sheet
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
CONTROL
BITS
14-BIT AUXILIARY MODULUS MSB VALUE (MOD2_MSB) DBR1
F3
F2
F1
M14
M13
M12
M11
M10
M9
M8
M7
DB8
DB7
DB6
DB5
DB4
M6
M5
M4
M3
M2
M1
F14
F13
..........
F2
F1
FRAC2_MSB WORD
M14
M13
..........
M2
M1
MOD2_MSB VALUE
0
0
..........
0
0
0
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
0
2
0
0
..........
1
1
3
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
16381
1
1
..........
0
0
16380
1
1
..........
0
1
16382
1
1
..........
0
1
16381
1
1
..........
1
0
16382
1
1
..........
1
0
16382
1
1
.........
1
1
16383
1
1
.........
1
1
16383
DB3
DB2
DB1
DB0
C4(1) C3(1) C2(0) C1(1)
1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY A WRITE TO REGISTER 0.
15360-051
14-BIT AUXILIARY FRACTIONAL MSB VALUE (FRAC2_MSB) DBR 1
Figure 51. Register 13 Details
11.
12.
13.
14.
Register 3.
Register 2.
Register 1.
Ensure that >16 ADC clock cycles elapse between the write
of Register 10 and Register 0. For example, if ADC clock =
99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10
section for more information.
15. Register 0.
REGISTER 13
Control Bits
With C4 to C1 (Bits[DB3:DB0]) set to 1101, Register 13 is
programmed. Figure 51 shows the input data format for
programming this register.
14-Bit Auxiliary Fractional MSB Value (FRAC2_MSB)
This value is used with the auxiliary fractional LSB value
(Register 2, Bits[DB31:DB18]) to generate the total auxiliary
fractional FRAC2 value.
For fPFD > 75 MHz (initially lock with halved fPFD), use the
following sequence:
FRAC2 = (FRAC2_MSB × 214) + FRAC2_LSB
These bits can be set to all zeros to ensure software
compatibility with the ADF5355.
14-Bit Auxiliary Modulus MSB Value (MOD2_MSB)
This value is used with the auxiliary fractional MSB value
(Register 2, Bits[DB17:DB4]) to generate the total auxiliary
modulus MOD2 value.
MOD2 = (MOD2_MSB × 214) + MOD2_LSB
REGISTER INITIALIZATION SEQUENCE
At initial power-up, after the correct application of voltages to
the supply pins, the ADF5356 registers must be programmed in
sequence. For f ≤ 75 MHz, use the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Register 13.
Register 12.
Register 11.
Register 10.
Register 9.
Register 8.
Register 7.
Register 6.
Register 5.
Register 4.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
Rev. 0 | Page 32 of 38
Register 13 (for halved fPFD).
Register 12.
Register 11.
Register 10.
Register 9.
Register 8.
Register 7.
Register 6 (bleed current setting using the desired fPFD).
Register 5.
Register 4 (with the R divider doubled to halve fPFD).
Register 3.
Register 2 (for halved fPFD).
Register 1 (for halved fPFD).
Ensure that >16 ADC clock cycles elapse between the write
of Register 10 and Register 0. For example, if ADC clock =
99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10
section for more information.
Register 0 (for halved fPFD; autocalibration enabled).
Register 13 (for the desired fPFD).
Register 4 (with the R divider set for the desired fPFD).
Register 2 (for the desired fPFD).
Register 1 (for the desired fPFD).
Register 0 (for the desired fPFD; autocalibration disabled).
Data Sheet
ADF5356
FREQUENCY UPDATE SEQUENCE
1.
2.
3.
4.
5.
6.
Register 13.
Register 10.
Register 2.
Register 1.
Ensure that >16 ADC clock cycles elapse between the write
of Register 10 and Register 0. For example, if ADC clock =
99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10
section for more information.
Register 0.
For fPFD > 75 MHz (initially lock with halved fPFD), the sequence
must be as follows:
1.
2.
3.
4.
5.
6.
Register 13 (for halved fPFD).
Register 10.
Register 4 (with the R divider doubled to halve fPFD).
Register 2 (for halved fPFD).
Register 1 (for halved fPFD).
Ensure that >16 ADC clock cycles elapse between the write
of Register 10 and Register 0. For example, if ADC clock =
99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10
section for more information.
7. Register 0 (for halved fPFD; autocalibration enabled).
8. Register 13 (for the desired fPFD).
9. Register 4 (with the R divider doubled to halve fPFD)
10. Register 2 (for the desired fPFD).
11. Register 1 (for the desired fPFD).
12. Register 0 (for desired fPFD; autocalibration disabled).
fPFD = fREFIN × ((1 + D)/(R × (1 + T)))
(8)
where:
fREFIN is the reference input frequency.
D is the reference doubler bit.
R is the fREFIN reference division factor.
T is the reference divide by 2 bit (0 or 1).
For example, in a universal mobile telecommunication system
(UMTS) where a 2112.8 MHz RF output frequency (fRFOUT) is
required, a 122.88 MHz reference frequency input (fREFIN) is available. Note that the ADF5356 VCO operates in the frequency range
of 3400 MHz to 6800 MHz. Therefore, the RF divider of 2 must be
used (VCO frequency = 4225.6 MHz, RFOUT = VCO frequency/RF
divider = 4225.6 MHz/2 = 2112.8 MHz).
The feedback path is also important. In this example, the VCO
output is fed back before the output divider (see Figure 52). In
this example, the 122.88 MHz reference signal is divided by 2 to
generate an fPFD of 61.44 MHz. The desired channel spacing is
200 kHz.
fPFD
PFD
VCO
÷2
RFOUT
N
DIVIDER
Figure 52. Loop Closed Before Output Divider
The worked example is as follows:
N = VCOOUT/fPFD = 4225.6 MHz/61.44 MHz =
68.7760416666666667
INT = int(VCO frequency/fPFD) = 68
where int() is a function indicating the integer result.
FRAC = 0.7760416666666667
The frequency change occurs on the write to Register 0.
MOD1 = 16,777,216
RF SYNTHESIZER—A WORKED EXAMPLE
FRAC1 = int(MOD1 × FRAC) = 13,019,818
Use the following equations to program the ADF5356 synthesizer:
Remainder = 0.6666666667 or 2/3
RFOUT
INT
FRAC2
MOD2 f / RF Divider
PFD
MOD1
15360-052
Frequency updates require updating the auxiliary modulator
(FRAC2/MOD2) in Register 2 and Register 13, the fractional value
(FRAC1) in Register 1, and the integer value (INT) in Register 0.
It is recommended to perform a temperature dependent VTUNE
calibration by updating Register 10 first. Therefore, for fPFD ≤
75 MHz, the sequence must be as follows:
MOD2 = fPFD/GCD(fPFD, fCHSP) =
61.44 MHz/GCD(61.44 MHz, 200 kHz) = 1536
FRAC1
(7)
FRAC2 = Remainder × 1536 = 1024
where:
fRFOUT is the RF output frequency.
INT is the integer division factor.
FRAC1 is the fractionality.
FRAC2 is the auxiliary fractionality (FRAC2 = (FRAC2_MSB ×
214) + FRAC2_LSB).
MOD2 is the auxiliary modulus (MOD2 = (MOD2_MSB × 214) +
MOD2_LSB).
MOD1 is the fixed 24-bit modulus.
RF Divider is the output divider that divides down the VCO
frequency.
From Equation 8,
fPFD = (122.88 MHz × (1 + 0)/2) = 61.44 MHz
2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +
FRAC2/MOD2)/224))/2
where:
INT = 68.
FRAC1 = 13,019,818.
FRAC2 = 1024.
MOD2 = 1536.
RF Divider = 2.
Rev. 0 | Page 33 of 38
(9)
(10)
ADF5356
Data Sheet
REFERENCE DOUBLER AND REFERENCE DIVIDER
Lock Time—A Worked Example
The on-chip reference doubler allows the input reference signal
to be doubled. The doubler is useful for increasing the PFD
comparison frequency. To improve the noise performance of
the system, increase the PFD frequency. Doubling the PFD
frequency typically improves noise performance by 3 dB.
Assume that fPFD = 61.44 MHz,
VCO Band Div = ceiling(fPFD/1,600,000) = 39
By combining
ALC Wait > (50 μs × fPFD)/Timeout
Synthesizer Lock Timeout > (20 μs × fPFD)/Timeout
The reference divide by 2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency.
It is found that
SPURIOUS OPTIMIZATION AND FAST LOCK
ALC Wait = 2.5 × Synthesizer Lock Timeout
Narrow loop bandwidths can filter unwanted spurious signals;
however, these bandwidths typically have a long lock time. A
wider loop bandwidth achieves faster lock times but may lead
to increased spurious signals inside the loop bandwidth.
The ALC wait and synthesizer lock timeout values must be set
to fulfill this equation. Both values are five bits wide; therefore,
the maximum value for either is 31. There are several suitable
values.
OPTIMIZING JITTER
The following values meet the criteria:
For the lowest jitter applications, use the highest possible PFD
frequency to minimize the contribution of in-band noise from
the PLL. Set the PLL filter bandwidth such that the in-band noise
of the PLL intersects with the open-loop noise of the VCO,
minimizing the contribution of both to the overall noise.
ALC Wait = 30
Synthesizer Lock Timeout = 12
Finally, rearrange as follows:
ALC wait > (50 μs × fPFD)/Timeout
Use the ADIsimPLL design tool for this task.
Timeout = ceiling((fPFD × 50 μs)/ALC Wait)
SPUR MECHANISMS
Timeout = ceiling((61.44 MHz × 50 μs)/30) = 103
This section describes the two different spur mechanisms that
arise with a fractional-N synthesizer and methods to minimize
them in the ADF5356.
Integer Boundary Spurs
One mechanism for fractional spur creation is the interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (the purpose of a
fractional-N synthesizer), spur sidebands appear on the VCO
output spectrum at an offset frequency that corresponds to the
beat note or the difference in frequency between an integer
multiple of the reference and the VCO frequency. These spurs
are attenuated by the loop filter and are more noticeable on
channels close to integer multiples of the reference where the
difference frequency can be inside the loop bandwidth (thus
the name, integer boundary spurs).
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. Feedthrough of low
levels of on-chip reference switching noise, through the
prescaler back to the VCO, can result in reference spur levels
as high as −85 dBc.
PLL LOCK TIME
The PLL lock time divides into a number of settings. All of
these settings are modeled in the ADIsimPLL design tool.
Synthesizer Lock Timeout
The synthesizer lock timeout ensures that the VCO calibration
digital-to-analog (DAC), which forces VTUNE, settles to a steady
value for the band select circuitry.
The timeout and synthesizer lock timeout variables programmed
in Register 9 select the length of time the DAC is allowed to
settle to the final voltage, before the VCO calibration process
continues to the next phase, which is VCO band selection. The
PFD frequency is the clock for this logic, and the duration is set by
Timeout Synthesize r Lock Timeout
f PFD
The calculated time must be equal to or greater than 20 μs.
VCO Band Selection
Use the PFD frequency again as the clock for the band selection
process. Calculate this value by
fPFD/(VCO Band Selection × 16) < 100 kHz
The band selection takes 11 cycles of the previously calculated
value. Calculate the duration by
11 × (VCO Band Selection × 16)/fPFD
Automatic Level Calibration Timeout
Use the automatic level calibration (ALC) function to choose
the correct bias current in the ADF5356 VCO core. Calculate
the time taken by
30 × ALC Wait × Timeout/fPFD
Much faster lock times than those detailed in this data sheet are
possible; contact Analog Devices, Inc., for more information.
Rev. 0 | Page 34 of 38
Data Sheet
ADF5356
PLL Low-Pass Filter Settling Time
The time taken for the loop to settle is inversely proportional to
the low-pass filter bandwidth. The settling time is also modeled
in the ADIsimPLL design tool.
The total lock time for changing frequencies is the sum of the
four separate times (synthesizer lock, VCO band selection, ALC
timeout, and PLL settling time) and is modeled in the ADIsimPLL
design tool.
Rev. 0 | Page 35 of 38
ADF5356
Data Sheet
APPLICATIONS INFORMATION
large as the exposed pad. On the PCB, there must be a minimum
clearance of 0.25 mm between the thermal pad and the inner
edges of the pad pattern. This clearance ensures the avoidance
of shorting.
POWER SUPPLIES
The ADF5356 contains four multiband VCOs that cover an
octave range of frequencies. To ensure the best performance, it is
vital to connect a low noise regulator, such as the ADM7150.
Connect the same regulator to the VVCO, VREGVCO, and VP pins.
To improve the thermal performance of the package, use thermal
vias on the PCB thermal pad. If vias are used, incorporate them
into the thermal pad at the 1.2 mm pitch grid. The via diameter
must be between 0.3 mm and 0.33 mm, and the via barrel must
be plated with 1 oz. of copper to plug the via.
For the 3.3 V supply pins, use one or two ADM7150 regulators,
one for the DVDD and AVDD supplies and one for VRF. Figure 53
shows the recommended connections.
PCB DESIGN GUIDELINES FOR A CHIP SCALE
PACKAGE
For a microwave PLL and VCO synthesizer, such as the ADF5356,
take care with the board stackup and layout. Do not consider
using FR4 material because it is too lossy above 3 GHz. Instead,
Rogers 4350, Rogers 4003, or Rogers 3003 dielectric material is
suitable.
The lands on the 32-lead, lead frame chip scale package are
rectangular. The PCB pad for these lands must be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. Center each land on the pad to
maximize the solder joint size.
Take care with the RF output traces to minimize discontinuities
and ensure the best signal integrity. Via placement and grounding
are critical.
The bottom of the chip scale package has a central exposed
thermal pad. The thermal pad on the PCB must be at least as
VIN
CIN
1µF
ON
EN
VOUT
ADM7150
VOUT = 3.3V
100nF
COUT
1µF
100nF
LOCK
DETECT
OFF
REF
BYP
CBYP
1µF
VREG
REF_SENSE
1nF
CREG
10µF
GND
1nF
FREF IN
17 6
27
5
16
4
26
10
32
25
30
VVCO VP DVDD AVDD AVDD CE PDB RF VRF CREG2 CREG1 MUXOUT
10pF
29 REF A
IN
1nF
FREF IN
RFOUTB 14
100Ω
1nF
VOUT
28 REF INB
7.5nH
1 CLK
VIN
CIN
1µF
OFF
CBYP
1µF
ON
VOUT
ADM7150
EN
BYP
CREG
10µF
VREG
REF
REF_SENSE
GND
VOUT = 5.0V
COUT
1µF
SPI-COMPATIBLE SERIAL BUS
VIN = 6.0V
7.5nH
1nF
2 DATA
RFOUTA+ 11
3 LE
ADF5356
RFOUTA– 12
1nF
VTUNE 20
430Ω
CPOUT 7
22 NIC
1µF
33nF
CPGND SDGND A
GND
8
31
9
AGNDVCO AGNDRF VREGVCO VREF VBIAS
13 18
21
15
19
10pF
Figure 53. Power Supplies
Rev. 0 | Page 36 of 38
23
6800pF
68Ω
24
0.1µF 10pF
0.1µF 10pF
0.1µF
15360-053
VIN = 6.0V
Data Sheet
ADF5356
OUTPUT MATCHING
The low frequency output can simply be ac-coupled to the next
circuit, if desired; however, if a higher output power is required,
use a pull-up inductor to increase the output power level.
VRF
7.5nH
100pF
50Ω
15360-054
RFOUTA+
For frequencies below 2 GHz, it is recommended to use a
100 nH inductor on the RFOUTA+/RFOUTA− pins and a 100 pF
ac coupling capacitor.
The RFOUTA+/RFOUTA− pins form a differential circuit. Provide
each output with the same (or similar) components where
possible, such as the same shunt inductor value, bypass
capacitor, and termination.
AC couple the higher frequency output, RFOUTB, directly to the
next appropriate circuit stage.
Figure 54. Optimum Output Stage
When differential outputs are not required, terminate the
unused output or combine it with both outputs using a balun.
RFOUTB is matched internally to a 50 Ω impedance and requires
no additional matching components.
Rev. 0 | Page 37 of 38
ADF5356
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
1
24
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PKG-004570
0.50
0.40
0.30
PIN 1
INDICATOR
9
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.
01-26-2016-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 55. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADF5356BCPZ
ADF5356BCPZ-RL7
EV-ADF5356SD1Z
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15360-0-8/17(0)
Rev. 0 | Page 38 of 38
Package Option
CP-32-12
CP-32-12
