24 GHz VCO and PGA
with 2-Channel PA Output
ADF5901
Data Sheet
FEATURES
Industrial sensors
Precision instrumentation
Tank level sensors
Smart sensors
Door opening
Energy saving
Commercial sensors: object detection and tracking
Cars, boats, aircraft, and UAVs (drones): collision avoidance
Intelligent transportation systems: intelligent traffic
monitoring and control
Surveillance and security
24 GHz to 24.25 GHz voltage controlled oscillator (VCO)
2-channel 24 GHz power amplifier (PA) with 8 dBm output
Single-ended outputs
2-channel muxed outputs with mute function
Programmable output power
N divider output (frequency discriminator)
24 GHz local oscillator (LO) output buffer
250 MHz signal bandwidth
Power control detector
Auxiliary 8-bit ADC
±5°C temperature sensor
4-wire serial peripheral interface (SPI)
Electrostatic discharge (ESD) performance
Human body model (HBM): 2000 V
Charged device model (CDM): 250 V
Qualified for automotive applications
GENERAL DESCRIPTION
The ADF5901 is a 24 GHz Tx monolithic microwave integrated
circuit (MMIC) with an on-chip, 24 GHz VCO with PGA and
dual Tx channels for radar systems. The on-chip, 24 GHz VCO
generates the 24 GHz signal for the two Tx channels and the LO
output. Each Tx channel contains a power control circuit. There
is also an on-chip temperature sensor.
APPLICATIONS
Automotive radars
Industrial radars
Microwave radar sensors
Control of all the on-chip registers is through a simple 4-wire
interface.
The ADF5901 comes in a compact 32-lead, 5 mm × 5 mm
LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
VREG
C1
TX_AHI
C2
RF_AHI
AHI
DVDD
VCO_AHI
REGULATOR
REFIN
RSET
REFERENCE
R-DIVIDER
ADF5901
MUXOUT
ADC
VCO
CAL
TXOUT1
TXOUT2
÷2
N-DIVIDER
ADC
TEMPERATURE
SENSOR
32-BIT
DATA
REGISTER
ATEST
ADC
CE
VTUNE
AUX
AUX
LOOUT
GND
13336-001
CLK
DATA
LE
DOUT
÷2
Figure 1.
Rev. B
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ADF5901
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 2 ..................................................................................... 17
Applications ....................................................................................... 1
Register 3 ..................................................................................... 18
General Description ......................................................................... 1
Register 4 ..................................................................................... 19
Functional Block Diagram .............................................................. 1
Register 5 ..................................................................................... 20
Revision History ............................................................................... 2
Register 6 ..................................................................................... 20
Specifications..................................................................................... 3
Register 7 ..................................................................................... 21
Timing Specifications .................................................................. 4
Register 8 ..................................................................................... 22
Absolute Maximum Ratings............................................................ 6
Register 9 ..................................................................................... 22
ESD Caution .................................................................................. 6
Register 10 ................................................................................... 23
Pin Configuration and Function Descriptions ............................. 7
Register 11 ................................................................................... 23
Typical Performance Characteristics ............................................. 9
Initialization Sequence .............................................................. 23
Theory of Operation ...................................................................... 11
Recalibration Sequence ............................................................. 23
Reference Input Section ............................................................. 11
Temperature Sensor ................................................................... 24
RF INT Divider ........................................................................... 11
RF Synthesis: a Worked Example ............................................. 24
INT, FRAC, and R Relationship ............................................... 11
Applications Information .............................................................. 25
R Counter .................................................................................... 11
Application of the ADF5901 in FMCW Radar ...................... 25
Input Shift Register..................................................................... 11
Outline Dimensions ....................................................................... 26
Program Modes .......................................................................... 11
Ordering Guide .......................................................................... 26
Register Maps .................................................................................. 13
Automotive Products ................................................................. 26
Register 0 ..................................................................................... 15
Register 1 ..................................................................................... 16
REVISION HISTORY
8/2017—Rev. A to Rev. B
Changes to Figure 17 ...................................................................... 13
Changes to Figure 20 ...................................................................... 17
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
Changes to Initialization Sequence Section and Recalibration
Sequence Section ............................................................................ 23
12/2015—Revision 0: Initial Version
7/2016—Rev. 0 to Rev. A
Changes to Applications Section .................................................... 1
Rev. B | Page 2 of 26
Data Sheet
ADF5901
SPECIFICATIONS
AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = 3.3 V ± 5%, AGND = 0 V, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise
noted. Operating temperature range is −40°C to +105°C.
Table 1.
Parameter
OPERATING CONDITIONS
RF Frequency Range
VCO CHARACTERISITICS
VTUNE
VTUNE Impedance
VCO Phase Noise Performance
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
Amplitude Noise
Static Pulling fVCO Change vs. Load
Dynamic Pulling Tx On/Off Switch Change
Dynamic Pulling Tx to Tx Switch Change
Pushing fVCO Change vs. AHI Change
Spurious Level Harmonics
Spurious Level Nonharmonics
POWER SUPPLIES
AHI, TX_AHI, RF_AHI, VCO_AHI, DVDD
Total Current, ITOTAL 1
Software Power-Down Mode
Hardware Power-Down Mode
Tx OUTPUT
Output Power
Output Impedance
On/Off Isolation
Tx to Tx Isolation
Power-Up/Power-Down Time
LO OUTPUT
Output Power
Output Impedance
On/Off Isolation
AUX PIN OUTPUT
Output Power
Output Frequency
Divide by 2 Output
Divide by 4 Output
Output Impedance
On/Off Isolation
AUX to LO Isolation
TEMPERATURE SENSOR
Analog Accuracy
Digital Accuracy
Sensitivity
Min
Typ
Max
Unit
24.25
GHz
2.8
100
V
kΩ
−88
−108
−128
−150
±2
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MHz
±10
±5
±5
−30
25 V/µs
V
0.4
V
500
500
µA
µA
TA = 25°C; AHI = 3.3 V; fREFIN = 100 MHz; RF = 24.125 GHz following initialization sequence in the Initialization Sequence section.
VDD selected from IO level bit (DB11 in Register 3).
TIMING SPECIFICATIONS
AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = 3.3 V ± 5%, AGND = 0 V, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise
noted. Operating temperature range is −40°C to +105°C.
Table 2. Write Timing
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
Limit at TMIN to TMAX
20
10
10
25
25
10
20
10
15
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
Rev. B | Page 4 of 26
Description
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
LE setup time to DOUT
CLK setup time to DOUT
Data Sheet
ADF5901
Write Timing Diagram
t4
t5
CLK
t2
DATA
t3
DB30
DB31 (MSB)
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
LE
t1
t6
DB31
(MSB)
DOUT
DB30
DB1
DB0
13336-002
t8
t9
Figure 2. Write Timing Diagram
500µA
VDD/2
CL
10pF
500µA
IOH
13336-003
TO DOUT AND
MUXOUT PINS
IOL
Figure 3. Load Circuit for DOUT/MUXOUT Timing, CL = 10 pF
Rev. B | Page 5 of 26
ADF5901
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
AHI to GND
AHI to TX_AHI
AHI to RF_AHI
AHI to VCO_AHI
AHI to DVDD
VTUNE to GND
Digital Input/Output Voltage to GND
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
θJA Thermal Impedance 1 (Paddle
Soldered)
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Transistor Count
CMOS
Bipolar
ESD
Charged Device Model
Human Body Model
1
Rating
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +3.6 V
−0.3 V to DVDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
150°C
40.83 °C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
260°C
40 sec
177,381
2315
250 V
2000 V
Two signal planes (that is, on top and bottom surfaces of the board), two
buried planes, and nine vias.
Rev. B | Page 6 of 26
Data Sheet
ADF5901
32
31
30
29
28
27
26
25
C2
C1
VCO_AHI
VTUNE
AUX
AUX
RSET
MUXOUT
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADF5901
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
ATEST
GND
LOOUT
GND
GND
RF_AHI
REFIN
AHI
DOUT
LE
DATA
CLK
CE
GND
VREG
DVDD
13336-004
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
TXOUT1
GND
TX_AHI
TX_AHI
GND
TXOUT2
GND
NOTES
1. THE LFCSP HAS AN EXPOSED PAD
THAT MUST BE CONNECTED TO GND.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 3, 6, 8,
10, 12, 13,
19
2
4, 5
Mnemonic
GND
Description
RF Ground. Tie all ground pins together.
TXOUT1
TX_AHI
7
9
11
14
TXOUT2
ATEST
LOOUT
RF_AHI
15
REFIN
16
AHI
17
DVDD
18
20
VREG
CE
21
CLK
22
DATA
23
LE
24
25
DOUT
MUXOUT
26
RSET
27
28
AUX
AUX
24 GHz Tx Output 1.
Voltage Supply for the Tx Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground plane
as close as possible to this pin. TX_AHI must be the same value as AHI.
24 GHz Tx Output 2.
Analog Test Pin.
LO Output.
Voltage Supply for the RF Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground plane
as close as possible to this pin. RF_AHI must be the same value as AHI.
Reference Input. This pin is a CMOS input with a nominal threshold of DVDD/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 14. This input can be driven from a TTL or CMOS crystal oscillator, or it can be
ac-coupled.
Voltage Supply for the Analog Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground
plane as close as possible to this pin.
Digital Power Supply. This supply may range from 3.135 V to 3.465 V. Place decoupling capacitors (0.1 μF, 1 nF,
and 10 pF) to the ground plane as close as possible to this pin. DVDD must be the same value as AHI.
Internal 1.8 V Regulator Output. Connect a 220 nF capacitor to ground as close as possible to this pin.
Chip Enable. A logic low on this pin powers down the device. Taking the pin high powers up the device,
depending on the status of the power-down bit, PD1.
Serial Clock Input. This serial clock input clocks in the serial data to the registers. The data is latched into the
32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This input is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
16 latches with the latch selected via the control bits.
Serial Data Output.
Multiplexer Output. This multiplexer output allows either the scaled RF or the scaled reference frequency to be
accessed externally.
Resistor Setting Pin. Connecting a 5.1 kΩ resistor between this pin and GND sets an internal current. The
nominal voltage potential at the RSET pin is 0.62 V.
Auxiliary Output. The VCO/2 output or VCO/4 is available.
Complementary Auxiliary Output. The VCO/2 output or VCO/4 is available.
Rev. B | Page 7 of 26
ADF5901
Data Sheet
Pin No.
29
30
Mnemonic
VTUNE
VCO_AHI
31
32
C1
C2
EP
Description
Control Input to the VCO. This voltage determines the output.
Voltage Supply for the VCO Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground
plane as close as possible to this pin. VCO_AHI must be the same value as AHI.
Decoupling Capacitor 1. Place a 47 nF capacitor to ground as close as possible to this pin.
Decoupling Capacitor 2. Place a 220 nF capacitor to ground as close as possible to this pin.
Exposed Pad. The LFCSP has an exposed pad that must be connected to GND.
Rev. B | Page 8 of 26
Data Sheet
ADF5901
TYPICAL PERFORMANCE CHARACTERISTICS
6
12
4
OUTPUT POWER (dBm)
8
6
–40°C
+25°C
+105°C
OUTSIDE OF SPECIFIED RANGE
Tx1
Tx2
4
2
24.00
24.05
24.10
24.15
24.20
24.25
0
–2
–40°C
+25°C
+105°C
OUTSIDE OF SPECIFIED RANGE
–4
–6
13336-005
0
23.95
2
–8
23.95
24.30
13336-008
OUTPUT POWER (dBm)
10
24.00
24.05
OUTPUT FREQUENCY (GHz)
24.10
24.15
24.20
24.25
24.30
OUTPUT FREQUENCY (GHz)
Figure 5. Tx Output Power vs. Output Frequency
Figure 8. LO Output Power vs. Output Frequency
0
12
–1
–2
OUTPUT POWER (dBm)
8
6
4
3.135V
–40°C
+25°C
3.300V
+105°C
3.465V
OUTSIDE OF SPECIFIED RANGE
0
23.95
24.00
24.05
24.10
24.15
24.20
–4
–5
–6
–40°C
+25°C
+105°C
OUTSIDE OF SPECIFIED RANGE
AUX
AUX
–7
–8
13336-006
2
–3
24.25
13336-009
OUTPUT POWER (dBm)
10
–9
–10
11.99
24.30
12.01
12.03
Figure 6. Transmitter 1 (Tx1) Output Power Variation with Temperature and
Supply vs. Output Frequency
12.07
12.09
12.11
12.13
Figure 9. AUX/AUX Output Power vs. Output Frequency with Divide by 2
Selected
15
5
4
–40°C
+25°C
+105°C
10
3
5
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
12.05
OUTPUT FREQUENCY (GHz)
OUTPUT FREQUENCY (GHz)
0
–5
–10
–40°C
+25°C
+105°C
OUTSIDE OF SPECIFIED RANGE
AUX
AUX
2
1
0
–1
–2
13336-007
–20
0
10
20
30
40
50
60
70
80
90
13336-010
–3
–15
–4
–5
5.99
100
Tx AMPLITUDE CALIBRATION REFERENCE CODE
6.00
6.01
6.02
6.03
6.04
6.05
6.06
6.07
OUTPUT FREQUENCY (GHz)
Figure 7. Tx Output Power vs. Tx Amplitude Calibration Reference Code
Figure 10. AUX/AUX Output Power vs. Output Frequency with Divide by 4
Selected
Rev. B | Page 9 of 26
ADF5901
Data Sheet
3.5
250
1.8
1.6
3.0
200
1.5
–40°C
+25°C
+105°C
OUTSIDE OF SPECIFIED RANGE
0.4
OUTPUT FREQUENCY (GHz)
0
–20
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
13336-012
PHASE NOISE (dBc/Hz)
–30
–140
–150
100k
1M
110
120
90
100
80
70
60
50
40
Figure 13. ATEST Voltage and ADC Code vs. Temperature
–10
10k
30
TEMPERATURE (ºC)
Figure 11. VTUNE Frequency Range
1k
0
0
24.50
20
24.38
0
24.25
10
24.13
–10
24.10
0.2
–20
23.88
50
–40
0
23.75
100
0.6
13336-011
0.5
0.8
–30
1.0
150
1.0
10M
FREQUENCY OFFSET (Hz)
Figure 12. Open-Loop Phase Noise on Tx1 Output at 24.125 GHz
Rev. B | Page 10 of 26
13336-013
ATEST (V)
VTUNE (V)
1.2
2.0
ADC CODE (Count)
1.4
2.5
Data Sheet
ADF5901
THEORY OF OPERATION
REFERENCE INPUT SECTION
R DIVIDER
POWER-DOWN
CONTROL
NC
BUFFER
13336-014
SW3
NO
RF INT DIVIDER
The RF INT counter allows a division ratio in the RF feedback
counter. Division ratios from 75 to 4095 are allowed.
INT, FRAC, AND R RELATIONSHIP
Generate the RF VCO frequency (RFOUT) using the INT and
FRAC values in conjunction with the R counter, as follows:
RFOUT = fREF × (INT + (FRAC/225)) × 2
(1)
where:
RFOUT is the output frequency of internal VCO.
fREF is the internal reference frequency.
INT is the preset divide ratio of the binary 12-bit counter
(75 to 4095).
FRAC is the numerator of the fractional division (0 to 225 − 1).
fREF = REFIN × ((1 + D)/(R × (1 + T)))
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit (0 or 1).
R is the preset divide ratio of the binary, 5-bit, programmable
reference counter (1 to 32).
T is the REFIN divide by 2 bit (0 or 1).
N = INT + FRAC/225
TO CAL
BLOCK
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
TO CAL
BLOCK
Figure 16. Reference Divider
The ADF5901 digital section includes a 5-bit RF R counter,
a 12-bit RF N counter, and a 25-bit FRAC counter. Data is
clocked into the 32-bit input shift register on each rising edge of
CLK. The data is clocked in MSB first. Data is transferred from
the input shift register to one of 12 latches on the rising edge of
LE. The destination latch is determined by the state of the five
control bits (C5, C4, C3, C2, and C1) in the input shift register.
These are the five LSBs (DB4, DB3, DB2, DB1, and DB0,
respectively), as shown in Figure 2. Table 5 shows the truth
table for these bits. Figure 17 and Figure 18 show a summary of
how the latches are programmed.
PROGRAM MODES
Table 5 and Figure 19 through Figure 30 show how to set up the
program modes in the ADF5901.
Several settings in the ADF5901 are double buffered. These
include the LSB fractional value, R counter value (R divider),
reference doubler, clock divider, RDIV2, and MUXOUT. This
means that two events must occur before the device uses a new
value for any of the double-buffered settings. First, the new
value is latched into the device by writing to the appropriate
register. Second, a new write must be performed on Register R5.
For example, updating the fractional value can involve a write to
the 13 LSB bits in Register R6 and the 12 MSB bits in Register R5.
Write to Register R6 first, followed by the write to Register R5.
The frequency change begins after the write to Register R0.
Double buffering ensures that the bits written to in Register R6
do not take effect until after the write to Register R5.
FRAC
VALUE
13336-015
INT
REG
÷2
DIVIDER
INPUT SHIFT REGISTER
Figure 14. Reference Input Stage
FROM RF
INPUT STAGE
5-BIT
R COUNTER
The 5-bit R counter allows the input reference frequency (REFIN)
to be divided down to supply the reference clock to the VCO
calibration block. Division ratios from 1 to 32 are allowed.
TO R COUNTER
SW1
RF N DIVIDER
×2
DOUBLER
R COUNTER
100kΩ
SW2
REFIN NC
REFIN
13336-016
The reference input stage is shown in Figure 14. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This configuration ensures that there is no loading of
the REFIN pin on power-down.
Figure 15. RF N Divider
Rev. B | Page 11 of 26
ADF5901
Data Sheet
Table 5. C5, C4, C3, C2, and C1 Truth Table
Control Bits
C5 (DB4)
0
0
0
0
0
0
0
0
0
0
0
0
C4 (DB3)
0
0
0
0
0
0
0
0
1
1
1
1
C3 (DB2)
0
0
0
0
1
1
1
1
0
0
0
0
C2 (DB1)
0
0
1
1
0
0
1
1
0
0
1
1
Rev. B | Page 12 of 26
C1 (DB0)
0
1
0
1
0
1
0
1
0
1
0
1
Register
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
Data Sheet
ADF5901
REGISTER MAPS
PUP LO
PUP Tx2
PUP Tx1
PUP ADC
VCO CAL
PUP VCO
Tx1 AMP CAL
RESERVED
Tx2 AMP CAL
RESERVED
PUP NCNTR
PUP RCNTR
AUX BUFFER
GAIN
RESERVED
AUX DIV
REGISTER 0 (R0)
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
1
0
0
0
0
0
0
0
AG2
AG1
AG0
AD
1
1
1
1
PRC
PNC
1
DB2
DB1
DB0
Tx2C Tx1C PVCO VCAL PADC PTx2 PTx1 PLO C5(0) C4(0) C3(0) C2(0) C1(0)
REGISTER 1 (R1)
RESERVED
CONTROL
BITS
Tx AMP CAL REF CODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
DB2
DB1
DB0
TAR7 TAR6 TAR5 TAR4 TAR3 TAR2 TAR1 TAR0 C5(0) C4(0) C3(0) C2(0) C1(1)
ADC START
REGISTER 2 (R2)
RESERVED
ADC
AVERAGE
CONTROL
BITS
ADC CLOCK DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
AS
AA0 AA0
AC7
AC6
AC5 AC4
AC3 AC2 AC1
DB2
DB1
DB0
AC0 C5(0) C4(0) C3(0) C2(1) C1(0)
IO LEVEL
REGISTER 3 (R3)
MUXOUT DBR1
RESERVED
CONTROL
BITS
READBACK CONTROL
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
M3
M2
M1
M0
IOL
RC5
DB2
DB1
DB0
RC4 RC3 RC2 RC1 RC0 C5(0) C4(0) C3(0) C2(1) C1(1)
TEST BUS
TO ADC
RESERVED
RESERVED
TEST BUS
TO PIN
N DIV TO
MUXOUT EN
REGISTER 4 (R4)
CONTROL
BITS
ANALOG TEST BUS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
NDM
0
0
0
0
TBA
TBP
AB9
AB8
AB7
AB6
AB5 AB4 AB3
DB2
DB1
DB0
AB2 AB1 AB0 C5(0) C4(0) C3(1) C2(0) C1(0)
REGISTER 5 (R5)
RESERVED
INTEGER WORD
CONTROL
BITS
FRAC MSB WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
DB2
DB1
DB0
F13 C5(0) C4(0) C3(1) C2(0) C1(1)
REGISTER 6 (R6)
FRAC LSB WORD
CONTROL
BITS
DBR1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F12
F11
F10
F9
F8
F7
F6
F5
1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 5.
Figure 17. Register Summary (Register 0 to Register 6)
Rev. B | Page 13 of 26
F4
F3
F2
F1
F0
DB2
DB1
DB0
C5(0) C4(0) C3(1) C2(1) C1(0)
13336-017
RESERVED
ADF5901
Data Sheet
DBR1
CLOCK DIVIDER
REF DOUBLER
DBR1
DBR1
RDIV2
RESERVED
RESERVED
MASTER
RESET
REGISTER 7 (R7)
R DIVIDER
CONTROL
BITS
DBR1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
MR
C1D11 C1D10 C1D9 C1D8 C1D7 C1D6 C1D5 C1D4 C1D3 C1D2 C1D1 C1D0
1
RD2
RD
R4
R3
R2
R1
R0
DB2
DB1
DB0
C5(0) C4(0) C3(1) C2(1) C1(1)
REGISTER 8 (R8)
CONTROL
BITS
FREQENCY CAL DIVIDER
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FC9
FC8
FC7
FC6
FC5
DB2
DB1
DB0
FC4 FC3 FC2 FC1 FC0 C5(0) C4(1) C3(0) C2(0) C1(0)
REGISTER 9 (R9)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
DB2
DB1
DB0
C5(0) C4(1) C3(0) C2(0) C1(1)
REGISTER 10 (R10)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
1
1
1
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
1
0
DB2
DB1
DB0
C5(0) C4(1) C3(0) C2(1) C1(0)
CNTR
RESET
REGISTER 11 (R11)
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 5.
Figure 18. Register Summary (Register 7 to Register 11)
Rev. B | Page 14 of 26
0
0
0
0
0
DB2
DB1
DB0
CR C5(0) C4(1) C3(0) C2(1) C1(1)
13336-018
RESERVED
PUP LO
PUP Tx1
PUP Tx2
PUP ADC
VCO CAL
PUP VCO
Tx1 AMP CAL
Tx2 AMP CAL
RESERVED
RESERVED
PUP NCNTR
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
1
0
0
0
0
0
0
0
AG2
AG1
AG0
1
1
PRC
1
PNC
1
AD
AUX DIV
0
POWER DOWN LO
0
DIV 2
1
POWER UP LO
1
DIV 1
PTx1
POWER DOWN Tx1
0
POWER DOWN RCNTR
1
POWER UP Tx1
1
POWER UP RCNTR
PTx2
AG1 AG0
AUX BUFFER GAIN
0
0
BUFFER DISABLED
0
0
1
GAIN SETTING 1
0
1
0
GAIN SETTING 2
0
1
1
GAIN SETTING 3
1
0
0
GAIN SETTING 4
1
0
1
GAIN SETTING 5
1
1
0
GAIN SETTING 6
1
1
1
GAIN SETTING 7
PUP Tx1
0
PUP Tx2
PUP NCNTR
0
POWER DOWN Tx2
0
POWER DOWN NCNTR
1
POWER UP Tx2
1
POWER UP NCNTR
PNC
DB0
PUP LO
PUP RCNTR
PNC
0
DB1
1
PLO
AG2
DB2
Tx2C Tx1C PVCO VCAL PADC PTx2 PTx1 PLO C5(0) C4(0) C3(0) C2(0) C1(0)
AD
PADC PUP ADC
Tx2 AMP CAL
0
POWER DOWN ADC
0
NORMAL OPERATION
1
POWER UP ADC
1
Tx2 AMP CAL
Tx2C
VCAL VCO CAL
Tx1 AMP CAL
0
NORMAL OPERATION
0
NORMAL OPERATION
1
VCO FULL CAL
1
Tx1 AMP CAL
Tx1C
PVCO
PUP VCO
0
POWER DOWN VCO
1
POWER UP VCO
13336-019
AUX BUFFER
GAIN
RESERVED
PUP RCNTR
ADF5901
AUX DIV
Data Sheet
Figure 19. Register 0 (R0)
REGISTER 0
Power-Up N Counter
Control Bits
With Bits[C5:C1] set to 00000, Register R0 is programmed.
Figure 19 shows the input data format for programming this
register.
Bit DB14 provides the power-up bit for the N counter block.
Setting this bit to 0 performs a power-down of the counter
block. Setting this bit to 1 returns the counter block to normal
operation.
Auxiliary Buffer Gain
Tx2 Amplitude Calibration
Bits[DB23:DB21] set the auxiliary output buffer gain (see
Figure 19).
Bit DB12 provides the control bit for amplitude calibration of
the Transmitter 2 (Tx2) output. Set this bit to 0 for normal
operation. Setting this bit to 1 performs an amplitude
calibration of the Tx2 output.
Auxiliary Divide by 2
Bit DB20 selects the auxiliary output divider. Setting this bit to 0
selects divide by 2 (6 GHz output). Setting the bit to 1 selects
divide by 1 (12 GHz output).
Power-Up R Counter
Bit DB15 provides the power-up bit for the R counter block.
Setting this bit to 0 performs a power-down of the counter block.
Setting this bit to 1 returns the counter block to normal
operation.
Tx1 Amplitude Calibration
Bit DB11 provides the control bit for amplitude calibration of
the Tx1 output. Set this bit to 0 for normal operation. Setting
this bit to 1 performs an amplitude calibration of the Tx1
output.
Power-Up VCO
Bit DB10 provides the power-up bit for the VCO. Setting this bit
to 0 performs a power-down of the VCO. Setting this bit to 1
performs a power-up of the VCO.
Rev. B | Page 15 of 26
ADF5901
Data Sheet
VCO Calibration
Power-Up LO Output
Bit DB9 provides the control bit for frequency calibration of the
VCO. Set this bit to 0 for normal operation. Setting this bit to 1
performs a VCO frequency and amplitude calibration.
Bit DB5 provides the power-up bit for the LO output. Setting
this bit to 0 performs a power-down of the LO output. Setting
this bit to 1 performs a power-up of the LO output.
Power-Up ADC
REGISTER 1
Bit DB8 provides the power-up bit for the ADC. Setting this bit to
0 performs a power-down of the ADC. Setting this bit to 1
performs a power-up of the ADC.
Control Bits
With Bits[C5:C1] set to 00001, Register R1 is programmed.
Figure 20 shows the input data format for programming this
register.
Power-Up Tx2 Output
Bit DB7 provides the power-up bit for the Tx2 output. Setting
this bit to 0 performs a power-down of the Tx2 output. Setting
this bit to 1 performs a power-up of the Tx2 output. Only one
Tx output can be powered up at any time, either Tx1 (DB6) or
Tx2 (DB7).
Tx Amplitude Calibration Reference Code
Bits[DB12:DB5] set the Tx amplitude calibration reference code
(see Figure 20) for the two Tx outputs during calibration.
Calibrate the output power on the Tx outputs from −20 dBm to
8 dBm by setting the Tx amplitude calibration reference code
(see Figure 7).
Power-Up Tx1 Output
Bit DB6 provides the power-up bit for the Tx1 output. Setting
this bit to 0 performs a power-down of the Tx1 output. Setting
this bit to 1 performs a power-up of the Tx1 output. Only one
Tx output can be powered up at any time, either Tx1 (DB6) or
Tx2 (DB7).
Tx AMP CAL REF CODE
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
TAR7
TAR6
.......... TAR1 TAR0
Tx AMP CAL REF CODE
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
252
1
1
..........
0
1
253
1
1
..........
1
0
254
1
1
.........
1
1
255
Figure 20. Register 1 (R1)
Rev. B | Page 16 of 26
DB2
DB1
DB0
TAR7 TAR6 TAR5 TAR4 TAR3 TAR2 TAR1 TAR0 C5(0) C4(0) C3(0) C2(0) C1(1)
1
13336-020
1
ADF5901
RESERVED
ADC
AVERAGE
CONTROL
BITS
ADC CLOCK DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
AS
AA0
AS
ADC START
0
NORMAL OPERATION
1
START ADC CONVERSION
AA0
AC7
AC6
AC7
ADC AVERAGE
AC5 AC4
AC3 AC2 AC1
DB1
DB0
ADC CLOCK DIVIDER
AC6
.
AC1
AC0
0
.
0
1
0
0
.
1
0
2
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
DB2
AC0 C5(0) C4(0) C3(0) C2(1) C1(0)
1
AA1
AA0
0
0
1
1
1
.
0
0
124
0
1
2
1
1
.
0
1
125
1
0
3
1
1
4
1
1
.
1
0
126
1
1
.
1
1
127
13336-021
ADC START
Data Sheet
Figure 21. Register 2 (R2)
REGISTER 2
ADC Average
Control Bits
Bits[DB14:DB13] program the ADC average, which is the
number of averages of the ADC output (see Figure 21).
With Bits[C5:C1] set to 00010, Register R2 is programmed.
Figure 21 shows the input data format for programming this
register.
ADC Clock Divider
ADC Start
Bit DB15 starts the ADC conversion. Setting this bit to 1 starts
an ADC conversion.
Bits[DB12:DB5] program the clock divider, which is used as the
sampling clock for the ADC (see Figure 21). The output of the
R divider block clocks the ADC clock divider. Program a
divider value to ensure the ADC sampling clock is 1 MHz.
Rev. B | Page 17 of 26
Data Sheet
RESERVED
IO LEVEL
ADF5901
MUXOUT DBR 1
CONTROL
BITS
READBACK CONTRO L
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
1
1
0
0
0
0
1
0
M3 M2 M1 M0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1DBR
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
= DOUBLE-BUFFERED REGISTER.
M3
1
M2
M1
M0
IOL
RC5
DB2
DB1
DB0
RC4 RC3 RC2 RC1 RC0 C5(0) C4(0) C3(0) C2(1) C1(1)
MUXOUT
TRISTATE OUTPUT
LOGIC HIGH
LOGIC LOW
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
RESERVED
RESERVED
CAL BUSY
RESERVED
RESERVED
RESERVED
R-DIVIDER/2
N-DIVIDER/2
RESERVED
RESERVED
RESERVED
IOL
IO LEVEL
0
1.8V LOGIC OUTPUTS
1
3.3V LOGIC OUTPUTS
RC5 RC4 RC3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
.
.
.
0
0
1
0
0
1
0
0
1
.
.
.
.
.
.
1
1
1
RC2
0
0
0
0
1
1
1
1
0
0
0
0
1
.
1
1
1
.
.
1
RC1
0
0
1
1
0
0
1
1
0
0
1
1
0
.
0
1
1
.
.
1
RC0
0
1
0
1
0
1
0
1
0
1
0
1
0
.
1
0
1
.
.
1
READBACK CONTRO L
NONE
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGSITER 5
REGISTER 6
REGISTER 7
REGISTER 8
REGISTER 9
REGISTER 10
REGISTER11
RESERVED
RESERVED
ADC READBACK
RESERVED
RESERVED
RESERVED
RESERVED
10849-022
0
Figure 22. Register 3 (R3)
REGISTER 3
Input/Output (IO) Level
Control Bits
Bit DB11 controls the DOUT logic levels. Setting this bit to 0 sets
the DOUT logic level to 1.8 V. Setting this bit to 1 sets the DOUT
logic level to 3.3 V.
With Bits[C5:C1] set to 00011, Register R3 is programmed.
Figure 22 shows the input data format for programming this
register.
MUXOUT Control
Bits[DB15:DB12] control the on-chip multiplexer of the
ADF5901. See Figure 22 for the truth table.
Readback Control
Bits[DB10:DB5] control the readback data to DOUT on the
ADF5901. See Figure 22 for the truth table.
Rev. B | Page 18 of 26
RESERVED
TEST BUS
TO PIN
RESERVED
TEST BUS
TO ADC
ADF5901
N DIV TO
MUXOUT EN
Data Sheet
CONTROL
BITS
ANALOG TEST BUS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
NDM
0
0
TBA
NDM
0
0
TBA TBP
AB8
AB9
AB7
AB6
AB5 AB4 AB3
DB2
DB1
DB0
AB2 AB1 AB0 C5(0) C4(0) C3(1) C2(0) C1(0)
TEST BUS TO ADC
0
NORMAL OPERATION
1
TEST BUS TO ADC
AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0
ANALOG TEST BUS
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
259
NONE
TEMPERATURE SENSOR
N DIV TO MUXOUT EN
0
ENABLE NDIV TO MUXOUT
1
NORMAL OPERATION
TBP
TEST BUS TO PIN
0
NORMAL OPERATION
1
TEST BUS TO PIN
13336-023
0
Figure 23. Register 4 (R4)
INTEGER WORD
CONTROL
BITS
FRAC MSB WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
F24
F23
F22
F21
F20
F19
F18
F17
F16
N11
N10
...
N4
N3
N2
N1
N0
INTEGER WORD
0
0
...
0
0
0
0
0
NOT ALLOWED
0
0
...
0
0
0
0
1
NOT ALLOWED
0
0
..........
0
0
0
0
0
...
0
0
0
1
0
NOT ALLOWED
0
0
..........
0
1
1
F24
F23
..........
F14
F13
F15
F14
DB2
DB1
DB0
F13 C5(0) C4(0) C3(1) C2(0) C1(1)
FRAC MSB WORD
(FRAC)*
.
.
...
.
.
.
.
.
...
0
0
..........
1
0
2
0
0
...
0
1
0
1
0
NOT ALLOWED
0
0
..........
1
1
3
0
0
...
0
1
0
1
1
75
.
.
..........
.
.
.
0
0
...
0
1
1
0
0
76
.
.
..........
.
.
.
.
.
...
.
.
.
.
.
...
.
.
..........
.
.
.
1
1
...
1
1
1
0
1
4093
1
1
..........
0
0
4092
1
1
...
1
1
1
1
0
4094
1
1
..........
0
1
4093
1
1
...
1
1
1
1
1
4095
1
1
..........
1
0
4094
1
1
.........
1
1
4095
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R5, AND THE 13-BIT LSB REGISTER STORED IN
REGISTER R6. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 213.
13336-024
RESERVED
Figure 24. Register 5 (R5)
REGISTER 4
Test Bus to ADC
Control Bits
Bit DB16 controls the ATEST pin. Set this bit to 0 for normal
operation. Setting this bit to 1 connects the analog test bus to
the ADC input.
With Bits[C5:C1] set to 00100, Register R4 is programmed.
Figure 23 shows the input data format for programming this
register.
N Divider to MUXOUT Enable
Bit DB21 controls the internal N divider signal for MUXOUT.
Setting this bit to 0 enables the internal N divider signal to
MUXOUT. Setting this bit to 1 returns the device to normal
operation.
Test Bus to Pin
Bit DB15 controls the ATEST pin. Setting this bit to 0 sets the
ATEST pin to high impedance. Setting this bit to 1 connects the
analog test bus to the ATEST pin.
Analog Test Bus
Bits[DB14:DB5] control the analog test bus. This analog test bus
allows access to internal test signals for the temperature sensor.
See Figure 23 for the truth table.
Rev. B | Page 19 of 26
ADF5901
Data Sheet
REGISTER 5
REGISTER 6
Control Bits
Control Bits
With Bits[C5:C1] set to 00101, Register R5 is programmed.
Figure 24 shows the input data format for programming this
register.
With Bits[C5:C1] set to 00110, Register R6 is programmed.
Figure 25 shows the input data format for programming
this register.
13-Bit LSB FRAC Value
These 13 bits (Bits[DB17:DB5]), together with Bits[DB16:DB5]
(FRAC MSB word) in Register R5, control what is loaded as the
FRAC value into the fractional interpolator. This FRAC value
partially determines the overall RF division factor. It is also used
in Equation 1. These 13 bits are the least significant bits (LSB)
of the 25-bit FRAC value, and Bits[DB14:DB3] (FRAC MSB
word) in Register R5 are the most significant bits (MSB). See
the RF Synthesis: a Worked Example section for more
information.
These 12 bits (Bits[DB28:DB17]) set the INT value, which
determines the integer part of the RF division factor. This INT
value is used in Equation 5. See the RF Synthesis: a Worked
Example section for more information. All integer values from
75 to 4095 are allowed.
12-Bit MSB Fractional Value (FRAC)
These 12 bits (Bits[DB16:DB5]), together with Bits[DB17:DB5]
(FRAC LSB word) in Register R6, control what is loaded as the
FRAC value into the fractional interpolator. This FRAC value
partially determines the overall RF division factor. It is also used
in Equation 1. These 12 bits are the most significant bits (MSB)
of the 25-bit FRAC value, and Bits[DB17:DB5] (FRAC LSB
word) in Register R6 are the least significant bits (LSB). See the
RF Synthesis: a Worked Example section for more information.
RESERVED
FRAC LSB WORD
CONTROL
BITS
DBR1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F12
F11
F12
1DBR
= DOUBLE-BUFFERED REGISTER.
F10
F11
F9
F8
F7
..........
F1
F0
F6
F5
F4
F3
F2
0
0
..........
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
8188
1
1
..........
0
1
8189
1
1
..........
1
0
8190
1
1
.........
1
1
8191
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R5, AND THE 13-BIT LSB REGISTER STORED IN
REGISTER R6. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 213.
Rev. B | Page 20 of 26
F0
DB1
DB0
C5(0) C4(0) C3(1) C2(1) C1(0)
FRAC LSB WORD
(FRAC)*
0
Figure 25. Register 6 (R6)
F1
DB2
13336-025
12-Bit Integer Value (INT)
DBR 1
CLOCK DIVIDER
REF DOUBLER
DBR1
RDIV2
RESERVED
CONTROL
BITS
DBR1
R DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
MR
MR
1
C1D11 C1D10 C1D9 C1D8 C1D7 C1D6 C1D5 C1D4 C1D3 C1D2 C1D1 C1D0 RD2
R4
R3
R2
R1
R0
DB2
DB1
DB0
C5(0) C4(0) C3(1) C2(1) C1(1)
MASTER RESET
0
DISABLED
RD2
RDIV2
1
ENABLED
0
DISABLED
1
ENABLED
C1D11 C1D10
1DBR
RD
= DOUBLE-BUFFERED REGISTER.
RD
REF
DOUBLER
.......... C1D2 C1D0
CLOCK DIVIDER
0
DISABLED
1
ENABLED
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
R4
R3
R2
R1
R0
R DIVIDER (R)
.
.
..........
.
.
.
0
0
0
0
1
1
.
.
..........
.
.
.
0
0
0
1
0
2
.
.
..........
.
.
.
.
.
.
.
.
.
1
1
..........
0
0
4092
.
.
.
.
.
.
1
1
..........
0
1
4093
.
.
.
.
.
.
1
1
..........
1
0
4094
1
1
1
0
0
28
1
1
.........
1
1
4095
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31
13336-026
RESERVED
DBR1
ADF5901
MASTER
RESET
Data Sheet
Figure 26. Register 7 (R7)
REGISTER 7
Reference Doubler
Control Bits
Setting DB10 to 0 feeds the REFIN signal directly to the 5-bit
R counter, disabling the doubler. Setting this bit to 1 multiplies
the REFIN frequency by a factor of 2 before the REFIN signal is
fed into the 5-bit R counter.
With Bits[C5:C1] set to 00111, Register R7 is programmed.
Figure 26 shows the input data format for programming
this register.
Master Reset
Bit DB25 provides a master reset bit for the device. Setting this
bit to 1 performs a reset of the device and all register maps.
Setting this bit to 0 returns the device to normal operation.
Clock Divider
Bits[DB23:DB12] set a divider for the VCO frequency calibration.
Load the divider such that the time base is 10 µs (see Figure 26).
The maximum allowable REFIN frequency when the doubler is
enabled is 50 MHz.
5-Bit R Divider
The 5-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the VCO calibration block. Division ratios from 1 to 31 are
allowed.
Divide by 2 (RDIV2)
Setting the DB11 bit to 1 inserts a divide by 2 toggle flip flop
between the R counter and VCO calibration block.
Rev. B | Page 21 of 26
ADF5901
Data Sheet
CONTROL
BITS
FREQENCY CAL DIVIDER
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FC9
0
FC7
FC8
FC6
DB2
DB1
DB0
FC4 FC3 FC2 FC1 FC0 C5(0) C4(1) C3(0) C2(0) C1(0)
FC5
FREQUENCY CAL
DIVIDER
FC9
FC8
...
FC4
FC3
FC2
FC1
FC0
0
0
...
0
0
0
0
0
0
0
0
...
0
0
0
0
1
1
0
0
...
0
0
0
1
0
2
.
.
...
.
.
.
.
.
...
.
.
...
.
.
.
.
.
...
1
1
...
1
1
1
0
1
1021
1
1
...
1
1
1
1
0
1023
1
1
...
1
1
1
1
1
1024
13336-027
0
Figure 27. Register 8 (R8)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
DB2
DB1
DB0
C5(0) C4(1) C3(0) C2(0) C1(1)
Figure 28. Register 9 (R9)
REGISTER 8
REGISTER 9
Control Bits
Control Bits
With Bits[C5:C1] set to 01000, Register R8 is programmed.
Figure 27 shows the input data format for programming this
register.
With Bits[C5:C1] set to 01001, Register R9 is programmed.
Figure 28 shows the input data format for programming this
register.
Frequency Calibration Clock
Bits[DB14:DB5] set a divider for the VCO frequency calibration
clock. Load the divider such that the time base is 10 µs (see
Figure 27).
Rev. B | Page 22 of 26
13336-028
CONTROL
BITS
RESERVED
Data Sheet
ADF5901
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
1
1
1
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
1
0
DB2
DB1
DB0
C5(0) C4(1) C3(0) C2(1) C1(0)
13336-029
CONTROL
BITS
RESERVED
CNTR
RESET
Figure 29. Register 10 (R10)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DB1
DB0
CR C5(0) C4(1) C3(0) C2(1) C1(1)
CR
CNTR RESET
0
DISABLED
1
ENABLED
13336-030
0
DB2
Figure 30. Register 11 (R11)
REGISTER 10
Control Bits
With Bits[C5:C1] set to 01010, Register R10 is programmed.
Figure 29 shows the input data format for programming this
register.
REGISTER 11
Control Bits
With Bits[C5:C1] set to 01011, Register R11 is programmed.
Figure 30 shows the input data format for programming this
register.
Counter Reset
Bit DB5 provides a counter reset bit for the counters. Setting
this bit to 1 performs a counter reset of the device counters.
Setting this bit to 0 returns the device to normal operation.
INITIALIZATION SEQUENCE
After powering up the device, administer the following
programming sequence. The following sequence locks the VCO
to 24.125 GHz with a 100 MHz reference and a 50 MHz
reference divider frequency:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Write 0x02000007 to Register R7 to perform a master reset.
Write 0x0000002B to Register R11 to reset the counters.
Write 0x0000000B to Register R11 to enable the counters.
Write 0x1D32A64A to Register R10.
Write 0x2A20B929 to Register R9.
Write 0x40003E88 to Register R8 to set the frequency
calibration divider clock to 100 kHz.
Write 0x809FE520 to Register R0 to power up the device
and LO (10 µs).
Write 0x011F4827 to Register R7 to set the R counter clock
to 50 MHz and the calibration clock to 100 kHz.
Write 0x00000006 to Register R6 to set the LSB FRAC = 0.
10. Write 0x01E28005 to Register R5 to set INT = 241 and
MSB FRAC = 1024. Therefore, N = 240.25.
11. Write 0x00200004 to Register R4 to set the ATEST pin to
high impedance.
12. Write 0x01890803 to Register R3 to set the IO level to
VDD = 3.3 V.
13. Write 0x00020642 to Register R2 to set the ADC clock to
1 MHz.
14. Write 0xFFF7FFE1 to Register R1 to set the Tx amplitude
level.
15. Write 0x809FE720 to Register R0 to set the VCO frequency
calibration (800 µs).
16. Write 0x809FE560 to Register R0 to power Tx1 on, Tx2 off,
and LO on.
17. Write 0x809FED60 to Register R0 to set the Tx1 amplitude
calibration (400 µs).
18. Write 0x809FE5A0 to Register R0 to turn Tx1 off, Tx2 on,
and LO on.
19. Write 0x809FF5A0 to Register R0 to set the Tx2 amplitude
calibration (400 µs).
20. Write 0x2800B929 to Register R9.
21. Write 0x809F25A0 to Register R0 to disable the R and N
counters.
RECALIBRATION SEQUENCE
The ADF5901 can be recalibrated after the initialization
sequence is complete and the device is powered up. The
recalibration sequence must be run for every 10°C temperature
change; the temperature can be monitored using the
temperature sensor (see the Temperature Sensor section).
1.
2.
Rev. B | Page 23 of 26
Write 0x809FE520 to Register R0 to enable the counters.
Tx1 and Tx2 are off, and LO is on.
Write 0x2A20B929 to Register R9.
ADF5901
Data Sheet
3.
Write 0xFFF7FFE1 to Register R1 to set the Tx amplitude
level.
4. Write 0x809FE720 to Register R0 to set the VCO frequency
calibration (800 µs).
5. Write 0x809FE560 to Register R0 to power Tx1 on, Tx2 off,
and LO on.
6. Write 0x809FED60 to Register R0 to set the Tx1 amplitude
calibration (400 µs).
7. Write 0x89FE5A0 to Register R0 to power Tx1 off, Tx2 on,
and LO on.
8. Write 0x809FF5A0 to Register R0 to set the Tx2 amplitude
calibration (400 µs).
9. Write 0x2800B929 to Register R9.
10. Write 0x809F25A0 to Register R0 to disable the R and N
counters.
TEMPERATURE SENSOR
The ADF5901 has an on-chip temperature sensor that can be
accessed on the ATEST pin or as a digital word on DOUT
following an ADC conversion. The temperature sensor operates
over the full operating temperature range of −40°C to +105°C.
The accuracy can be improved by performing a one-point
calibration at room temperature and storing the result in
memory.
With the temperature sensor on the analog test bus and test bus
connected to the ATEST pin (Register 4 set to 0x0000A064) the
ATEST voltage can be converted to temperature with the
following equation:
Temperature ( C) =
(V
ATEST
− VOFF )
VGAIN
(3)
Convert the DOUT word to temperature with the following
equation:
Temperature ( C) =
4.
5.
6.
OFF
(4)
where:
ADC is the ADC code read back on DOUT.
VLSB = 7.33 mV, the ADC LSB voltage.
VOFF = 0.699 V, the offset voltage.
VGAIN = 6.4 × 10−3, the voltage gain.
RF SYNTHESIS: A WORKED EXAMPLE
The following equation governs how to program the ADF5901:
RFOUT = (INT + (FRAC/225)) × (fREF) × 2
(5)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
fREF = REFIN × ((1 + D)/(R × (1 + T)))
(6)
where:
REFIN is the reference frequency input.
D is the reference doubler bit, DB10 in Register R7 (0 or 1).
R is the reference division factor.
T is the reference divide by 2 bit, DB11 in Register R7 (0 or 1).
For example, in a system where a 24.125 GHz RF frequency
output (RFOUT) is required and a 100 MHz reference frequency
input (REFIN) is available, fREF is set to 50 MHz.
From Equation 6,
From Equation 5,
24.125 GHz = 50 MHz × (N + FRAC/225) × 2
Calculating the N and FRAC values,
N = int(RFOUT/(fREF × 2)) = 241
FRAC = FMSB × 213 + FLSB
FMSB = int(((RFOUT/(fREF × 2)) − N) × 212) = 1024
FLSB = int(((((RFOUT/(fREF × 2)) − N) × 212) − FMSB) × 213) = 0
The temperature sensor result can be converted to a digital
word with the ADC and readback on DOUT with the following
sequence:
3.
LSB
VGAIN
fREF = (100 MHz × (1 + 0)/(1 × (1 + 1)) = 50 MHz
where:
VATEST is the voltage on the ATEST pin.
VOFF = 0.699 V, the offset voltage.
VGAIN = 6.4 × 10−3, the voltage gain.
1.
2.
((ADC × V ) − V )
Write 0x809FA5A0 to Register R0 to enable the counters.
Write 0x00012064 to Register R4 to connect the analog test
bus to the ADC and VTEMP to the analog test bus.
Write 0x00028C82 to Register R2 to start the ADC
conversion.
Write 0x018902C3 to Register R3 to set the output ADC
data to DOUT.
Read back DOUT.
Write 0x809F25A0 to Register R0 to disable R and N
counters.
where:
FMSB is the 12-bit MSB FRAC value in Register R5.
FLSB is the 13-bit LSB FRAC value in Register R6.
int() makes an integer of the argument in parentheses.
Rev. B | Page 24 of 26
Data Sheet
ADF5901
APPLICATIONS INFORMATION
APPLICATION OF THE ADF5901 IN FMCW RADAR
Figure 31 shows the application of the ADF5901 in a frequency
modulated continuous wave (FMCW) radar system.
In the FMCW radar system, the ADF4159 generates the
sawtooth or triangle ramps necessary for this type of radar to
operate.
The ADF4159 controls the VTUNE pin on the ADF5901 (Tx)
MMIC and thus the frequency of the VCO and the Tx output
signal on TXOUT1 or TXOUT2. The LO signal from the ADF5901
is fed to the LO input on the ADF5904.
The ADF5904 downconverts the signal from the four receiver
antennas to baseband with the LO signal from the Tx MMIC.
The downconverted baseband signals from the four receiver
channels on the ADF5904 are fed to the ADAR7251 4-channel,
continuous time, Σ-Δ analog-to-digital converter (ADC).
A digital signal processor (DSP) follows the ADC to handle the
target information processing.
LOOP
FILTER
VTUNE
CP
ADF4159
RFINA
AUX
RFINB
AUX
ADF5901
TXOUT1
TXOUT2
LOOUT
LO_IN
RX1_RF
RX2_RF
ADAR7251
RX BASEBAND
ADF5904
RX3_RF
RX4_RF
Figure 31. FMCW Radar with ADF5901
Rev. B | Page 25 of 26
13336-031
DSP
ADF5901
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
1
24
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PKG-004570
SEATING
PLANE
PIN 1
INDICATOR
9
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.
01-26-2016-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 32. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
ORDERING GUIDE
Model 1
ADF5901ACPZ
ADF5901ACPZ-RL7
ADF5901WCCPZ
ADF5901WCCPZ-RL7
EV-ADF5901SD2Z
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Package Option
CP-32-12
CP-32-12
CP-32-12
CP-32-12
Z = RoHS Compliant Part.
AUTOMOTIVE PRODUCTS
The ADF5901W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks
and registered trademarks are the property of their respective
owners.
D13336-0-8/17(B)
Rev. B | Page 26 of 26
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