24 GHz, ISM Band, Multichannel
FMCW Radar Transmitter
ADF5902
Data Sheet
FEATURES
APPLICATIONS
24 GHz to 24.25 GHz VCO (industrial, scientific, and medical
(ISM) radio band)
2-channel 24 GHz power amplifier with 8 dBm output
Single-ended outputs
2-channel muxed outputs with mute function
Programmable output power
LO output buffer
RF frequency range: 24 GHz to 24.25 GHz
Power control detector
Auxiliary 8-bit ADC
High and low speed FMCW ramp generation
25-bit fixed modulus allows subhertz frequency resolution
PFD frequencies up to 110 MHz
Normalized phase noise floor of −222 dBc/Hz
Programmable charge pump currents
±5°C temperature sensor
4-wire SPI
ESD performance
HBM: 2000 V
CDM: 250 V
Qualified for automotive applications
Automotive radars
Industrial radars
Microwave radar sensors
GENERAL DESCRIPTION
The ADF5902 is a 24 GHz transmitter (Tx) monolithic microwave
integrated circuit (MMIC) with an on-chip, 24 GHz voltage
controlled oscillator (VCO). The VCO features a fractional-N
frequency synthesizer with waveform generation capability
with programmable grid array (PGA) and dual transmitter
channels for radar systems. The on-chip, 24 GHz VCO
generates the 24 GHz signal for the two transmitter channels
and the local oscillator (LO) output. Each transmitter channel
contains a power control circuit. There is also an on-chip
temperature sensor.
Control of all the on-chip registers is through a simple, 4-wire
serial peripheral interface (SPI).
The ADF5902 comes in a compact, 32-lead, 5 mm × 5 mm
LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
C1
TX_AHI
C2
LE
DOUT
AHI
32-BIT
DATA
REGISTER
VCO_AHI CP_AHI
READBACK
CONTROL
VREG
RSET
REGULATOR
BIAS
GND
DVDD
RDIV
NDIV
RAMP
STATUS
ADC
ADC OUTPUT
FREQUENCY COUNTER
CE
REFIN
DVDD
ADF5902
CLK
DATA
RF_AHI
VCO
CAL
MUXOUT
TXOUT1
R DIVIDER
+
PHASE
FREQUENCY
DETECTOR
–
CHARGE
PUMP
TXOUT2
÷2
N DIVIDER
ADC
TEMPERATURE
SENSOR
RAMP
GENERATION
ADC
ATEST
FMCW RAMP GENERATION PLL
16746-001
TX_DATA
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
CPOUT
VTUNE
LOOUT
GND
Figure 1.
Rev. A
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ADF5902
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 6 ..................................................................................... 22
Applications ....................................................................................... 1
Register 7 ..................................................................................... 23
General Description ......................................................................... 1
Register 8 ..................................................................................... 24
Functional Block Diagram .............................................................. 1
Register 9 ..................................................................................... 24
Revision History ............................................................................... 2
Register 10 ................................................................................... 25
Specifications..................................................................................... 3
Register 11 ................................................................................... 25
Timing Specifications .................................................................. 5
Register 12 ................................................................................... 26
Absolute Maximum Ratings............................................................ 6
Register 13 ................................................................................... 27
Thermal Resistance ...................................................................... 6
Register 14 ................................................................................... 28
ESD Caution .................................................................................. 6
Register 15 ................................................................................... 29
Pin Configuration and Function Descriptions ............................. 7
Register 16 ................................................................................... 30
Typical Performance Characteristics ............................................. 9
Register 17 ................................................................................... 30
Theory of Operation ...................................................................... 11
Applications Information .............................................................. 31
Reference Input Section ............................................................. 11
Initialization Sequence .............................................................. 31
RF INT Divider ........................................................................... 11
Recalibration Sequence ............................................................. 32
INT, FRAC, and R Relationship ............................................... 11
Temperature Sensor ................................................................... 33
R Counter .................................................................................... 11
RF Synthesis: A Worked Example ............................................ 33
PFD and Charge Pump .............................................................. 11
Reference Doubler...................................................................... 33
Input Shift Register..................................................................... 11
Frequency Measurement Procedure ........................................ 34
Program Modes .......................................................................... 12
Waveform Generation ............................................................... 34
Register Maps .................................................................................. 13
Waveform Deviations and Timing ........................................... 34
Register 0 ..................................................................................... 16
Ramp and Modulation............................................................... 35
Register 1 ..................................................................................... 17
Application of the ADF5902 in FMCW Radar ...................... 37
Register 2 ..................................................................................... 18
Outline Dimensions ....................................................................... 39
Register 3 ..................................................................................... 19
Ordering Guide .......................................................................... 39
Register 4 ..................................................................................... 20
Automotive Products ................................................................. 39
Register 5 ..................................................................................... 21
REVISION HISTORY
1/2020—Rev. 0 to Rev. A
Changes to Figure 23 ...................................................................... 15
Changes to Figure 41 ...................................................................... 30
11/2018—Revision 0: Initial Version
Rev. A | Page 2 of 39
Data Sheet
ADF5902
SPECIFICATIONS
AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = CP_AHI = 3.3 V ± 5%, GND = 0 V, dBm referred to 50 Ω, TA = TMAX to TMIN, unless
otherwise noted. The operating temperature range is −40°C to +105°C.
Table 1.
Parameter
OPERATING CONDITIONS
RF Frequency Range
VCO CHARACTERISTICS
VTUNE
VTUNE Impedance
VCO Phase Noise Performance
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
Amplitude Noise
Static Pulling VCO Frequency (fVCO) Change
vs. Load
Dynamic Pulling Transmitter On or Off Switch
Change
Dynamic Pulling Transmitter to Transmitter
Switch Change
Pushing fVCO Change vs. AHI Change
Spurious Level Harmonics
Spurious Level Nonharmonics
POWER SUPPLIES
AHI, TX_AHI, RF_AHI, VCO_AHI, DVDD, CP_AHI
Total Current (ITOTAL)1
Software Power-Down Mode
Hardware Power-Down Mode
TRANSMITTER OUTPUT
Output Power
Output Impedance
On to Off Isolation
Transmitter to Transmitter Isolation
Power-Up/Power-Down Time
LO OUTPUT
Output Power
Output Impedance
On to Off Isolation
PHASE FREQUENCY DETECTOR (PFD)
Phase Detector Frequency2
CHARGE PUMP
Charge Pump Current (ICP) Sink and Source
Current
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Tristate Leakage Current
Sink and Source Matching
ICP vs. VCP
ICP vs. Temperature
Min
Typ
Max
Unit
24.25
GHz
2.5
100
V
kΩ
−88
−108
−128
−150
±2
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MHz
±10
MHz
At 1 MHz offset
Open-loop into 2:1 voltage standing wave ratio
(VSWR) load
Open-loop
±5
MHz
Open-loop
±5
−30
25 V/μs
V
0.4
V
500
500
μA
μA
1
Following the initialization sequence described in the Initialization Sequence section, TA = 25°C, AHI = 3.3 V, fREFIN = 100 MHz, and RF = 24.025 GHz.
Guaranteed by design. Sample tested to ensure compliance.
3
This specification can be used to calculate phase noise for any application. Use the formula ((Normalized Phase Noise Floor) + 10 log(fPFD) + 20 logN) to calculate
in-band phase noise performance as seen at the VCO output.
4
The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at an offset frequency (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
5
DVDD selected from the IO level bit (Bit DB11 in Register 3).
2
Rev. A | Page 4 of 39
Data Sheet
ADF5902
TIMING SPECIFICATIONS
Write Timing Specifications
AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = CP_AHI = 3.3 V ± 5%, GND = 0 V, dBm referred to 50 Ω, TA = TMIN to TMAX, unless
otherwise noted. The operating temperature range is −40°C to +105°C.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
Limit at TMIN to TMAX
20
10
10
25
25
10
20
10
15
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
t4
Description
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
LE setup time to DOUT
CLK setup time to DOUT
t5
CLK
t2
DATA
t3
DB2
(CONTROL BIT C3)
DB30
DB31 (MSB)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTRO BIT C1)
7
LE
1
6
DB31
(MSB)
DOUT
DB30
DB1
DB0
16746-002
8
9
Figure 2. Write Timing Diagram
500µA
DVDD/2
CL
10pF
500µA
IOH
16746-003
TO DOUT AND
MUXOUT PINS
IOL
Figure 3. Load Circuit for DOUT/MUXOUT Timing, CL = 10 pF
Rev. A | Page 5 of 39
ADF5902
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
AHI to GND
AHI to TX_AHI
AHI to RF_AHI
AHI to VCO_AHI
AHI to DVDD
AHI to CP_AHI
VTUNE to GND
Digital Input/Output Voltage to GND
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Electrostatic Discharge (ESD)
Charged Device Model (CDM)
Human Body Model (HBM)
Rating
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +3.6 V
−0.3 V to DVDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
150°C
260°C
40 sec
The ADF5902 is a high performance RF integrated circuit with
an ESD rating of 2 kV and is ESD sensitive. Take proper
precautions for handling and assembly.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 4. Thermal Resistance
Package Type
CP-32-123
1
θJA1
48.18
θJC2
26.86
Unit
°C/W
θJA is the natural convection junction-to-ambient thermal resistance
measured in a one cubic foot sealed enclosure.
2
θJC is the junction-to-case thermal resistance.
3
Test Condition 1: thermal impedance simulated values are based on use of a
PCB with the thermal impedance pad soldered to GND.
ESD CAUTION
250 V
2000 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 6 of 39
Data Sheet
ADF5902
32
31
30
29
28
27
26
25
C2
C1
VCO_AHI
VTUNE
CPOUT
CP_AHI
RSET
MUXOUT
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADF5902
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
DOUT
LE
DATA
CLK
CE
TX_DATA
VREG
DVDD
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
16746-004
ATEST
GND
LOOUT
GND
GND
RF_AHI
REFIN
AHI
9
10
11
12
13
14
15
16
GND
TXOUT1
GND
TX_AHI
TX_AHI
GND
TXOUT2
GND
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1, 3, 6, 8, 10,
12, 13
2
4, 5
Mnemonic
GND
Description
RF Ground. Tie all GND pins together.
TXOUT1
TX_AHI
7
9
11
14
TXOUT2
ATEST
LOOUT
RF_AHI
15
REFIN
16
AHI
17
DVDD
18
19
VREG
TX_DATA
20
21
CE
CLK
22
DATA
23
LE
24
25
26
DOUT
MUXOUT
RSET
27
CP_AHI
28
CPOUT
24 GHz Transmitter Output 1.
Voltage Supply for the Transmitter Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the
ground plane as close as possible to this pin. TX_AHI must be the same value as AHI.
24 GHz Transmitter Output 2.
Analog Test Output Pin.
LO Output.
Voltage Supply for the RF Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground
plane as close as possible to this pin. RF_AHI must be the same value as AHI.
Reference Input. This pin is a CMOS input with a nominal threshold of DVDD/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 17. This input can be driven from a TTL or CMOS crystal oscillator, or it can
be ac-coupled.
Voltage Supply for the Analog Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the
ground plane as close as possible to this pin.
Digital Power Supply. This supply may range from 3.135 V to 3.465 V. Place decoupling capacitors (0.1 μF,
1 nF, and 10 pF) to the ground plane as close as possible to this pin. DVDD must be the same value as AHI.
Internal 1.8 V Regulator Output. Connect a 220 nF capacitor to ground as close as possible to this pin.
Transmit Data Pin. This pin controls some of the ramping functionality. Synchronize the rising edge of the
TX_DATA signal to the rising edge of REFIN.
Chip Enable. A logic low on this pin powers down the device. Taking the pin high powers up the device.
Serial Clock Input. This serial clock input clocks in the serial data to the registers. The data is latched into the
32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded to one of the
18 latches with the latch selected via the control bits.
Serial Data Output.
Multiplexer Output. This multiplexer output allows various internal signals to be accessed externally.
Resistor Setting Pin. Connecting a 5.1 kΩ resistor between this pin and GND sets an internal current. The
nominal voltage potential at the RSET pin is 0.62 V.
Charge Pump Power Supply. This supply may range from 3.135 V to 3.465 V. Place decoupling capacitors
(0.1 μF, 1 nF, and 10 pF) to the ground plane as close as possible to this pin. CP_AHI must be the same value
as AHI.
Charge Pump Output. When the charge pump is enabled, this output provides ±ICP to the external loop
filter, which, in turn, drives the VCO.
Rev. A | Page 7 of 39
ADF5902
Data Sheet
Pin No.
29
30
Mnemonic
VTUNE
VCO_AHI
31
32
C1
C2
EP
Description
Control Input to the VCO. This voltage determines the output.
Voltage Supply for the VCO Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground
plane as close as possible to this pin. VCO_AHI must be the same value as AHI.
Decoupling Capacitor 1. Place a 47 nF capacitor to ground as close as possible to this pin.
Decoupling Capacitor 2. Place a 220 nF capacitor to ground as close as possible to this pin.
Exposed Pad. The exposed pad must be connected to GND.
Rev. A | Page 8 of 39
Data Sheet
ADF5902
TYPICAL PERFORMANCE CHARACTERISTICS
6
12
4
LO OUTPUT POWER (dBm)
8
6
–40°C
+25°C
+105°C
OUTSIDE OF SPECIFIED RANGE
Tx1
Tx2
4
2
2
0
–2
–40°C
+25°C
+105°C
OUTSIDE OF SPECIFIED RANGE
–4
24.00
24.05
24.10
24.15
24.20
24.25
24.30
OUTPUT FREQUENCY (GHz)
–8
23.95
16746-005
0
23.95
24.10
24.15
24.20
24.25
24.30
Figure 8. LO Output Power vs. Output Frequency
12
24.250
10
24.200
FREQUENCY (GHz)
8
6
4
3.135V
–40°C
3.300V
+25°C
3.465V
+105°C
OUTSIDE OF SPECIFIED RANGE
2
0
23.95
24.00
24.05
24.10
24.15
24.20
24.150
24.100
24.050
24.25
24.30
OUTPUT FREQUENCY (GHz)
24.000
16746-006
Tx1 OUTPUT POWER (dBm)
24.05
OUTPUT FREQUENCY (GHz)
Figure 5. Transmitter (Tx) Output Power vs. Output Frequency
0
Figure 6. Transmitter 1 (Tx1) Output Power Variation vs. Output Frequency
with Temperature and Supply
100
200
300
TIME (µs)
400
500
600
500
600
Figure 9. Triangular Ramp with Delay
24.250
15
–40°C
+25°C
+105°C
10
24.200
5
FREQUENCY (GHz)
Tx OUTPUT POWER (dBm)
24.00
16746-008
–6
16746-009
Tx OUTPUT POWER (dBm)
10
0
–5
–10
24.150
24.100
24.050
0
10
20
30
40
50
60
70
80
90
Tx AMPLITUDE CALIBRATION REFERENCE CODE
100
24.000
16746-007
–20
0
Figure 7. Transmitter (Tx) Output Power vs. Transmitter (Tx) Amplitude
Calibration Reference Code
Rev. A | Page 9 of 39
100
200
300
TIME (µs)
400
Figure 10. Dual Triangular Ramp
16746-010
–15
ADF5902
Data Sheet
4
24.300
3
2
24.200
1
CURRENT (mA)
FREQUENCY (GHz)
24.250
24.150
0
PUMP UP SETTING 7
PUMP DOWN SETTING 7
–1
–2
24.100
–3
OUTSIDE OF SPECIFIED RANGE
24.050
–4
100
200
300
TIME (µs)
400
500
600
–5
0
1.0
1.5
2.0
2.5
3.0
CHARGE PUMP VOLTAGE (V)
Figure 14. Charge Pump Output Characteristics, CP_AHI = 3.3 V, at 25°C
Figure 11. Sawtooth Ramp
–40
3.5
3.0
25°C,AHI = 3.3V, ICP = 2.24mA
300kHz LOOP BW FILTER, fPFD = 100MHz
PHASE NOISE (dBc/Hz)
–60
2.5
2.0
1.5
–40°C
+25°C
+105°C
1.0
–80
–100
–120
–140
0.5
24.10
24.15
24.20
24.25
OUTPUT FREQUENCY (MHz)
–160
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFET (Hz)
Figure 15. Closed-Loop Phase Noise on Transmitter 1 at 24.125 GHz
Figure 12. VTUNE Frequency Range
0
250
1.8
–10
–20
1.6
200
–30
–50
1.2
–60
–70
–80
–90
–100
150
1.0
0.8
100
0.6
ADC CODE (Count)
1.4
–40
ATEST (V)
–110
0.4
–120
–130
50
0.2
Figure 13. Open-Loop Phase Noise on Transmitter 1 Output at 24.125 GHz
Rev. A | Page 10 of 39
0
120
110
90
80
70
60
50
40
30
20
0
100
FREQUENCY OFFSET (Hz)
10M
0
1M
10
100k
–10
10k
–20
1k
–30
–150
16746-012
–140
–40
PHASE NOISE (dBc/Hz)
16746-113
24.05
16746-011
0
24.00
TEMPERATURE (ºC)
Figure 16. ATEST Voltage and ADC Code vs. Temperature
16746-013
VTUNE (V)
0.5
16746-112
0
16746-109
24.000
Data Sheet
ADF5902
THEORY OF OPERATION
REFERENCE INPUT SECTION
R DIVIDER
REFIN
100kΩ
The 5-bit R counter allows the input reference frequency (REFIN)
to be divided down to supply the reference clock to the PFD
and VCO calibration block. Division ratios from 1 to 32 are
allowed.
TO R COUNTER
BUFFER
SW1
SW3
NO2
PFD AND CHARGE PUMP
16746-014
1NC = NORMALLY CLOSED
2NO = NORMALLY OPEN
The PFD receives inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 20 shows a simplified schematic of the PFD.
Figure 17. Reference Input Stage
RF INT DIVIDER
The RF INT counter allows a division ratio in the RF feedback
counter. Division ratios from 75 to 4095 are allowed.
INT, FRAC, AND R RELATIONSHIP
HIGH
D1
Q1
CLR1
DELAY
25
RFOUT = fPFD × (INT + (FRAC/2 )) × 2
fPFD = REFIN × ((1 + D)/(R × (1 + T)))
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit (0 or 1).
R is the preset divide ratio of the binary, 5-bit, programmable
reference counter (1 to 32).
T is the REFIN divide by 2 bit (0 or 1).
N = INT + FRAC/225
TO PFD/
CAL BLOCK
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
16746-116
INT
VALUE
U3
CHARGE
PUMP
CP
(1)
where:
RFOUT is the output frequency of the internal VCO.
fPFD is the phase frequency detector (PFD) frequency.
INT is the preset divide ratio of the binary 12-bit counter
(75 to 4095).
FRAC is the numerator of the fractional division (0 to 225 − 1).
N COUNTER
UP
U1
+IN
Generate the RF VCO frequency (RFOUT) using the INT and
FRAC values in conjunction with the R counter, as follows:
FROM RF
INPUT STAGE
TO PFD/
CAL BLOCK
R COUNTER
SW2
RF N DIVIDER
÷2
DIVIDER
HIGH
CLR2
DOWN
D2
Q2
U2
–IN
16746-120
NC1
5-BIT
R
COUNTER
×2
DOUBLER
Figure 19. Reference Divider
POWER-DOWN
CONTROL
NC1
REFIN
16746-117
The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This configuration ensures that there is no loading of
the REFIN pin on power-down.
Figure 20. PFD Simplified Schematic
The PFD includes a fixed delay element that sets the width of the
antibacklash pulse, which is typically 1 ns. This pulse ensures that
there is no dead zone in the PFD transfer function and provides
a consistent reference spur level.
INPUT SHIFT REGISTER
The ADF5902 digital section includes a 5-bit RF R counter,
a 12-bit RF N counter, and a 25-bit FRAC counter. Data is
clocked to the 32-bit input shift register on each rising edge of
CLK. The data is clocked in MSB first. Data is transferred from
the input shift register to one of 18 latches on the rising edge of
LE. The destination latch is determined by the state of the five
control bits (C5, C4, C3, C2, and C1) in the input shift register.
These are the five LSBs (DB4, DB3, DB2, DB1, and DB0,
respectively), as shown in Figure 2. Table 6 shows the truth table
for these bits. Figure 21 and Figure 22 show a summary of how
the latches are programmed.
Figure 18. RF N Divider
Rev. A | Page 11 of 39
ADF5902
Data Sheet
PROGRAM MODES
Table 6 and Figure 24 through Figure 42 show how to set up the
program modes in the ADF5902.
Several settings in the ADF5902 are double buffered. These
include the LSB fractional value, R counter value (R divider),
reference doubler, clock divider, RDIV2, and MUXOUT. This
means that two events must occur before the device uses a new
value for any of the double buffered settings. First, the new
value is latched into the device by writing to the appropriate
register. Second, a new write must be performed on Register R5.
For example, updating the fractional value can involve a write to
the 13 LSB bits in Register R6 and the 12 MSB bits in Register R5.
Write to Register R6 first, followed by the write to Register R5.
The frequency change begins after the write to Register R5.
Double buffering ensures that the bits written to in Register R6
do not take effect until after the write to Register R5.
Table 6. C5, C4, C3, C2, and C1 Truth Table
C5 (DB4)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
C4 (DB3)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
Control Bits
C3 (DB2)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
C2 (DB1)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Rev. A | Page 12 of 39
C1 (DB0)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
Data Sheet
ADF5902
REGISTER MAPS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
PUP LO
PUP Tx1
PUP Tx2
PUP ADC
VCO CAL
PUP VCO
RESERVED
Tx1 AMP CAL
Tx2 AMP CAL
REGISTER 0 (R0)
CONTROL
BITS
DB7 DB6 DB5 DB4 DB3
DB2
DB1
DB0
Tx2C Tx1C PVCO VCAL PADC PTx2 PTx1 PLO C5(0) C4(0) C3(0) C2(0) C1(0)
REGISTER 1 (R1)
RESERVED
CONTROL
BITS
Tx AMP CAL REF CODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
DB2
DB1
DB0
TAR7 TAR6 TAR5 TAR4 TAR3 TAR2 TAR1 TAR0 C5(0) C4(0) C3(0) C2(0) C1(1)
ADC START
REGISTER 2 (R2)
RESERVED
ADC
AVERAGE
CONTROL
BITS
ADC CLOCK DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
AS
AA0 AA0
AC7
AC6
AC5 AC4
AC3 AC2 AC1
DB2
DB1
DB0
AC0 C5(0) C4(0) C3(0) C2(1) C1(0)
IO LEVEL
REGISTER 3 (R3)
MUXOUT DBR 1
RESERVED
CONTROL
BITS
READBACK CONTROL
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
M3
M2
M1
M0
IOL
RC5
DB2
DB1
DB0
RC4 RC3 RC2 RC1 RC0 C5(0) C4(0) C3(0) C2(1) C1(1)
REGISTER 4 (R4)
CONTROL
BITS
RAMP STATUS/ANALOG TEST BUS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
AB14 AB13 AB12 AB11 AB10
AB9
AB8
AB7
AB6
AB5 AB4 AB3
DB2
DB1
DB0
AB2 AB1 AB0 C5(0) C4(0) C3(1) C2(0) C1(0)
RESERVED
RAMP ON
REGISTER 5 (R5)
INTEGER WORD
CONTROL
BITS
FRAC MSB WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
RON
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
DB2
DB1
DB0
F13 C5(0) C4(0) C3(1) C2(0) C1(1)
REGISTER 6 (R6)
FRAC LSB WORD
CONTROL
BITS
DBR1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
1DBR
0
0
0
0
0
0
0
0
0
0
0
0
0
F12
F11
F10
F9
F8
F7
F6
F5
= DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 5.
Figure 21. Register Summary (Register 0 to Register 6)
Rev. A | Page 13 of 39
F4
F3
F2
F1
F0
DB2
DB1
DB0
C5(0) C4(0) C3(1) C2(1) C1(0)
16746-017
RESERVED
ADF5902
Data Sheet
DBR 1
CLOCK DIVIDER
REF DOUBLER
DBR 1
DBR 1
RDIV2
RESERVED
RESERVED
MASTER
RESET
REGISTER 7 (R7)
R DIVIDER
CONTROL
BITS
DBR1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
MR
C1D11 C1D10 C1D9 C1D8 C1D7 C1D6 C1D5 C1D4 C1D3 C1D2 C1D1 C1D0 RD2
1
RD
R4
R3
R2
R1
R0
DB2
DB1
DB0
C5(0) C4(0) C3(1) C2(1) C1(1)
REGISTER 8 (R8)
CONTROL
BITS
FREQENCY CAL DIVIDER
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FC9
FC8
FC7
FC6
FC5
DB2
DB1
DB0
FC4 FC3 FC2 FC1 FC0 C5(0) C4(1) C3(0) C2(0) C1(0)
REGISTER 9 (R9)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
DB2
DB1
DB0
C5(0) C4(1) C3(0) C2(0) C1(1)
REGISTER 10 (R10)
CONTROL
BITS
RESERVED
1
1
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
1
0
RAMP
MODE
CNTR
RESET
1
RESERVED
0
SING FULL
TRI RAMP
0
RESERVED
0
SD RESET
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
DB2
DB1
DB0
C5(0) C4(1) C3(0) C2(1) C1(0)
REGISTER 11 (R11)
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDR
0
SFT RM1 RM0
0
DB2
DB1
DB0
CR C5(0) C4(1) C3(0) C2(1) C1(1)
CHARGE PUMP
CURRENT
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
1
0
CC3
CC2
CC1
CC0
1
CTRI
0
0
0
0
0
1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 5.
Figure 22. Register Summary (Register 7 to Register 12)
Rev. A | Page 14 of 39
0
0
0
0
0
DB2
DB1
DB0
C5(0) C4(1) C3(1) C2(0) C1(0)
16746-018
DBR 1
RESERVED
CP TRISTATE
DBR 1
RESERVED
REGISTER 12 (R12)
Data Sheet
ADF5902
RESERVED
CLK DIV
SEL
LE SEL
CLK DIV
MODE
REGISTER 13 (R13)
CLOCK DIVIDER 2
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
DB2
DB1
DB0
LES CDM1 CDM0 C2D11 C2D10 C2D9 C2D8 C2D7 C2D6 C2D5 C2D4 C2D3 C2D2 C2D1 C2D0 CDS1 CDS0 C5(0) C4(1) C3(1) C2(0) C1(1)
TX RAMP CLK
Tx_DATA INV
REGISTER 14 (R14)
DEVIATION
SEL
RESERVED
DEVIATION OFFSET
CONTROL
BITS
DEVIATION WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
TDI
TRC
0
0
0
DS1
DS0
DO3
DO2
DO1
DO0 DW15 DW14 DW13 DW12 DW11 DW10 DW9
DW8 DW7 DW6
DB2
DB1
DB0
DW5 DW4 DW3 DW2 DW1 DW0 C5(0) C4(1) C3(1) C2(1) C1(0)
REGISTER 15 (R15)
STEP
SEL
RESERVED
CONTROL
BITS
STEP WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
SS1
SS0 SW19 SW18 SW17 SW16 SW15 SW14 SW13 SW12 SW11 SW10 SW9
SW8 SW7
SW6
DB2
DB1
DB0
SW5 SW4 SW3 SW2 SW1 SW0 C5(0) C4(1) C3(1) C2(1) C1(1)
RESERVED
RAMP DEL
DELAY
SELECT
RESERVED
Tx_DATA
TRIGGER
RESERVED
REGISTER 16 (R16)
CONTROL
BITS
DELAY START WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
1
DSL1 DSL0
0
0
TR1
RD
0
0
DS11 DS10 DS9
DS8
DS7
DS6
DS5
DB2
DB1
DB0
DS4 DS3 DS2 DS1 DS0 C5(1) C4(0) C3(0) C2(0) C1(0)
REGISTER 17 (R17)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 23. Register Summary (Register 13 to Register 17)
Rev. A | Page 15 of 39
0
0
0
0
0
DB2
DB1
DB0
C5(1) C4(0) C3(0) C2(0) C1(1)
16746-121
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
PUP LO
PUP Tx1
PUP Tx2
PUP ADC
VCO CAL
PUP VCO
RESERVED
Tx1 AMP CAL
Data Sheet
Tx2 AMP CAL
ADF5902
CONTROL
BITS
DB8 DB7 DB6 DB5 DB4 DB3
DB2
DB1
DB0
Tx2C Tx1C PVCO VCAL PADC PTx2 PTx1 PLO C5(0) C4(0) C3(0) C2(0) C1(0)
PLO
PTx1
PTx2
PUP LO
0
POWER DOWN LO
1
POWER UP LO
PUP Tx1
0
POWER DOWN Tx1
1
POWER UP Tx1
PUP Tx2
0
POWER DOWN Tx2
1
POWER UP Tx2
PADC PUP ADC
Tx2 AMP CAL
0
POWER DOWN ADC
0
NORMAL OPERATION
1
POWER UP ADC
1
Tx2 AMP CAL
Tx2C
0
NORMAL OPERATION
0
NORMAL OPERATION
1
VCO FULL CAL
1
Tx1 AMP CAL
PVCO
PUP VCO
0
POWER DOWN VCO
1
POWER UP VCO
16746-019
VCAL VCO CAL
Tx1 AMP CAL
Tx1C
Figure 24. Register 0 (R0)
REGISTER 0
VCO Calibration
Control Bits
With Bits[C5:C1] set to 00000, Register R0 is programmed.
Figure 24 shows the input data format for programming this
register.
Bit DB9 provides the control bit for frequency calibration of the
VCO. Set this bit to 0 for normal operation. Setting this bit to 1
performs a VCO frequency and amplitude calibration. Bit DB9
is shown as VCO CAL in Figure 24.
Reserved
Power-Up ADC
Bits[DB31:DB13] are reserved and must be set as shown in
Figure 24.
Transmitter 2 (Tx2) Amplitude Calibration
Bit DB12 provides the control bit for amplitude calibration of
the Tx2 output. Set this bit to 0 for normal operation. Setting
this bit to 1 performs an amplitude calibration of the Tx2
output. Bit DB12 is shown as Tx2 AMP CAL in Figure 24.
Tx1 Amplitude Calibration
Bit DB11 provides the control bit for amplitude calibration of
the Tx1 output. Set this bit to 0 for normal operation. Setting
this bit to 1 performs an amplitude calibration of the Tx1
output. Bit DB11 is shown as Tx1 AMP CAL in Figure 24.
Power-Up VCO
Bit DB10 provides the power-up bit for the VCO. Setting this bit
to 0 performs a power-down of the VCO. Setting this bit to 1
performs a power-up of the VCO. Bit DB10 is shown as PUP
VCO in Figure 24.
Bit DB8 provides the power-up bit for the ADC. Setting this bit
to 0 performs a power-down of the ADC. Setting this bit to 1
performs a power-up of the ADC. Bit DB8 is shown as PUP ADC
in Figure 24.
Power-Up Tx2 Output
Bit DB7 provides the power-up bit for the Tx2 output. Setting
this bit to 0 performs a power-down of the Tx2 output. Setting
this bit to 1 performs a power-up of the Tx2 output. Only one
transmitter output can be powered up at any time, either Tx1
(DB6) or Tx2 (DB7). Bit DB7 is shown as PUP Tx2 in Figure 24.
Power-Up Tx1 Output
Bit DB6 provides the power-up bit for the Tx1 output. Setting
this bit to 0 performs a power-down of the Tx1 output. Setting
this bit to 1 performs a power-up of the Tx1 output. Only one
Tx output can be powered up at any time, either Tx1 (DB6) or
Tx2 (DB7). Bit DB6 is shown as PUP Tx1 in Figure 24.
Power-Up LO Output
Bit DB5 provides the power-up bit for the LO output. Setting
this bit to 0 performs a power-down of the LO output. Setting
this bit to 1 performs a power-up of the LO output. Bit DB5 is
shown as PUP LO in Figure 24.
Rev. A | Page 16 of 39
Data Sheet
ADF5902
Tx AMP CAL REF CODE
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
DB1
DB0
TAR7 TAR6 TAR5 TAR4 TAR3 TAR2 TAR1 TAR0 C5(0) C4(0) C3(0) C2(0) C1(1)
.......... TAR1 TAR0
Tx AMP CAL REF CODE
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
252
1
1
..........
0
1
253
1
1
..........
1
0
254
1
1
.........
1
1
255
TAR7 TAR6
Figure 25. Register 1 (R1)
REGISTER 1
Transmitter Amplitude Calibration Reference Code
Control Bits
Bits[DB12:DB5] set the transmitter amplitude calibration
reference code for the two transmitter outputs during
calibration. Calibrate the output power on the transmitter
outputs from −20 dBm to 8 dBm by setting the transmitter
amplitude calibration reference code (see Figure 7).
Bits[DB12:DB5] are shown as Tx AMP CAL REF CODE
in Figure 25.
With Bits[C5:C1] set to 00001, Register R1 is programmed.
Figure 25 shows the input data format for programming this
register.
Reserved
Bits[DB31:DB13] are reserved and must be set as shown in
Figure 25.
Rev. A | Page 17 of 39
16746-020
1
DB2
Data Sheet
RESERVED
ADC
AVERAGE
CONTROL
BITS
ADC CLOCK DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
AS
AS
ADC START
0
NORMAL OPERATION
1
START ADC CONVERSION
AA0 AA0
AC7
AC6
AC7
AC5 AC4
AC3 AC2 AC1
AC1
AC0
AC6
.
0
0
.
0
1
1
0
0
.
1
0
2
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
1
1
2
1
1
.
0
0
124
0
1
3
4
1
1
.
0
1
125
1
1
.
1
0
126
1
1
.
1
1
127
AA0
0
0
1
1
DB1
DB0
ADC CLOCK DIVIDER
ADC AVERAGE
AA1
DB2
AC0 C5(0) C4(0) C3(0) C2(1) C1(0)
16746-021
ADC START
ADF5902
Figure 26. Register 2 (R2)
REGISTER 2
ADC Start
Control Bits
Bit DB15 starts the ADC conversion. Setting this bit to 1 starts
an ADC conversion.
With Bits[C5:C1] set to 00010, Register R2 is programmed.
Figure 26 shows the input data format for programming this
register.
Reserved
Bits[DB31:DB16] are reserved and must be set as shown in
Figure 26.
ADC Average
Bits[DB14:DB13] program the ADC average, which is the
number of averages of the ADC output (see Figure 26).
ADC Clock Divider
Bits[DB12:DB5] program the clock divider, which is used as the
sampling clock for the ADC (see Figure 26). The output of the
R divider block clocks the ADC clock divider. Program a
divider value to ensure the ADC sampling clock is 1 MHz.
Rev. A | Page 18 of 39
ADF5902
RESERVED
IO LEVEL
Data Sheet
MUXOUT DBR 1
CONTROL
BITS
READBACK CONTROL
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
1
1
0
0
0
1
0
0
M3 M2 M1 M0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1DBR = DOUBLE-BUFFERED REGISTER.
1
M3
M2
M1
M0
IOL
RC5
DB2
DB1
DB0
RC4 RC3 RC2 RC1 RC0 C5(0) C4(0) C3(0) C2(1) C1(1)
MUXOUT
TRISTATE OUTPUT
LOGIC HIGH
LOGIC LOW
R DIVIDER OUTPUT
N DIVIDER OUTPUT
RESERVED
RESERVED
CAL BUSY
RESERVED
RESERVED
RESERVED
R DIVIDER/2
N DIVIDER/2
RESERVED
RESERVED
RAMP STATUS TO MUXOIUT
IOL
IO LEVEL
0
1.8V LOGIC OUTPUTS
1
3.3V LOGIC OUTPUTS
RC5 RC4 RC3 RC2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
0
0
1
.
.
.
.
0
1
0
1
RC1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
RC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
.
1
0
.
0
.
1
.
0
.
0
.
0
.
1
.
1
.
0
.
1
0
0
0
1
1
1
0
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
.
0
.
1
1
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
.
1
1
0
1
0
1
0
1
READBACK CONTROL
NONE
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGSITER 5
REGISTER 6
REGISTER 7
REGISTER 8
REGISTER 9
REGISTER 10
REGISTER 11
REGISTER 12
REGISTER 13 SEL = 0
REGISTER 14 SEL = 0
REGISTER 15 SEL = 0
REGISTER 16 SEL = 0
REGISTER 17
RESERVED
ADC READBACK
RESERVED
FREQ READBACK
RESERVED
REGISTER 13 SEL = 1
REGISTER 14 SEL = 1
REGISTER 15 SEL = 1
REGISTER 16 SEL = 1
REGISTER 13 SEL = 2
REGISTER 14 SEL = 2
REGISTER 15 SEL = 2
REGISTER 16 SEL = 2
REGISTER 13 SEL = 3
REGISTER 14 SEL = 3
REGISTER 15 SEL = 3
REGISTER 16 SEL = 3
RESERVED
16746-022
0
Figure 27. Register 3 (R3)
REGISTER 3
MUXOUT Control
Control Bits
Bits[DB15:DB12] control the on-chip multiplexer of the
ADF5902. See Figure 27 for the truth table.
With Bits[C5:C1] set to 00011, Register R3 is programmed.
Figure 27 shows the input data format for programming this
register.
Reserved
Bits[DB31:DB16] are reserved and must be set as shown in
Figure 27.
Input/Output (I/O) Level
Bit DB11 controls the DOUT logic levels. Setting this bit to 0
sets the DOUT logic level to 1.8 V. Setting this bit to 1 sets the
DOUT logic level to 3.3 V.
Readback Control
Bits[DB10:DB5] control the readback data to DOUT on the
ADF5902. See Figure 27 for the truth table.
Rev. A | Page 19 of 39
ADF5902
Data Sheet
CONTROL
BITS
RAMP STATUS/ANALOG TEST BUS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
0
0
0
0
AB14 AB13 AB12 AB11 AB10 AB9
AB8
AB7
AB6
AB5 AB4
AB3
DB7
DB6 DB5 DB4 DB3
AB2
AB1 AB0 C5(0) C4(0) C3(1) C2(0) C1(0)
AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0
DB2
DB1
DB0
ANALOG TEST BUS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0x00C0 RAMP COMPLETE TO MUXOUT
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0x0100
RAMP DOWN TO MUXOUT
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
0x0503
TEMPERATURE SENSOR TO ATEST
0
0
0
1
0
0
1
0
0
0
0
0
0
1
1
0x0903
TEMPERATURE SENSOR TO ADC
NONE
16746-023
RESERVED
Figure 28. Register 4 (R4)
REGISTER 4
Ramp Status/Analog Test Bus
Control Bits
Bits[DB19:DB5] control the analog test bus and the ramp status
to MUXOUT (see Figure 28).
With Bits[C5:C1] set to 00100, Register R4 is programmed.
Figure 28 shows the input data format for programming this
register.
Reserved
The analog test bus allows access to internal test signals for the
temperature sensor which can be connected to the ATEST pin
or the internal ADC.
Bits[DB31:DB20] are reserved and must be set as shown in
Figure 28.
Setting Bits DB[19:5] to 0 (no value) sets the ATEST pin to high
impedance.
For ramp status outputs on MUXOUT, the MUXOUT bits in
Register R3 (Bits[DB15:DB12]) must be set to 1111 to access
these modes.
Rev. A | Page 20 of 39
INTEGER WORD
CONTROL
BITS
FRAC MSB WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
R1
RON
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
N11
N10
...
N4
N3
N2
N1
N0
INTEGER WORD
0
0
...
0
0
0
0
0
NOT ALLOWED
F24
F23
..........
F14
F13
FRAC MSB WORD
(FRAC)*
0
0
...
0
0
0
0
1
NOT ALLOWED
0
0
..........
0
0
0
0
0
...
0
0
0
1
0
NOT ALLOWED
0
0
..........
0
1
1
.
.
...
.
.
.
.
.
...
0
0
..........
1
0
2
0
0
...
0
1
0
1
0
NOT ALLOWED
0
0
..........
1
1
3
0
0
...
0
1
0
1
1
75
.
.
..........
.
.
.
0
0
...
0
1
1
0
0
76
.
.
..........
.
.
.
.
.
...
.
.
.
.
.
...
.
.
..........
.
.
.
1
1
...
1
1
1
0
1
4093
1
1
..........
0
0
4092
1
1
...
1
1
1
1
0
4094
1
1
..........
0
1
4093
1
1
...
1
1
1
1
1
4095
1
1
..........
1
0
4094
1
1
.........
1
1
4095
RAMP ON
0
RAMP DISABLED
1
RAMP ENABLED
DB2
DB1
DB0
F13 C5(0) C4(0) C3(1) C2(0) C1(1)
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R5, AND THE 13-BIT LSB REGISTER STORED IN
REGISTER R6. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 213.
16746-024
RESERVED
ADF5902
RAMP ON
Data Sheet
Figure 29. Register 5 (R5)
When using the TX_DATA pin to trigger the ramp off in
continuous ramp modes, the ramp stops at the initial frequency,
a write to Register R6 is not required. When using the TX_
DATA pin in single ramp modes, a write to Register R6 is not
required prior to repeating the single ramp function.
REGISTER 5
Control Bits
With Bits[C5:C1] set to 00101, Register R5 is programmed.
Figure 29 shows the input data format for programming this
register.
12-Bit Integer Value (INT)
Reserved
Bits[DB31:DB30] are reserved and must be set as shown in
Figure 29.
Ramp On
When Bit DB29 is set to 1, the ramp is started. When Bit DB29
is set to 0, the ramp function is disabled.
In continuous ramp modes, the ramp stops when Bit DB29 is
set to 0. For applications that require the ramp to stop at the
initial frequency, a write to Register R6 is required prior to
disabling the ramp function. In single ramp modes, a write to
Register R6 is required prior to repeating the single ramp
function.
These 12 bits (Bits[DB28:DB17]) set the INT value, which
determines the integer part of the RF division factor. This INT
value is used in Equation 5. See the RF Synthesis: A Worked
Example section for more information. All integer values from 75
to 4095 are allowed.
12-Bit MSB Fractional Value (FRAC)
Bits[DB16:DB5], together with Bits[DB17:DB5] (FRAC LSB
word) in Register R6, control what is loaded as the FRAC value
into the fractional interpolator. This FRAC value partially
determines the overall RF division factor. It is also used in
Equation 1. These 12 bits are the most significant bits (MSB) of
the 25-bit FRAC value, and Bits[DB17:DB5] (FRAC LSB word)
in Register R6 are the least significant bits (LSB). See the RF
Synthesis: A Worked Example section for more information.
Rev. A | Page 21 of 39
ADF5902
Data Sheet
CONTROL
BITS
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
F12
0
F11
F10
F9
F8
F7
F6
F5
F4
F3
F12
F11
..........
F1
F0
FRAC LSB WORD
(FRAC)*
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
8188
1
1
..........
0
1
8189
1
1
..........
1
0
8190
1
1
.........
1
1
8191
F2
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R5, AND THE 13-BIT LSB REGISTER STORED IN
REGISTER R6. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 213.
1DBR = DOUBLE-BUFFERED REGISTER.
F1
F0
DB2
DB1
DB0
C5(0) C4(0) C3(1) C2(1) C1(0)
16746-025
FRAC LSB WORD
RESERVED
Figure 30. Register 6 (R6)
REGISTER 6
13-Bit LSB FRAC Value
Control Bits
These 13 bits (Bits[DB17:DB5]), together with Bits[DB16:DB5]
(FRAC MSB word) in Register R5, control what is loaded as the
FRAC value into the fractional interpolator. This FRAC value
partially determines the overall RF division factor. It is also used
in Equation 1. These 13 bits are the least significant bits (LSB)
of the 25-bit FRAC value, and Bits[DB16:DB5] (FRAC MSB
word) in Register R5 are the most significant bits (MSB). See
the RF Synthesis: A Worked Example section for more
information.
With Bits[C5:C1] set to 00110, Register R6 is programmed.
Figure 30 shows the input data format for programming
this register.
Reserved
Bits[DB31:DB18] are reserved and must be set as shown in
Figure 30.
Rev. A | Page 22 of 39
DBR1
RDIV2
RESERVED
DBR1
CLOCK DIVIDER
R DIVIDER
CONTROL
BITS
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
MR
MR
1
C1D11C1D10 C1D9 C1D8 C1D7 C1D6 C1D5 C1D4 C1D3 C1D2 C1D1 C1D0 RD2
R4
R3
R2
R1
R0
DB2
DB1
DB0
C5(0) C4(0) C3(1) C2(1) C1(1)
MASTER RESET
0
DISABLED
1
ENABLED
C1D11 C1D10
1DBR
RD
= DOUBLE-BUFFERED REGISTER.
RD2
RDIV2
0
DISABLED
1
ENABLED
RD
REF
DOUBLER
.......... C1D2 C1D0
CLOCK DIVIDER (CLK 1)
0
DISABLED
1
ENABLED
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
R4
R3
R2
R1
R0
R DIVIDER (R)
.
.
..........
.
.
.
0
0
0
0
1
1
.
.
..........
.
.
.
0
0
0
1
0
2
.
.
..........
.
.
.
.
.
.
.
.
.
1
1
..........
0
0
4092
.
.
.
.
.
.
1
1
..........
0
1
4093
.
.
.
.
.
.
1
1
..........
1
0
4094
1
1
1
0
0
28
1
1
.........
1
1
4095
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31
16746-026
RESERVED
REF DOUBLER
DBR1
ADF5902
MASTER
RESET
Data Sheet
Figure 31. Register 7 (R7)
REGISTER 7
Divide by 2 (RDIV2)
Control Bits
Setting the DB11 bit to 1 inserts a divide by 2 toggle flip flop
between the R counter and VCO calibration block.
With Bits[C5:C1] set to 00111, Register R7 is programmed.
Figure 31 shows the input data format for programming
this register.
Reference Doubler
Reserved
Bits[DB31:DB26] are reserved and must be set as shown in
Figure 31.
Master Reset
Bit DB25 provides a master reset bit for the device. Setting this
bit to 1 performs a reset of the device and all register maps.
Setting this bit to 0 returns the device to normal operation.
Clock Divider
Bits[DB23:DB12] controls the clock divider (CLK1) value (see
Figure 31). The CLK1 value sets a divider for the VCO frequency
calibration. Load the divider such that PFD frequency (fPFD)/
CLK1 is less than or equal to 25 kHz.
For example, for fPFD = 50 MHz, set CLK1 = 2048 so that fPFD/
CLK1 < 25 kHz.
The CLK1 value is also used to determine the duration of the
time step in ramp mode. See the Ramp and Modulation section
for more information.
Setting DB10 to 0 feeds the REFIN signal directly to the 5-bit
R counter, disabling the doubler. Setting this bit to 1 multiplies
the REFIN frequency by a factor of 2 before the REFIN signal is
fed to the 5-bit R counter. When the doubler is disabled, the
REFIN falling edge is the active edge at the PFD input to the
fractional synthesizer. When the doubler is enabled, both the
rising and falling edges of REFIN become active edges at the
PFD input.
When the reference doubler is enabled, for optimum phase
noise performance, it is recommended to only use charge pump
current settings of 0b0000 to 0b0111, that is, 0.28 mA to 2.24 mA
in Register 12. In this case, the best practice is to design the loop
filter for a charge pump current of 1.12 mA or 1.4 mA and then
use the programmable charge pump current to adjust the
frequency response.
The maximum allowable REFIN frequency when the doubler is
enabled is 50 MHz.
5-Bit R Divider
The 5-bit R counter allows the input reference frequency (REFIN) to
be divided down to produce the reference clock to the VCO
calibration block. Division ratios from 1 to 31 are allowed.
Rev. A | Page 23 of 39
ADF5902
Data Sheet
CONTROL
BITS
FREQENCY CAL DIVIDER
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FC9
FC8
FC7
FC6
DB1
DB0
FC4 FC3 FC2 FC1 FC0 C5(0) C4(1) C3(0) C2(0) C1(0)
FC5
FREQUENCY CAL
DIVIDER
FC9
FC8
...
FC4
FC3
FC2
FC1
FC0
0
0
...
0
0
0
0
0
0
0
0
...
0
0
0
0
1
1
0
0
...
0
0
0
1
0
2
.
.
...
.
.
.
.
.
...
.
.
...
.
.
.
.
.
...
1
1
...
1
1
1
0
1
1021
1
1
...
1
1
1
1
0
1023
1
1
...
1
1
1
1
1
1024
16746-027
0
DB2
Figure 32. Register 8 (R8)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
DB2
DB1
DB0
C5(0) C4(1) C3(0) C2(0) C1(1)
16746-028
CONTROL
BITS
RESERVED
Figure 33. Register 9 (R9 0x2A20B929)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
DB2
DB1
DB0
C5(0) C4(1) C3(0) C2(0) C1(1)
16746-131
CONTROL
BITS
RESERVED
Figure 34. Register 9 (R9 0x2800B929)
REGISTER 8
REGISTER 9
Control Bits
The bits in Register 9 are reserved and must be programmed as
shown in Figure 32 using a hexadecimal word of 0x2A20B929,
prior to the VCO calibration.
With Bits[C5:C1] set to 01000, Register R8 is programmed.
Figure 32 shows the input data format for programming this
register.
The bits in Register 9 must be programmed as described in
Figure 32, using a hexadecimal word of 0x2800B929 for normal
operation.
Reserved
Bits[DB31:DB15] are reserved and must be set as shown in
Figure 32.
See the Applications Information section for more information.
Frequency Calibration Divider
Bits[DB14:DB5] set a divider for the VCO frequency calibration
clock. Load the divider such that the PFD frequency (fPFD)/
frequency calibration divider is less than or equal to 100 kHz
(see Figure 32).
Rev. A | Page 24 of 39
Data Sheet
ADF5902
CONTROL
BITS
0
0
1
1
1
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
1
0
CNTR
RESET
0
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB2
DB1
DB0
16746-029
RESERVED
C5(0) C4(1) C3(0) C2(1) C1(0)
RESERVED
SING FULL
TRI
SD RESET
RESERVED
Figure 35. Register 10 (R10 0x1D32A64A)
RAMP
MODE
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDR
0
SFT RM1 RM0
DB2
DB1
DB0
CR C5(0) C4(1) C3(0) C2(1) C1(1)
0
CR
CNTR RESET
0
DISABLED
1
ENABLED
SDR SD RESET
0
ENABLED
1
DISABLED
SFT SING FULL TRI
0
DISABLED
ENABLED
RM1 RM0
RAMP MODE
0
0
CONTINUOUS SAWTOOTH
0
1
SINGLE SAWTOOTH BURST
1
0
CONTINUOUS TRIANGULAR
1
1
SINGLE RAMP BURST
16746-030
1
Figure 36. Register 11 (R11)
REGISTER 10
Single Full Triangle
The bits in Register 10 are reserved and must be programmed
as shown in Figure 35 using a hexadecimal word of 0x1D32A64A.
When Bit DB9 is set to 1, the single full triangle function is
enabled. When Bit DB9 is set to 0, this function is disabled. To
use the single full triangle function, ramp mode (Register 11,
Bits DB[8:7]) must be set to 0b11, single sawtooth burst. For
more information, see the Ramp and Modulation section.
REGISTER 11
Control Bits
With Bits[C5:C1] set to 01011, Register R11 is programmed.
Figure 36 shows the input data format for programming this
register.
Reserved
Bits[DB31:DB12], Bit DB10, and Bit DB6 are reserved and must
be set as shown in Figure 36.
SD Reset
For most applications, set Bit DB11 to 0. When this bit is set to 0,
the Σ-Δ (SD) modulator is reset on each write to Register R5. If
it is not required that the SD modulator be reset on each write to
Register R5, set this bit to 1.
Ramp Mode
Bits[DB8:DB7] determine the type of generated waveform (see
Figure 36). For more information, see the Ramp and
Modulation section.
Counter Reset
Bit DB5 provides a counter reset bit for the counters. Setting
this bit to 1 performs a counter reset of the device counters.
Setting this bit to 0 returns the device to normal operation.
Bit DB5 is shown as CNTR RESET in Figure 36.
Rev. A | Page 25 of 39
DBR1
RESERVED
CHARGE PUMP
CURRENT
CP TRISTATE
DBR1
Data Sheet
RESERVED
ADF5902
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
1
CC3
0
CC2
CC1
CC0
1
CTRI
0
0
CTRI
CP
TRISTATE
0
1
DISABLED
ENABLED
0
0
0
0
0
0
0
0
DB2
DB1
DB0
C5(0) C4(1) C3(1) C2(0) C1(0)
ICP (mA)
CC2
CC1
CC0
0
0
0
0
0.28
5.1kΩ
0
0
0
1
0.56
0
0
1
0
0.84
0
0
1
1
1.12
0
1
0
0
1.40
0
1
0
1
1.68
0
1
1
0
1.96
0
1
1
1
2.24
1
0
0
0
2.52
1
0
0
1
2.80
1
0
1
0
3.08
1
0
1
1
3.36
1
1
0
0
3.64
1
1
0
1
3.92
1
1
1
0
4.20
1
1
1
1
4.48
1DBR
= DOUBLE-BUFFERED REGISTER.
16746-135
CC3
Figure 37. Register 12 (R12)
REGISTER 12
Charge Pump Current Setting
Control Bits
Bits[DB20:DB17] set the charge pump current (see Figure 37). Set
these bits to the charge pump current that the loop filter is
designed with. The best practice is to design the loop filter for a
charge pump current of 2.24 mA or 2.52 mA and then use the
programmable charge pump current to adjust the frequency
response. See the Reference Doubler section for information on
setting the charge pump current when the doubler is enabled.
With Bits[C5:C1] set to 01100, Register R12 is programmed.
Figure 37 shows the input data format for programming this
register.
Reserved
Bits[DB31:DB21] and Bit DB16 are reserved and must be set as
shown in Figure 37.
Charge Pump Tristate
When Bit DB15 is set to 1, the charge pump is placed in tristate
mode. For normal charge pump operation, set this bit to 0.
Rev. A | Page 26 of 39
CLK DIV
SEL
RESERVED
CLK DIV
MODE
ADF5902
LE SEL
Data Sheet
CLOCK DIVIDER 2
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
LES
0
0
0
DB2
DB1
DB0
LES CDM1 CDM0 C2D11 C2D10 C2D9 C2D8 C2D7 C2D6 C2D5 C2D4 C2D3 C2D2 C2D1 C2D0 CDS1 CDS0 C5(0) C4(1) C3(1) C2(0) C1(1)
LE SEL
0
LE FROM PIN
1
LE SYNC WITH REFIN
CDM1 CDM0
0
0
1
1
0
1
0
1
CLOCK DIVIDER MODE
CLOCK DIVIDER OFF
RESERVED
CDS1
CDS0
0
0
CLK DIV SEL
LOAD CLK DIV 0
0
1
LOAD CLK DIV 1
1
0
LOAD CLK DIV 2
1
1
LOAD CLK DIV 3
FREQ MEASUREMENT
RAMP DIVIDER
C2D11 C2D10
C2D1 C2D0
CLOCK DIVIDER 2 (CLK 2)
0
0
0
0
.
.
.
0
0
0
0
.
.
.
...
...
...
...
...
...
...
0
0
1
1
.
.
.
0
1
0
1
.
.
.
0
1
2
3
.
.
.
1
1
1
1
1
1
1
1
...
...
...
...
0
0
1
1
0
1
0
1
4092
4093
4094
4095
16746-136
0
Figure 38. Register 13 (R13)
REGISTER 13
Clock Divider Mode
Control Bits
Bits[DB20:DB19] are used to enable ramp divider mode. When
using any of the ramp modes, set Bits[CDM1:CDM0] to 11.
Otherwise, set these bits to 0b00.
With Bits[C5:C1] set to 01101, Register R13 is programmed.
Figure 38 shows the input data format for programming this
register.
12-Bit Clock Divider (CLK2) Value
Bits[DB18:DB7] program the clock divider (CLK2) timer when
the device operates in ramp mode (see the Ramp and
Modulation section).
Reserved
Bits[DB31:DB22] are reserved and must be set as shown in
Figure 38.
Clock Divider Select
LE Select
In some applications, it is necessary to synchronize the LE pin
with the reference signal. To perform this synchronization,
Bit DB21 must be set to 1. Synchronization is performed
internally on the device.
Bits[DB6:DB5] select the segment of the ramp CLK2 is used (see
Figure 38). For more information, see the Ramp and Modulation
section. Bits[DB6:DB5] are shown as CLK DIV SEL in Figure 38.
Rev. A | Page 27 of 39
Data Sheet
TX RAMP CLK
Tx_DATA INV
ADF5902
DEVIATION
SEL
RESERVED
DEVIATION OFFSET
CONTROL
BITS
DEVIATION WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
TDI
TRC
0
0
0
DS1
DS0
DO3
DO2
DO1
DO0 DW15 DW14 DW13 DW12 DW11 DW10 DW9
DW8 DW7 DW6
DB2
DB1
DB0
DW5 DW4 DW3 DW2 DW1 DW0 C5(0) C4(1) C3(1) C2(1) C1(0)
TDI Tx_DATA INV
DISABLED
1
ENABLED
DW15 DW14
TRC
TX RAMP CLK
0
1
CLK DIV
Tx_DATA PIN
DO3 DO3 DO1 DO0
...
DW1 DW0
DEVIATION WORD
0
1
...
1
1
32,767
DEV OFFSET
.
.
...
.
.
.
0
0
0
0
0
0
0
...
1
1
3
0
0
0
1
1
0
0
...
1
0
2
0
0
1
0
2
0
0
...
0
1
1
.
.
.
.
.
0
0
...
0
0
0
.
.
.
.
.
1
1
...
1
1
–1
0
1
1
1
7
1
1
...
1
0
1
0
0
0
8
0
0
1
9
1
.
0
...
...
...
0
.
0
1
.
0
–2
–3
1
1
.
1
DS1
DS0
0
0
LOAD DEVIATION 0
0
1
LOAD DEVIATION 1
1
0
LOAD DEVIATION 2
1
1
LOAD DEVIATION 3
.
–32,768
DEVIATION SEL
16746-137
0
Figure 39. Register 14 (R14)
REGISTER 14
TX_DATA Ramp Clock
Control Bits
When Bit DB30 is set to 0, the clock divider clock is used to
clock the ramp. When Bit DB30 is set to 1, the TX_DATA pin
is used to clock the ramp.
With Bits[C5:C1] set to 01110, Register R14 is programmed.
Figure 39 shows the input data format for programming this
register.
Reserved
Deviation Select
Bits[DB26:DB25] select the deviation word to be loaded (see
Figure 39).
Bits[DB29:DB27] are reserved and must be set as shown in
Figure 39.
4-Bit Deviation Offset Word
TX_DATA Invert
When Bit DB31 is set to 0, events triggered by TX_DATA occur
on the rising edge of the TX_DATA pulse. When Bit DB31 is set
to 1, events triggered by TX_DATA occur on the falling edge of
the TX_DATA pulse.
Bits DB[24:21] determine the deviation offset word. The
deviation offset word affects the deviation resolution (see the
Ramp and Modulation section).
16-Bit Deviation Word
Bits[DB20:DB5] determine the signed deviation word in twos
complement format. The deviation word defines the deviation
step (see the Ramp and Modulation section).
Rev. A | Page 28 of 39
Data Sheet
ADF5902
CONTROL
BITS
STEP WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
SS1
SS0 SW19 SW18 SW17 SW16 SW15 SW14 SW13 SW12 SW11 SW10 SW9
0
0
SS1
SS0
0
0
LOAD STEP 0
0
1
LOAD STEP 1
1
0
LOAD STEP 2
1
1
LOAD STEP 3
STEP SEL
...
SW19 SW18
SW8 SW7
SW6
DB2
DB1
DB0
SW5 SW4 SW3 SW2 SW1 SW0 C5(0) C4(1) C3(1) C2(1) C1(1)
STEP WORD
SW1
SW0
0
0
...
0
0
0
0
0
...
0
1
1
0
0
...
1
0
2
0
0
...
1
1
3
.
.
...
.
.
.
.
.
...
.
.
.
.
.
...
.
.
.
1
1
...
0
0
1,048,572
1
1
...
0
1
1,048,573
1
1
...
1
0
1,048,574
1
1
...
1
1
1,048,575
16746-138
STEP
SEL
RESERVED
Figure 40. Register 15 (R15)
REGISTER 15
Step Select
Control Bits
Bits[DB26:DB25] select the step word to be loaded (see Figure 40).
With Bits[C5:C1] set to 01111, Register R15 is programmed.
Figure 40 shows the input data format for programming this
register.
20-Bit Step Word
Reserved
Bits[DB22:DB3] determine the step word. The step word is the
number of steps in the ramp (see the Ramp and Modulation
section).
Bits[DB31:DB27] are reserved and must be set as shown in
Figure 40.
Rev. A | Page 29 of 39
RAMP DEL
DEL SEL
Tx_DATA
TRIGGER
RESERVED
RESERVED
Data Sheet
RESERVED
ADF5902
CONTROL
BITS
DELAY START WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
1
DSL1 DSL0
TR1
0
0
TR1
0
0
RD
DS11 DS10 DS9
DS8
DISABLED
1
ENABLED
0
0
LOAD DELAY 0
0
1
LOAD DELAY 1
1
0
LOAD DELAY 2
1
1
LOAD DELAY 3
RD
RAMP DEL
0
DISABLED
1
ENABLED
DS5
DB0
DS4 DS3 DS2 DS1 DS0 C5(1) C4(0) C3(0) C2(0) C1(0)
DS10
...
0
0
...
0
0
0
0
0
...
0
1
1
0
0
...
1
0
2
0
0
...
1
1
3
.
.
...
.
.
.
.
.
...
.
.
.
.
.
...
.
.
.
1
1
...
0
0
4092
1
1
...
0
1
4093
1
1
...
1
0
4094
1
1
...
1
1
4095
DELAY SELECT
DSL1 DSL0
DS6
DS11
T X DATA TRIGGER
0
DS7
DB1
DS1
DS0
DELAY START WORD
16746-139
0
DB2
Figure 41. Register 16 (R16)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DB2
DB1
DB0
C5(1) C4(0) C3(0) C2(0) C1(1)
16746-140
CONTROL
BITS
RESERVED
Figure 42. Register 17 (R17)
REGISTER 16
When Bit DB20 is set to 0, this function is disabled.
Control Bits
When activating continuous triangular or continuous sawtooth
ramps, a pulse applied to the TX_DATA pin is required after
Bit DB29 of Register 5 is toggled high. To stop the continuous
triangular or sawtooth ramps, a TX_DATA pulse is required
after Bit DB29 of Register 5 is toggled low.
With Bits[C5:C1] set to 10000, Register R16 is programmed.
Figure 41 shows the input data format for programming this
register.
Reserved
Bits[DB31:DB25], Bits[DB22:DB21], and Bits[DB18:DB17] are
reserved and must be set as shown in Figure 41.
When Bit DB20 is set to 0, this function is disabled.
Ramp Delay
When Bit DB19 is set to 1, the delay between ramps function is
enabled. When Bit DB19 is set to 0, this function is disabled.
Delay Select
Bits[DB24:DB23] select the delay word to be loaded.
12-Bit Delay Word
TX_DATA Trigger
Bits[DB16:DB5] determine the delay word. The delay word
determines the duration of the ramp start delay.
When Bit DB20 is set to 1, a logic high on the TX_DATA pin
activates the ramp in conjunction with Bit DB29 of Register 5.
Synchronize the active edge of the pulse applied to the TX_
DATA pin to the rising edge of the REFIN reference input.
REGISTER 17
The pulse duration applied to the TX_DATA pin must be a
minimum width of 4 × 1/fPFD, where fPFD is the phase frequency
detector (PFD) frequency.
The bits in Register 17 are reserved and must be programmed
as described in Figure 42 using a hexadecimal word of
0x00000011.
Rev. A | Page 30 of 39
Data Sheet
ADF5902
APPLICATIONS INFORMATION
INITIALIZATION SEQUENCE
After powering up the device, administer the programming
sequence shown in Table 7.
Table 7. Initialization Sequence
Step
Register
1
R7
2
R11
3
R11
4
R13
5
R10
6
R9
7
R8
8
R0
Delay of 10 μs
9
R7
10
R6
11
R5
12
R4
13
R3
14
R2
15
R1
16
R0
Delay of 1200 μs
17
R0
18
R0
Delay of 500 μs
19
R0
20
R0
Delay of 500 μs
21
R17
22
R16
23
R15
24
R15
25
R15
26
R15
27
R14
28
R14
29
30
R14
R14
0x052038EE
0x73C720E
31
32
33
34
35
36
37
38
39
40
41
Delay of 100 μs
42
R13
R13
R13
R13
R12
R9
R7
R6
R5
R4
R3
R11
This sequence locks the VCO to 24.025 GHz with a 100 MHz
reference. The ramp-up rate is 200 MHz at 144 μs. The rampdown rate is 200 MHz at 9 μs.
Hexadecimal Code
0x02000007
0x0000002B
0x0000000B
0x0018000D
0x1D32A64A
0x2A20B929
0x40003E88
0x800FE520
Description
Master reset
Reset the counters
Enable counters
Enable ramp divider
Reserved
VCO calibration setup
Set the VCO frequency calibration divider clock to 100 kHz
Power up the device and LO
0x01800827
0x00000006
0x01E38005
0x00000004
0x01897803
0x00020642
0xFFF7FFE1
0x800FE720
PFD = 50 MHz, CLK1 = 2048
Set the LSB FRAC = 0
N = 241.175
Set the ATEST pin to high impedance
Sets the I/O level to 3.3 V, CAL_BUSY to MUXOUT
Set ADC clock to 1 MHz
Set the transmitter amplitude level
Start the VCO frequency calibration
0x800FE560
0x800FED60
Turn Tx1 on, Tx2 off, and LO on
Tx1 amplitude calibration
0x800FE5A0
0x800FF5A0
Turn Tx1 off, Tx2 on, and LO on
Tx2 amplitude calibration
0x00000011
0x00000010
0x0000120F
0x0200012F
0x0400120F
0x0600012F
0x012038EE
0x033C720E
0x0018050D
0x0018052D
0x0018054D
0x0018056D
0x004F000C
0x2800B929
0x0100A027
0x00000006
0x00F04005
0x00002004
0x0189F803
Reserved
Ramp delay register
Load step register with STEP_SEL = 0, step word is 144
Load step register with STEP_SEL = 1, step word is 9
Load step register with STEP_SEL = 2, step word is 144
Load step register with STEP_SEL = 3, step word is 9
Load deviation register with DEV_SEL = 0, DEV = 455, DEV offset = 9
Load deviation register with DEV_SEL = 1, dev word= −1820, DEV
offset = 9
Load deviation register with DEV_SEL = 2, dev word = 455, dev offset = 9
Load deviation register with DEV_SEL = 3, dev word = −1820 dev
offset = 9
Load the clock register with CLK DIV SEL = 0, CLK2_0 = 10
Load the clock register with CLK DIV SEL = 1, CLK2_1 = 10
Load the clock register with CLK DIV SEL = 2, CLK2_2 = 10
Load the clock register with CLK DIV SEL = 3, CLK2_3 = 10
Charge pump current = 2.24 mA
Normal Operation
PFD = 100 MHz, CLK1 = 10
Set the LSB FRAC = 0
INT =120, MSB FRAC = 512; lock to 24.025 GHz
Ramp down to MUXOUT
I/O voltage level to 3.3 V
0x0000010B
Select ramp mode
Rev. A | Page 31 of 39
ADF5902
Data Sheet
RECALIBRATION SEQUENCE
The ADF5902 can be recalibrated after the initialization sequence
is complete and the device is powered up. The recalibration
sequence must be run for every 10°C temperature change. The
temperature can be monitored using the temperature sensor
(see the Temperature Sensor section).
Table 8. Recalibration Sequence
Step Number from
Initialization Sequence
6
9
10
11
12
13
14
15
Delay of 1200 μs
17
18
Delay of 500 μs
19
20
Delay of 500 μs
36
37
38
39
40
41
Delay of 100 μs
42
Register
R0
R9
R7
R6
R5
R4
R3
R2
R1
R0
Hexadecimal Code
0x800FE500
0x2A20B929
0x01800827
0x00000006
0x01E38005
0x00000004
0x01897803
0x00020642
0xFFF7FFE1
0x800FE700
Description
Turn Tx1 off, Tx2 off and LO off
Reserved
PFD = 50 MHz, CLK1 = 2048
Set the LSB FRAC = 0
N = 241.175
Set the ATEST pin to high impedance
I/O level to 3.3 V, CAL_BUSY to MUXOUT
Set ADC clock to 1 MHz
Set the transmitter amplitude level
Start the VCO frequency calibration
R0
R0
0x800FE560
0x800FED60
Turn Tx1 on, Tx2 off, and LO on
Tx1 amplitude calibration
R0
R0
0x800FE5A0
0x800FF5A0
Turn Tx1 off, Tx2 on, and LO on
Tx2 amplitude calibration
R9
R7
R6
R5
0x2800B929
0x0100A027
0x00000006
0x00F04005
R4
R3
0x00002004
0x0189F803
Reserved
PFD set to 100 MHz, CLK_DIV1 = 10
Set the LSB FRAC = 0
Set INT word to 120, set MSB FRAC = 512; lock to
24.025 GHz
Ramp down to MUXOUT
I/O voltage level to 3.3 V
R11
0x0000010B
Select ramp mode
Rev. A | Page 32 of 39
Data Sheet
ADF5902
TEMPERATURE SENSOR
RF SYNTHESIS: A WORKED EXAMPLE
The ADF5902 has an on-chip temperature sensor that can be
accessed on the ATEST pin or as a digital word on DOUT
following an ADC conversion. The temperature sensor operates
over the full operating temperature range of −40°C to +105°C.
The accuracy can be improved by performing a one-point
calibration at room temperature and storing the result in
memory.
The following equation governs how to program the ADF5902:
With the temperature sensor on the analog test bus and test bus
connected to the ATEST pin (Register 4 set to 0x0000A064), the
ATEST voltage can be converted to temperature with the
following equation:
Temperatur e ( C)
V
ATEST
VOFF
(3)
VGAIN
RFOUT = (INT + (FRAC/225)) × fREF × 2
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
fREF = REFIN × ((1 + D)/(R × (1 + T)))
where:
REFIN is the reference frequency input.
D is the reference doubler bit, DB10 in Register R7 (0 or 1).
R is the reference division factor.
T is the reference divide by 2 bit, DB11 in Register R7 (0 or 1).
From Equation 6,
fREF = (100 MHz × (1 + 0)/(1 × (1 + 1)) = 50 MHz
The temperature sensor result can be converted to a digital
word with the ADC and readback on DOUT with the following
sequence:
From Equation 5,
1.
Calculating the N and FRAC values,
3.
4.
5.
6.
Write 0x00012064 to Register R4 to connect the analog test
bus to the ADC and the temperature sensor to the analog
test bus.
Write 0x0002A802 to Register R2 to start the ADC
conversion.
Write 0x0189FAC3 to Register R3 to set the ADC output
data to DOUT.
Read back DOUT.
Write 0x00002064 to Register R4 to reset Register R4 to the
initial value.
Write 0x00020642 to Register R2 to reset Register R2 to the
initial value.
Convert the DOUT word to temperature with the following
equation:
Temperatur e ( C)
ADC V V
LSB
(6)
For example, in a system where a 24.125 GHz RF frequency
output (RFOUT) is required and a 100 MHz reference frequency
input (REFIN) is available, fREF is set to 50 MHz.
where:
VATEST is the voltage on the ATEST pin.
VOFF = 0.699 V, the offset voltage.
VGAIN = 6.4 × 10−3, the voltage gain.
2.
(5)
OFF
VGAIN
24.125 GHz = 50 MHz × (N + FRAC/225) × 2
N = int(RFOUT/(fREF × 2)) = 241
FRAC = FMSB × 213 + FLSB
FMSB = int(((RFOUT/(fREF × 2)) − N) × 212) = 1024
FLSB = int(((((RFOUT/(fREF × 2)) − N) × 212) − FMSB) × 213) = 0
where:
FMSB is the 12-bit MSB FRAC value in Register R5.
FLSB is the 13-bit LSB FRAC value in Register R6.
int() makes an integer of the argument in parentheses.
REFERENCE DOUBLER
The on-chip reference doubler allows the input reference signal to
be doubled. This doubling is useful for increasing the PFD comparison frequency. Doubling the PFD frequency typically improves
the noise performance of the system by 3 dB.
(4)
where:
ADC is the ADC code read back on DOUT.
VLSB = 7.33 mV, the ADC LSB voltage.
VOFF = 0.699 V, the offset voltage.
VGAIN = 6.4 × 10−3, the voltage gain.
Rev. A | Page 33 of 39
ADF5902
Data Sheet
9.
Frequency Counter Value Delta = (216 − Frequency 1) +
Frequency 2.
16746-142
TIME
Figure 45. Single Sawtooth Burst
Where Frequency 2 > Frequency 1,
TIME
Figure 46. Continuous Sawtooth Ramp
Frequency Counter Value Delta = Frequency 2 − Frequency 1.
FREQUENCY
10. Calculate the output frequency using the following formula:
Output Frequency = (Frequency Counter Value Delta/
CLKDIV) × fPFD × NDIV × 2
where:
CLKDIV = ((CLK2 × 212) + CLK1).
fPFD = fREF/RDIV.
NDIV = INT value + (FRAC value/(225)).
TIME
Figure 47. Continuous Triangular Ramp
WAVEFORM DEVIATIONS AND TIMING
11. Set Register R13 and Register R7 back to the original
settings and enable the ramp function in Register R5 if
required.
TIMER
The ADF5902 is capable of generating five types of waveforms
in the frequency domain: single ramp burst, single triangular
burst, single sawtooth burst, continuous sawtooth ramp, and
continuous triangular ramp. Figure 43 through Figure 47 show
the types of waveforms available.
fDEV
FREQUENCY
WAVEFORM GENERATION
TIME
Figure 48. Waveform Timing
FREQUENCY
The key parameters that define a ramp are
16746-141
TIME
16746-143
7.
8.
16716-144
4.
5.
6.
16746-145
3.
TIME
Figure 44. Single Triangular Burst
Figure 43. Single Ramp Burst
Rev. A | Page 34 of 39
Frequency deviation
Time per step
Number of steps
16746-146
2.
In Register R3, set the readback control bits
(Bits[DB10:DB5]) to 26.
Read back the frequency counter value on DOUT and
record this value as Frequency 1 (see Figure 3).
In Register R7, set the CLK1 bits (Bits[DB23:DB12]) to
1808.
In Register R13, set the CLK2 bits (Bits[DB18:DB7]) to 10.
In Register R5, set the ramp on bit (Bit DB29) to 0.
In Register R13, Set the clock divider mode bits
(Bits[DB20:DB19]) to 2.
Allow a minimum delay of 428 μs (CLKDIV/fPFD (sec)).
In Register R3, set the readback control bits
(Bits[DB10:DB5]) to 26.
Read back the frequency counter value on DOUT and
record this value as Frequency 2.
Where Frequency 1 > Frequency 2,
FREQUENCY
1.
FREQUENCY
Use the following procedure to measure the output locked
frequency of the ADF5902:
FREQUENC
FREQUENCY MEASUREMENT PROCEDURE
Data Sheet
ADF5902
Frequency Deviation
The frequency deviation for each frequency hop is set by
fDEV = (fPFD/225) × (DEV × 2DEV_OFFSET)
(7)
where:
fPFD is the PFD frequency.
DEV is a 16-bit word (Bits[DB20:DB5] in Register R14).
DEV_OFFSET is a 4-bit word (Bits[DB24:DB21] in Register R14).
Time per step
CLK DIV SEL (Register R13, Bits[DB6:DB5]).
DEV SEL (Register R14, Bits[DB26:DB25]).
Step SEL (Register R15, Bits[DB26:DB25]).
Typically, each register must be written multiple times, one time
for each slope.
The time between each frequency hop is set by
Timer = CLK1 × CLK2 × (1/fPFD)
There are numerous ramp shapes available (see the Waveform
Generation section). Depending on the chosen shape, some or
all of the ramp slopes must be programmed. Figure 49 shows
what must be programmed for each shape. The slope being
programmed is controlled by
(8)
where:
CLK1 and CLK2 are the 12-bit clock values (12-bit CLK1 divider in
Register R7 and 12-bit CLK2 divider in Register R13).
Bits[DB20:DB19] in Register R13 must be set to 11 for ramp
divider.
fPFD is the PFD frequency.
Either CLK1 or CLK2 must be greater than 1, that is, CLK1 =
CLK2 = 1 is not allowed.
The frequency deviation for each step of a slope is set by
fDEV = (fPFD/225) × (DEV × 2DEV_OFFSET)
where:
fDEV is the frequency deviation of a step.
fPFD is the PFD frequency.
DEV is the deviation value (Register R14, Bits[DB20:DB5]).
DEV_OFFSET is the deviation offset (Register R14,
Bits[DB24:DB21]).
The time for each step of a slope is set by
Number of Steps
A 20-bit step value (Bits[DB24:DB5] in Register R15) defines
the number of frequency hops that take place. The INT value
cannot be incremented by more than 28 = 256 from its starting
value.
RAMP AND MODULATION
Timer = CLK1 × CLK2 × (1/fPFD)
where:
Timer is the time per step.
CLK1 is the CLK1 value (Register R7, Bits[23:12]).
CLK2 is the CLK2 value (Register R13, Bits[18:7]).
CLK1 is common to all slopes.
All ramps are generated according to the scheme shown in
Figure 49. The total ramp is separated into four sections. Each
section consists of a delay section and a slope section. Each
slope is made up of one or more steps. Each step has a
programmed frequency deviation and step time.
The number of steps per slope is programmed in Register R15,
Bits[DB24:DB5].
When programming the registers for a ramp, write the registers
in descending order. Then write to Register R5 to enable the
ramp (Register R5, Bit DB29 = 1) must be last.
Rev. A | Page 35 of 39
FREQUENCY
ADF5902
Data Sheet
O
SL
PE
0
DELAY 1
DELAY 0
SL
O
PE
O
SL
1
PE
2
DELAY 3
SL
O
PE
DELAY 2
3
DELAY 0
TIME
SLOPE 3
STEP SELECT (REG 15, BITS[DB26:DB25]) = 0b11
STEP WORD (REG 15, BITS[DB24:DB5]) = X
DEV SELECT (REG 14, BITS[DB26:DB25]) = 0b11
DEV OFFSET (REG 14, BITS[DB24:DB21]) = X
DEV WORD (REG 14, BITS[DB20:DB5]) = –X (NOTE: NEGATIVE)
DELAY 0
DELAY SELECT (REG 16, BITS[DB24:DB23]) = 0b00
RAMP DELAY (REG 16, BITS[DB19]) = 1
DELAY WORD (REG 16, BITS[DB16:DB5]) = X
CLK DIV MODE (REG 13, BITS[DB20:DB19]) = 0b11
CLK2 DIVIDER (REG 13, BITS[DB18:DB7]) = X
CLK2 DIV SELECT (REG 13, BITS[DB6:DB5]) = 0b11
DELAY 3
DELAY SELECT (REG 16, BITS[DB24:DB23]) = 0b11
RAMP DELAY (REG 16, BITS[DB19]) = 1
DELAY WORD (REG 16, BITS[DB16:DB5]) = X
SLOPE 0
STEP SELECT (REG 15, BITS[DB26:DB25]) = 0b00
STEP WORD (REG 15, BITS[DB24:DB5]) = X
DEV SELECT (REG 14, BITS[DB26:DB25]) = 0b00
DEV OFFSET (REG 14, BITS[DB24:DB21]) = X
DEV WORD (REG 14, BITS[DB20:DB5]) = X
CLK DIV MODE (REG 13, BITS[DB20:DB19]) = 0b11
CLK2 DIVIDER (REG 13, BITS[DB18:DB7]) = X
CLK2 DIV SELECT (REG 13, BITS[DB6:DB5]) = 0b00
DELAY 1
DELAY SELECT (REG 16, BITS[DB24:DB23]) = 0b01
RAMP DELAY (REG 16, BITS[DB19]) = 1
DELAY WORD (REG 16, BITS[DB16:DB5]) = X
SLOPE 2
STEP SELECT (REG 15, BITS[DB26:DB25]) = 0b10
STEP WORD (REG 15, BITS[DB24:DB5]) = X
DELAY 2
DELAY SELECT (REG 16, BITS[DB24:DB23]) = 0b10
RAMP DELAY (REG 16, BITS[DB19]) = 1
DELAY WORD (REG 16, BITS[DB16:DB5]) = X
DEV SELECT (REG 14, BITS[DB22:DB25]) = 0b10
DEV OFFSET (REG 14, BITS[DB24:DB21]) = X
DEV WORD (REG 14, BITS[DB20:DB5]) = X
SLOPE 1
STEP SELECT (REG 15, BITS[DB26:DB25]) = 0b01
STEP WORD (REG 15, BITS[DB24:DB5]) = X
CLK DIV MODE (REG 13, BITS[DB20:DB19]) = 0b11
CLK2 DIVIDER (REG 13, BITS[DB18:DB7]) = X
CLK2 DIV SELECT (REG 13, BITS[DB6:DB5]) = 0b10
DEV SELECT (REG 14, BITS[DB26:DB25]) = 0b01
DEV OFFSET (REG 14, BITS[DB24:DB21]) = X
DEV WORD (REG 14, BITS[DB20:DB5]) = –X (NOTE: NEGATIVE)
CLK DIV MODE (REG 13, BITS[DB20:DB19]) = 0b11
CLK2 DIVIDER (REG 13, BITS[DB18:DB7]) = X
CLK2 DIV SELECT (REG 13, BITS[DB6:DB5]) = 0b01
NOTES
- CONTINUOUS SAWTOOTH RAMP:
- RAMP MODE (REG 11, BITS[DB8:DB7]) MUST BE SET TO 0b00.
- SLOPE 0 AND 2 MUST BE PROGRAMMED (EVEN
IF SLOPE 0 AND SLOPE 2 ARE THE SAME).
- CONTINUOUS TRIANGULAR RAMP:
- RAMP MODE (REG 11, BITS[DB8:DB7]) MUST BE SET TO 0b10.
- SLOPE 0, SLOPE 1, SLOPE 2, AND SLOPE 3 MUST BE PROGRAMMED.
- SINGLE SAWTOOTH RAMP:
- RAMP MODE (REG 11, BITS[DB8:DB7]) MUST BE SET TO 0b01.
- SLOPE 0 MUST BE PROGRAMMED.
- SINGLE RAMP BURST:
- RAMP MODE (R11BITS[DB8:DB7]) MUST BE SET TO 0b11.
- SLOPE 0 MUST BE PROGRAMMED.
- SINGLE TRIANGULAR RAMP:
- RAMP MODE (REG 11, BITS[DB8:DB7]) MUST BE SET TO 0b11.
- SLOPE 0 AND SLOPE 1 MUST BE PROGRAMMED.
- SING FULL TRI (REG 11, BIT[DB9]) = 1.
- WHEN PROGRAMMING SLOPE 1 OR SLOPE 3, DEV WORD
MUST BE NEGATIVE TO DECREASE THE FREQUENCY.
- NEGATIVE VALUES ARE TWOS COMPLEMENT BINARY.
- X = DON’T CARE.
Figure 49. Ramp Sections
Rev. A | Page 36 of 39
16746-147
- ALL DELAYS ARE OPTIONAL.
- DELAY 0 TO DELAY 3 ARE ENABLED BY REG 16, BITS[DB19].
Data Sheet
ADF5902
External Control of Ramp Steps
Figure 50 shows the ramp complete signal on MUXOUT.
The internal ramp clock can be bypassed and each step can be
triggered by a pulse on the TX_DATA pin. This process allows
transparent control of each step. Enable this feature by setting
Bit DB30 in Register R14 to 1.
FREQUENCY
FREQUENCY
Ramp Complete and Ramp-Down Signals to MUXOUT
RFOUT
VOLTAGE
TIME
TX_DATA
To activate this function, set Bits[DB15:DB12] in Register R3
to 1111, and set Bits[DB19:DB5] in Register R4 to 0x00C0.
TIME
16746-150
Figure 50. Ramp Complete Signal on MUXOUT
VOLTAGE
TIME
16746-148
TIME
Figure 52. External Control of Ramp Steps
Figure 51 shows the ramp-down signal on MUXOUT.
FREQUENCY
APPLICATION OF THE ADF5902 IN FMCW RADAR
Figure 53 shows the application of the ADF5902 in a frequency
modulated continuous wave (FMCW) radar system.
In the FMCW radar system, the ADF5902 generates the
sawtooth or triangle ramps necessary for this type of radar to
operate.
TIME
TIME
16746-149
VOLTAGE
The ADF5902 CPOUT pin controls the VTUNE pin on the ADF5902
transmitter MMIC and thus the frequency of the VCO and the
transmitter output signal on TXOUT1 or TXOUT2. The LO signal
from the ADF5902 is fed to the LO input on the ADF5904.
Figure 51. Ramp-Down Signal on MUXOUT
To activate this function, set Bits[DB15:DB12] in Register R3
to 1111, and set Bits[DB19:DB5] in Register R4 to 0x0100.
The ADF5904 downconverts the signal from the four receiver
antennas to baseband with the LO signal from the transmitter
MMIC.
The downconverted baseband signals from the four receiver
channels on the ADF5904 are fed to the ADAR7251 4-channel,
continuous time, Σ-Δ ADC.
A digital signal processor (DSP) follows the ADC to handle the
target information processing.
Rev. A | Page 37 of 39
ADF5902
Data Sheet
LOOP FILTER
CP OUT
VTUNE
ADF5902
TXOUT1
TXOUT2
LOOUT
LO_IN
ADAR7251
Rx BASEBAND
ADF5904
RX3_RF
RX4_RF
Figure 53. FMCW Radar with the ADF5902
Rev. A | Page 38 of 39
16746-031
DSP
RX1_RF
RX2_RF
Data Sheet
ADF5902
OUTLINE DIMENSIONS
0.30
0.25
0.18
1
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
8
17
TOP VIEW
0.80
0.75
0.70
TOP VIEW
PKG-004570
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
32
25
24
0.50
0.40
0.30
16
9
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
10-20-2017-C
PIN 1
INDICATOR
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
Figure 54. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
ORDERING GUIDE
Model1
ADF5902WCCPZ
ADF5902WCCPZ-RL7
EV-ADF5902SD1Z
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Package Option
CP-32-12
CP-32-12
Z = RoHS Compliant Part.
AUTOMOTIVE PRODUCTS
The ADF5902W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2018–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16746-0-1/20(A)
Rev. A | Page 39 of 39
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