High Performance, Narrow-Band Transceiver IC ADF7021-V
FEATURES
High performance, low power, narrow-band transceiver Enhanced performance ADF7021-N with external VCO Frequency bands using external VCO: 80 MHz to 960 MHz Improved adjacent channel power (ACP) and adjacent channel rejection (ACR) compared with the ADF7021-N Programmable IF filter bandwidths: 9 kHz, 13.5 kHz, and 18.5 kHz Modulation schemes: 2FSK, 3FSK, 4FSK, MSK Spectral shaping: Gaussian and raised cosine filtering Data rates: 0.05 kbps to 24 kbps Power supply: 2.3 V to 3.6 V Programmable output power: −16 dBm to +13 dBm in 63 steps Automatic power amplifier (PA) ramp control Receiver sensitivity −125 dBm at 250 bps, 2FSK −122 dBm at 1 kbps, 2FSK Patent pending, on-chip image rejection calibration On-chip fractional-N PLL On-chip, 7-bit ADC and temperature sensor Fully automatic frequency control (AFC) loop Digital received signal strength indication (RSSI) Integrated Tx/Rx switch Leakage current in power-down mode: 0.1 μA
APPLICATIONS
Narrow-band, short-range device (SRD) standards ETSI EN 300 220 500 mW output power capability in 869 MHz g3 subband with external PA High performance receiver rejection, blocking, and adjacent channel power (ACP) FCC Part 90 (meets Emission Mask D requirements) FCC Part 95 ARIB STD-T67 Wireless metering Narrow-band wireless telemetry
FUNCTIONAL BLOCK DIAGRAM
RSET TEMP SENSOR CE CREG[1:4] MUXOUT MUX 7-BIT ADC LDO[1:4] TEST MUX
RLNA
LNA RFIN RFIN IF FILTER RSSI/ LOG AMP
2FSK 3FSK 4FSK DEMODULATOR
CLOCK AND DATA RECOVERY
TxRxCLK Tx/Rx CONTROL TxRxDATA SWD
GAIN AGC CONTROL
SLE SERIAL PORT SDATA SREAD SCLK
ADF7021-V
PA RAMP
AFC CONTROL
RFOUT
÷1/÷2
÷2
DIV P
N/N + 1
Σ-Δ MODULATOR
2FSK 3FSK 4FSK MOD CONTROL
GAUSSIAN/ RAISED COSINE FILTER
BUFFER
3FSK ENCODING CP PFD DIV R OSC CLK DIV
08635-001
L2
CPOUT
OSC1
OSC2
CLKOUT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADF7021-V TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 RF and PLL Specifications........................................................... 4 Transmission Specifications ........................................................ 5 Receiver Specifications ................................................................ 6 Digital Specifications ................................................................... 9 General Specifications ............................................................... 10 Timing Characteristics .............................................................. 10 Timing Diagrams........................................................................ 11 Absolute Maximum Ratings.......................................................... 14 ESD Caution ................................................................................ 14 Pin Configuration and Function Descriptions ........................... 15 Typical Performance Characteristics ........................................... 17 Frequency Synthesizer ................................................................... 21 Reference Input ........................................................................... 21 MUXOUT.................................................................................... 22 Voltage Controlled Oscillator (VCO) ...................................... 23 Choosing a VCO for Best System Performance ..................... 23 Transmitter ...................................................................................... 24 RF Output Stage .......................................................................... 24 Modulation Schemes .................................................................. 24 Spectral Shaping ......................................................................... 26 Modulation and Filtering Options ........................................... 27 Transmit Latency ........................................................................ 27 Test Pattern Generator ............................................................... 27 Receiver Section .............................................................................. 28 RF Front End ............................................................................... 28 IF Filter......................................................................................... 28 RSSI/AGC .................................................................................... 28 Demodulation, Detection, and CDR ....................................... 30 Receiver Setup............................................................................. 32 FSK Demodulator Optimization .............................................. 33 AFC Operation ........................................................................... 34 Automatic Sync Word Detection (SWD) ................................ 35 Applications Information .............................................................. 36 IF Filter Bandwidth Calibration ............................................... 36 LNA/PA Matching ...................................................................... 37 Image Rejection Calibration ..................................................... 38 Packet Structure and Coding .................................................... 39 Programming After Initial Power-Up ..................................... 39 Applications Circuit ................................................................... 42 Serial Interface ................................................................................ 43 Readback Format........................................................................ 43 Interfacing to a Microcontroller/DSP ..................................... 44 Register 0—N Register............................................................... 45 Register 1—Oscillator Register................................................. 46 Register 2—Transmit Modulation Register ............................ 47 Register 3—Transmit/Receive Clock Register ........................ 48 Register 4—Demodulator Setup Register ............................... 49 Register 5—IF Filter Setup Register ......................................... 50 Register 6—IF Fine Calibration Setup Register ..................... 51 Register 7—Readback Setup Register ...................................... 52 Register 8—Power-Down Test Register .................................. 53 Register 9—AGC Register ......................................................... 54 Register 10—AFC Register ....................................................... 55 Register 11—Sync Word Detect Register ................................ 56 Register 12—SWD/Threshold Setup Register ........................ 56 Register 13—3FSK/4FSK Demodulation Register ................. 57 Register 14—Test DAC Register ............................................... 58 Register 15—Test Mode Register ............................................. 59 Outline Dimensions ....................................................................... 60 Ordering Guide .......................................................................... 60
REVISION HISTORY
4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 60
ADF7021-V
GENERAL DESCRIPTION
The ADF7021-V is a high performance, low power, narrow-band RF transceiver based on the ADF7021-N. The architecture of the ADF7021-V transceiver is similar to that of the ADF7021-N except that an external VCO is used by the on-chip RF synthesizer for applications that require improved phase noise performance. The ADF7021-V is designed to operate in both the license-free ISM bands and in the licensed bands from 80 MHz to 960 MHz. To minimize RF feedthrough and spurious emissions, the external VCO operates at 2× or 4× the desired RF frequency; the ADF7021-V supports a maximum VCO frequency operation of 1920 MHz. The 4× VCO operation is programmable by enabling an additional on-chip divide-by-2 outside the RF synthesizer loop and offers improved phase noise performance. As with the ADF7021-N receiver, the IF filter bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz are supported, making the ADF7021-V ideally suited to worldwide narrow-band telemetry applications. The part has both Gaussian and raised cosine transmit data filtering options to improve spectral efficiency for narrow-band applications. It is suitable for circuit applications targeted at the following: • • • • • European ETSI EN 300 220 North American FCC Part 15, Part 90, and Part 95 Japanese ARIB STD-T67 Korean short-range device regulations Chinese short-range device regulations The transmit section contains a low noise fractional-N PLL with an output resolution of 10 >10 >25 >25 >10 >20 5 >5 5 < t14 < (¼ × tBIT) >¼ × tBIT Unit ns ns ns ns ns ns ns ns ns ns ns ns μs μs Description SDATA to SCLK setup time SDATA to SCLK hold time SCLK high duration SCLK low duration SCLK to SLE setup time SLE pulse width SCLK to SREAD data valid, readback SREAD hold time after SCLK, readback SCLK to SLE disable time, readback TxRxCLK negative edge to SLE TxRxDATA to TxRxCLK setup time (Tx mode) TxRxCLK to TxRxDATA hold time (Tx mode) TxRxCLK negative edge to SLE SLE positive edge to positive edge of TxRxCLK (Rx mode)
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ADF7021-V
TIMING DIAGRAMS
Serial Interface
t3
SCLK
t4
t1
t2
DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
SDATA
DB31 (MSB)
DB30
t6
SLE
t5
Figure 2. Serial Interface Timing Diagram
t1
SCLK
t2
SDATA REG 7 DB0 (CONTROL BIT C1) SLE
t3
t10
X RV16 RV15 RV2 RV1 X
SREAD
t8
t9
Figure 3. Serial Interface Readback Timing Diagram
2FSK/3FSK Timing
±1 × DATA RATE/32 1/DATA RATE
TxRxCLK
Figure 4. TxRxDATA/TxRxCLK Timing Diagram in Receive Mode
1/DATA RATE TxRxCLK
TxRxDATA
DATA
08635-005
FETCH
SAMPLE
Figure 5. TxRxDATA/TxRxCLK Timing Diagram in Transmit Mode
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08635-004
TxRxDATA
DATA
08635-003
08635-002
ADF7021-V
4FSK Timing
In 4FSK receive mode, MSB/LSB synchronization should be guaranteed by detection of the SWD pin in the receive bit stream.
REGISTER 0 WRITE SWITCH FROM Rx TO Tx
tSYMBOL tBIT t11 t12
t13
SLE
TxRxCLK
TxRxDATA
Rx SYMBOL MSB
Rx SYMBOL LSB
Rx SYMBOL MSB
Rx SYMBOL LSB
Tx SYMBOL MSB
Tx SYMBOL LSB
Tx SYMBOL MSB
Figure 6. Receive-to-Transmit Timing Diagram in 4FSK Mode
REGISTER 0 WRITE SWITCH FROM Tx TO Rx
t15 t14 tBIT
SLE
tSYMBOL
TxRxCLK
TxRxDATA
Tx SYMBOL MSB
Tx SYMBOL LSB
Tx SYMBOL MSB
Tx SYMBOL LSB
Rx SYMBOL MSB
Rx SYMBOL LSB
Figure 7. Transmit-to-Receive Timing Diagram in 4FSK Mode
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08635-007
Tx/Rx MODE
Tx MODE
Rx MODE
08635-006
Tx/Rx MODE
Rx MODE
Tx MODE
ADF7021-V
UART/SPI Mode
UART mode is enabled by setting Register 0, Bit DB28 to 1. SPI mode is enabled by setting Register 0, Bit DB28 to 1 and setting Register 15, Bits[DB19:DB17] to 0x7. The transmit/receive data clock is available on the CLKOUT pin.
tBIT
CLKOUT (TRANSMIT/RECEIVE DATA CLOCK IN SPI MODE. NOT USED IN UART MODE.)
FETCH
SAMPLE
TxRxCLK (TRANSMIT DATA INPUT IN UART/SPI MODE.)
Tx BIT
Tx BIT
Tx BIT
Tx BIT
Tx BIT
TxRxDATA (RECEIVE DATA OUTPUT IN UART/SPI MODE.)
HIGH-Z
Tx/Rx MODE
Tx MODE
Figure 8. Transmit Timing Diagram in UART/SPI Mode
tBIT
CLKOUT (TRANSMIT/RECEIVE DATA CLOCK IN SPI MODE. NOT USED IN UART MODE.) TxRxCLK (TRANSMIT DATA INPUT IN UART/SPI MODE.)
FETCH SAMPLE
HIGH-Z
TxRxDATA (RECEIVE DATA OUTPUT IN UART/SPI MODE.)
Rx BIT
Rx BIT
Rx BIT
Rx BIT
Rx BIT
Tx/Rx MODE
Rx MODE
Figure 9. Receive Timing Diagram in UART/SPI Mode
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08635-009
08635-008
ADF7021-V ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Table 7.
Parameter VDD to GND1 Analog I/O Voltage to GND1 Digital I/O Voltage to GND1 Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature MLF θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature
1
Rating −0.3 V to +5 V −0.3 V to VDDx + 0.3 V −0.3 V to VDDx + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 26°C/W 260°C 40 sec
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of 10 ppm tolerance, but compensation for the frequency error of the crystal is necessary to comply with the absolute frequency error specifications of narrow-band regulations (for example, ARIB STD-T67 and ETSI EN 300 220). The oscillator circuit is enabled by setting Bit DB12 in Register 1 high. It is enabled by default on power-up and is disabled by bringing CE low. Errors in the crystal can be corrected using the automatic frequency control (AFC) feature or by adjusting the fractional-N value (see the N Counter section).
CLKOUT Divider and Buffer
The CLKOUT circuit takes the reference clock signal from the oscillator section, shown in Figure 32, and supplies a divideddown, 50:50 mark/space signal to the CLKOUT pin. The CLKOUT signal is inverted with respect to the reference clock. An even divide from 2 to 30 is available; this divide number is set in Register 1, Bits[DB10:DB7]. On power-up, the CLKOUT defaults to divide-by-8.
VDD CLKOUT ENABLE BIT
OSC1
Figure 33. CLKOUT Stage
OSC1
CP2
OSC2
CP1
08635-030
Figure 32. Crystal Oscillator Circuit on the ADF7021-V
To disable CLKOUT, set the divide number to 0. The output buffer can drive a load of up to 20 pF with a 10% rise time at 4.8 MHz. Faster edges can result in some spurious feedthrough to the output. A series resistor (1 kΩ) can be used to slow the clock edges to reduce these spurs at the CLKOUT frequency.
Two parallel resonant capacitors are required for oscillation at the correct frequency. Their values are dependent on the crystal specification. The resonant capacitors should be selected to ensure that the series value of capacitance added to the PCB track capacitance adds up to the specified load capacitance of the crystal, usually 12 pF to 20 pF. Track capacitance values vary from 2 pF to 5 pF, depending on board layout. When possible, choose capacitors that have a very low temperature coefficient to ensure stable frequency operation over all conditions.
R Counter
The 3-bit R counter divides the reference input frequency by an integer from 1 to 7. The divided-down signal is presented as the reference clock to the phase frequency detector (PFD). The divide ratio is set in Register 1, Bits[DB6:DB4]. Maximizing the PFD frequency reduces the N value. This reduces the noise multiplied at a rate of 20 log(N) to the output and reduces occurrences of spurious components. Register 1 defaults to R = 1 on power-up. PFD (Hz) = XTAL/R
Using a TCXO Reference
A single-ended reference (TCXO, VCXO, or OCXO) can also be used with the ADF7021-V. This is recommended for applications that have absolute frequency accuracy requirements of 10 MHz. To avoid having very small or very large values in the fractional register, choose a suitable reference frequency. In addition to spurious considerations, the selection of a high performance VCO with very low phase noise is essential to minimize the ACP performance of the transmitter and to maximize the ACR and blocking resilience of the receiver.
REF TCXO/XTAL
÷R
PFD/CP ÷N
÷2 MUX ÷2 TO PA
SYNTH FREQUENCY
Figure 37. Voltage Controlled Oscillator (VCO)
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08635-036
ADF7021-V
ADF7021-V TRANSMITTER
RF OUTPUT STAGE
The power amplifier (PA) of the ADF7021-V is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dBm into a 50 Ω load at a maximum frequency of 960 MHz. The PA output current and, consequently, the output power are programmable over a wide range. The PA configuration is shown in Figure 38. The output power is set using Register 2, Bits[DB18:DB13].
REGISTER 2, BITS[DB12:DB11] 2 IDAC 6 REGISTER 2, BITS[DB18:DB13]
1 DATA BITS
2
3
4
...
8
...
16
PA RAMP 0 (NO RAMP) PA RAMP 1 (256 CODES PER BIT) PA RAMP 2 (128 CODES PER BIT) PA RAMP 3 (64 CODES PER BIT) PA RAMP 4 (32 CODES PER BIT) PA RAMP 5 (16 CODES PER BIT) PA RAMP 6 (8 CODES PER BIT) PA RAMP 7 (4 CODES PER BIT)
Figure 39. PA Ramping Settings
RFOUT + REGISTER 2, BIT DB7 REGISTER 0, BIT DB27
08635-037
PA Bias Currents
The PA_BIAS bits (Register 2, Bits[DB12:DB11]) facilitate an adjustment of the PA bias current to further extend the output power control range, if necessary. If this feature is not required, the default value of 9 μA is recommended. If output power greater than 10 dBm is required, a PA bias setting of 11 μA is recommended. The output stage is powered down by resetting Register 2, Bit DB7 to 0.
RFGND FROM VCO
Figure 38. PA Configuration
The PA is equipped with overvoltage protection, which makes it robust in severe mismatch conditions. Depending on the application, users can design a matching network for the PA to exhibit optimum efficiency at the desired radiated output power level for a wide range of antennas, such as loop or monopole antennas. See the LNA/PA Matching section for more information.
MODULATION SCHEMES
The ADF7021-V supports 2FSK, 3FSK, and 4FSK modulation. The implementation of these modulation schemes is shown in Figure 40.
REF PFD/ CHARGE PUMP LOOP FILTER VCO ÷2 TO PA STAGE
PA Ramping
When the PA is switched on or off quickly, its changing input impedance momentarily disturbs the VCO output frequency. This process is called VCO pulling, and it manifests as spectral splatter or spurs in the output spectrum around the desired carrier frequency. Some radio emissions regulations place limits on these PA transient-induced spurs (for example, the ETSI EN 300 220 regulations). By gradually ramping the PA on and off, PA transient spurs are minimized. The ADF7021-V has built-in PA ramping configurability. As Figure 39 illustrates, there are eight ramp rate settings, defined as a certain number of PA setting codes per one data bit period. The PA steps through each of its 64 code levels but at different speeds for each setting. The ramp rate is set by configuring Bits[DB10:DB8] in Register 2. If the PA is enabled/disabled by the PA_ENABLE bit (Register 2, Bit DB7), it ramps up and down. If it is enabled/disabled by the Tx/Rx bit (Register 0, Bit DB27), it ramps up and turns hard off.
÷N FRACTIONAL_N THIRD-ORDER Σ-Δ MODULATOR Tx_FREQUENCY_ DEVIATION 2FSK GAUSSIAN OR RAISED COSINE FILTERING TxRxDATA MUX 3FSK 1 – D 2 PR SHAPING 4FSK BIT SYMBOL MAPPER PRECODER INTEGER_N
Figure 40. Transmit Modulation Implementation
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08635-039
4FSK
08635-038
ADF7021-V
Setting the Transmit Data Rate
In all modulation modes except for oversampled 2FSK mode, an accurate clock is provided on the TxRxCLK pin to latch the data from the microcontroller into the transmit section at the required data rate. The exact frequency of this clock is defined by
Three-Level Frequency Shift Keying (3FSK)
In three-level FSK modulation—3FSK, also known as modified duobinary FSK and as partial response maximum likelihood Class 4 (PRML4) signaling—the binary data (Logic 0 and Logic 1) is mapped onto three distinct frequencies: the carrier frequency (fC), the carrier frequency minus a deviation frequency (fC − fDEV), and the carrier frequency plus the deviation frequency (fC + fDEV). A Logic 0 is mapped to the carrier frequency, whereas a Logic 1 is mapped onto either the fC − fDEV frequency or the fC + fDEV frequency.
0 –1 +1
DATA CLK =
XTAL DEMOD_CLK_DIVIDE × CDR_CLK_DIVIDE ×32
where: XTAL is the crystal or TCXO frequency. DEMOD_CLK_DIVIDE is the divider that sets the demodulator clock rate (Register 3, Bits[DB9:DB6]). CDR_CLK_DIVIDE is the divider that sets the CDR clock rate (Register 3, Bits[DB17:DB10]). See the Register 3—Transmit/Receive Clock Register section for more programming information.
fC – fDEV
fC
fC + fDEV
RF FREQUENCY
Setting the FSK Transmit Deviation Frequency
In all modulation modes, the deviation from the center frequency is set using the Tx_FREQUENCY_DEVIATION bits (Register 2, Bits[DB27:DB19]). The deviation from the center frequency in Hz is as follows: For direct RF output,
f DEV (Hz) = PFD × Tx_FREQUENCY_DEVIATION 2 16 PFD × Tx_FREQUENCY_DEVIATION 216
Figure 41. 3FSK Symbol-to-Frequency Mapping
Compared with 2FSK, this bit-to-frequency mapping results in a reduced transmission bandwidth because some energy is removed from the RF sidebands and transferred to the carrier frequency. At low modulation index, 3FSK improves the transmit spectral efficiency by up to 25% when compared with 2FSK. The bit-to-symbol mapping for 3FSK is implemented using a linear convolutional encoder that also permits Viterbi detection to be used in the receiver. A block diagram of the transmit hardware used to realize this system is shown in Figure 42. The convolutional encoder polynomial used to implement the transmit spectral shaping is P(D) = 1 − D2 where: P is the convolutional encoder polynomial. D is the unit delay operator. A digital precoder with transfer function 1/P(D) implements an inverse modulo-2 operation of the 1 − D2 shaping filter in the transmitter.
Tx DATA 0, 1
PRECODER 1/P(D)
With RF_DIVIDE_BY_2 (Register 1, Bit DB18) enabled, f DEV (Hz) = 0.5 ×
where Tx_FREQUENCY_DEVIATION is a number from 1 to 511 (Register 2, Bits[DB27:DB19]). In 4FSK modulation, the four symbols (00, 01, 11, 10) are transmitted as ±3 × fDEV and ±1 × fDEV.
Binary Frequency Shift Keying (2FSK)
Binary frequency shift keying is implemented by setting the N value for the center frequency and then toggling it with the TxRxDATA line. The deviation from the center frequency is set using the Tx_FREQUENCY_DEVIATION bits (Register 2, Bits[DB27:DB19]). 2FSK is selected by setting the MODULATION_SCHEME bits (Register 2, Bits[DB6:DB4]) to 000. Minimum shift keying (MSK) or Gaussian minimum shift keying (GMSK) is supported by selecting 2FSK modulation and using a modulation index of 0.5. A modulation index of 0.5 is set by configuring Register 2, Bits[DB27:DB19] for an fDEV = 0.25 × transmit data rate.
0, 1
CONVOLUTIONAL ENCODER P(D)
0, +1, –1
Figure 42. 3FSK Encoding
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08635-041
fC + fDEV FSK MOD fC – fDEV CONTROL AND DATA FILTERING
fC
08635-040
TO N DIVIDER
ADF7021-V
The signal mapping of the input binary transmit data to the three-level convolutional output is shown in Table 9. The convolutional encoder restricts the maximum number of sequential +1s or −1s to two and delivers an equal number of +1s and −1s to the FSK modulator, thus ensuring equal spectral energy in both RF sidebands.
Table 9. Three-Level Signal Mapping of the Convolutional Encoder
TxDATA Precoder Output Encoder Output 1 1 +1 0 0 0 1 0 −1 1 1 +1 0 0 0 0 1 0 1 1 +1 0 1 0 0 1 0 1 0 −1
The inner deviation frequencies (+fDEV and −fDEV) are set using the Tx_FREQUENCY_DEVIATION bits (Bits[DB27:DB19] in Register 2). The outer deviation frequencies are automatically set to three times the inner deviation frequency. The transmit clock from Pin TxRxCLK is available after writing to Register 3 in the power-up sequence for receive mode. The MSB of the first symbol should be clocked into the ADF7021-V on the first transmit clock pulse from the ADF7021-V after writing to Register 3. See Figure 6 and Figure 7 for more timing information; see Figure 54 and Figure 55 for the power-up sequences.
Oversampled 2FSK
In oversampled 2FSK, there is no data clock from the TxRxCLK pin. Instead, the transmit data at the TxRxDATA pin is sampled at 32 times the programmed rate. Oversampled 2FSK is the only modulation mode that can be used with the UART mode interface for data transmission (see the Interfacing to a Microcontroller/DSP section for more information).
Another property of this encoding scheme is that the transmitted symbol sequence is dc-free, which facilitates symbol detection and frequency measurement in the receiver. In addition, no code rate loss is associated with this three-level convolutional encoder; that is, the transmitted symbol rate is equal to the data rate presented at the transmit data input. 3FSK is selected by setting the MODULATION_SCHEME bits (Register 2, Bits[DB6:DB4]) to 010. It can also be used with raised cosine filtering to further increase the spectral efficiency of the transmit signal.
SPECTRAL SHAPING
Gaussian or raised cosine filtering can be used to improve transmit spectral efficiency. The ADF7021-V supports Gaussian filtering (bandwidth time [BT] = 0.5) on 2FSK modulation. Raised cosine filtering can be used with 2FSK, 3FSK, or 4FSK modulation. The roll-off factor (alpha) of the raised cosine filter has programmable options of 0.5 and 0.7. Both the Gaussian and raised cosine filters are implemented using linear phase digital filter architectures that deliver precise control over the BT and alpha filter parameters, and guarantee a transmit spectrum that is very stable over temperature and supply variation.
Four-Level Frequency Shift Keying (4FSK)
In 4FSK modulation, two bits per symbol spectral efficiency is realized by mapping consecutive input bit-pairs in the Tx data bit stream to one of four possible symbols (−3, −1, +1, +3). Thus, the transmitted symbol rate is half the input bit rate. These symbols are mapped to equally spaced discrete frequencies centered on the RF carrier at −3fDEV, −1fDEV, +1fDEV, and +3fDEV where fDEV is programmed using the Tx_FREQUENCY_ DEVIATION bits (Bits[DB27:DB19] in Register 2) and is also equal to half the frequency spacing between adjacent symbols. By minimizing the separation between symbol frequencies, 4FSK can have high spectral efficiency. The bit-to-symbol mapping for 4FSK is gray coded and is shown in Figure 43.
Tx DATA 0 0 0 1 1 0 1 1
Gaussian Frequency Shift Keying (GFSK)
Gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the transmit data. The BT product of the Gaussian filter used is 0.5. Gaussian filtering can be used only with 2FSK modulation. GFSK is selected by setting Register 2, Bits[DB6:DB4] to 001.
Raised Cosine Filtering
Raised cosine filtering provides digital prefiltering of the transmit data by using a raised cosine filter with a roll-off factor (alpha) of either 0.5 or 0.7. The alpha is set to 0.5 by default, but the raised cosine filter bandwidth can be increased to provide less aggressive data filtering by using an alpha of 0.7 (set Register 2, Bit DB30 to Logic 1). Raised cosine filtering can be used with 2FSK, 3FSK, and 4FSK modulation. Raised cosine filtering is enabled by setting Register 2, Bits[DB6:DB4] as shown in Table 10.
t
08635-042
f
+3fDEV
SYMBOL FREQUENCIES
+fDEV
–fDEV
–3fDEV
Figure 43. 4FSK Bit-to-Symbol Mapping
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ADF7021-V
MODULATION AND FILTERING OPTIONS
The various modulation and data filtering options for the ADF7021-V are described in Table 10.
Table 10. Modulation and Filtering Options
Modulation Binary FSK 2FSK MSK1 OQPSK with Half Sine Baseband Shaping2 GFSK GMSK3 RC2FSK Oversampled 2FSK Three-Level FSK 3FSK RC3FSK Four-Level FSK 4FSK RC4FSK
1 2
The figures for latency in Table 11 assume that the positive TxRxCLK edge is used to sample data (default). If the TxRxCLK is inverted by setting Register 2, Bits[DB29:DB28], an additional 0.5 bit latency can be added to all values in Table 11.
Table 11. Bit/Symbol Latency in Transmit Mode for Various Modulation Schemes
Modulation 2FSK GFSK RC2FSK, alpha = 0.5 RC2FSK, alpha = 0.7 3FSK RC3FSK, alpha = 0.5 RC3FSK, alpha = 0.7 4FSK RC4FSK, alpha = 0.5 RC4FSK, alpha = 0.7 Latency 1 bit 4 bits 5 bits 4 bits 1 bit 5 bits 4 bits 1 symbol 5 symbols 4 symbols
Data Filtering None None None Gaussian Gaussian Raised cosine None None Raised cosine None Raised cosine
Register 2, Bits[DB6:DB4] 000 000 000 001 001 101 100 010 110 011 111
TEST PATTERN GENERATOR
The ADF7021-V has a number of built-in test pattern generators that can be used to facilitate radio link setup or RF measurement. A full list of the supported test patterns is shown in Table 12. The data rate for these test patterns is the programmed data rate set in Register 3. The PN9 sequence is suitable for test modulation when carrying out adjacent channel power (ACP) or occupied bandwidth measurements.
Table 12. Transmit Test Pattern Generator Options
Test Pattern Normal Transmit carrier only Transmit +fDEV tone only Transmit −fDEV tone only Transmit 1010 pattern Transmit PN9 sequence Transmit SWD pattern repeatedly Register 15, Bits[DB10:DB8] 000 001 010 011 100 101 110
MSK is 2FSK modulation with a modulation index = 0.5. Offset quadrature phase shift keying (OQPSK) with half sine baseband shaping is spectrally equivalent to MSK. 3 GMSK is GFSK with a modulation index = 0.5.
TRANSMIT LATENCY
Transmit latency is the delay time from the sampling of a bit/symbol by the TxRxCLK signal to when that bit/symbol appears at the RF output. The latency without any data filtering is 1 bit. The addition of data filtering adds a further latency as indicated in Table 11. It is important that the ADF7021-V be left in transmit mode after the last data bit is sampled by the data clock to account for this latency. The ADF7021-V should stay in transmit mode for a time equal to the number of latency bit periods for the applied modulation scheme. This ensures that all of the data sampled by the TxRxCLK signal appears at RF.
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ADF7021-V RECEIVER SECTION
RF FRONT END
The ADF7021-V is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from powerline-induced interference problems. Figure 44 shows the structure of the receiver front end. The many programming options allow users to trade off sensitivity, linearity, and current consumption to best suit their application. To achieve a high level of resilience against spurious reception, the low noise amplifier (LNA) features a differential input. Switch SW2 shorts the LNA input when transmit mode is selected (Register 0, Bit DB27 = 0). This feature facilitates the design of a combined LNA/PA matching network, avoiding the need for an external Tx/Rx switch. See the LNA/PA Matching section for details on the design of the matching network.
I (TO FILTER) RFIN Tx/Rx SELECT (REG 0, BIT DB27) RFIN LNA_MODE (REG 9, BIT DB25) LNA_BIAS (REG 9, BITS[DB27:DB26]) LNA_GAIN (REG 9, BITS[DB21:DB20]) LNA/MIXER_ENABLE (REG 8, BIT DB6)
If the AGC loop is disabled, the gain of the IF filter can be set to one of three levels by using the FILTER_GAIN bits (Register 9, Bits[DB23:DB22]). The filter gain is adjusted automatically if the AGC loop is enabled.
IF Filter Bandwidth and Center Frequency Calibration
To compensate for manufacturing tolerances, the IF filter should be calibrated after power-up to ensure that the bandwidth and center frequency are correct. Coarse and fine calibration schemes are provided to offer a choice between fast calibration (coarse calibration) and high filter centering accuracy (fine calibration). Coarse calibration is enabled by setting Register 5, Bit DB4 high. Fine calibration is enabled by setting Register 6, Bit DB4 high. For details on when it is necessary to perform a filter calibration, and in what applications to use either a coarse calibration or fine calibration, see the IF Filter Bandwidth Calibration section.
RSSI/AGC
The RSSI is implemented as a successive compression log amp following the baseband (BB) channel filtering. The log amp achieves ±3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. The offset correction circuit uses the BBOS_CLK_DIVIDE bits (Bits DB5:DB4] in Register 3) and should be set between 1 MHz and 2 MHz. The RSSI level is converted for user readback and for digitally controlled AGC by an 80-level (7-bit) flash ADC. This level can be converted to input power in dBm. By default, the AGC is on when powered up in receive mode.
OFFSET CORRECTION 1 A A A LATCH FSK DEMOD
SW2
LNA
LO
Q (TO FILTER) MIXER_LINEARITY (REG 9, BIT DB28)
Figure 44. RF Front End
The LNA is followed by a quadrature downconversion mixer, which converts the RF signal to the IF frequency of 100 kHz. An important consideration is that the output frequency of the synthesizer must be programmed to a value 100 kHz below the center frequency of the received channel. The LNA has two basic operating modes: high gain/low noise mode and low gain/ low power mode. To switch between these two modes, use the LNA_MODE bit (Register 9, Bit DB25). The mixer is also configurable for either a low current mode or an enhanced linearity mode using the MIXER_LINEARITY bit (Register 9, Bit DB28). Based on the specific sensitivity and linearity requirements of the application, it is recommended that the LNA_MODE bit and the MIXER_LINEARITY bit be adjusted as shown in Table 14. The gain of the LNA is configured by the LNA_GAIN bits (Register 9, Bits[DB21:DB20]) and can be set by the user or by the automatic gain control (AGC) logic.
08635-043
IFWR
IFWR
IFWR
IFWR
CLK RSSI ADC
R
Figure 45. RSSI Block Diagram
RSSI Thresholds
When the RSSI is above AGC_HIGH_THRESHOLD (Register 9, Bits[DB17:DB11]), the gain is reduced. When the RSSI is below AGC_LOW_THRESHOLD (Register 9, Bits[DB10:DB4]), the gain is increased. The thresholds default to 70 (high threshold) and 30 (low threshold) on power-up in receive mode. A delay (set by AGC_CLK_DIVIDE in Register 3, Bits[DB31:DB26]) is programmed to allow for settling of the loop. A value of 33 is recommended to give an AGC update rate of 3 kHz. The user has the option of changing the two threshold values from the defaults of 70 and 30 (Register 9). The default AGC setup values should be adequate for most applications. The threshold values must be more than 30 apart for the AGC to operate correctly.
IF FILTER
IF Filter Settings
Out-of-band interference is rejected by means of a fifth-order Butterworth polyphase IF filter centered on a frequency of 100 kHz. The bandwidth of the IF filter can be programmed to 9 kHz, 13.5 kHz, or 18.5 kHz in Register 4, Bits[DB31:DB30], and should be chosen as a compromise between interference rejection and attenuation of the desired signal.
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ADF7021-V
Offset Correction Clock
In Register 3, the user should set the BBOS_CLK_DIVIDE bits (Bits[DB5:DB4]) to give a baseband offset clock (BBOS CLK) frequency between 1 MHz and 2 MHz. BBOS CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE) where BBOS_CLK_DIVIDE can be set to 4, 8, 16, or 32.
The total AFC settling time depends on the number of AGC gain changes during reception of a packet. A total of five gain changes gives a worst-case AGC settling time of 5 × 333 μs. To allow for AGC settling, the preamble length should be adjusted accordingly.
RSSI Formula (Converting to dBm)
The RSSI formula is Input Power (dBm) = (−130 dBm + (Readback Code + Gain Mode Correction)) × 0.5 where: Readback Code is given by Bit RV7 to Bit RV1 in the readback register (see Figure 57 and the Readback Format section). Gain Mode Correction is given by the values in Table 13. The LNA gain (LG2, LG1) and filter gain (FG2, FG1) values are also obtained from the readback register, as part of an RSSI readback.
Table 13. Gain Mode Correction
LNA Gain (LG2, LG1) H (1, 0) M (0, 1) M (0, 1) M (0, 1) L (0, 0) Filter Gain (FG2, FG1) H (1, 0) H (1, 0) M (0, 1) L (0, 0) L (0, 0) Gain Mode Correction 0 24 38 58 86
AGC Information and Timing
AGC is selected by default and operates by setting the appropriate LNA and filter gain settings for the measured RSSI level. To enter one of the LNA/mixer modes listed in Table 14, the user can disable AGC by writing to Register 9. After each gain change, the AGC loop waits for a programmed time to allow transients to settle. This AGC update rate is set according to AGC Update Rate (Hz) =
SEQ _ CLK _ DIVIDE (Hz) AGC _ CLK _ DIVIDE
where: SEQ_CLK_DIVIDE = 100 kHz (Register 3, Bits[DB25:DB18]). AGC_CLK_DIVIDE is set by Register 3, Bits[DB31:DB26]. A value of 33 is recommended. It is recommended that AGC_CLK_DIVIDE be set to a value of 33, which allows a settling time of 333 μs for each gain change. By using the recommended setting for AGC_CLK_DIVIDE, the total AGC settling time is
AGC Settling Time (sec) = Number of AGC Gain Changes AGC Update Rate (Hz)
An additional factor should be introduced to account for losses in the front-end-matching network/antenna.
Table 14. LNA/Mixer Modes (Register 9 Settings)
LNA_MODE (Bit DB25) 0 0 1 1 1 1 LNA_GAIN (Bits[DB21:DB20]) 30 30 10 10 3 3 MIXER_LINEARITY (Bit DB28) 0 1 0 1 0 1 Sensitivity (2FSK, Data Rate = 4.8 kbps, fDEV = 4 kHz) (dBm) −116.5 −113 −108 −102 −99 −91 Rx Current Consumption (mA) 20.1 20.1 17.9 17.9 17.9 17.9 Input IP3 (dBm) −24 −20 −13.5 −9 −5 −3
Receiver Mode High Sensitivity Mode (Default) Enhanced Linearity, High Gain Medium Gain Enhanced Linearity, Medium Gain Low Gain Enhanced Linearity, Low Gain
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ADF7021-V
DEMODULATION, DETECTION, AND CDR
System Overview
An overview of the demodulation, detection, and clock and data recovery (CDR) of the received signal on the ADF7021-V is shown in Figure 46.
LIMITERS I Q CORRELATOR DEMODULATOR MUX LINEAR DEMODULATOR
The quadrature outputs of the IF filter are first limited and then fed to a digital frequency correlator that performs filtering and frequency discrimination of the 2FSK/3FSK/4FSK spectrum. For 2FSK modulation, data is recovered by comparing the output levels from two correlators. The performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of additive white Gaussian noise (AWGN). This method of FSK demodulation provides approximately 3 dB to 4 dB better sensitivity than a linear demodulator.
POST DEMOD FILTER
Linear Demodulator
Figure 48 shows a block diagram of the linear demodulator.
I LIMITERS Q LEVEL IF
TxRxDATA CLOCK AND DATA RECOVERY MUX
THRESHOLD DETECTION 2FSK/3FSK/4FSK
POST DEMOD FILTER
TxRxCLK
FREQUENCY
08635-045
Figure 46. Overview of Demodulation, Detection, and CDR Process
FREQUENCY READBACK AND AFC LOOP
The quadrature outputs of the IF filter are first limited and then fed to either the correlator FSK demodulator or to the linear FSK demodulator. The correlator demodulator is used to demodulate 2FSK, 3FSK, and 4FSK. The linear demodulator is used for frequency measurement and is enabled when the AFC loop is active. The linear demodulator can also be used to demodulate 2FSK. Following the demodulator, a digital postdemodulator filter removes excess noise from the demodulator signal output. Threshold/slicer detection is used for data recovery of 2FSK and 4FSK. Data recovery of 3FSK can be implemented using either threshold detection or Viterbi detection. An on-chip CDR PLL is used to resynchronize the received bit stream to a local clock. It outputs the retimed data and clock on the TxRxDATA and TxRxCLK pins, respectively.
Figure 48. Block Diagram of Linear FSK Demodulator
A digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. The discriminator output is filtered and averaged using a combined averaging filter and envelope detector. The demodulated 2FSK data from the postdemodulator filter is recovered by slicing against the output of the envelope detector, as shown in Figure 48. This method of demodulation corrects for frequency errors between the transmitter and receiver when the received spectrum is close to or within the IF bandwidth. This envelope detector output is also used for AFC readback and provides the frequency estimate for the AFC control loop.
Postdemodulator Filter
A second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. The bandwidth of this postdemodulator filter is programmable and must be optimized for the user’s data rate and the received modulation type. If the bandwidth is too narrow, performance degrades due to intersymbol interference (ISI). If the bandwidth is too wide, excess noise degrades the performance of the receiver. The POST_DEMOD_BW bits (Register 4, Bits[DB29:DB20]) set the bandwidth of this filter.
Correlator Demodulator
The correlator demodulator can be used for 2FSK, 3FSK, and 4FSK demodulation. Figure 47 shows the operation of the correlator demodulator for 2FSK.
FREQUENCY CORRELATOR DISCRIM BW I LIMITERS Q IF – fDEV IF IF + fDEV OUTPUT LEVELS: 2FSK = +1, –1 3FSK = +1, 0, –1 4FSK = +3, +1, –1, –3
Figure 47. 2FSK Correlator FSK Demodulator Operation
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08635-046
REG 4, BITS[DB9:DB8] REG 4, BITS[DB19:DB10] Rx_INVERT DISCRIMINATOR_BW REG 4, BIT DB7 DOT_PRODUCT
08635-047
VITERBI DETECTION 3FSK
LINEAR DISCRIMINATOR
ENVELOPE DETECTOR
+ SLICER 2FSK
2FSK RxDATA
RxCLK
REG 4, BITS[DB29:DB20]
ADF7021-V
2FSK Bit Slicer/Threshold Detection
2FSK demodulation can be implemented using the correlator FSK demodulator or the linear FSK demodulator. In both cases, threshold detection is used for data recovery at the output of the postdemodulator filter. The output signal levels of the correlator demodulator are always centered about 0. Therefore, the slicer threshold level can be fixed at 0, and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. This results in robust data recovery that does not suffer from the classic baseline wander problems that exist in more traditional FSK demodulators. When the linear demodulator is used for 2FSK demodulation, the output of the envelope detector is used as the slicer threshold, and this output tracks frequency errors that are within the IF filter bandwidth. When used with Viterbi detection, the receiver sensitivity for 3FSK is typically 3 dB greater than that obtained using threshold detection. When the Viterbi detector is enabled, however, the receiver bit latency is increased by twice the Viterbi path memory length.
Clock and Data Recovery (CDR)
An oversampled digital clock and data recovery (CDR) PLL is used to resynchronize the received bit stream to a local clock in all modulation modes. The oversampled clock rate of the PLL (CDR CLK) must be set at 32 times the symbol rate (see the Register 3—Transmit/Receive Clock Register section). The maximum data/symbol rate tolerance of the CDR PLL is determined by the number of zero-crossing symbol transitions in the transmitted packet. For example, if using 2FSK with a 101010 preamble, a maximum tolerance of ±3.0% of the data rate is achieved. However, this tolerance is reduced during recovery of the remainder of the packet, where symbol transitions may not be guaranteed to occur at regular intervals. To maximize the data rate tolerance of the CDR, some form of encoding and/or data scrambling is recommended that guarantees a number of transitions at regular intervals. For example, using 2FSK with Manchester-encoded data achieves a data rate tolerance of ±2.0%. The CDR PLL is designed for fast acquisition of the recovered symbols during preamble and typically achieves bit synchronization within five-symbol transitions of preamble. In 4FSK modulation, the tolerance using the +3, −3, +3, −3 preamble is ±3% of the symbol rate (or ±1.5% of the data rate). However, this tolerance is reduced during recovery of the remainder of the packet, where symbol transitions may not be guaranteed to occur at regular intervals. To maximize the symbol/data rate tolerance of the CDR, the remainder of the 4FSK packet should be constructed so that the transmitted symbols retain close to dc-free properties by using data scrambling and/or by inserting specific dc-balancing symbols into the transmitted bit stream at regular intervals, such as after every 8 or 16 symbols. In 3FSK modulation, the linear convolutional encoder scheme guarantees that the transmitted symbol sequence is dc-free, facilitating symbol detection. However, Tx data scrambling is recommended to limit the run length of 0 symbols in the transmit bit stream. Using 3FSK, the CDR data rate tolerance is typically ±0.5%.
3FSK and 4FSK Threshold Detection
4FSK demodulation is implemented using the correlator demodulator followed by the postdemodulator filter and threshold detection. The output of the postdemodulator filter is a four-level signal that represents the transmitted symbols (−3, −1, +1, +3). Threshold detection of 4FSK requires three threshold settings: one that is always fixed at 0 and two that are programmable and are symmetrically placed above and below 0 using the 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13, Bits[DB10:DB4]). 3FSK demodulation is implemented using the correlator demodulator, followed by a postdemodulator filter. The output of the postdemodulator filter is a three-level signal that represents the transmitted symbols (−1, 0, +1). Data recovery of 3FSK can be implemented using threshold detection or Viterbi detection. Threshold detection is implemented using two thresholds that are programmable and are symmetrically placed above and below 0 using the 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13, Bits[DB10:DB4]).
3FSK Viterbi Detection
Viterbi detection of 3FSK operates on a four-state trellis and is implemented using two interleaved Viterbi detectors operating at half the symbol rate. The Viterbi detector is enabled by Register 13, Bit DB11. To facilitate different run-length constraints in the transmitted bit stream, the Viterbi path memory length is programmable in steps of 4 bits, 6 bits, 8 bits, or 32 bits by setting the VITERBI_ PATH_MEMORY bits (Register 13, Bits[DB14:DB13]). This value should be set equal to or greater than the maximum number of consecutive 0s in the interleaved transmit bit stream.
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ADF7021-V
RECEIVER SETUP
Correlator Demodulator Setup
To enable the correlator for various modulation modes, see Table 15.
Table 15. Enabling the Correlator Demodulator
Received Modulation 2FSK 3FSK 4FSK DEMOD_SCHEME (Register 4, Bits[DB6:DB4]) 001 010 011
Table 17. Assignment of Correlator K Value for 4FSK
K Even Odd Register 4, Bit DB7 0 1 Register 4, Bits[DB9:DB8] 00 00
Linear Demodulator Setup
The linear demodulator can be used for 2FSK demodulation. To enable the linear demodulator, set the DEMOD_SCHEME bits (Register 4, Bits[DB6:DB4]) to 000.
Postdemodulator Filter Setup
The 3 dB bandwidth of the postdemodulator filter should be set according to the received modulation type and data rate. The bandwidth is controlled by Register 4, Bits[DB29:DB20] and is given by
POST _ DEMOD _ BW = 2 11 × π × f CUTOFF DEMOD CLK
To optimize receiver sensitivity, the correlator bandwidth must be optimized for the specific deviation frequency and modulation used by the transmitter. The discriminator bandwidth is controlled by Register 4, Bits[DB19:DB10], and is defined as
DISCRIMINATOR _ BW =
(DEMOD CLK × K )
400 × 10 3
where: DEMOD CLK is as defined in the Register 3—Transmit/Receive Clock Register section. K is set for each modulation mode as follows: For 2FSK,
⎛ 100 × 10 3 K = Round ⎜ ⎜f DEV ⎝ ⎞ ⎟ ⎟ ⎠ ⎞ ⎟ ⎟ ⎠ ⎞ ⎟ ⎟ ⎠
where fCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator filter.
Table 18. Postdemodulator Filter Bandwidth Settings for 2FSK/3FSK/4FSK Modulation Schemes
Received Modulation 2FSK 3FSK 4FSK Postdemodulator Filter Bandwidth, fCUTOFF (Hz) 0.75 × data rate 1 × data rate 1.6 × symbol rate (0.8 × data rate)
For 3FSK,
⎛ 100 × 10 3 K = Round ⎜ ⎜ 2× f DEV ⎝
3FSK Viterbi Detector Setup
The Viterbi detector can be used for 3FSK data detection; it is activated by setting Register 13, Bit DB11, to Logic 1. The Viterbi path memory length is programmable in steps of 4, 6, 8, or 32 bits (VITERBI_PATH_MEMORY, Register 13, Bits[DB14:DB13]). The path memory length should be set equal to or greater than the maximum number of consecutive 0s in the interleaved transmit bit stream. The Viterbi detector also uses threshold levels to implement the maximum likelihood detection algorithm. These thresholds are programmable via the 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13, Bits[DB10:DB4]). These bits are assigned as follows: 3FSK/4FSK_SLICER_THRESHOLD =
⎛ Tx _ FREQUENCY _ DEVIATION × K 57 × ⎜ ⎜ 100 × 10 3 ⎝ ⎞ ⎟ ⎟ ⎠
For 4FSK,
⎛ 100 × 10 3 K = Round 4FSK ⎜ ⎜ 4× f DEV ⎝
where: Round is rounded to the nearest integer. Round4FSK is rounded to the nearest of the following integers: 32, 31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3. fDEV is the transmit frequency deviation in Hz. For 4FSK, fDEV is the frequency deviation used for the ±1 symbols (that is, the inner frequency deviations). To optimize the coefficients of the correlator, Register 4, Bit DB7 and Register 4, Bits[DB9:DB8] must also be assigned. The value of these bits depends on whether K is odd or even. These bits are assigned according to Table 16 and Table 17.
Table 16. Assignment of Correlator K Value for 2FSK and 3FSK
K Even Even Odd Odd K/2 Even Odd N/A N/A (K + 1)/2 N/A N/A Even Odd Register 4, Bit DB7 0 0 1 1 Register 4, Bits[DB9:DB8] 00 10 00 10
where K is the value calculated for correlator discriminator bandwidth.
3FSK Threshold Detector Setup
To activate threshold detection of 3FSK, Register 13, Bit DB11, should be set to Logic 0. The 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13, Bits[DB10:DB4]) should be set as described in the 3FSK Viterbi Detector Setup section.
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ADF7021-V
3FSK CDR Setup
In 3FSK, a transmit preamble of at least 40 bits of continuous 1s is recommended to ensure a maximum number of symbol transitions for the CDR to acquire lock. The clock and data recovery for 3FSK requires a number of parameters in Register 13 to be set (see Table 19).
11001100…) can also be used, but result in a longer synchronization time of the received bit stream in the receiver. The preamble must allow enough bits for AGC settling of the receiver and CDR acquisition (see Table 20). The remaining fields that follow the preamble do not need to use dc-free coding. For these fields, the ADF7021-V can accommodate coding schemes with a run length of greater than eight bits without any performance degradation. Refer to the AN-915 Application Note for more information.
4FSK Threshold Detector Setup
The threshold for the 4FSK detector is set using the 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13, Bits[DB10:DB4]). The threshold should be set as follows: 3FSK/4FSK_SLICER_THRESHOLD =
4FSK Preamble and Data Coding
The recommended preamble bit pattern for 4FSK is a repeating 00100010… bit sequence. This two-level sequence of repeating −3, +3, −3, +3 symbols is dc-free and maximizes the symbol timing performance and data recovery of the 4FSK preamble in the receiver. The minimum recommended length of the preamble is 32 bits (16 symbols). The remainder of the 4FSK packet should be constructed so that the transmitted symbols retain close to a dc-free balance by using data scrambling and/or by inserting specific dc-balancing symbols in the transmitted bit stream at regular intervals, such as after every 8 or 16 symbols.
⎛ 4FSK Outer Tx Deviation × K ⎞ ⎟ 78 × ⎜ ⎜ ⎟ 100 × 10 3 ⎝ ⎠ where K is the value calculated for correlator discriminator bandwidth.
FSK DEMODULATOR OPTIMIZATION
2FSK Preamble
The recommended preamble bit pattern for 2FSK, GFSK, and RC2FSK is a dc-free pattern (such as a 10101010… pattern). Preamble patterns with longer run-length constraints (such as
Table 19. 3FSK CDR Settings
Parameter (Register 13) PHASE_CORRECTION (Bit DB12) 3FSK_CDR_THRESHOLD (Bits[DB21:DB15])
Recommended Setting 1
62 × ⎜ ⎜ ⎝
Purpose Phase correction is on ⎛ Tx _ FREQUENCY _ DEVIATION × K ⎞ Sets CDR decision threshold levels
100 × 10 3
⎟ ⎟ ⎠
3FSK_PREAMBLE_TIME_VALIDATE (Bits[DB25:DB22])
where K is the value calculated for correlator discriminator bandwidth. 15
Preamble detector time qualifier
Table 20. Preamble Bit Length for 2FSK Modulation
Demodulator Correlator (AFC off ) Mod index = 2 Mod index = 1 Mod index = 0.5 Linear (AFC off ) fDEV = 4.2 kHz fDEV = 2.2 kHz fDEV = 1.6 kHz Correlator (AFC on) Linear (AFC on) Correlator + bypass CDR (AFC off )
1 2
Sensitivity Degradation from Specifications 0 dB 0 dB 0 dB 3 dB 3 dB 3 dB 2 dB 3 dB 2 dB to 3 dB 4
Rx Frequency Error Tolerance (1% PER) ±30% × fDEV ±25% × fDEV ±20% × fDEV ±0.5 × IFBW 1 ±0.5 × IFBW1 ±0.5 × IFBW1 AFC pull-in range 2 AFC pull-in range2 ±50% × fDEV 5
Minimum Preamble (Bits) 16 16 16 64 112 128 96 to 128 3 96 to 128 8
This value is generally true; however, some sensitivity degradation may occur close to the edge of the IF filter. Limited to ±0.5 × IFBW or AFC pull-in range, whichever is less. 3 Dependent on modulation index and fDEV. At higher modulation indexes (1.0 or greater) and higher fDEV (>4.0 kHz), the minimum preamble length is 96 bits. The minimum preamble length increases as the modulation index and fDEV are reduced. 4 Dependent on the performance of the symbol timing recovery module on the external microcontroller. 5 Depends on the pulse width mark/space ratio of Logic 1 to Logic 0 that the symbol timing recovery scheme on the external microcontroller can tolerate. In this mode, the mark/space ratio of the recovered bit stream increases with frequency error. In the absence of frequency error, the mark/space ratio is 50:50, that is, the width of a Logic 1 is the same as the width of a Logic 0. Rev. 0 | Page 33 of 60
ADF7021-V
Correlator Demodulator and Low Modulation Indexes
The modulation index in 2FSK is defined as
Modulation Index = 2 × f DEV Data Rate
Internal AFC
The ADF7021-V supports a real-time, internal, automatic frequency control loop. In this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer-N divider using an internal proportional integral (PI) control loop. The internal AFC control loop parameters are controlled in Register 10. The internal AFC loop is activated by setting Bit DB4 in Register 10 to 1. A scaling coefficient must also be entered, based on the crystal frequency in use. This is set up using Bits[DB16:DB5] in Register 10 and should be calculated as follows: ⎛ 2 24 × 500 ⎞ ⎟ AFC _ SCALING _ FACTOR = Round ⎜ ⎜ XTAL ⎟ ⎝ ⎠
The receiver sensitivity performance and receiver frequency tolerance can be maximized at low modulation indexes by increasing the discriminator bandwidth of the correlator demodulator. For modulation indexes of less than 0.4, it is recommended that the correlator bandwidth be doubled by calculating K as follows:
⎛ 100 3 K = Round ⎜ ⎜ 2× f DEV ⎝
⎞ ⎟ ⎟ ⎠
The DISCRIMINATOR_BW value in Register 4 should be recalculated using the new K value. Figure 29 illustrates the improved sensitivity that can be achieved for 2FSK modulation, at low modulation indexes, by doubling the correlator bandwidth.
Maximum AFC Range
The maximum frequency correction range of the AFC loop is programmable using Register 10, Bits[DB31:DB24]. The maximum AFC correction range is the difference in frequency between the upper and lower limits of the AFC tuning range. For example, if the maximum AFC correction range is set to 10 kHz, the AFC can adjust the receiver LO within the fLO ± 5 kHz range. However, when RF_DIVIDE_BY_2 (Register 1, Bit DB18) is enabled, the programmed range is halved. The user should account for this halving by doubling the programmed maximum AFC range. The recommended maximum AFC correction range should be ≤1.5 × IF filter bandwidth. If the maximum frequency correction range is set to be >1.5 × IF filter bandwidth, the attenuation of the IF filter can degrade the AFC loop sensitivity. The adjacent channel rejection (ACR) performance of the receiver can be degraded when AFC is enabled and the AFC correction range is close to or greater than the IF filter bandwidth. However, because the AFC correction range is programmable, the user can trade off AFC correction range and ACR performance of the receiver. When AFC errors are removed using either the internal or external AFC, further improvement in receiver sensitivity can be obtained by reducing the IF filter bandwidth using the IF_FILTER_BW bits (Register 4, Bits[DB31:DB30]).
AFC OPERATION
The ADF7021-V also supports a real-time AFC loop that is used to remove frequency errors due to mismatches between the transmit and receive crystals/TCXOs. The AFC loop uses the linear frequency discriminator block to estimate frequency errors. The linear FSK discriminator output is filtered and averaged to remove the FSK frequency modulation using a combined averaging filter and envelope detector. In receive mode, the output of the envelope detector provides an estimate of the average IF frequency. The two methods of AFC supported on the ADF7021-V are external AFC and internal AFC.
External AFC
With external AFC, the user reads back the frequency information through the ADF7021-V serial port and applies a frequency correction value to the synthesizer-N divider. The frequency information is obtained by reading the signed, 16-bit AFC readback value, as described in the Readback Format section, and by applying the following formula: Frequency Readback (Hz) = (AFC READBACK × DEMOD CLK)/218 Although the AFC readback value is a signed number, under normal operating conditions, it is positive. In the absence of frequency errors, the frequency readback value is equal to the IF frequency of 100 kHz.
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ADF7021-V
AUTOMATIC SYNC WORD DETECTION (SWD)
The ADF7021-V also supports automatic detection of the sync or ID fields. To activate this mode, the sync (or ID) word must be preprogrammed into the ADF7021-V. In receive mode, this preprogrammed word is compared to the received bit stream. When a valid match is identified, the external SWD pin is asserted by the ADF7021-V on the next Rx clock pulse. This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational requirements of the microprocessor and reduces the overall power consumption. The SWD signal can also be used to frame the received packet by staying high for a preprogrammed number of bytes. The data packet length can be set in Register 12, Bits[DB15:DB8]. The SWD pin status can be configured by setting Bits[DB7:DB6] in Register 12. Bits[DB5:DB4] in Register 11 are used to set the length of the sync/ID word, which can be 12, 16, 20, or 24 bits long. A value of 24 bits is recommended to minimize false sync word detection in the receiver that can occur during recovery of the remainder of the packet or when a noise/no signal is present at the receiver input. The transmitter must transmit the sync byte MSB first, LSB last to ensure proper alignment in the receiver sync-byte-detection hardware. An error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. The error tolerance value is assigned in Register 11, Bits[DB7:DB6].
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ADF7021-V APPLICATIONS INFORMATION
IF FILTER BANDWIDTH CALIBRATION
The IF filter should be calibrated on every power-up in receive mode to correct for errors in the bandwidth and filter center frequency due to process variations. The automatic calibration requires no external intervention when it is initiated by a write to Register 5. Depending on numerous factors, such as IF filter bandwidth, received signal bandwidth, and temperature variation, the user must determine whether to carry out a coarse calibration or a fine calibration. The performance of both calibration methods is shown in Table 21.
Table 21. IF Filter Calibration Specifications
Filter Calibration Method Coarse Calibration Fine Calibration
1
Lower Tone Frequency (kHz) =
XTAL IF_CAL_LOWER_TONE_DIVIDE × 2 Upper Tone Frequency (kHz) = XTAL IF_CAL_UPPER_TONE_DIVIDE × 2 It is recommended that the lower tone and the upper tone be set as shown in Table 22.
Table 22. IF Filter Fine Calibration Tone Frequencies
IF Filter Bandwidth (kHz) 9 13.5 18.5 Lower Tone Frequency (kHz) 78.1 79.4 78.1 Upper Tone Frequency (kHz) 116.3 116.3 119
Center Frequency Accuracy1 100 kHz ± 2.5 kHz 100 kHz ± 0.6 kHz
Calibration Time (Typ) 200 μs 8.2 ms
After calibration.
Calibration Setup
IF filter calibration is initiated by writing to Register 5 and setting the IF_CAL_COARSE bit (Bit DB4). This initiates a coarse filter calibration. If the IF_FINE_CAL bit (Register 6, Bit DB4) has already been set high, the coarse calibration is followed by a fine calibration; otherwise, the calibration ends. When initiated by writing to the part, calibration is performed automatically without user intervention. The calibration time is 200 μs for coarse calibration and 8.2 ms for fine calibration, during which time the ADF7021-V should not be accessed. The IF filter calibration logic requires that the IF_FILTER_DIVIDER bits (Register 5, Bits[DB13:DB5]) be set such that XTAL (Hz) IF _ FILTER _ DIVIDER
= 50 kHz
Because the filter attenuation is slightly asymmetrical, it is necessary to have a small offset in the filter center frequency to provide near equal rejection at the upper and lower adjacent channels. The calibration tones listed in Table 22 provide this small positive offset in the IF filter center frequency. In some applications, an offset may not be required, and the user may wish to center the IF filter at 100 kHz exactly. In this case, the user can alter the tone frequencies from those given in Table 22 to adjust the fine calibration result. The calibration algorithm adjusts the filter center frequency and measures the RSSI 10 times during the calibration. The time for an adjustment plus RSSI measurement is given by IF Tone Calibration Time = IF_CAL_DWELL_TIME SEQ CLK
It is recommended that the IF tone calibration time be at least 800 μs. The total time for the IF filter fine calibration is given by IF Filter Fine Calibration Time = IF Tone Calibration Time × 10
The fine calibration uses two internally generated tones at certain offsets around the IF filter. The two tones are attenuated by the IF filter, and the level of this attenuation is measured using the RSSI. The filter center frequency is adjusted to allow equal attenuation of both tones. The attenuation of the two test tones is then remeasured. This process continues for a maximum of 10 RSSI measurements, at which point the calibration algorithm sets the IF filter center frequency to within 0.6 kHz of 100 kHz. The frequency of these tones is set in Register 6 by the IF_CAL_LOWER_TONE_DIVIDE bits (Bits[DB12:DB5]) and the IF_CAL_UPPER_TONE_DIVIDE bits (Bits[DB20:DB13]), as shown in the following equations.
When to Use Coarse Calibration
It is recommended that a coarse calibration be performed on every power-up in receive mode. This calibration typically takes 200 μs. The FILTER_CAL_COMPLETE signal from MUXOUT (set using Bits[DB31:DB29] in Register 0) can be used to monitor the filter calibration duration or to signal the end of calibration. The ADF7021-V should not be accessed during calibration.
Rev. 0 | Page 36 of 60
ADF7021-V
When to Use Fine Calibration
In cases where the receive signal bandwidth is very close to the bandwidth of the IF filter, it is recommended that a fine filter calibration be performed every time that the unit powers up in receive mode. A fine calibration should be performed if OBW + Coarse Calibration Variation > IF_FILTER_BW where: OBW is the 99% occupied bandwidth of the transmit signal. Coarse Calibration Variation is 2.5 kHz. IF_FILTER_BW is set by Register 4, Bits[DB31:DB30]. The FILTER_CAL_COMPLETE signal from MUXOUT (set by Register 0, Bits[DB31:DB29]) can be used to monitor the filter calibration duration or to signal the end of calibration. A coarse filter calibration is automatically performed prior to a fine filter calibration.
LNA/PA MATCHING
The ADF7021-V exhibits optimum performance in terms of sensitivity, transmit power, and current consumption only if its RF input and output ports are properly matched to the antenna impedance. For cost-sensitive applications, the ADF7021-V is equipped with an internal Tx/Rx switch that facilitates the use of a simple, combined passive LNA/PA matching network. Alternatively, an external Tx/Rx switch such as the ADG919 can be used, which yields a slightly improved receiver sensitivity and lower transmitter power consumption.
Internal Tx/Rx Switch
Figure 49 shows the ADF7021-V in a configuration where the internal Tx/Rx switch is used with a combined LNA/PA matching network. This is the configuration used on the EVAL-ADF7021-VDBxZ evaluation board. For most applications, the slight performance degradation of 1 dB to 2 dB caused by the internal Tx/Rx switch is acceptable, allowing the user to take advantage of the cost-saving potential of this solution. The design of the combined matching network must compensate for the reactance presented by the networks in the Tx and the Rx paths, taking the state of the Tx/Rx switch into consideration.
VBAT
When to Use Single Fine Calibration
In applications where the receiver powers up numerous times in a short period, it is necessary to perform fine calibration only once, on the initial power-up in receive mode. After the initial coarse calibration and fine calibration, the result of the fine calibration can be read back through the serial interface using the FILTER_CAL_READBACK result (see the Filter Bandwidth Calibration Readback section). On subsequent power-ups in receive mode, the filter is manually adjusted using the previous fine filter calibration result. This manual adjustment is performed using the IF_FILTER_ADJUST bits (Register 5, Bits[DB19:DB14]). This method should only be used if the successive power-ups in receive mode are over a short duration, during which time there is little variation in temperature ( 6 and KP < 7. The recommended settings for optimal AFC performance are KI = 11 and KP = 4. To trade off between AFC settling time and AFC accuracy, the KI and KP parameters can be adjusted from the recommended settings (staying within the allowable range) such that AFC Correction Range = MAX_AFC_RANGE × 500 Hz •
•
When RF_DIVIDE_BY_2 (Register 1, Bit DB18) is enabled, the programmed AFC correction range is halved. The user must account for this halving by doubling the programmed MAX_AFC_RANGE value. Signals that are within the AFC pull-in range but outside the IF filter bandwidth are attenuated by the IF filter. As a result, the signal can be below the sensitivity point of the receiver and, therefore, not detectable by the AFC.
Rev. 0 | Page 55 of 60
AE1
KP3
KP2
M11
KI4
KI3
KI2
KI1
M9
M8
M7
M6
M5
M4
M3
M2
M1
DB0
ADF7021-V
REGISTER 11—SYNC WORD DETECT REGISTER
SYNC_BYTE_ LENGTH MATCHING_ TOLERANCE
SYNC_BYTE_SEQUENCE CONTROL BITS
SB24 DB31
SB23 DB30
SB22 DB29
SB21 DB28
SB20 DB27
SB19 DB26
SB18 DB25
SB17 DB24
SB16 DB23
SB15 DB22
SB14 DB21
SB13 DB20
SB12 DB19
SB11 DB18
SB10 DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (1)
C4 (1)
C3 (0)
PL2 0 0 1 1
PL1 0 1 0 1
SYNC_BYTE_ LENGTH 12 BITS 16 BITS 20 BITS 24 BITS
MATCHING_ MT2 MT1 TOLERANCE
08635-072
0 0 1 1
0 1 0 1
ACCEPT 0 ERRORS ACCEPT 1 ERROR ACCEPT 2 ERRORS ACCEPT 3 ERRORS
Figure 73. Register 11—Sync Word Detect Register Map
REGISTER 12—SWD/THRESHOLD SETUP REGISTER
LOCK_ THRESHOLD_ MODE SWD_MODE
DATA_PACKET_LENGTH
CONTROL BITS
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
C4 (1)
C3 (1)
C2 (0)
DPx DATA_PACKET_LENGTH 0 1 ... 255 INVALID 1 BYTE ... 255 BYTES
ILx SWD_MODE 0 1 2 3 SWD PIN LOW SWD PIN HIGH AFTER NEXT SYNC WORD SWD PIN HIGH AFTER NEXT SYNC WORD FOR DATA PACKET LENGTH NUMBER OF BYTES SWD PIN HIGH
LMx LOCK_THRESHOLD_MODE 0 1 2 3 THRESHOLD FREE RUNNING LOCK THRESHOLD AFTER NEXT SYNC WORD LOCK THRESHOLD AFTER NEXT SYNC WORD FOR DATA PACKET LENGTH NUMBER OF BYTES LOCK THRESHOLD
C1 (0)
LM2
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
LM1
IL2
IL1
DB0
Figure 74. Register 12—SWD/Threshold Setup Register Map
Lock threshold locks the threshold of the envelope detector. This has the effect of locking the slicer in linear demodulation
and locking the AFC and AGC loops when using linear or correlator demodulation.
Rev. 0 | Page 56 of 60
08635-073
C1 (1)
MT2
MT1
SB9
SB8
SB7
SB6
SB5
SB4
SB3
SB2
SB1
PL2
PL1
DB0
ADF7021-V
REGISTER 13—3FSK/4FSK DEMODULATION REGISTER
See the Receiver Setup section for information about programming these settings.
PHASE_ CORRECTION 3FSK_VITERBI_ DETECTOR VITERBI_ PATH_ MEMORY
3FSK_PREAMBLE_ TIME_VALIDATE
3FSK_CDR_THRESHOLD
3FSK/4FSK_ SLICER_THRESHOLD
CONTROL BITS
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
PTV4 DB25
PTV3 DB24
PTV2 DB23
PTV1 DB22
DB10
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (0)
C4 (1)
C3 (1)
VT7 0 0 0 0 . . 1
... ... ... ... ... ... ... ...
VT3 0 0 0 0 . . 1
VT2 0 0 1 1 . . 1
VT1 0 1 0 1 . . 1
3FSK_CDR_ THRESHOLD OFF 1 2 3 . . 127
3FSK_VITERBI_ VD1 DETECTOR 0 DISABLED 1 ENABLED PHASE_ PC1 CORRECTION 0 DISABLED 1 ENABLED
ST7 VM2 VM1 0 0 1 1 0 1 0 1 VITERBI_PATH _ MEMORY 4 BITS 6 BITS 8 BITS 32 BITS 0 0 0 0 . . 1
... ... ... ... ... ... ... ...
ST3 0 0 0 0 . . 1
ST2 0 0 1 1 . . 1
ST1 0 1 0 1 . . 1
3FSK/4FSK_SLICER_ THRESHOLD OFF 1 2 3 . . 127
PTV4 PTV3 PTV2 PTV1 0 0 0 0 . . 1 0 0 0 0 . . 1 0 0 1 1 . . 1 0 1 0 1 . . 1
3FSK_PREMABLE_ TIME_VALIDATE 0 1 2 3 . . 15
C1 (1)
08635-074
VM2
VM1
VD1
VT7
VT6
VT5
VT4
VT3
VT2
VT1
ST7
ST6
ST5
ST4
ST3
ST2
Figure 75. Register 13—3FSK/4FSK Demodulation Register Map
Rev. 0 | Page 57 of 60
PC1
ST1
DB0
ADF7021-V
REGISTER 14—TEST DAC REGISTER
PULSE_ EXTENSION ED_PEAK_ RESPONSE ED_LEAK_ FACTOR TEST_ TDAC_EN
ADDRESS BITS
TEST_DAC_GAIN
TEST_DAC_OFFSET
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
TO16 DB20
TO15 DB19
TO14 DB18
TO13 DB17
TO12 DB16
TO11 DB15
TO10 DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (1)
C4 (1)
C3 (1)
EFx 0 1 2 3 4 5 6 7
ED_LEAK_FACTOR LEAKAGE = 2^–8 2^–9 2^–10 2^–11 2^–12 2^–13 2^–14 2^–15
ERx PULSE_EXTENSION 0 1 2 3 NO PULSE EXTENSION EXTENDED BY 1 EXTENDED BY 2 EXTENDED BY 3
TGx 0 1 ... 15
TEST_DAC_GAIN NO GAIN × 2^1 ... × 2^15
TE1 0 1
TEST_TDAC_EN TEST DAC DISABLED TEST DAC ENABLED
PEx 0 1 2 3
ED_PEAK_RESPONSE FULL RESPONSE TO PEAK 0.5 RESPONSE TO PEAK 0.25 RESPONSE TO PEAK 0.125 RESPONSE TO PEAK
C1 (0)
08635-075
TG4
TG3
TG2
TG1
TO9
TO8
TO7
TO6
TO5
TO4
TO3
TO2
TO1
ER2
ER1
PE2
PE1
Figure 76. Register 14—Test DAC Register Map
The demodulator tuning parameters, PULSE_EXTENSION, ED_LEAK_FACTOR, and ED_PEAK_RESPONSE, can be enabled only by setting Register 15, Bits[DB7:DB4] to 0x9.
Using the On-Chip Test DAC
The on-chip test DAC can be used to implement analog demodulation or to provide access for measurement of FSK demodulator output SNR or CNR. For detailed information about using the test DAC, see the AN-852 Application Note. The test DAC allows the postdemodulator filter output for both linear and correlator demodulators to be viewed externally. The test DAC also takes the 16-bit filter output and converts it to a high frequency, single-bit output using a second-order, error feedback Σ-Δ converter. The output can be viewed on the SWD pin. This signal, when filtered appropriately, can then be used to do the following: • Monitor the signals at the FSK postdemodulator filter output. This allows the demodulator output SNR to be measured. Eye diagrams of the received bit stream can also be constructed to measure the received signal quality. Provide analog FM demodulation.
Whereas the correlators and filters are clocked by DEMOD CLK, the test DAC is clocked by CDR CLK. Note that although the test DAC functions in regular user mode, the best performance is achieved when CDR CLK is increased to or above the frequency of DEMOD CLK. The CDR block does not function when this condition exists. Programming Register 14 enables the test DAC. Both the linear and correlator demodulator outputs can be multiplexed into the DAC. Register 14 allows a fixed offset term to be removed from the signal (to remove the IF component in the linear demodulator case). It also has a signal gain term to allow the usage of the maximum dynamic range of the DAC.
•
Rev. 0 | Page 58 of 60
TE1
EF3
EF2
EF1
DB0
ADF7021-V
REGISTER 15—TEST MODE REGISTER
CAL_ OVERRIDE FORCE_LD_ HIGH REG1_PD
ANALOG_TEST_ MODES PLL_TEST_ MODES PFD/CP_ TEST_MODES Σ-Δ_TEST_ MODES Tx_TEST_ MODES Rx_TEST_ MODES ADDRESS BITS
CLK_MUX
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB11
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (1)
C4 (1)
C3 (1)
COx CAL_OVERRIDE 0 1 2 3 AUTO CAL OVERRIDE GAIN OVERRIDE BW OVERRIDE BW AND GAIN RD1 0 1 REG1_PD NORMAL POWER-DOWN FH1 0 1 AMx 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FORCE_LD_HIGH NORMAL FORCE
PCx PFD/CP_TEST_MODES 0 1 2 3 4 5 6 7 DEFAULT, NO BLEED (+VE) CONSTANT BLEED (–VE) CONSTANT BLEED (–VE) PULSED BLEED (–VE) PULSE BLD, DELAY UP CP PUMP UP CP TRISTATE CP PUMP DN SDx 0 1 2 3 4 5 6 7 Σ-Δ_TEST_MODES DEFAULT, 3RD-ORDER Σ-Δ, NO DITHER 1ST-ORDER Σ-Δ 2ND-ORDER Σ-Δ DITHER TO FIRST STAGE DITHER TO SECOND STAGE DITHERTO THIRD STAGE DITHER × 8 DITHER × 32
ANALOG_TEST_MODES BAND GAP VOLTAGE 40µA CURRENT FROM REG4 FILTER I CHANNEL: STAGE 1 FILTER I CHANNEL: STAGE 2 FILTER I CHANNEL: STAGE 1 FILTER Q CHANNEL: STAGE 1 FILTER Q CHANNEL: STAGE 2 FILTER Q CHANNEL: STAGE 1 ADC REFERENCE VOLTAGE BIAS CURRENT FROM RSSI 5µA FILTER COARSE CAL OSCILLATOR OUTPUT ANALOG RSSI I CHANNE L OFFSET LOOP +VE FBACK V (I CH) SUMMED OUTPUT OF RSSI RECTIFIER+ SUMMED OUTPUT OF RSSI RECTIFIER– BIAS CURRENT FROM BB FILTER
TMx Tx_TEST_MODES 0 1 2 3 4 5 6 NORMAL OPERATION Tx CARRIER ONLY Tx +fDEV TONE ONLY Tx –fDEV TONE ONLY Tx "1010" PATTERN Tx PN9 DATA SEQUENCE Tx SWD PATTERN REPEATEDLY RTx Rx_TEST_MODES NORMAL SCLK, SDATA I,Q REVERSE I,Q I,Q TO TxRxCLK, TxRxDATA 3FSK SLICER ON TxRxDATA CORRELATOR SLICER ON TxRxDATA LINEAR SLICER ON TxRxDATA SDATA TO CDR ADDITIONAL FILTERING ON I,Q ENABLE REG 14 DEMOD PARAMETERS POWER DOWN DDT AND ED IN T/4 MODE ENVELOPE DETECTOR WATCHDOG DISABLED RESERVED PROHIBIT CAL ACTIVE FORCE CAL ACTIVE ENABLE DEMOD DURING CAL
PMx 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PLL_TEST_MODES NORMAL OPERATION R DIV N DIV RCNTR/2 ON MUXOUT NCNTR/2 ON MUXOUT ACNTR TO MUXOUT PFD PUMP UP TO MUXOUT PFD PUMP DNTO MUXOUT S DATA TO MUXOUT (OR SREAD) ANALOG LOCK DETECT ON MUXOUT END OF COARSE CAL ON MUXOUT END OF FINE CAL ON MUXOUT FORCE NEW PRESCALER CONFIG FOR ALL N TEST MUX SELECTS DATA LOCK DETECT PRECISION RESERVED
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CMx CLK_MUX ON CLKOUT PIN 0 1 2 3 4 5 6 7 NORMAL, NO OUTPUT DEMOD CLK CDR CLK SEQ CLK BB OFFSET CLK Σ-Δ CLK ADC CLK TxRxCLK
C1 (1)
08635-076
AM4
AM3
AM2
AM1
CM3
CM2
CM1
PM4
PM3
PM2
PM1
CO2
CO1
TM3
TM2
TM1
RD1
PC3
PC2
PC1
SD3
SD2
SD1
FH1
RT4
RT3
RT2
Figure 77. Register 15—Test Mode Register Map
• •
Analog RSSI can be viewed on the TEST_A pin by setting ANALOG_TEST_MODES (Bits[DB27:DB24]) to 11. Tx_TEST_MODES can be used to enable modulation test.
•
The CDR block can be bypassed by setting Rx_TEST_ MODES to 4, 5, or 6, depending on the demodulator used.
Rev. 0 | Page 59 of 60
RT1
DB0
ADF7021-V OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
4.25 4.10 SQ 3.95
0.50 0.40 0.30
25 24
13
12
0.25 MIN 5.50 REF
1.00 0.85 0.80
12° MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 78. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-3) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADF7021-VBCPZ ADF7021-VBCPZ-RL EVAL-ADF70XXMBZ2 EVAL-ADF7021-VDB1Z EVAL-ADF7021-VDB2Z
1
Temperature Range −40°C to +85°C −40°C to +85°C
Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Platform Mother Board 450 MHz to 470 MHz Daughter Board 868 MHz to 870 MHz Daughter Board
Package Option CP-48-3 CP-48-3
Z = RoHS Compliant Part.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08635-0-4/10(0)
Rev. 0 | Page 60 of 60
042809-A
SEATING PLANE
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
