ADF7023-JBCPZ-RL

Data Sheet High Performance, Low Power, ISM Band FSK/GFSK/MSK/GMSK Transceiver IC ADF7023-J FEATURES Ultralow power, high performance transceiver Frequency bands: 902 MHz to 958 MHz Data rates supported: 1 kbps to 300 kbps 2.2 V to 3.6 V power supply Single-ended and differential power amplifiers (PAs) Low IF receiver with programmable IF bandwidths 100 kHz, 150 kHz, 200 kHz, 300 kHz Receiver sensitivity (BER) −116 dBm at 1.0 kbps, 2FSK, GFSK −107.5 dBm at 38.4 kbps, 2FSK, GFSK −106.5 dBm at 50 kbps, 2FSK, GFSK −105 dBm at 100 kbps, 2FSK, GFSK −104 dBm at 150 kbps, GFSK, GMSK −103 dBm at 200 kbps, GFSK, GMSK −100.5 dBm at 300 kbps, GFSK, GMSK Very low power consumption 12.8 mA in PHY_RX mode (maximum front-end gain) 11.9 mA in PHY_RX mode (AGC off, ADC off) 24.1 mA in PHY_TX mode (10 dBm output, single-ended PA) 0.75 µA in PHY_SLEEP mode (32 kHz RC oscillator active) 1.28 µA in PHY_SLEEP mode (32 kHz XTAL oscillator active) 0.33 µA in PHY_SLEEP mode (Deep Sleep Mode 1) RF output power of −20 dBm to +13.5 dBm (single-ended PA) RF output power of −20 dBm to +10 dBm (differential PA) Patented fast settling automatic frequency control (AFC) Digital received signal strength indication (RSSI) Integrated PLL loop filter and Tx/Rx switch Fast automatic voltage controlled oscillator (VCO) calibration Automatic synthesizer bandwidth optimization On-chip, low power, custom 8-bit processor Radio control Packet management Smart wake mode Rev. D SPORT mode support High speed synchronous serial interface to Tx and Rx Data for direct interfacing to processors and DSPs Packet management support Highly flexible for a wide range of packet formats Insertion/detection of preamble/sync word/CRC/address Manchester and 8b/10b data encoding and decoding Data whitening Smart wake mode Current saving low power mode with autonomous receiver wake up, carrier sense, and packet reception Downloadable firmware modules Image rejection calibration, fully automated (patent pending) 128-bit AES encryption/decryption with hardware acceleration and key sizes of 128 bits, 192 bits, and 256 bits Reed-Solomon error correction with hardware acceleration 240-byte packet buffer for Tx/Rx data Efficient SPI control interface with block read/write access Integrated battery alarm and temperature sensor Integrated RC and 32.768 kHz crystal oscillator On-chip, 8-bit ADC 5 mm × 5 mm, 32-lead, LFCSP package APPLICATIONS Smart metering IEEE 802.15.4g Home automation Process and building control Wireless sensor networks (WSNs) Wireless healthcare Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADF7023-J Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interrupts in Sport Mode .......................................................... 48 Applications ....................................................................................... 1 ADF7023-J Memory Map ............................................................. 49 Revision History ............................................................................... 3 BBRAM ........................................................................................ 49 Functional Block Diagram .............................................................. 4 Modem Configuration RAM (MCR) ...................................... 49 General Description ......................................................................... 4 Program ROM ............................................................................ 49 Specifications..................................................................................... 6 Program RAM ............................................................................ 49 RF and Synthesizer Specifications .............................................. 6 Packet RAM ................................................................................ 50 Transmitter Specifications ........................................................... 7 SPI Interface .................................................................................... 51 Receiver Specifications ................................................................ 9 General Characteristics ............................................................. 51 Timing and Digital Specifications ............................................ 12 Command Access ....................................................................... 51 Auxilary Block Specifications ................................................... 13 Status Word ................................................................................. 51 General Specifications ............................................................... 14 Command Queuing ................................................................... 52 Timing Specifications ................................................................ 15 Memory Access........................................................................... 53 Absolute Maximum Ratings.......................................................... 16 Low Power Modes .......................................................................... 56 ESD Caution ................................................................................ 16 Example Low Power Modes ...................................................... 59 Pin Configuration and Function Descriptions ........................... 17 Low Power Mode Timing Diagrams........................................ 61 Typical Performance Characteristics ........................................... 19 WUC Setup ................................................................................. 62 Terminology .................................................................................... 26 Firmware Timer Setup ............................................................... 63 Radio Control.................................................................................. 27 Calibrating the RC Oscillator ................................................... 63 Radio States ................................................................................. 27 Downloadable Firmware Modules ............................................... 65 Initialization ................................................................................ 29 Writing a Module to Program RAM........................................ 65 Commands .................................................................................. 30 Image Rejection Calibration Module ...................................... 65 Automatic State Transitions ...................................................... 32 AES Encryption and Decryption Module............................... 65 State Transition and Command Timing.................................. 33 Reed-Solomon Coding Module ............................................... 65 Sport Mode ...................................................................................... 37 Radio Blocks .................................................................................... 67 Packet Structure in Sport Mode ............................................... 37 Frequency Synthesizer ............................................................... 67 Sport Mode in Transmit ............................................................ 37 Crystal Oscillator........................................................................ 68 Sport Mode in Receive ............................................................... 37 Modulation .................................................................................. 68 Transmit Bit Latencies in Sport Mode ..................................... 37 RF Output Stage.......................................................................... 69 Packet Mode .................................................................................... 40 PA/LNA Interface ....................................................................... 69 Preamble ...................................................................................... 40 Receive Channel Filter ............................................................... 69 Sync Word ................................................................................... 41 Image Channel Rejection .......................................................... 69 Payload ......................................................................................... 42 Automatic Gain Control (AGC)............................................... 70 CRC .............................................................................................. 43 RSSI .............................................................................................. 70 Postamble..................................................................................... 44 2FSK/GFSK/MSK/GMSK Demodulation............................... 72 Transmit Packet Timing ............................................................ 44 Clock Recovery ........................................................................... 73 Data Whitening .......................................................................... 45 Manchester Encoding ................................................................ 45 Recommended Receiver Settings for 2FSK/GFSK/MSK/GMSK ......................................................... 73 8b/10b Encoding ........................................................................ 45 Peripheral Features ......................................................................... 76 Interrupt Generation ...................................................................... 46 Analog-to-Digital Converter .................................................... 76 Rev. D | Page 2 of 104 Data Sheet ADF7023-J Temperature Sensor ....................................................................76 Command Reference ...................................................................... 80 Test DAC ......................................................................................76 Register Maps .................................................................................. 81 Transmit Test Modes ..................................................................76 BBRAM Register Description ................................................... 83 Silicon Revision Readback .........................................................76 MCR Register Description......................................................... 94 Applications Information ...............................................................77 Packet RAM Register Description ..........................................101 Application Circuit .....................................................................77 Outline Dimensions ......................................................................102 Host Processor Interface ............................................................77 Ordering Guide .........................................................................102 PA/LNA Matching ......................................................................78 REVISION HISTORY 3/14—Rev. C to Rev. D Changes to Figure 54 ......................................................................42 Changes to Transmit Packet Timing Section and Figure 56 .....44 Changes to Figure 69 ......................................................................58 Changes to Figure 72 ......................................................................61 Change to Power Amplifier (PA) Section ....................................69 Changes to Table 88 and Table 89 .................................................91 Change to Table 94 ..........................................................................92 Change to Table 99 ..........................................................................94 Change to Table 107 ........................................................................95 Change to Table 114 ........................................................................98 5/13—Rev. B to Rev. C Added t15 to Table 7 and Figure 3 ..................................................15 Changed Register 0x018 200 kbps Data Rate from 0x18 to 0x22; Table 31...................................................................................67 1/13—Rev. A to Rev. B Change to Accuracy of Temperature Readback Parameter, Table 5 ...............................................................................................13 Changes to Table 9 ..........................................................................17 Change to PHY_TX Section ..........................................................27 Changes to Table 12 ........................................................................36 Changes to Figure 56 ......................................................................44 Changes to Interrupts in Sport Mode Section .............................48 Changes to Table 26 ........................................................................52 Changes to Table 28 ........................................................................57 Changes to Table 29 ........................................................................62 Changes to Crystal Oscillator Section and Table 32 ...................73 Change to Power Amplifier (PA) Section ....................................74 Changes to Figure 84 ......................................................................77 Changes to Table 44 ........................................................................79 Changes to Table 95 ........................................................................93 Change to Table 99 ..........................................................................94 Change to Table 137 ..................................................................... 100 Updated Outline Dimensions ..................................................... 102 6/12—Rev. 0 to Rev. A Changes to General Descriptions Section...................................... 4 Changes to Calibration Time and to ADC Parameter in Table 5 ..........................................................................................13 Changes to Table 7 and to table summary statement and changes to Figure 2 and Figure 3 .................................................. 15 Changes to Figure 5 and Figure 7 ................................................. 19 Changes to Figure 43 ...................................................................... 25 Changes to PHY_SLEEP Section .................................................. 27 Changes to State Transition and Command Timing Section and changes to Table 11 .................................................................. 33 Changes to Table 12 ........................................................................ 34 Changes to Figure 49 and Figure 50 ............................................. 38 Changes to Figure 51 and Figure 52 ............................................. 39 Changes to Figure 53 ...................................................................... 41 Changes to Addressing Section ..................................................... 42 Changes to Table 20 and changes to CRC Section...................... 43 Changes to Figure 56 ...................................................................... 44 Changes to Command Access Section ......................................... 51 Changes to Table 28 ........................................................................ 57 Changes to Figure 69 ...................................................................... 58 Changes to Table 29 ........................................................................ 62 Added Calibrating the RC Oscillator Section ............................. 63 Added Figure 75; Renumbered Sequentially ............................... 64 Changes to Automatic PA Ramp Section and changes to Image Channel Rejection Section ............................................................. 69 Changes to Temperature Sensor Section and changes to Table 42 ............................................................................................. 76 Changes to Support for External PA and LNA Control Section and changes to Table 44 .................................................................. 79 Changes to Table 47 ........................................................................ 81 Changes to Table 48 ........................................................................ 82 Changes to Table 69 ........................................................................ 86 Changes to Table 70 ........................................................................ 86 Changes to Table 76 ........................................................................ 88 Changes to Table 77 and to Table 78 ............................................ 89 Changes to Table 83 and to Table 85 ............................................ 91 Changes to Table 93 and added Table 94; Renumbered Sequentially ...................................................................................... 92 Added Table 95 and Table 96 ........................................................ 93 Changes to Table 100 ...................................................................... 94 Changes to Table 110 ...................................................................... 96 Added Table 123 and Table 124..................................................... 98 Changes to Table 144 ....................................................................101 5/11—Revision 0: Initial Version Rev. D | Page 3 of 104 ADF7023-J Data Sheet FUNCTIONAL BLOCK DIAGRAM ADCIN_ATB3 FSK ASK DEMOD RFIO_1P RSSI/ LOGAMP RFIO_1N MUX LNA 8-BIT ADC 4kB ROM MAC 8-BIT RISC PROCESSOR IRQ CTRL CS 2kB RAM CDR AFC AGC 256 BYTE PACKET RAM PA IRQ_GP3 SPI MISO SCLK MOSI 64 BYTE BBRAM LOOP FILTER DIVIDER PA CHARGE PUMP 26MHz OSC PFD 256 BYTE MCR RAM TEST DAC DIVIDER GPIO1 fDEV PA RAMP PROFILE Σ-Δ MODULATOR LDO4 LDO3 LDO2 ADF7023-J LDO1 GPIO BIAS WAKE-UP CONTROL TIMER UNIT GAUSSIAN FILTER ANALOG TEST CREGRFx CREGVCO CREGSYNTH CREGDIGx RBIAS TEMP SENSOR BATTERY MONITOR XOSC32KN_ATB2 1GPIO REFERS TO PINS 17, 18, 19, 20, 25, AND 27. 32kHz OSC 32kHz RCOSC CLOCK DIVIDER 26MHz OSC XOSC32KP_GP5_ATB1 XOSC26N XOSC26P 09555-001 RFO2 Figure 1. GENERAL DESCRIPTION The ADF7023-J is a very low power, high performance, highly integrated 2FSK/GFSK/MSK/GMSK transceiver designed for operation in the 902 MHz to 958 MHz frequency band, which covers the ARIB Standard T96 band at 950 MHz. Data rates from 1 kbps to 300 kbps are supported. The transmit RF synthesizer contains a VCO and a low noise fractional-N phase locked loop (PLL) with an output channel frequency resolution of 400 Hz. The VCO operates at twice the fundamental frequency to reduce spurious emissions. The receive and transmit synthesizer bandwidths are automatically, and independently, configured to achieve optimum phase noise, modulation quality, and settling time. The transmitter output power is programmable from −20 dBm to +13.5 dBm, with automatic PA ramping to meet transient spurious specifications. The part possesses both single-ended and differential PAs, which allow for Tx antenna diversity. The receiver is exceptionally linear, achieving an IP3 specification of −12.2 dBm and −11.5 dBm at maximum gain and minimum gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm at maximum gain and minimum gain, respectively. The receiver achieves an interference blocking specification of 66 dB at a ±2 MHz offset and 74 dB at a ±10 MHz offset. Thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. The receiver features a novel, high speed, AFC loop, allowing the PLL to find and correct any RF frequency errors in the recovered packet. A patent pending image rejection calibration scheme is available by downloading the image rejection calibration firmware module to program RAM. The algorithm does not require the use of an external RF source nor does it require any user intervention once initiated. The results of the calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver. The ADF7023-J operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance. The device can enter a low power sleep mode in which the configuration settings are retained in the battery backup random access memory (BBRAM). The ADF7023-J features an ultralow power, on-chip, communications processor. The communications processor, which is an 8-bit RISC processor, performs the radio control, packet management, and smart wake mode (SWM) functionality. The communications processor eases the processing burden of the companion processor by integrating the lower layers of a typical communication protocol stack. The communications processor also permits the download and execution of firmware modules. Available modules include image rejection (IR) calibration, advanced encryption standard (AES) encryption, and Reed-Solomon coding. These firmware modules are available online at ftp://ftp.analog.com/pub/RFL/FirmwareModules. The communications processor provides a simple command-based radio control interface for the host processor. A single-byte command transitions the radio between states or performs a radio function. The communications processor provides support for generic packet formats. The packet format is highly flexible and fully programmable, thereby ensuring its compatibility with proprietary packet profiles. In transmit mode, the communications processor can be configured to add preamble, sync word, and CRC to the payload data stored in packet RAM. In receive mode, the Rev. D | Page 4 of 104 Data Sheet ADF7023-J communications processor can detect and interrupt the host processor on reception of preamble, sync word, address, and CRC and store the received payload to packet RAM. The ADF7023-J uses an efficient interrupt system comprising MAC level interrupts and PHY level interrupts that can be individually set. The payload data plus the 16-bit CRC can be encoded/decoded using Manchester or 8b/10b encoding. Alternatively, data whitening and dewhitening can be applied. The SWM allows the ADF7023-J to wake up autonomously from sleep using the internal wake-up timer without intervention from the host processor. After wake-up, the ADF7023-J is controlled by the communications processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption. The smart wake mode can wake the host processor on an interrupt condition. These interrupt conditions can be configured to include the reception of valid preamble, sync word, CRC, or address match. Wake-up from sleep mode can also be triggered by the host processor. For systems requiring very accurate wake-up timing, a 32 kHz oscillator can be used to drive the wake-up timer. Alternatively, the internal RC oscillator can be used, which gives lower current consumption in sleep. The ADF7023-J features an AES engine with hardware acceleration that provides 128-bit block encryption and decryption with key sizes of 128 bits, 192 bits, and 256 bits. Both electronic code book (ECB) and Cipher Block Chaining Mode 1 (CBC Mode 1) are supported. The AES engine can be used to encrypt/decrypt packet data and can be used as a standalone engine for encryption/decryption by the host processor. The AES engine is enabled on the ADF7023-J by downloading the AES firmware module to program RAM. An on-chip, 8-bit ADC provides readback of an external analog input, the RSSI signal, or an integrated temperature sensor. An integrated battery voltage monitor raises an interrupt flag to the host processor whenever the battery voltage drops below a userdefined threshold. Rev. D | Page 5 of 104 ADF7023-J Data Sheet SPECIFICATIONS VDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V and TA = 25°C. RF AND SYNTHESIZER SPECIFICATIONS Table 1. Parameter RF CHARACTERISTICS Frequency Range PHASE-LOCKED LOOP Channel Frequency Resolution Phase Noise at Offset of 600 kHz 800 kHz 600 kHz 800 kHz 1 MHz 2 MHz 10 MHz VCO Calibration Time Synthesizer Settling Time Min Typ 902 Max Unit 958 MHz 396.7 Hz −116.3 −119.4 −113.8 −117.2 −126 −131 −142 142 56 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz µs µs Integer Boundary Spurious 3 (26 MHz × N) + 0.1 MHz −39 dBc (26 MHz × N) + 1.0 MHz −79 dBc CRYSTAL OSCILLATOR Crystal Frequency Recommended Load Capacitance Maximum Crystal ESR Pin Capacitance Start-Up Time 26 7 18 1800 2.1 310 388 MHz pF Ω pF µs µs Test Conditions/Comments PA output power = 10 dBm, RF frequency = 950 MHz 130 kHz closed-loop bandwidth 1 130 kHz closed-loop bandwidth 223 kHz closed-loop bandwidth 2 223 kHz closed-loop bandwidth Frequency synthesizer settles to within ±5 ppm of the target frequency within this time following the VCO calibration, transmit, and receive, 2FSK/GFSK/MSK/GMSK N = 35 or 36 Using 130 kHz synthesizer bandwidth, integer boundary spur at 910 MHz (26 MHz × 35), inside synthesizer loop bandwidth Using 130 kHz synthesizer bandwidth, integer boundary spur at 910 MHz (26 MHz × 35), outside synthesizer loop bandwidth Parallel load resonant crystal 26 MHz crystal with 18 pF load capacitance Capacitance for XOSC26P and XOSC26N 26 MHz crystal with 7 pF load capacitance 26 MHz crystal with 18 pF load capacitance 130 kHz closed-loop bandwidth recommended for T96/15.4 g, 50 kbps and 100 kbps data rates (see Table 31). 223 kHz closed-loop bandwidth recommended for T96/15.4 g, 200 kbps data rate (see Table 31). 3 As the 26 MHz XTAL is fixed, integer boundary spurs occur at 910 MHz and 936 MHz (N = 35 and N = 36). 1 2 Rev. D | Page 6 of 104 Data Sheet ADF7023-J TRANSMITTER SPECIFICATIONS Table 2. Parameter DATA RATE 2FSK/GFSK/MSK/GMSK Data Rate Resolution MODULATION ERROR RATIO (MER) 1 10 kbps to 49.5 kbps 49.6 kbps to 129.5 kbps 129.6 kbps to 179.1 kbps 179.2 kbps to 239.9 kbps 240 kbps to 300 kbps MODULATION ERROR RATIO 15.4 g DATA RATES 50 kbps 100 kbps 200 kbps 100 kbps MODULATION 2FSK/GFSK/MSK/GMSK Frequency Deviation Deviation Frequency Resolution Gaussian Filter Bandwidth-Time (BT) Product SINGLE-ENDED PA Maximum Power 3 Min Typ 1 Max Unit 300 kbps bps 100 25.4 25.3 23.9 23.3 23 dB dB dB dB dB 25.4 28.9 25.9 24.3 dB dB dB dB 0.1 409.5 100 0.5 Test Conditions/Comments RF frequency = 957.2 MHz, GFSK Modulation index = 1 Modulation index = 1 Modulation index = 0.5 Modulation index = 0.5 Modulation index = 0.5 With T96 look-up table (LUT) 2 Modulation index = 1 Modulation index = 1 Modulation index = 1 Modulation index = 0.5 kHz Hz 13.5 dBm Minimum Power Transmit Power Variation vs. Temperature −20 ±0.5 dBm dB Transmit Power Variation vs. VDD Transmit Power Flatness ±1 ±1 dB dB 0.5 dB Programmable in 63 steps 10 −20 ±1 dBm dBm dB Programmable Transmit Power Variation vs. VDD Transmit Power Flatness ±2 ±1 dB dB Programmable Step Size −20 dBm to +10 dBm 0.5 dB Programmable Step Size −20 dBm to +13.5 dBm DIFFERENTIAL PA Maximum Power3 Minimum Power Transmit Power Variation vs. Temperature Rev. D | Page 7 of 104 Programmable, separate PA and LNA match 4 From −40°C to +85°C, RF frequency = 958.0 MHz From 2.2 V to 3.6 V, RF frequency = 958.0 MHz From 902 MHz to 928 MHz and 950 MHz to 958 MHz From −40°C to +85°C, RF frequency = 958.0 MHz From 2.2 V to 3.6 V, RF frequency = 958.0 MHz From 902 MHz to 928 MHz and 950 MHz to 958 MHz Programmable in 63 steps ADF7023-J Parameter SPURIOUS EMISSIONS 30 MHz to 710 MHz 710 MHz to 945 MHz 945 MHz to 950 MHz 958 MHz to 960 MHz 960 MHz to 1 GHz 1 GHz to 1.215 GHz 1.215 GHz to 1.8845 GHz 1.8845 GHz to 1.9196 GHz 5 1.9196 GHz to 3 GHz 3 GHz to 5 GHz OPTIMUM PA LOAD IMPEDANCE Single-Ended PA in Transmit Mode fRF = 915 MHz fRF = 954MHz Single-Ended PA in Receive Mode fRF = 915 MHz fRF = 954 MHz Differential PA in Transmit Mode fRF = 915 MHz fRF = 954 MHz Data Sheet Min Typ Max Unit −65 −63 −66 −60.7 −64 −72 −76 −69 −66 −69 dBm/100 kHz dBm/1 MHz dBm/100 kHz dBm/100 kHz dBm/100 kHz dBm/1 MHz dBm/1 MHz dBm/1 MHz dBm/1 MHz dBm/1 MHz 50.8 + j10.2 38.5 + j5.9 Ω Ω 9.4 − j124 8.8 − j118.5 Ω Ω Test Conditions/Comments Measured as per TELEC T-245 for T96 compliance, 950 MHz to 958 MHz band, single-ended PA with combined output. For spurious emissions compliance in the 1.8845 GHz to 1.9196 GHz frequency band, a seventh-order PA harmonic filter is used. This has an insertion loss of up to 1.5 dB. DR = 100 kbps, MI = 1, n = 2, fC = 957.3 MHz PA Impedance in Rx mode Load impedance between RFIO_1P and RFIO_1N to ensure maximum output power 20.5 + j36.4 28.1 + j17.3 Ω Ω MER is a measure of signal to noise ratio at optimal eye sampling point. Optimized PLL bandwidth settings vs. data rate defined in Table 31. 3 Measured as the maximum unmodulated power. 4 A combined single-ended PA and LNA match can reduce the maximum achievable output power by up to 1 dB. 5 This includes the second harmonic. 1 2 Rev. D | Page 8 of 104 Data Sheet ADF7023-J RECEIVER SPECIFICATIONS Table 3. Parameter 2FSK/MSK INPUT SENSITIVITY, BIT ERROR RATE (BER) Min Typ Max Unit 1.0 kbps −116 dBm 10 kbps −111 dBm 38.4 kbps −107.5 dBm 50 kbps −106.5 dBm 100 kbps −105 dBm 150 kbps −104 dBm 200 kbps −103 dBm 300 kbps −100.5 dBm 50 kbps −107.4 dBm 100 kbps −105 dBm 100 kbps −106 dBm 200 kbps −102 dBm 200 kbps −103.3 dBm 1.0 kbps −115.5 dBm 9.6 kbps −110.6 dBm 38.4 kbps −106 dBm 50 kbps −104.3 dBm 100 kbps −102.6 dBm 150 kbps −101 dBm 200 kbps −99.1 dBm 300 kbps −97.9 dBm GFSK/GMSK INPUT SENSITIVITY, BER 2FSK/MSK INPUT SENSITIVITY, PACKET ERROR RATE (PER) Rev. D | Page 9 of 104 Test Conditions/Comments At BER = 1E − 3, RF frequency = 915 MHz, LNA and PA matched separately 1 Frequency deviation = 4.8 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 9.6 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 20 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 12.5 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 25 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 37.5 kHz, IF filter bandwidth = 150 kHz Frequency deviation = 50 kHz, IF filter bandwidth = 200 kHz Frequency deviation = 75 kHz, IF filter bandwidth = 300 kHz At BER = 1E − 3, RF frequency = 954 MHz, LNA and PA matched separately1 Frequency deviation = 25 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 50 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 40 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 100 kHz, IF filter bandwidth = 200 kHz Frequency deviation = 80 kHz, IF filter bandwidth = 200 kHz At PER = 1%, RF frequency = 915 MHz, LNA and PA matched separately,1 packet length = 128 bits, packet mode Frequency deviation = 4.8 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 9.6 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 20 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 12.5 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 25 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 37.5 kHz, IF filter bandwidth = 150 kHz Frequency deviation = 50 kHz, IF filter bandwidth = 200 kHz Frequency deviation = 75 kHz, IF filter bandwidth = 300 kHz ADF7023-J Parameter GFSK/GMSK INPUT SENSITIVITY, PER Data Sheet Min Typ Max Unit 50 kbps −104.1 dBm 100 kbps −101.1 dBm 100 kbps −102.2 dBm 200 kbps −98.5 dBm 200 kbps −99.5 dBm Minimum LNA Gain Maximum LNA Gain LNA AND MIXER, INPUT IP2 −11.5 −12.2 dBm dBm Maximum LNA Gain, Maximum Mixer Gain Minimum LNA Gain, Minimum Mixer Gain LNA AND MIXER, 1 dB COMPRESSION POINT Maximum LNA Gain, Maximum Mixer Gain Minimum LNA Gain, Minimum Mixer Gain ADJACENT CHANNEL REJECTION CW Interferer 18.5 27 dBm dBm −21.9 −21 dBm dBm LNA AND MIXER, INPUT IP3 Receiver LO frequency (fLO) = 920.8 MHz, fSOURCE1 = fLO + 1.1 MHz, fSOURCE2 = fLO + 1.3 MHz RF frequency = 915 MHz ±200 kHz Offset 38 dB +400 kHz Offset −400 kHz Offset 51 33/39 dB dB −6 dB CO-CHANNEL REJECTION BLOCKING RF Frequency = 954 MHz ±2 MHz ±10 MHz ±60 MHz IMAGE CHANNEL ATTENUATION 954 MHz Test Conditions/Comments At PER = 1%, RF frequency = 954 MHz, LNA and PA matched separately, packet length = 20 octets, packet mode Frequency deviation = 25 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 50 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 40 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 100 kHz, IF filter bandwidth = 200 kHz Frequency deviation = 80 kHz, IF filter bandwidth = 200 kHz Receiver LO frequency (fLO) = 914.8 MHz, fSOURCE1 = fLO + 0.4 MHz, fSOURCE2 = fLO + 0.7 MHz Desired signal at −87 dBm, CW interferer power level increased until BER = 62−6, image calibrated IF BW = 100 kHz, wanted signal: fDEV = 25 kHz, DR = 50 kbps Uncalibrated/internal calibration; using an IF of 200 kHz, −400 kHz is the image frequency Desired signal at −87 dBm, data rate = 50 kbps, frequency deviation = 25 kHz, RF frequency = 954 MHz Desired signal 3 dB above the input sensitivity level, data rate = 50 kbps, CW interferer power level increased until BER = 10−3 (see the Typical Performance Characteristics section for blocking at other offsets and IF bandwidths), image calibrated 65 72 76 36/43.8 Rev. D | Page 10 of 104 dB dB dB dB Measured as image attenuation at the IF filter output, carrier wave interferer at 400 kHz below the channel frequency, 100 kHz IF filter bandwidth Uncalibrated/calibrated Data Sheet Parameter AFC Accuracy Maximum Pull-In Range 300 kHz IF Filter Bandwidth 200 kHz IF Filter Bandwidth 150 kHz IF Filter Bandwidth 100 kHz IF Filter Bandwidth PREAMBLE LENGTH AFC Off, AGC Lock on Sync Word Detection 38.4 kbps 300 kbps AFC On, AFC and AGC Lock on Preamble Detection 9.6 kbps 38.4 kbps 50 kbps 100 kbps 150 kbps 200 kbps 300 kbps AFC On, AFC and AGC Lock on Sync Word Detection 38.4 kbps 300 kbps RSSI Range at Input Linearity Absolute Accuracy SATURATION (MAXIMUM INPUT LEVEL) 2FSK/GFSK/MSK/GMSK LNA INPUT IMPEDANCE Receive Mode fRF = 915 MHz fRF = 954 MHz Transmit Mode fRF = 915 MHz fRF = 954 MHz Rx SPURIOUS EMISSIONS 2 Maximum < 1 GHz Maximum > 1 GHz 1 2 ADF7023-J Min Typ Max 1 Unit Test Conditions/Comments kHz Achievable pull-in range dependent on discriminator bandwidth and modulation ±150 ±100 ±75 ±50 kHz kHz kHz kHz 8 24 Bits Bits 46 44 50 52 54 58 64 Bits Bits Bits Bits Bits Bits Bits 14 32 Bits Bits −97 to −26 ±2 ±3 dBm dB dB 12 dBm 75.9 − j32.3 74.6 − j32.5 Ω 7.7 + j8.6 7.7 + j8.9 Ω Ω −66 −62 dBm dBm Sync word length 24 bits Sync word tolerance = 0 Sync word tolerance = 1 Ω Sensitivity for combined matching network case is typically 1 dB less than separate matching networks. Follow the matching and layout guidelines to achieve the relevant ARIB-T96/TELEC T-245 specifications. Rev. D | Page 11 of 104 Minimum number of preamble bits to ensure the minimum PER across the full input power range (see Table 41) Sync word length 24 bits Sync word tolerance = 0 Sync word tolerance = 1 At antenna input, unfiltered conductive At antenna input, unfiltered conductive ADF7023-J Data Sheet TIMING AND DIGITAL SPECIFICATIONS Table 4. Parameter Rx AND Tx TIMING PARAMETERS Min Typ Max Unit PHY_ON to PHY_RX (on CMD_PHY_RX) 300 µs PHY_ON to PHY_TX (on CMD_PHY_TX) 296 µs LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL GPIO Rise/Fall GPIO Load Maximum Output Current ATB OUTPUTS ADCIN_ATB3 and ATB4 Output High Voltage, VOH Output Low Voltage, VOL Maximum Output Current XOSC32KP_GP5_ATB1 and XOSC32KN_ATB2 Output High Voltage, VOH Output Low Voltage, VOL Maximum Output Current 0.7 × VDD 0.2 × V DD ±1 10 VDD − 0.4 0.4 5 10 5 Test Conditions/Comments See the State Transition and Command Timing section for more details Includes VCO calibration and synthesizer settling Includes VCO calibration and synthesizer settling, does not include PA ramp-up V V µA pF V V ns pF mA IOH = 500 µA IOL = 500 µA Used for external PA and LNA control 1.8 0.1 0.5 V V mA VDD 0.1 5 V V mA Rev. D | Page 12 of 104 Data Sheet ADF7023-J AUXILARY BLOCK SPECIFICATIONS Table 5. Parameter 32 kHz RC OSCILLATOR Frequency Frequency Accuracy Frequency Drift Temperature Coefficient Voltage Coefficient Calibration Time 32 kHz XTAL OSCILLATOR Frequency Start-Up Time WAKE UP CONTROLLER (WUC) Hardware Timer Wake-Up Period Firmware Timer Wake-Up Period ADC Resolution DNL INL Conversion Time Input Capacitance BATTERY MONITOR Absolute Accuracy Alarm Voltage Setpoint Alarm Voltage Step Size Start-Up Time Current Consumption TEMPERATURE SENSOR Range Resolution Accuracy of Temperature Readback Min Typ Max Unit Test Conditions/Comments 32.768 1.5 kHz % After calibration After calibration at 25°C 0.14 4 1.25 %/°C %/V ms 32.768 630 kHz ms 61 × 10−6 1.31 × 105 sec 1 216 Hardware periods 8 ±1 ±1 1 12.4 Bits LSB LSB 32.768 kHz crystal with 7 pF load capacitance Firmware counter counts of the number of hardware wake-ups, resolution of 16 bits Maximum input voltage at ADCIN_ATB3 is 1.8 V VDD from 2.2 V to 3.6 V, TA = 25°C VDD from 2.2 V to 3.6 V, TA = 25°C µs pF ±45 mV V mV µs µA When enabled 0.3 °C °C With averaging +7/−4 °C ±4 °C ±3 °C 1.7 2.7 62 100 30 −40 +85 Rev. D | Page 13 of 104 5-bit resolution Overtemperature range −40°C to +85°C (calibrated at +25°C) Overtemperature range −36°C to +84°C (calibrated at +25°C) Overtemperature range −12°C to +79°C (calibrated at +25°C) ADF7023-J Data Sheet GENERAL SPECIFICATIONS Table 6. Parameter TEMPERATURE RANGE, TA VOLTAGE SUPPLY VDD TRANSMIT CURRENT CONSUMPTION Single-Ended PA, 915 MHz −10 dBm 0 dBm 10 dBm 13.5 dBm Differential PA, 915 MHz −10 dBm 0 dBm 5 dBm 10 dBm POWER MODES PHY_SLEEP (Deep Sleep Mode 2) Min −40 Typ 2.2 Max +85 Unit °C Test Conditions/Comments 3.6 V Applied to VDDBAT1 and VDDBAT2 In the PHY_TX state, single-ended PA matched to 50 Ω, differential PA matched to 100 Ω, separate single-ended PA and LNA match, combined differential PA and LNA match 10.3 13.3 24.1 32.1 mA mA mA mA 9.3 12 16.7 28 mA mA mA mA 0.18 µA PHY_SLEEP (Deep Sleep Mode 1) 0.33 µA PHY_SLEEP (RCO Wake Mode) 0.75 µA PHY_SLEEP (XTO Wake Mode) 1.28 µA PHY_OFF 1 mA PHY_ON 1 mA 11.9 12.8 mA mA 21.78 µA 11.75 µA PHY_RX (ADC, AGC Off ) PHY_RX (ADC, AGC On) SMART WAKE MODE Rev. D | Page 14 of 104 Sleep mode, wake-up configuration values (BBRAM) not retained Sleep mode, wake-up configuration values (BBRAM) retained WUC active, RC oscillator running, wake-up configuration values retained (BBRAM) WUC active, 32 kHz crystal running, wake-up configuration values retained (BBRAM) Device in PHY_OFF state, 26 MHz oscillator running, digital and synthesizer regulators active, all register values retained Device in PHY_ON state, 26 MHz oscillator running, digital, synthesizer, VCO, and RF regulators active, baseband filter calibration performed, all register values retained Device in PHY_Rx state, ADC off, manual AGC gain Device in PHY_RX state Average current consumption Autonomous reception every 1 sec, with receive dwell time of 1.25 ms, using RC oscillator, data rate = 38.4 kbps Autonomous reception every 1 sec, with receive dwell time of 0.5 ms, using RC oscillator, data rate = 300 kbps Data Sheet ADF7023-J TIMING SPECIFICATIONS VDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, VGND = GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Table 7. SPI Interface Timing Parameter t2 t3 t4 t5 t6 t7 t8 t9 t11 t12 t13 t14 t15 Limit 85 85 85 170 10 5 5 85 270 310 20 20 25 Unit ns min ns min ns min ns min ns max ns min ns min ns min ns min µs typ ns max ns max µs max Test Conditions/Comments CS low to SCLK setup time SCLK high time SCLK low time SCLK period SCLK falling edge to MISO delay MOSI to SCLK rising edge setup time MOSI to SCLK rising edge hold time SCLK falling edge to CS hold time CS high time CS low to MISO high wake-up time, 26 MHz crystal with 7 pF load capacitance, TA = 25°C SCLK rise time SCLK fall time Communications processor initialization time. Do not issue a command during this time. Alternatively, poll status word and wait for the CMD_READY bit to go high. Timing Diagrams CS t11 t2 t3 t4 t13 t5 t14 t9 SCLK t6 BIT 7 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 2 1 0 7 BIT 0 X BIT 7 t8 t7 MOSI BIT 6 7 6 5 4 3 7 Figure 2. SPI Interface Timing CS t9 t15 7 SCLK t12 6 5 4 3 2 1 0 t6 MISO SLEEP SPI READY WAKE UP Figure 3. PHY_SLEEP to SPI Ready State Timing (SPI Ready T12 After Falling Edge of CS) Rev. D | Page 15 of 104 09555-003 X SPI STATE 09555-002 MISO ADF7023-J Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Connect the exposed paddle of the LFCSP package to ground. Table 8. Parameter VDDBAT1, VDDBAT2 to GND Operating Temperature Range Industrial Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature Rating −0.3 V to +3.96 V −40°C to +85°C −65°C to +125°C 150°C 26°C/W 260°C 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance, RF integrated circuit with an ESD rating of 16 BITS LSB SYNC_BYTE_0 SYNC_BYTE_1 SYNC_BYTE_2 APPEND UNUSED BITS WITH PREAMBLE (0101..) MSB 16 BITS ≥ SYNC_WORD_LENGTH > 8 BITS LSB SYNC_BYTE_1 SYNC_BYTE_2 APPEND UNUSED BITS WITH PREAMBLE (0101..) MSB SYNC_BYTE_2 APPEND UNUSED BITS WITH PREAMBLE (0101..) Figure 53. Transmit Sync Word Configuration Rev. D | Page 41 of 104 09555-068 SYNC_WORD_LENGTH ≤ 8 BITS LSB ADF7023-J Data Sheet Table 18. Sync Word Programming Examples Required Sync Word (Binary, First Bit Being First in Time) 000100100011010001010110 111010011100101000100 0001001000110100 011100001110 00010010 011100 SYNC_ BYTE_0 1 0x12 0x5D 0xXX 0xXX 0xXX 0xXX SYNC_ BYTE_11 0x34 0x39 0x12 0x57 0xXX 0xXX SYNC_ BYTE_2 0x56 0x44 0x34 0x0E 0x12 0x5C Transmitted Sync Word (Binary, First Bit Being First in Time) 0001_0010_0011_0100_0101_0110 0101_1101_0011_1001_0100_0100 0001_0010_0011_0100 0101_0111_0000_1110 0001_0010 0101_1100 Receiver Sync Word Match Length (Bits) 24 21 16 12 8 6 X = don’t care. Choice of Sync Word The sync word should be chosen to have low correlation with the preamble and have good autocorrelation properties. When the AFC is set to lock on detection of sync word (AFC_LOCK_MODE = 3 and PREAMBLE_MATCH = 0), the sync word should be chosen to be dc free, and it should have a run length limit not greater than four bits. PAYLOAD The host processor writes the transmit data payload to the packet RAM. The location of the transmit data in the packet RAM is defined by the TX_BASE_ADR value register (Address 0x124). The TX_BASE_ADR value is the location of the first byte of the transmit payload data in the packet RAM. On reception of a valid sync word, the communications processor automatically loads the receive payload to the packet RAM. The RX_BASE_ADR register value (Address 0x125) sets the location in the packet RAM of the first byte of the received payload. For more details on packet RAM memory, see the ADF7023-J Memory Map section. The communications processor calculates the actual received payload length as RxPayload Length = Length + LENGTH_OFFSET − 4 where: Length is the length field (the first byte in the received payload). LENGTH_OFFSET is a programmable offset (set in the PACKET_LENGTH_CONTROL register (Address 0x126). The LENGTH_OFFSET value allows compatibility with systems where the length field in the proprietary packet may also include the length of the CRC and/or the sync word. The ADF7023-J defines the payload length as the number of bytes from the end of the sync word to the start of the CRC. In variable packet length mode, the PACKET_LENGTH_MAX value defines the maximum packet length that can be received, as described in Figure 54. TX PAYLOAD LENGTH = PACKET_LENGTH_MAX + LENGTH_OFFSET - 4 RX PAYLOAD LENGTH = PACKET_LENGTH_MAX + LENGTH_OFFSET - 4 FIXED PREAMBLE Byte Orientation The over-the-air arrangement of each transmitted packet RAM byte can be set to MSB first or LSB first using the DATA_BYTE setting in the PACKET_LENGTH_CONTROL register (Address 0x126). The same orientation setting should be used on the transmit and receive sides of the RF link. Packet Length Modes The ADF7023-J can be used in both fixed and variable length packet systems. Fixed or variable length packet mode is set using the PACKET_LEN variable setting in the PACKET_ LENGTH_CONTROL register (Address 0x126). For a fixed packet length system, the length of the transmit and received payload is set by the PACKET_LENGTH_MAX register (Address 0x127). The payload length is defined as the number of bytes from the end of the sync word to the start of the CRC. In variable packet length mode, the communications processor extracts the length field from the received payload data. In transmit mode, the length field must be the first byte in the transmit payload. SYNC WORD PAYLOAD CRC TX PAYLOAD LENGTH = LENGTH + LENGTH_OFFSET - 4 RX PAYLOAD LENGTH = LENGTH + LENGTH_OFFSET - 4 VARIABLE PREAMBLE SYNC LENGTH WORD PAYLOAD CRC 09555-125 1 SYNC_WORD_ LENGTH Bits in SYNC_CONTROL Register (0x120) 24 21 16 12 8 6 Figure 54. Payload Length in Fixed and Variable Length Packet Modes Addressing The ADF7023-J provides a very flexible address-matching scheme, allowing matching of a single address, multiple addresses, and broadcast addresses. Addresses of up to 32 bits in length are supported. The address information can be included at any section of the transmit payload. The location of the starting byte of the address data in the received payload is set in the ADDRESS_MATCH_OFFSET register (Address 0x129), as illustrated in Figure 55. The number of bytes in the first address field is set in the ADDRESS_LENGTH register (Address 0x12A). These settings allow the communications processor to extract the address information from the received packet. Rev. D | Page 42 of 104 Data Sheet ADF7023-J The address data is then compared against a list of known addresses that are stored in BBRAM (Address 0x12B to Address 0x137). Each stored address byte has an associated mask byte, thereby allowing matching of partial sections of the address bytes, which is useful for checking broadcast addresses or a family of addresses that have a unique identifier in the address sequence. The format and placement of the address information in the payload data should match the address check settings at the receiver to ensure exact address detection and qualification. Table 19 shows the register locations in the BBRAM that are used for setup of the address checking. When Register 0x12A (number of bytes in the first address field) is set to 0x00, address checking is disabled. Note that if static register fixes are employed (see Table 90), then the space available for address matching will be reduced. PREAMBLE ADDRESS DATA SYNC WORD PAYLOAD CRC 09555-126 ADDRESS_MATCH_OFFSET Figure 55. Address Match Offset Table 19. Address Check Register Setup Address (BBRAM) 0x129, ADDRESS_MATCH_ OFFSET Description1 Position of first address byte in the received packet (first byte after sync word = 0) Number of bytes in the first address field (NADR_1) Address 1 Match Byte 0 Address 1 Mask Byte 0 Address 1 Match Byte 1 Address 1 Mask Byte 1 … Address 1 Match Byte NADR_1 − 1 Address 1 Mask Byte NADR_1 − 1 0x00 to end or NADR_2 for another address check sequence 0x12A, ADDRESS_LENGTH 0x12B 0x12C 0x12D 0x12E … 1 NADR_1 = the number of bytes in the first address field; NADR_2 = the number of bytes in the second address field. The host processor should set the INTERRUPT_ADDRESS_ MATCH bit in the INTERRUPT_SOURCE_0 register (Address 0x336) if an interrupt is required on the IRQ_GP3 pin. Additional information on interrupts is contained in the Interrupt Generation section. Example Address Check Consider a system with 16-bit address lengths, in which the first byte is located in the 10th byte of the received payload data. The system also uses broadcast addresses in which the first byte is always 0xAA. To match the exact address, 0xABCD or any broadcast address in the form 0xAAXX, the ADF7023-J must be configured as shown in Table 20. Table 20. Example Address Check Configuration BBRAM Address 0x129 0x12A Value 0x09 0x02 0x12B 0x12C 0x12D 0x12E 0x12F 0xAB 0xFF 0xCD 0xFF 0x02 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0xAA 0xFF 0x00 0x00 0x00 0xXX 0xXX 0xXX Description Location in payload of the first address byte Number of bytes in the first address field, NADR_1 = 2 Address 1 Match Byte 0 Address 1 Mask Byte 0 Address 1 Match Byte 1 Address 1 Mask Byte 1 Number of bytes in the second address field, NADR_2 = 2 Address 2 Match Byte 0 Address 2 Mask Byte 0 Address 2 Match Byte 1 Address 2 Mask Byte 1 End of addresses (indicated by 0x00) Don’t care Don’t care Don’t care CRC An optional CRC-16 can be appended to the packet by setting CRC_EN =1 in the PACKET_LENGTH_CONTROL register (Address 0x126). In receive mode, this bit enables CRC detection on the received packet. A default polynomial is used if PROG_CRC_EN = 0 in the SYMBOL_MODE register (Address 0x11C). The default CRC polynomial is g(x) = x16 + x12 + x5 + 1 Any other 16-bit polynomial can be used if PROG_CRC_EN = 1, and the polynomial is set in CRC_POLY_0 and CRC_POLY_1 (Address 0x11E and Address 0x11F, respectively). The setup of the CRC is described in Table 21. The CRC is initialized with 0x0000. Table 21.CRC Setup CRC_EN Bit in the PACKET_LENGTH CONTROL Register 0 1 PROG_CRC_EN Bit in the SYMBOL_MODE Register X1 0 1 1 1 Description CRC is disabled in transmit, and CRC detection is disabled in receive. CRC is enabled in transmit, and CRC detection is enabled in receive, with the default CRC polynomial. CRC is enabled in transmit, and CRC detection is enabled in receive, with the CRC polynomial defined by CRC_POLY_0 and CRC_POLY_1. X = don’t care. Rev. D | Page 43 of 104 ADF7023-J Data Sheet POSTAMBLE To convert a user-defined polynomial to the 2-byte value, the polynomial should be written in binary format. The x16 coefficient is assumed equal to 1 and is, therefore, discarded. The remaining 16 bits then make up CRC_POLY_0 (most significant byte) and CRC_POLY_1 (least significant byte). Two examples of setting common 16-bit CRCs are shown in Table 22. The communications processor automatically appends two bytes of postamble to the end of the transmitted packet. Each byte of the postamble is 0x55. The first byte is transmitted immediately after the CRC. The PA ramp-down begins immediately after the first postamble byte. The second byte is transmitted while the PA is ramping down. Table 22. Example Programming of CRC_POLY_0 and CRC_POLY_1 Polynomial x16 + x15 + x2 + 1 (CRC-16-IBM) x16 + x13 + x12 + x11 x10 + x8 + x6 + x5 + x2 + 1 (CRC-16-DNP) Binary Format 1_1000_0000_ 0000_0101 1_0011_1101_ 0110_0101 CRC_POLY_0 0x80 CRC_POLY_1 0x05 0x3D 0x65 On the receiver, if the received packet is valid, the RSSI is automatically measured during the first postamble byte, and the result is stored in the RSSI_READBACK register (Address 0x312). The RSSI is measured by the communications processor 17 µs after the last CRC bit. TRANSMIT PACKET TIMING The PA ramp timing in relation to the transmit packet data is described in Figure 56. After the CMD_PHY_TX command is issued, a VCO calibration is carried out, followed by a delay for synthesizer settling. The PA ramp follows the synthesizer settling. After the PA starts to ramp up at the programmed rate, there is 1-byte delay before the start of modulation (preamble). At the beginning of the second byte of postamble, the PA ramps down. The communications processor then transitions to the PHY_ON state or the PHY_RX state (if the TX_TO_RX_AUTO_TURNAROUND is enabled or the CMD_PHY_RX command is issued). To enable CRC detection on the receiver, with the default CRC or user-defined 16-bit CRC, CRC_EN in the PACKET_LENGTH_ CONTROL register (Address 0x126) should be set to 1. An interrupt can be generated on reception of a CRC verified packet (see the Interrupt Generation section). STATE TRANSITION TIME TO PHY_TX (See Table 12) RAMP TIME 1 BYTE RAMP TIME CMD_PHY_TX PA OUTPUT COMMUNICATIONS PROCESSOR FW_STATE PREAMBLE 142µs 55µs VCO CAL SYNTH PA RAMP = 0x00 (BUSY) SYNC WORD PAYLOAD PHY_TX = 0x14 (PHY_TX) Figure 56. Transmit Packet Timing Rev. D | Page 44 of 104 CRC POSTAMBLE PA RAMP 09555-227 TX DATA Data Sheet ADF7023-J DATA WHITENING Data whitening can be employed to avoid long runs of 1s or 0s in the transmitted data stream. This ensures sufficient bit transitions in the packet, which aids in receiver clock and data recovery because the encoding breaks up long runs of 1s or 0s in the transmit packet. The data, excluding the preamble and sync word, is automatically whitened before transmission by XOR’ing the data with an 8-bit pseudorandom sequence. At the receiver, the data is XOR’ed with the same pseudorandom sequence, thereby reversing the whitening. The linear feedback shift register polynomial used is x7 + x1 + 1. Data whitening and dewhitening are enabled by setting DATA_WHITENING = 1 in the SYMBOL_MODE register (Address 0x11C). MANCHESTER ENCODING Manchester encoding can be used to ensure a dc-free (zero mean) transmission. The encoded over-the-air bit rate (chip rate) is double the rate set by the DATA_RATE variable (Address 0x10C and Address 0x10D). A Binary 0 is mapped to 10, and a Binary 1 is mapped to 01. Manchester encoding and decoding are applied to the payload data and the CRC. Manchester encoding and decoding are enabled by setting MANCHESTER_ENC = 1 in the SYMBOL_MODE register (Address 0x11C). 8b/10b ENCODING 8b/10b encoding is a byte-orientated encoding scheme that maps an 8-bit byte to a 10-bit data block. It ensures that the maximum number of consecutive 1s or 0s (that is, run length) in any 10-bit transmitted symbol is five. The advantage of this encoding scheme is that dc balancing is employed without the efficiency loss of Manchester encoding. The rate loss for 8b/10b encoding is 0.8, whereas for Manchester encoding, it is 0.5. Encoding and decoding are applied to the payload data and the CRC. The 8b/10b encoding and decoding are enabled by setting EIGHT_TEN_ENC =1 in the SYMBOL_MODE register (Address 0x11C). Rev. D | Page 45 of 104 ADF7023-J Data Sheet INTERRUPT GENERATION The ADF7023-J uses a highly flexible, powerful interrupt system with support for MAC level interrupts and PHY level interrupts. To enable an interrupt source, the corresponding mask bit must be set. When an enabled interrupt occurs, the IRQ_GP3 pin goes high, and the interrupt bit of the status word is set to Logic 1. The host processor can use either the IRQ_GP3 pin or the status word to check for an interrupt. After an interrupt is asserted, the ADF7023-J continues operations unaffected, unless it is directed to do otherwise by the host processor. An outline of the interrupt source and mask system is shown in Table 23. Following an interrupt condition, the host processor should clear the relevant interrupt flag so that further interrupts assert the IRQ_GP3 pin. This is performed by writing a Logic 1 to the bit that is high in either the INTERRUPT_SOURCE_0 or the INTERRUPT_SOURCE_1 register. If multiple bits in the interrupt source registers are high, they can be cleared individually or altogether by writing Logic 1 to them. The IRQ_GP3 pin goes low when all the interrupt source bits are cleared. As an example, take the case where a battery alarm (in the INTERRUPT_SOURCE_1 register) interrupt occurs. The host processor should do the following: MAC interrupts can be enabled by writing a Logic 1 to the relevant bits of the INTERRUPT_MASK_0 register (Address 0x100) and PHY level interrupts by writing a Logic 1 to the relevant bits of the INTERRUPT_MASK_1 register (Address 0x101). The structure of these memory locations is described in Table 23. 1. In the case of an interrupt condition, the interrupt source can be determined by reading the INTERRUPT_SOURCE_0 register (Address 0x336) and the INTERRUPT_SOURCE_1 register (Address 0x337). The bit that corresponds to the relevant interrupt condition is high. The structure of these two registers is shown in Table 24. 3. 2. Read the interrupt source registers. In this example, if none of the interrupt flags in INTERRUPT_SOURCE_0 are enabled, only INTERRUPT_SOURCE_1 must be read. Clear the interrupt by writing 0x80 (or 0xFF) to INTERRUPT_SOURCE_1. Respond to the interrupt condition. Table 23. Structure of the Interrupt Mask Registers Register INTERRUPT_MASK_0, Address 0x100 Bit 7 Name INTERRUPT_NUM_WAKEUPS 6 INTERRUPT_SWM_RSSI_DET 5 INTERRUPT_AES_DONE 4 INTERRUPT_TX_EOF 3 INTERRUPT_ADDRESS_MATCH 2 INTERRUPT_CRC_CORRECT 1 INTERRUPT_SYNC_DETECT 0 INTERRUPT_PREAMBLE_DETECT Description Interrupt when the number of WUC wake-ups (NUMBER_OF_WAKEUPS[15:0]) has reached the threshold (NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0]) 1: interrupt enabled; 0: interrupt disabled Interrupt when the measured RSSI during smart wake mode has exceeded the RSSI threshold value (SWM_RSSI_THRESH, Address 0x108) 1: interrupt enabled; 0: interrupt disabled Interrupt when an AES encryption or decryption command is complete; available only when the AES firmware module has been loaded to the ADF7023-J program RAM 1: interrupt enabled; 0: interrupt disabled Interrupt when a packet has finished transmitting 1: interrupt enabled; 0: interrupt disabled Interrupt when a received packet has a valid address match 1: interrupt enabled; 0: interrupt disabled Interrupt when a received packet has the correct CRC 1: interrupt enabled; 0: interrupt disabled Interrupt when a qualified sync word has been detected in the received packet 1: interrupt enabled; 0: interrupt disabled Interrupt when a qualified preamble has been detected in the received packet 1: interrupt enabled; 0: interrupt disabled Rev. D | Page 46 of 104 Data Sheet Register INTERRUPT_MASK_1, Address 0x101 ADF7023-J Bit 7 Name BATTERY_ALARM 6 CMD_READY 5 4 Reserved WUC_TIMEOUT 3 2 1 Reserved Reserved SPI_READY 0 CMD_FINISHED Description Interrupt when the battery voltage has dropped below the threshold value (BATTERY_MONITOR_THRESHOLD_VOLTAGE, Address 0x32D) 1: interrupt enabled; 0: interrupt disabled Interrupt when the communications processor is ready to load a new command; mirrors the CMD_READY bit of the status word 1: interrupt enabled; 0: interrupt disabled Interrupt when the WUC has timed out 1: interrupt enabled; 0: interrupt disabled Interrupt when the SPI is ready for access 1: interrupt enabled; 0: interrupt disabled Interrupt when the communications processor has finished performing a command 1: interrupt enabled; 0: interrupt disabled Table 24. Structure of the Interrupt Source Registers Register INTERRUPT_SOURCE_0, Address: 0x336 INTERRUPT_SOURCE_1, Address: 0x337 Bit 7 Name INTERRUPT_NUM_WAKEUPS 6 INTERRUPT_SWM_RSSI_DET 5 INTERRUPT_AES_DONE 4 3 INTERRUPT_TX_EOF INTERRUPT_ADDRESS_MATCH 2 1 INTERRUPT_CRC_CORRECT INTERRUPT_SYNC_DETECT 0 INTERRUPT_PREAMBLE_DETECT 7 BATTERY_ALARM 6 CMD_READY 5 4 3 2 1 0 Reserved WUC_TIMEOUT Reserved Reserved SPI_READY CMD_FINISHED Interrupt Description Asserted when the number of WUC wake-ups (NUMBER_OF_WAKEUPS[15:0]) has reached the threshold (NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0]) Asserted when the measured RSSI during smart wake mode has exceeded the RSSI threshold value (SWM_RSSI_THRESH, Address 0x108) Asserted when an AES encryption or decryption command is complete; available only when the AES firmware module has been loaded to the ADF7023-J program RAM Asserted when a packet has finished transmitting (packet mode only) Asserted when a received packet has a valid address match (packet mode only) Asserted when a received packet has the correct CRC (packet mode only) Asserted when a qualified sync word has been detected in the received packet Asserted when a qualified preamble has been detected in the received packet Asserted when the battery voltage has dropped below the threshold value (BATTERY_MONITOR_THRESHOLD_VOLTAGE, Address 0x32D) Asserted when the communications processor is ready to load a new command; mirrors the CMD_READY bit of the status word Asserted when the WUC has timed out Asserted when the SPI is ready for access Asserted when the communications processor has finished performing a command Rev. D | Page 47 of 104 ADF7023-J Data Sheet INTERRUPTS IN SPORT MODE In sport mode, the interrupts from INTERRUPT_SOURCE_1 are all available. However, only INTERRUPT_NUM_WAKEUPS, INTERRUPT_SWM_RSSI_DET, INTERRUPT_PREAMBLE_ DETECT and INTERRUPT_SYNC_DETECT are available from INTERRUPT_SOURCE_0. A second interrupt pin is provided on GP4, which gives a dedicated sport mode interrupt on either preamble or sync word detection. For more details, see the Sport Mode section. Following receipt of the packet in SPORT mode, re-issue the PHY_RX command to re-enable the interrupts for the next packet. Rev. D | Page 48 of 104 Data Sheet ADF7023-J ADF7023-J MEMORY MAP 11-BIT ADDRESSES 0x3FF ADDRESS [12:0] PROGRAM RAM 2kB MCR 256 BYTES 0x300 CS NOT USED MISO PROGRAM ROM 4kB SPI SCLK COMMS PROCESSOR CLOCK COMMS PROCESSOR 8-BIT RISC ENGINE BBRAM 64 BYTES 0x100 0x0FF SPI/CP MEMORY ARBITRATION INSTRUCTION/DATA [7:0] ADDRESS/ DATA MUX 0x13F PACKET RAM 256 BYTES ADDRESS[10:0] 0x010 0x00F DATA[7:0] RESERVED 0x000 09555-070 MOSI Figure 57. ADF7023-J Memory Map This section describes the various memory locations used by the ADF7023-J. The radio control, packet management, and smart wake mode capabilities of the part are realized using an integrated RISC processor, which executes instructions stored in the embedded program ROM. There is also a local RAM, subdivided into three sections, that is used as a data packet buffer, both for transmitted and received data (packet RAM), and for storing the radio and packet management configuration (BBRAM and MCR). The RAM addresses of these memory banks are 11 bits long. MODEM CONFIGURATION RAM (MCR) The 256-byte modem configuration RAM (MCR) contains the various registers used for direct control or observation of the physical layer radio blocks of the ADF7023-J. The contents of the MCR are not retained in the PHY_SLEEP state. PROGRAM ROM The program ROM consists of 4 kB of nonvolatile memory. It contains the firmware code for radio control, packet management, and smart wake mode. BBRAM PROGRAM RAM The battery backup RAM contains the main radio and packet management registers used to configure the radio. On application of battery power to the ADF7023-J for the first time, the entire BBRAM should be initialized by the host processor with the appropriate settings. After the BBRAM is written to, the CMD_CONFIG_DEV command should be issued to update the radio and communications processor with the current BBRAM settings. The CMD_CONFIG_DEV command can be issued in the PHY_OFF state or the PHY_ON state only. The program RAM consists of 2 kB of volatile memory. This memory space is used for software modules, such as AES encryption, IR calibration, and Reed-Solomon coding, which are available from Analog Devices. The software modules are downloaded to the program RAM memory space over the SPI by the host processor. See the Downloadable Firmware Modules section for details on loading a firmware module to program RAM. The BBRAM is used to maintain settings needed at wake-up from sleep mode by the wake-up controller. Upon wake-up from sleep, in smart wake mode, the BBRAM contents are read by the on-chip processor to recover the packet management and radio parameters. Rev. D | Page 49 of 104 ADF7023-J Data Sheet PACKET RAM The packet RAM consists of 256 bytes of memory space. The first 16 bytes of this memory space are allocated for use by the on-chip processor. The remaining 240 bytes of this memory space are allocated for storage of data from valid received packets and packet data to be transmitted. The communications processor stores received payload data at the memory location indicated by the value of the RX_BASE_ADR register (Address 0x125), the receive address pointer. The value of the TX_BASE_ADR TRANSMIT AND RECEIVE PACKET TX_BASE_ADR 0x010 TX_BASE_ADR RX_BASE_ADR register (Address 0x124), the transmit address pointer, determines the start address of data to be transmitted by the communications processor. This memory can be arbitrarily assigned to store single or multiple transmit or receive packets, with and without overlap. The RX_BASE_ADR value should be chosen to ensure that there is enough allocated packet RAM space for the maximum receiver payload length. 240 BYTE TRANSMIT OR RECEIVE PACKET 0x010 TX_BASE_ADR (PACKET 1) MULTIPLE TRANSMIT AND RECEIVE PACKETS 0x010 TRANSMIT PAYLOAD TRANSMIT PAYLOAD TX_BASE_ADR (PACKET 2) TRANSMIT PAYLOAD 2 RX_BASE_ADR (PACKET 1) TRANSMIT OR RECEIVE PAYLOAD RX_BASE_ADR RECEIVE PAYLOAD RECEIVE PAYLOAD RX_BASE_ADR (PACKET 2) 0x0FF 0x0FF Figure 58. Example Packet RAM Configurations Using the Tx Packet and Rx Packet Address Pointers Rev. D | Page 50 of 104 0x0FF 09555-071 RECEIVE PAYLOAD 2 Data Sheet ADF7023-J SPI INTERFACE GENERAL CHARACTERISTICS STATUS WORD The ADF7023-J is equipped with a 4-wire SPI interface, using the SCLK, MISO, MOSI, and CS pins. The ADF7023-J always acts as a slave to the host processor. Figure 59 shows an example connection diagram between the processor and the ADF7023-J. The diagram also shows the direction of the signal flow for each pin. The SPI interface is active, and the MISO outputs enabled, only while the CS input is low. The interface uses a word length of eight bits, which is compatible with the SPI hardware of most processors. The data transfer through the SPI interface occurs with the most significant bit first. The MOSI input is sampled at the rising edge of SCLK. As commands or data are shifted in from the MOSI input at the SCLK rising edge, the status word or data is shifted out at the MISO pin synchronous with the SCLK clock falling edge. If CS is brought low, the most significant bit of the status word appears on the MISO output without the need for a rising clock edge on the SCLK input. The status word of the ADF7023-J is automatically returned over the MISO each time a byte is transferred over the MOSI. Shifting in double SPI_NOP commands (see Table 27) causes the status word to be shifted out as shown in Figure 61. The meaning of the various bit fields is illustrated in Table 25. The FW_STATE variable can be used to read the current state of the communications processor and is described in Table 26. If it is busy performing an action or state transition, FW_STATE is busy. The FW_STATE variable also indicates the current state of the radio. Figure 59. SPI Interface Connections COMMAND ACCESS The ADF7023-J is controlled through commands. Command words are single octet instructions that control the state transitions of the communications processor and access to the registers and packet RAM. The complete list of valid commands is given in the Command Reference section. Commands that have a CMD prefix are handled by the communications processor. Memory access commands have an SPI prefix and are handled by an independent controller. Thus, SPI commands can be issued independent of the state of the communications processor. A command is initiated by bringing CS low and shifting in the command word over the SPI, as shown in Figure 60. All commands are executed on the last positive edge of the SCLK input. The CS input must be brought high again after a command has been shifted into the ADF7023-J to enable the recognition of successsive command words. This is because a single command can be issued only during a CS low period (with the exception of a double NOP command). The ADF7023-J interrupt handler can also be configured to generate an interrupt signal on IRQ_GP3 when the communications processor is ready to accept a new command (CMD_READY in the INTERRUPT_SOURCE_1 register [Address 0x337]) or when it has finished processing a command (CMD_FINISHED in the INTERRUPT_SOURCE_1 register [Address 0x337]). CS MOSI SPI_NOP SPI_NOP MISO IGNORE STATUS Figure 61. Reading the Status Word Using a Double SPI_NOP Command Table 25. Status Word Bit [7] Name SPI_READY [6] IRQ_STATUS [5] CMD_READY [4:0] FW_STATE CS MISO CMD IGNORE 09555-027 MOSI 09555-028 HOST PROCESSOR 09555-026 ADF7023-J GPIO SCLK MOSI MISO IRQ CS SCLK MOSI MISO IRQ_GP3 The SPI_READY variable is used to indicate when the SPI is ready for access. The CMD_READY variable is used to indicate when the communications processor is ready to accept a new command. The status word should be polled and the CMD_READY bit examined before issuing a command to ensure that the communications processor is ready to accept a new command. It is not necessary to check the CMD_READY bit before issuing a SPI memory access command. It is possible to queue one command while the communications processor is busy. This is discussed in the Command Queuing section. Figure 60. Command Write (No Parameters) Rev. D | Page 51 of 104 Description 0: SPI is not ready for access. 1: SPI is ready for access. 0: no pending interrupt condition. 1: pending interrupt condition (mirrors the IRQ_GP3 pin). 0: the radio controller is not ready to receive a radio controller command. 1: the radio controller is ready to receive a radio controller command. Indicates the ADF7023-J state (in Table 26). ADF7023-J Data Sheet Table 26. FW_STATE Description COMMAND QUEUING Value 0x0F 0x00 0x11 0x12 0x13 0x14 0x06 0x05 0x08 0x09 0x0A The CMD_READY status bit is used to indicate that the command queue used by the communications processor is empty. The queue is one command deep. The FW_STATE bit is used to indicate the state of the communications processor. The operation of the status word and these bits is illustrated in Figure 62 when a CMD_PHY_ON command is issued in the PHY_OFF state. State Initializing Busy, performing a state transition PHY_OFF PHY_ON PHY_RX PHY_TX PHY_SLEEP Performing CMD_GET_RSSI Performing CMD_AES_DECRYPT_INIT Performing CMD_AES_DECRYPT Performing CMD_AES_ENCRYPT Operation of the status word when a command is being queued is illustrated in Figure 63 when a CMD_PHY_ON command is issued in the PHY_OFF state followed quickly by a CMD_PHY_ RX command. The CMD_PHY_RX command is issued while FW_STATE is busy (that is, transitioning between the PHY_OFF and PHY_ON states) but the CMD_READY bit is high, indicating that the command queue is empty. After the CMD_PHY_RX command is issued, the CMD_READY bit transitions to a logic low, indicating that the command queue is full. After the PHY_OFF to PHY_ON transition is finished, the PHY_RX command is processed immediately by the communications processor, and the CMD_READY bit goes high, indicating that the command queue is empty and another command can be issued. ISSUE CMD_PHY_ON CS CMD_READY STATUS WORD COMMUNICATIONS PROCESSOR ACTION = 0x11 (PHY_OFF) 0xB1 = 0x00 (BUSY) = 0x12 (PHY_ON) 0xA0 0x80 0xB2 TRANSITION RADIO FROM PHY_OFF TO PHY_ON WAITING FOR COMMAND 09555-138 FW_STATE WAITING FOR COMMAND Figure 62. Operation of the CMD_READY and FW_STATE Bits in Transitioning the ADF7023-J from the PHY_OFF State to the PHY_ON State ISSUE CMD_PHY_ON ISSUE CMD_PHY_RX CS CMD_READY STATUS WORD COMMUNICATIONS PROCESSOR ACTION = 0x11 (PHY_OFF) 0xB1 WAITING FOR COMMAND = 0x00 (BUSY) 0x80 0xA0 0x12 0x80 = 0x00 (BUSY) 0xA0 0xB3 TRANSITION RADIO FROM PHY_ON TO PHY_RX WAITING FOR COMMAND 0xB2 TRANSITION RADIO FROM PHY_OFF TO PHY_ON = 0x13 (PHY_RX) IN PHY_ON, READING NEW COMMAND Figure 63. Command Queuing and Operation of the CMD_READY and FW_STATE Bits in Transitioning the ADF7023-J from the PHY_OFF State to the PHY_ON State and Then to the PHY_RX State Rev. D | Page 52 of 104 09555-139 FW_STATE Data Sheet ADF7023-J MEMORY ACCESS Block Write Memory locations are accessed by invoking the relevant SPI command. An 11-bit address is used to identify registers or locations in the memory space. The most significant three bits of the address are incorporated into the SPI command by appending them as the LSBs of the command word. Figure 64 illustrates command, address, and data partitioning. The various SPI memory access commands are different, depending on the memory location being accessed (see Table 27). MCR, BBRAM, and packet RAM memory locations can be written to in block format using the SPI_MEM_WR command. The SPI_MEM_WR command code is 00011xxxb, where xxxb represent Bits[10:8] of the first 11-bit address. If more than one data byte is written, the write address is automatically incremented for every byte sent until CS is set high, which terminates the memory access command (see Figure 65 for more details). The maximum block write for the MCR, packet RAM, and BBRAM memories is 256 bytes, 256 bytes, and 64 bytes, respectively. These maximum block-write lengths should not be exceeded. An SPI command should be issued only if the SPI_READY bit in the INTERRUPT_SOURCE_1 register (Address 0x337) of the status word bit is high. The ADF7023-J interrupt handler can also be configured to generate an interrupt signal on IRQ_GP3 when the SPI_READY bit is high. An SPI command should not be issued while the communications processor is initializing (FW_STATE = 0x0F). SPI commands can be issued in any other communications processor state, including the busy state (FW_STATE = 0x00). This allows the ADF7023-J memory to be accessed while the radio is transitioning between states. Example Write 0x00 to the ADC_CONFIG_HIGH register (Address 0x35A). • • • • • The first five bits of the SPI_MEM_WR command are 00011. The 11-bit address of ADC_CONFIG_HIGH is 01101011010. The first byte sent is 00011011 or 0x1B. The second byte sent is 01011010 or 0x5A. The third byte sent is 0x00. Thus, 0x1B, 0x5A, 0x00 is written to the part. CS MEMORY ADDRESS BITS[7:0] SPI MEMORY ACCESS COMMAND DATA BYTE 5 BITS MEMORY ADDRESS BITS[10:0] DATA n × 8 BITS 09555-029 MOSI Figure 64. SPI Memory Access Command/Address Format Table 27. Summary of SPI Memory Access Commands SPI Command SPI_MEM_WR SPI_MEM_RD SPI_MEMR_WR SPI_MEMR_RD SPI_NOP Command Value 0x18 (packet RAM), 0x19 (BBRAM), 0x1B (MCR), 0x1E (program RAM) 0x38 (packet RAM), 0x39 (BBRAM), 0x3B (MCR) 0x08 (packet RAM), 0x09 (BBRAM), 0x0B (MCR) 0x28 (packet RAM), 0x29 (BBRAM), 0x2B (MCR) 0xFF Description Write data to BBRAM, MCR, or packet RAM sequentially. An 11-bit address is used to identify memory locations. The most significant three bits of the address are incorporated into the command (xxxb). This command is followed by the remaining eight bits of the address. Read data from BBRAM, MCR, or packet RAM sequentially. An 11-bit address is used to identify memory locations. The most significant three bits of the address are incorporated into the command (xxxb). This command is followed by the remaining eight bits of the address, which is subsequently followed by the appropriate number of SPI_NOP commands. Write data to BBRAM, MCR, or packet RAM nonsequentially. Read data from BBRAM, MCR, or packet RAM nonsequentially. No operation. Use for dummy writes when polling the status word. Also used as dummy data on the MOSI line when performing a memory read. Rev. D | Page 53 of 104 ADF7023-J Data Sheet Random Address Write Random Address Read MCR, BBRAM, and packet RAM memory locations can be written to in a nonsequential manner using the SPI_MEMR_WR command. The SPI_MEMR_WR command code is 00001xxxb, where xxxb represent Bits[10:8] of the 11-bit address. The lower eight bits of the address should follow this command and then the data byte to be written to the address. The lower eight bits of the next address are entered, followed by the data for that address until all required addresses within that block are written, as shown in Figure 66. MCR, BBRAM, and packet RAM memory locations can be read from memory in a nonsequential manner using the SPI_MEMR_RD command. The SPI_MEMR_RD command code is 00101xxxb, where xxxb represent Bits[10:8] of the 11-bit address. This command is followed by the remaining eight bits of the address to be written. Each subsequent address byte is then written. The last address byte to be written should be followed by two SPI_NOP commands, as shown in Figure 68. The data bytes from memory, starting at the first address location, are available after the second status byte. Program RAM Write The program RAM can be written to only by using the memory block write, as illustrated in Figure 65. SPI_MEM_WR should be set to 0x1E. See the Downloadable Firmware Modules section for details on loading a firmware module to program RAM. Block Read Example Read the value stored in the ADC_CONFIG_HIGH register. • • MCR, BBRAM, and packet RAM memory locations can be read from in block format using the SPI_MEM_RD command. The SPI_MEM_RD command code is 00111xxxb, where xxxb represent Bits[10:8] of the first 11-bit address. This command is followed by the remaining eight bits of the address to be read and then two SPI_NOP commands (dummy byte). The first byte available after writing the address should be ignored, with the second byte constituting valid data. If more than one data byte is to be read, the write address is automatically incremented for subsequent SPI_NOP commands sent. See Figure 67 for more details. • • • • The first five bits of the SPI_MEM_RD command are 00111. The 11-bit address of ADC_CONFIG_HIGH is 01101011010. The first byte sent is 00111011 or 0x3B. The second byte sent is 01011010 or 0x5A. The third byte sent is 0xFF (SPI_NOP). The fourth byte sent is 0xFF. Thus, 0x3B5AFFFF is written to the part. The value shifted out on the MISO line while the fourth byte is sent is the value stored in the ADC_CONFIG_HIGH register. MOSI MISO SPI_MEM_WR IGNORE ADDRESS DATA FOR [ADDRESS] DATA FOR [ADDRESS + 1] DATA FOR [ADDRESS + 2] DATA FOR [ADDRESS + N] STATUS STATUS STATUS STATUS STATUS 09555-030 CS Figure 65. Memory (MCR, BBRAM, or Packet RAM) Block Write MOSI MISO SPI_MEMR_WR IGNORE ADDRESS 1 DATA FOR [ADDRESS 1] ADDRESS 2 DATA FOR [ADDRESS 2] DATA FOR [ADDRESS N] STATUS STATUS STATUS STATUS STATUS Figure 66. Memory (MCR, BBRAM, or Packet RAM) Random Address Write Rev. D | Page 54 of 104 09555-142 CS Data Sheet ADF7023-J MOSI SPI_MEM_RD ADDRESS SPI_NOP SPI_NOP SPI_NOP SPI_NOP MISO IGNORE STATUS STATUS DATA FROM ADDRESS DATA FROM ADDRESS + 1 DATA FROM ADDRESS + N 09555-143 MAX N = (256-INITIAL ADDRESS) CS Figure 67. Memory (MCR, BBRAM, or Packet RAM) Block Read MOSI SPI_MEMR_RD ADDRESS 1 MISO IGNORE STATUS ADDRESS 2 STATUS ADDRESS 3 ADDRESS 4 DATA FROM ADDRESS 1 DATA FROM ADDRESS 2 ADDRESS N SPI_NOP SPI_NOP DATA FROM ADDRESS N – 2 DATA FROM ADDRESS N – 1 DATA FROM ADDRESS N Figure 68. Memory (MCR, BBRAM, or Packet RAM) Random Address Read Rev. D | Page 55 of 104 09555-144 CS ADF7023-J Data Sheet LOW POWER MODES The ADF7023-J can be configured to operate in a broad range of energy sensitive applications where battery lifetime is critical. This includes support for applications where the ADF7023-J is required to operate in a fully autonomous mode or applications where the host processor controls the transceiver during low power mode operation. These low power modes are implemented using a hardware wake-up controller (WUC), a firmware timer, and the smart wake mode functionality of the on-chip communications processor. The hardware WUC is a low power WUC that comprises a 16-bit wake-up timer with a programmable prescaler. The 32.768 kHz RCOSC or XOSC provides the clock source for the timer. The firmware timer is a software timer residing on the ADF7023-J. The firmware timer is used to count the number of WUC timeouts and can be used to count the number of ADF7023-J wake-ups. The WUC and the firmware timer, therefore, provide a real-time clock capability. Using the low power WUC and the firmware timer, the SWM firmware allows the ADF7023-J to wake up autonomously from sleep without intervention from the host processor. During this wake-up period, the ADF7023-J is controlled by the communications processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby dramatically reducing overall system current consumption. The smart wake mode can then wake the host processor on an interrupt condition. An overview of the low power mode configuration is shown in Figure 69, and the register settings that are used for the various low power modes are described in Table 28. Rev. D | Page 56 of 104 Data Sheet ADF7023-J Table 28. Settings for Low Power Modes Low Power Mode Deep Sleep Modes Memory Address Register 0x30D 1 WUC_CONFIG_LOW Bit 3 Name WUC_BBRAM_EN WUC 0x30C1 WUC_CONFIG_HIGH [2:0] WUC_PRESCALER[2:0] WUC WUC WUC 0x30D1 0x30D1 0x30D1 WUC_CONFIG_LOW WUC_CONFIG_LOW WUC_CONFIG_LOW 6 5 4 WUC_RCOSC_EN WUC_XOSC32K_EN WUC_CLKSEL WUC 0x30D1 WUC_CONFIG_LOW 0 WUC_ARM WUC 0x30E 2, 0x30F2 WUC_VALUE_HIGH WUC_VALUE_LOW [7:0] [7:0] WUC_TIMER_VALUE[15:8] WUC_TIMER_VALUE[7:0] WUC 0x101 INTERRUPT_MASK_1 4 WUC_TIMEOUT Firmware Timer 0x100 INTERRUPT_MASK_0 7 INTERRUPT_NUM_WAKEUPS Firmware Timer 0x102 0x103 0x104 [7:0] [7:0] [7:0] 7 5 NUMBER_OF_WAKEUPS[7:0] NUMBER_OF_WAKEUPS[15:8] NUMBER_OF_WAKEUPS_IRQ_ THRESHOLD[7:0] NUMBER_OF_WAKEUPS_IRQ_ THRESHOLD[15:8] SWM_EN SWM_RSSI_QUAL SWM SWM 0x11A 0x11A NUMBER_OF_WAKEUPS_0 NUMBER_OF_WAKEUPS_1 NUMBER_OF_WAKEUPS_IRQ_ THRESHOLD_0 NUMBER_OF_WAKEUPS_IRQ_ THRESHOLD_1 MODE_CONTROL MODE_CONTROL SWM 0x108 SWM_RSSI_THRESH [7:0] SWM_RSSI_THRESH[7:0] SWM SWM 0x107 0x106 PARMTIME_DIVIDER RX_DWELL_TIME [7:0] [7:0] PARMTIME_DIVIDER[7:0] RX_DWELL_TIME[7:0] Firmware Timer 0x105 [7:0] Description 0: BBRAM contents are not retained during PHY_SLEEP. 1: BBRAM contents are retained during PHY_SLEEP. Sets the prescaler value of the WUC to give the 32.768 kHz Divider value (see Table 29). Enables the 32.768 kHz RC OSC. Enables the 32.768 kHz external OSC. Sets the WUC clock source. 1: RC OSC selected. 2: XOSC selected. Enable to ensure that the device wakes from the PHY_SLEEP state on a WUC timeout. The WUC timer value. WUC Interval(s) = WUC_TIMER_VALUE × 32.768 kHz Divider 32 , 768 Enables the interrupt on a WUC timeout. Enabling this interrupt enables the firmware timer. Interrupt is set when the NUMBER_OF WAKEUPS count exceeds the threshold. Number of ADF7023-J wake-ups. Threshold for the number of ADF7023-J wake-ups. When exceeded, the ADF7023-J exits low power mode. Enables smart wake mode. Enables RSSI prequalification in smart wake mode. RSSI threshold for RSSI prequalification. RSSI threshold (dBm) = SWM_RSSI_THRESH − 107. Tick rate for the Rx dwell timer. Time that the ADF7023-J remains awake during SWM. Receive Dwell Time = RX_DWELL_TIME × 6.5 MHz 128 × PARMTIME_DIVIDER SWM 0x100 INTERRUPT_MASK_0 6 0 1 3 INTERRUPT_SWM_RSSI_DET INTERRUPT_PREAMBLE_DETECT INTERRUPT_SYNC_DETECT INTERRUPT_ADDRESS_MATCH Various interrupts that can be used in SWM. It is necessary to write to the 0x30C and 0x30D registers in the following order: WUC_CONFIG_HIGH (Address 0x30C), directly followed by writing to WUC_CONFIG_LOW (Address 0x30D). 2 It is necessary to write to the 0x30E and 0x30F registers in the following order: WUC_VALUE_HIGH (Address 0x30E), directly followed by writing to WUC_VALUE_LOW (Address 0x30F). 1 Rev. D | Page 57 of 104 ADF7023-J Data Sheet INTERRUPT (IF ENABLED) ADF7023-J HOST DEEP SLEEP MODE 2 PHY_SLEEP BBRAM RETAINED? NO WAIT FOR HOST COMMAND NO WAIT FOR HOST COMMAND DEEP SLEEP MODE 1 YES WUC CONFIGURED? WUC AND RTC MODES YES SET WUC_TIMEOUT INTERRUPT INCREMENT NUMBER_OF_WAKEUPS NUMBER_OF_WAKEUPS > THRESHOLD? YES SET INTERRUPT_NUM_ WAKEUPS WAIT FOR HOST COMMAND SET INTERRUPT_ SWM_RSSI_DET REMAIN IN PHY_RX LOOKING FOR PREAMBLE, AND WAIT FOR HOST COMMAND NO NO SWM ENABLED? (SWM_EN = 1) YES RSSI QUAL ENABLED? (SWM_RSSI_QUAL) SMART WAKE MODE (CARRIER SENSE ONLY) YES MEASURE RSSI NO NO RSSI > THRESHOLD (SWM_RSSI_THRESH) YES RSSI INT ENABLED? (INTERRUPT_ SWM_RSSI_DET) YES NO NO AND RX_DWELL_TIME EXCEEDED NO PREAMBLE DETECTED? YES SET INTERRUPT_ PREAMBLE_DETECT YES SET INTERRUPT_ SYNC_DETECT YES SET INTERRUPT_ CRC_CORRECT YES SET INTERRUPT_ ADDRESS_MATCH YES SYNC WORD DETECTED? CRC CORRECT? YES NO ADDRESS MATCH? YES ANY INTERRUPT SET? YES WAIT FOR HOST COMMAND NO NO TIME IN RX > RX_DWELL_TIME? YES Figure 69. Low Power Mode Operation Rev. D | Page 58 of 104 09555-145 SMART WAKE MODE YES NO Data Sheet ADF7023-J EXAMPLE LOW POWER MODES WUC Mode with Firmware Timer Deep Sleep Mode 2 In this low power mode, the WUC is used to periodically wake the ADF7023-J from the PHY_SLEEP state, and the firmware timer is used to count the number of WUC timeouts. The combination of the WUC and the firmware timer provides a real-time clock (RTC) capability. Deep Sleep Mode 2 is suitable for applications where the host processor controls the low power mode timing and the lowest possible ADF7023-J sleep current is required. In this low power mode, the ADF7023-J is in the PHY_SLEEP state. The BBRAM contents are not retained. This low power mode is entered by issuing the CMD_HW_RESET command from any radio state. To wake the part from the PHY_SLEEP state, the CS pin should be set low. The initialization routine after a CMD_HW_RESET command should be followed, as detailed in the Radio Control section. Deep Sleep Mode 1 Deep Sleep Mode 1 is suitable for applications where the host processor controls the low power mode timing and the ADF7023-J configuration is retained during the PHY_SLEEP state. In this low power mode, the ADF7023-J is in the PHY_SLEEP state with the BBRAM contents retained. Before entering the PHY_SLEEP state, the WUC_BBRAM_EN bit (Address 0x30D) should be set to 1 to ensure that the BBRAM is retained. This low power mode is entered by issuing the CMD_PHY_SLEEP command from either the PHY_OFF or PHY_ON state. To exit the PHY_SLEEP state, the CS pin can be set low. The CS low initialization routine should then be followed, as detailed in the Radio Control section. WUC Mode In this low power mode, the hardware WUC is used to wake the ADF7023-J from the PHY_SLEEP state after a user-defined duration. At the end of this duration, the ADF7023-J can provide an interrupt to the host processor. While the ADF7023-J is in the PHY_SLEEP state, the host processor can optionally be in a deep sleep state to save power. Before issuing the CMD_PHY_SLEEP command, the host processor should configure the WUC and set the firmware timer threshold to zero (NUMBER_OF_WAKEUPS_IRQ_ THRESHOLD_x = 0, Address 0x104 and Address 0x105). The WUC_BBRAM_EN bit (Address 0x30D) should be set to 1 to ensure that the BBRAM is retained. On issuing the CMD_PHY_ SLEEP command, the device goes to sleep for a period until the hardware timer times out. At this point, the device wakes up, and, if the WUC_TIMEOUT bit (Address 0x101) or the INTERRUPT_NUM_WAKEUPS bit (Address 0x100) interrupts are enabled, the device asserts the IRQ_GP3 pin. The operation of this low power mode is illustrated in Figure 70. The host processor should set up the WUC and the firmware timer before entering the PHY_SLEEP state. The WUC_ BBRAM_EN bit (Address 0x30D) should be set to 1 to ensure that the BBRAM is retained. The WUC can be configured to time out at some standard time interval (for example, 1 sec, 60 sec). On issuing the CMD_PHY_SLEEP command, the device enters the PHY_SLEEP state for a period until the hardware timer times out. At this point, the device wakes up, increments the 16-bit firmware timer (NUMBER_OF_WAKEUPS_x, Address 0x102 and Address 0x103) and, if the WUC_TIMEOUT bit (Address 0x101) is enabled, the device asserts the IRQ_GP3 pin. If the 16-bit firmware count is less than or equal to the user set threshold (NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_x, Address 0x104 and Address 0x105), the device returns to the PHY_SLEEP state. With this method, the firmware count (NUMBER_OF_WAKEUPS_x) equates to a real-time interval. When the firmware count exceeds the user-set threshold (NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_x), the ADF7023-J asserts the IRQ_GP3 pin, if the INTERRUPT_NUM_ WAKEUPS bit (Address 0x100) is set, and enters the PHY_OFF state. The operation of this low power mode is illustrated in Figure 71. Smart Wake Mode (Carrier Sense Only) In this low power mode, the WUC, firmware timer, and smart wake mode are used to implement periodic RSSI measurements on a particular channel (that is, carrier sense). To enable this mode, the WUC and firmware timer should be configured before entering the PHY_SLEEP state. The WUC_BBRAM_EN bit (Address 0x30D) should be set to 1 to ensure that the BBRAM is retained. The RSSI measurement is enabled by setting the SWM_RSSI_QUAL bit = 1 and the SWM_EN bit = 1 (Address 0x11A). The INTERRUPT_SWM_RSSI_DET bit (Address 0x100) should also be enabled. If the measured RSSI value is below the user-defined threshold set in the SWM_RSSI_THRESH register (Address 0x108), the device returns to the PHY_SLEEP state. If the RSSI measurement is greater than the SWM_RSSI_THRESH value, the device sets the INTERRUPT_SWM_RSSI_DET interrupt to alert the host processor and remains in the PHY_RX state looking for preamble, or waiting for a host command. The operation of this low power mode is illustrated in Figure 72. Rev. D | Page 59 of 104 ADF7023-J Data Sheet Smart Wake Mode In this low power mode, the WUC, firmware timer, and smart wake mode are employed to periodically listen for packets. To enable this mode, the WUC and firmware timer should be configured and smart wake mode (SWM) enabled (the SWM_EN bit, Address 0x11A) before entering the PHY_SLEEP state. The WUC_BBRAM_EN bit (Address 0x30D) should be set to 1 to ensure that the BBRAM is retained. RSSI prequalification can be optionally enabled (SWM_RSSI_QUAL = 1, Address 0x11A). When RSSI prequalification is enabled, the ADF7023-J begins searching for the preamble only if the RSSI measurement is greater than the user-defined threshold. The ADF7023-J is in the PHY_RX state for a duration determined by the RX_DWELL_TIME setting (Address 0x106). If the ADF7023-J detects the preamble during the receive dwell time, it searches for the sync word. If the sync word routine is detected, the ADF7023-J loads the received data to packet RAM and checks for a CRC and address match, if enabled. If any of the receive packet interrupts has been set, the ADF7023-J returns to the PHY_ON state and waits for a host command. This low power mode terminates when a valid packet interrupt is received. Alternatively, this low power mode can be terminated via a firmware timer timeout. This can be useful if certain radio tasks (for example, IR calibration) or processor tasks must be run periodically while in the low power mode. The operation of this low power mode is illustrated in Figure 73. Exiting Low Power Mode As described in Figure 69, the ADF7023-J waits for a host command on any of the termination conditions of the low power mode. It is also possible to perform an asynchronous exit from low power mode using the following procedure: 1. 2. Bring the CS pin of the SPI low and wait until the MISO output goes high. Issue a CMD_HW_RESET command. The host processor should then follow the initialization procedure after a CMD_HW_RESET command, as described in the Initialization section. If the ADF7023-J receives preamble detection during the receive dwell time but the remainder of the received packet extends beyond the dwell time, the ADF7023-J extends the dwell time until all of the packet is received or the packet is recognized as invalid (for example, there is an incorrect sync word). Rev. D | Page 60 of 104 Data Sheet ADF7023-J LOW POWER MODE TIMING DIAGRAMS HOST: CMD_PHY_SLEEP HOST: START WUC ADF7023-J PHY_OFF OR PHY_ON PHY_SLEEP OPERATION PHY_OFF WUC TIMEOUT PERIOD INTERRUPT WUC_TIMEOUT (IF ENABLED) 09555-146 INTERRUPT INTERRUPT_NUM_WAKEUPS (IF ENABLED AND NUMBER_OF_WAKEUPS_IRQ_THRESHOLD = 0) Figure 70. Low Power Mode Timing When Using the WUC HOST: CMD_PHY_SLEEP INCREMENT FIRMWARE TIMER HOST: START WUC ADF7023-J OPERATION PHY_OFF OR PHY_ON PHY_SLEEP INCREMENT FIRMWARE TIMER PHY_SLEEP FIRMWARE TIMER > THRESHOLD PHY_SLEEP PHY_OFF WUC TIMEOUT PERIOD 09555-147 WUC TIMEOUT PERIOD × NUMBER_OF_WAKEUPS_IRQ_THRESHOLD REAL TIME INTERNAL INTERRUPT_ NUM_WAKEUPS Figure 71. Low Power Mode Timing When Using the WUC and the Firmware Timer HOST: CMD_PHY_SLEEP HOST: START WUC ADF7023-J OPERATION RSSI ≤ THRESHOLD PHY_OFF OR PHY_ON PHY_SLEEP RSSI WUC TIMEOUT PERIOD RSSI ≤ THRESHOLD PHY_SLEEP RSSI RSSI > THRESHOLD PHY_SLEEP RSSI PHY_RX 09555-148 WUC TIMEOUT PERIOD INTERRUPT_ SWM_RSSI_DET Figure 72. Low Power Mode Timing When Using the WUC, Firmware Timer, and SWM with Carrier Sense t ADF7023-J OPERATION INTERRUPT_ SWM_RSSI_DET INTERRUPT_ PREAMBLE_DETECT INTERRUPT_ SYNC_DETECT INTERRUPT_ CRC_CORRECT INTERRUPT_ ADDRESS_MATCH PHY_OFF OR PHY_ON NO PACKET DETECTED PHY_SLEEP WUC TIMEOUT PERIOD RX NO PACKET DETECTED PHY_SLEEP RX PACKET DETECTED PHY_SLEEP PHY_ON WUC TIMEOUT PERIOD INIT PHY_RX RECEIVE DWELL TIME (RX_DWELL_TIME) Figure 73. Low Power Mode Timing When Using the WUC, Firmware Timer, and SWM Rev. D | Page 61 of 104 09555-149 HOST: CMD_PHY_SLEEP HOST: START WUC ADF7023-J Data Sheet WUC SETUP The relevant fields of each register are detailed in Table 29. All four of these registers are write only. Circuit Description The WUC should be configured as follows: The ADF7023-J features a low power wake-up controller comprising a 16-bit wake-up timer with a 3-bit programmable prescaler, as illustrated in Figure 74. The prescaler clock source can be configured to use either the 32.76 kHz internal RC oscillator (RCOSC) or the 32.76 kHz external oscillator (XOSC). This combination of programmable prescaler and 16-bit down counter gives a total hardware timer range of 30.52 µs to 36.4 hours. 1. 2. 3. Clear all interrupts. Set required interrupts. Write to WUC_CONFIG_HIGH and WUC_CONFIG_ LOW. Ensure that the WUC_ARM bit = 1. Ensure that the WUC_BBRAM_EN bit = 1 (retain BBRAM during PHY_SLEEP). It is necessary to write to both registers together in the following order: WUC_CONFIG_HIGH directly followed by writing to WUC_CONFIG_LOW. Write to WUC_VALUE_HIGH and WUC_VALUE_LOW. This configures the WUC_TIMER_VALUE[15:0] and, thus, the WUC timeout period. The timer begins counting from the configured value after these registers have been written to. It is necessary to write to both registers together in the following order: WUC_VALUE_HIGH directly followed by writing to WUC_VALUE_LOW. Configuration and Operation The hardware WUC is configured via the following registers: • • • • 4. WUC_CONFIG_HIGH (Address 0x30C) WUC_CONFIG_LOW (Address 0x30D) WUC_VALUE_HIGH (Address 0x30E) WUC_VALUE_LOW (Address 0x30F) WUC WUC_VALUE_HIGH WUC_VALUE_LOW WUC_CONFIG_LOW[4] RC OSCILLATOR 32kHz XTAL 1 32.768kHz PRESCALER TICK RATE 16-BIT RELOAD VALUE 16-BIT DOWN COUNTER ADF7023-J WAKE-UP CIRCUIT 0 WUC_TIMEOUT INTERRUPT 09555-150 WUC_CONFIG_HIGH[2:0] TO FIRMWARE TIMER Figure 74. Hardware Wake-Up Controller (WUC) Table 29. WUC Register Settings WUC Setting WUC_VALUE_HIGH [7:0] Name WUC_TIMER_VALUE[15:8] Description WUC timer value. WUC Interval(s) = WUC_TIMER_VALUE × 32.768 kHz Divider 32 , 768 WUC_VALUE_LOW[7:0] WUC_CONFIG_HIGH[7] WUC_CONFIG_HIGH[6:3] WUC_TIMER_VALUE[7:0] Reserved RCOSC_COARSE_CAL_VALUE WUC timer value. Set to 0. RCOSC_COARSE_ CAL_VALUE 0000 0001 1000 1001 1100 1101 1110 1111 0110 0111 Rev. D | Page 62 of 104 Change in RC Oscillator Frequency +83% +66% +50% +33% +16% 0% −16% −33% −50% −66% Coarse Tune State State 10 State 9 State 8 State 7 State 6 State 5 State 4 State 3 State 2 State 1 Data Sheet ADF7023-J WUC Setting WUC_CONFIG_HIGH[2:0] Name WUC_PRESCALER Description WUC_PRESCALER 000 001 010 011 100 101 110 111 Set to 0. WUC_CONFIG_LOW[7] Reserved WUC_CONFIG_LOW[6] WUC_RCOSC_EN 1: enable. 0: disable RCOSC32K. WUC_CONFIG_LOW[5] WUC_XOSC32K_EN 1: enable. 0: disable XOSC32K. WUC_CONFIG_LOW[4] WUC_CLKSEL 1: RC 32.768 kHz oscillator. 0: external crystal oscillator. WUC_CONFIG_LOW [3] WUC_BBRAM_EN 1: enable power to BBRAM during the PHY_SLEEP state. 0: disable power to BBRAM during the PHY_SLEEP state. WUC_CONFIG_LOW[2:1] Reserved Set to 0. WUC_CONFIG_LOW[0] WUC_ARM 1: enable wake-up on WUC timeout event. 0: disable wake-up on WUC timeout event. FIRMWARE TIMER SETUP The ADF7023-J wakes up from the PHY_SLEEP state at the rate set by the WUC. A firmware timer, implemented by the on-chip processor, can be used to count the number of hardware wake-ups and generate an interrupt to the host processor. Thus, the ADF7023-J can be used to handle the wake-up timing of the host processor, reducing overall system power consumption. To set up the firmware timer, the host processor must set a value in the NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0] registers (Address 0x104 and Address 0x105). This 16-bit value represents the number of times the device wakes up before it interrupts the host processor. At each wake-up, the ADF7023-J increments the NUMBER_OF_WAKEUPS[15:0] registers (Address 0x102 and Address 103). If this value exceeds the value set by the NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0] registers, the NUMBER_OF_WAKEUPS[15:0] value is cleared to 0. At this time, if the INTERRUPT_NUM_WAKEUPS bit in the INTERRUPT_MASK_0 register (Address 0x100) is set, the device asserts the IRQ_GP3 pin and enters the PHY_OFF state. CALIBRATING THE RC OSCILLATOR There are two types of RC oscillator calibration, namely fine and coarse calibrations. A fine calibration of the RC oscillator is automatically performed upon wake-up from PHY_SLEEP and upon cold start. The user can also manually initiate a fine calibration. 32.768 kHz Divider 1 4 8 16 128 1024 8192 65,536 Tick Period 30.52 µs 122.1 µs 244.1 µs 488.3 µs 3.91 ms 31.25 ms 250 ms 2000 ms In order to meet the quoted RC oscillator frequency accuracy given in the Specifications section, it is necessary to perform a coarse calibration of the RC oscillator. Performing a Fine Calibration of the RC Oscillator This is performed as follows: 1. 2. 3. Write to the WUC_CONFIG_HIGH and WUC_CONFIG_LOW registers, setting the WUC_RCOSC_EN bit high. Write a 0 to WUC_RCOSC_CAL_EN in the WUC_FLAG_RESET register. Write a 1 to WUC_RCOSC_CAL_EN in the WUC_FLAG_RESET register. During calibration, the host microprocessor can write to and read from memory locations and issue commands to the ADF7023-J. The RC oscillator calibration status can be viewed in the WUC_STATUS register (Location 0x311). A fine calibration typically takes 1.5 ms. The result of a fine calibration can be read back from the following two registers: RCOSC_CAL_READBACK_HIGH (Location 0x34F) and RCOSC_CAL_READBACK_LOW (Location 0x350). Performing a Coarse Calibration of the RC Oscillator This calibration involves performing fine calibrations of the RC oscillator for different values of RCOSC_COARSE_CAL_VALUE to determine the optimum value to be written to WUC_CONFIG_HIGH (Location 0x30C[6:3]). Rev. D | Page 63 of 104 ADF7023-J Data Sheet Usually the optimum RCOSC_COARSE_CAL_VALUE is determined at 25°C once, and the result stored in the host microprocessor. This result can incorporated in the value written to WUC_CONFIG_HIGH prior to fine calibrations of the RC oscillator. The coarse calibration procedure is outlined in Figure 75. Typically, the optimum coarse tune state is State 5, so the algorithm starts in this state to minimize the number of iterations. Set i = 5 Set Coarse Cal State = i Initiate Fine Cal and wait 1.25 ms Readback Fine Cal result (i) and calculate Fine_Cal_Code_Delta(i) = Fine_Cal_Code(i) - 300 Increment i Set Coarse Cal state = i NO Is Fine_Cal_Code_Delta(i) YES positive? Decrement i Set Coarse Cal state = i Initiate Fine Cal and wait 1.25ms Initiate Fine Cal and wait 1.25ms Readback Fine Cal result (i) and calculate Fine_Cal_Code_Delta(i) = Fine_Cal_Code(i) - 300 Readback Fine Cal result (i) and calculate Fine_Cal_Code_Delta(i) = Fine_Cal_Code(i) - 300 YES Is ABS(Fine_Cal_Code_Delta(i)) < ABS(Fine_Cal_Code_Delta(i+1))? YES NO NO Is ABS(Fine_Cal_Code_Delta(i)) < ABS(Fine_Cal_Code_Delta(i-1))? NO Is i = 10? Is i = 1? Exit Optimum Coarse Cal State = i+1 Exit Optimum Coarse Cal State = i-1 Figure 75. RC Oscillator Coarse Calibration Algorithm Rev. D | Page 64 of 104 Exit Optimum Coarse Cal State = 10 09555-400 YES YES Exit Optimum Coarse Cal State = 1 NO Data Sheet ADF7023-J DOWNLOADABLE FIRMWARE MODULES The program RAM memory of the ADF7023-J can be used to store firmware modules for the communications processor that provide the ADF7023-J with extra functionality. The binary code for these firmware modules and details on their functionality are available from Analog Devices. These firmware modules are available online at ftp://ftp.analog.com/pub/RFL/FirmwareModules/ADF7023/. Three modules are briefly described in this section: image rejection calibration, AES encryption and decryption, and Reed-Solomon coding. WRITING A MODULE TO PROGRAM RAM The sequence to write a firmware module to program RAM is as follows: 4. 5. Ensure that the ADF7023-J is in PHY_OFF. Issue the CMD_RAM_LOAD_INIT command. Write the module to program RAM using an SPI memory block write (see the SPI Interface section). Issue the CMD_RAM_LOAD_DONE command. Issue the CMD_SYNC command. The downloadable AES firmware module supports 128-bit block encryption and decryption with key sizes of 128 bits, 192 bits, and 256 bits. Two modes are supported: ECB mode and CBC Mode 1. ECB mode simply encrypts/decrypts on a 128-bit block by block with a single secret key as illustrated in Figure 77. CBC Mode 1 encrypts after first adding (Modulo 2), a 128-bit usersupplied initialization vector. The resulting cipher text is then used as the initialization vector for the next block and so forth, as illustrated in Figure 78. Decryption provides the inverse functionality. The firmware also takes advantage of an on-chip hardware accelerator module to enhance throughput and minimize the latency of the AES processing. REED-SOLOMON CODING MODULE This coding module uses Reed-Solomon block coding to detect and correct errors in the received packet. A transmit message of k bytes in length is appended with an error checking code (ECC) of length n − k bytes to give a total message length of n bytes, as shown in Figure 76. n BYTES The firmware module is now stored on program RAM. IMAGE REJECTION CALIBRATION MODULE PREAMBLE The calibration system initially disables the ADF7023-J receiver, and an internal RF source is applied to the RF input at the image frequency. The algorithm then maximizes the receiver image rejection performance by iteratively minimizing the quadrature gain and phase errors in the polyphase filter. The calibration algorithm takes its initial estimates for quadrature phase correction (Address 0x118) and quadrature gain correction (Address 0x119) from BBRAM. After calibration, new optimum values of phase and gain are loaded back into these locations. These calibration values are maintained in BBRAM during sleep mode and are automatically reapplied from a wake-up event, which keeps the number of calibrations required to a minimum. Depending on the initial values of quadrature gain and phase correction, the calibration algorithm can take approximately 20 ms to find the optimum image rejection performance. However, the calibration time can be significantly less than this when the seed values used for gain and phase correction are close to optimum. The image rejection performance is also dependent on temperature. To maintain optimum image rejection performance, a calibration should be activated whenever a temperature change of more than 10°C occurs. The ADF7023-J on-chip temperature sensor can be used to determine when the temperature exceeds this limit. To run the IR calibration, issue a CMD_IR_CAL (Register 0xBD). In order for this to work successfully, ensure that the BB filter calibration is enabled in the MODE_CONTROL register (Address 0x11A). SYNC WORD PAYLOAD k BYTES ECC (n – k) BYTES 09555-151 1. 2. 3. AES ENCRYPTION AND DECRYPTION MODULE Figure 76. Packet Structure with Appended Reed-Solomon ECC The receiver decodes the ECC to detect and correct up to t bytes in error, where t = (n − k)/2. The firmware supports correction of up to five bytes in the n byte field. To correct t bytes in error, an ECC length of 2t bytes is required, and the byte errors can be randomly distributed throughout the payload and ECC fields. Reed-Solomon coding exhibits excellent burst error correction capability and is commonly used to improve the robustness of a radio link in the presence of transient interference or due to rapid signal fading conditions that can corrupt sections of the message payload. Reed-Solomon coding is also capable of improving the receiver’s sensitivity performance by several dB, where random errors tend to dominate under low SNR conditions and the receiver’s packet error rate performance is limited by thermal noise. The number of consecutive bit errors that can be 100% corrected is {(t − 1) × 8 + 1}. Longer, random bit-error patterns, up to t bytes, can also be corrected if the error patterns start and end at byte boundaries. The firmware also takes advantage of an on-chip hardware accelerator module to enhance throughput and minimize the latency of the Reed-Solomon processing. Rev. D | Page 65 of 104 ADF7023-J Data Sheet ECB MODE PLAIN TEXT 128 BITS AES ENCRYPT AES ENCRYPT AES ENCRYPT 128 BITS 128 BITS 128 BITS CIPHER TEXT 09555-152 KEY KEY KEY 128 BITS 128 BITS Figure 77. ECB Mode CBC MODE 1 PLAIN TEXT 128 BITS + INITIAL VECTOR KEY 128 BITS + + KEY 128 BITS KEY + KEY AES ENCRYPT AES ENCRYPT AES ENCRYPT AES ENCRYPT 128 BITS 128 BITS 128 BITS 128 BITS CIPHER TEXT Figure 78. CBC Mode 1 Rev. D | Page 66 of 104 09555-153 128 BITS Data Sheet ADF7023-J RADIO BLOCKS FREQUENCY SYNTHESIZER Synthesizer Bandwidth A fully integrated RF frequency synthesizer is used to generate both the transmit signal and the receiver’s local oscillator (LO) signal. The architecture of the frequency synthesizer is shown in Figure 79. The synthesizer loop filter is fully integrated on chip and has a programmable bandwidth. The communications processor automatically sets the bandwidth of the synthesizer when the device enters the PHY_TX or the PHY_RX state. Upon entering the PHY_TX state, the communications processor chooses the bandwidth based on the programmed modulation scheme (2FSK or GFSK) and the data rate. This ensures optimum modulation quality for each data rate. Upon entering the PHY_RX state, the communications processor sets a narrow bandwidth to ensure best receiver rejection. In all, there are eight bandwidth configurations. Each synthesizer bandwidth setting is described in Table 30. The receiver uses a fractional-N frequency synthesizer to generate the mixer’s LO for down conversion to the intermediate frequency (IF) of 200 kHz or 300 kHz. In transmit mode, a high resolution sigma-delta (Σ-Δ) modulator is used to generate the required frequency deviations at the RF output when FSK data is transmitted. To reduce the occupied FSK bandwidth, the transmitted bit stream can be filtered using a digital Gaussian filter, which is enabled via the RADIO_CFG_9 register (Address 0x115). The Gaussian filter uses a bandwidth time (BT) of 0.5. The VCO and the PLL loop filter of the ADF7023-J are fully integrated. To reduce the effect of pulling of the VCO by the power-up of the PA and to minimize spurious emissions, the VCO operates at twice the RF frequency. The VCO signal is then divided by 2, giving the required frequency for the transmitter and the required LO frequency for the receiver. Description Rx 2FSK/GFSK/MSK/GMSK Tx 2FSK/GFSK/MSK/GMSK Tx 2FSK/GFSK/MSK/GMSK Tx 2FSK/GFSK/MSK/GMSK Tx 2FSK/GFSK/MSK/GMSK Tx 2FSK/GFSK/MSK/GMSK Tx 2FSK/GFSK/MSK/GMSK A high speed, fully automatic calibration scheme is used to ensure that the frequency and amplitude characteristics of the VCO are maintained over temperature, supply voltage, and process variations. As part of the initial BBRAM configuration, do the following: • • ÷2 VCO LOOP FILTER N DIVIDER FRAC-N GAUSSIAN FILTER F_DEVIATION These values are retained in memory while VDDBAT remains valid, unless PHY_SLEEP is entered; in which case, the values must be reprogrammed. Table 31. T96 Custom Transmit Look-Up Table (LUT) ÷2 Σ-Δ DIVIDER INTEGER-N Figure 79. RF Frequency Synthesizer Architecture 09555-035 TX DATA Issue the SPI_MEM_WR command, writing 0x2 to Bits[5:4] of Register 0x113 (RADIO_CFG_7). Issue the CMD_CONFIG_DEV command. The custom transmit LUT must be written to the 0x010 to 0x018 packet RAM locations. This is achieved using a SPI_MEM_WR command and a block write as described in the Memory Access section. The LUT values are described in Table 31. RF FREQ CHARGE PUMP Closed-Loop Synthesizer Bandwidth (kHz) 92 130 174 174 226 305 382 The following procedure must be used to program the device for optimized PLL bandwidth settings during transmit operation. VCO CALIBRATION PFD Data Rate (kbps) All 1 to 49.5 49.6 to 99.1 99.2 to 129.5 129.6 to 179.1 179.2 to 239.9 240 to 300 For performance margin to the T96 specification limits, the PLL closed-loop bandwidth is optimized depending on the data rate. The calibration is automatically performed when the CMD_PHY_RX or the CMD_PHY_TX command is issued. The calibration duration is 142 µs, and if required, the CALIBRATION_STATUS register (Address 0x339) can be polled to indicate the completion of the VCO self calibration. After the VCO is calibrated, the frequency synthesizer settles to within ±5 ppm of the target frequency in 56 µs. 26MHz REF Table 30. Automatic Synthesizer Bandwidth Selections Register 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 Rev. D | Page 67 of 104 Data Rate = 50 kbps or 100 kbps (CLBW = 130 kHz) 0x10 0x10 0x0F 0x0F 0x1F 0x0F 0x1F 0x33 0x22 Data Rate = 200 kbps (CLBW = 223 kHz) 0x20 0x20 0x0F 0x0F 0x1F 0x05 0x1F 0x33 0x22 ADF7023-J Data Sheet Synthesizer Settling After the VCO calibration, a 56 µs delay is allowed for synthesizer settling. This delay is fixed at 56 µs by default and ensures that the synthesizer has fully settled when using any of the default synthesizer bandwidths. However, in some cases, it may be necessary to use a custom synthesizer settling delay. To use a custom delay, set the CUSTOM_ TRX_SYNTH_LOCK_TIME EN bit to 1 in the MODE_CONTROL register (Address 0x11A). The synthesizer settling delays for the PHY_RX and the PHY_TX state transitions can be set independently in the RX_SYNTH_LOCK_TIME register (Address 0x13E) and the TX_SYNTH_LOCK_TIME register (Address 0x13F). The settling time can be set in the 2 µs to 512 µs range in steps of 2 µs. Bypassing VCO Calibration It is possible to bypass the VCO calibration for ultrafast frequency hopping in transmit or receive. The calibration data for each RF channel should be stored in the host processor memory. The calibration data comprises two values: the VCO band select value and the VCO amplitude level. Read and Store Calibration Data 1. 2. Go to the PHY_TX or the PHY_RX state without bypassing the VCO calibration. Read the following MCR registers and store the calibrated data in memory on the host processor: a. VCO_BAND_READBACK (Address 0x3DA) b. VCO_AMPL_READBACK (Address 0x3DB) Bypassing VCO Calibration on CMD_PHY_TX or CMD_PHY_RX 1. 2. 3. 4. 5. 6. 7. 8. Ensure that the BBRAM is configured. Set VCO_OVRW_EN (Address 0x3CD) = 0x3. Set VCO_CAL_CFG (Address 0x3D0) = 0x0F. Set VCO_BAND_OVRW_VAL (Address 0x3CB) = stored VCO_BAND_READBACK (Address 0x3DA) for that channel. Set VCO_AMPL_OVRW_VAL (Address 0x3CC) = stored VCO_AMPL_READBACK (Address 0x3DB) for that channel. Set SYNTH_CAL_EN = 0 (in the CALIBRATION_ CONTROL register, Address 0x338). Set SYNTH_CAL_EN = 1 (in the CALIBRATION_ CONTROL register, Address 0x338). Issue CMD_PHY_TX or CMD_PHY_RX to go to the PHY_TX or PHY_RX state without the VCO calibration. CRYSTAL OSCILLATOR A 26 MHz crystal oscillator operating in parallel mode must be connected between the XOSC26P and XOSC26N pins. Two parallel loading capacitors are required for oscillation at the correct frequency. Their values are dependent upon the crystal specification. They should be chosen to ensure that the shunt value of capacitance added to the PCB track capacitance and the input pin capacitance of the ADF7023-J equals the specified load capacitance of the crystal, usually 10 pF to 20 pF. Track capacitance values vary from 2 pF to 5 pF, depending on board layout. The total load capacitance is described by CLOAD = C 1 + PIN + C PCB 1 1 2 + C1 C2 where: CLOAD is the total load capacitance. C1 and C2 are the external crystal load capacitors. CPIN is the ADF7023-J input capacitance of the XOSC26P and XOSC26N pins and is equal to 2.1 pF. CPCB is the PCB track capacitance. When possible, choose capacitors that have a very low temperature coefficient to ensure stable frequency operation over all conditions. The crystal frequency error can be corrected by means of an integrated digital tuning varactor. For a typical crystal load capacitance of 10 pF, a tuning range of 0 to +15 ppm is available via programming of a 3-bit DAC, according to Table 32. The 3-bit value should be written to the XOSC_CAP_DAC bits in the OSC_CONFIG register (Address 0x3D2). Alternatively, any error in the RF frequency due to crystal error can be adjusted for by offsetting the RF channel frequency using the RF channel frequency setting in BBRAM memory. Table 32. Crystal Frequency Pulling Programming XOSC_CAP_DAC 000 001 010 011 100 Pulling (ppm) +15 +11.25 +7.5 +3.75 0 MODULATION The ADF7023-J supports binary frequency shift keying (2FSK), minimum shift keying (MSK), binary level Gaussian filtered 2FSK (GFSK), and Gaussian filtered MSK (GMSK). The desired transmit and receive modulation formats are set in the RADIO_CFG_9 register (Address 0x115). When using 2FSK/GFSK/MSK/GMSK modulation, the frequency deviation can be set using the FREQ_DEVIATION[11:0] bits in the RADIO_CFG_1 register (Address 0x10D) and the RADIO_CFG_2 register (Address 0x10E). The data rate can be set in the 1 kbps to 300 kbps range using the DATA_RATE[11:0] parameter in the RADIO_CFG_0 register (Address 0x10C) and RADIO_CFG_1 register (Address 0x10D). For GFSK/GMSK modulation, the Gaussian filter uses a fixed BT of 0.5. Rev. D | Page 68 of 104 Data Sheet ADF7023-J RF OUTPUT STAGE PA/LNA INTERFACE Power Amplifier (PA) The ADF7023-J supports both single-ended and differential PA outputs. Only one PA can be active at a time. The differential PA and LNA share the same pins, RFIO_1P and RFIO_1N, which facilitate a simpler antenna interface. The single-ended PA output is available on the RFO2 pin. A number of PA/LNA antenna matching options are possible and are described in the PA/LNA Matching section. The ADF7023-J PA can be configured for single-ended or differential output operation using the PA_SINGLE_DIFF_SEL bit in the RADIO_CFG_8 register (Address 0x114). The PA level is set by the PA_LEVEL bit in the RADIO_CFG_8 register and has a range of 0 to 15. For finer control of the output power level, the PA_LEVEL_MCR register (Address 0x307) can be used. It offers more resolution with a setting range of 2 to 63. The relationship between the PA_LEVEL and PA_LEVEL_MCR settings is given by PA_LEVEL_MCR = 4 × PA_LEVEL + 3 The single-ended configuration can deliver 13.5 dBm output power. The differential PA can deliver 10 dBm output power and allows a straightforward interface to dipole antennae. The two PA configurations offer a Tx antenna diversity capability. Note that the two PAs cannot be enabled at the same time. Automatic PA Ramp The ADF7023-J has built-in up and down PA ramping for both single-ended and differential PAs. There are eight ramp rate settings, with the ramp rate defined as a certain number of PA power level settings per data bit period. The PA_RAMP variable in the RADIO_CFG_8 register (Address 0x114) sets this PA ramp rate, as illustrated in Figure 80. 1 2 3 4 ... 8 ... 16 The channel filter of the receiver is a fourth-order, active polyphase Butterworth filter with programmable bandwidths of 100 kHz, 150 kHz, 200 kHz, and 300 kHz. The fourth-order filter gives very good interference suppression of adjacent and neighboring channels and also suppresses the image channel by approximately 36 dB at a 100 kHz IF bandwidth and an RF frequency of 915 MHz. For channel bandwidths of 100 kHz to 200 kHz, an IF frequency of 200 kHz is used, which results in an image frequency located 400 kHz below the wanted RF frequency. When the 300 kHz bandwidth is selected, an IF frequency of 300 kHz is used, and the image frequency is located at 600 kHz below the wanted frequency. The bandwidth and center frequency of the IF filter are calibrated automatically after entering the PHY_ON state if the BB_CAL bit is set in the MODE_CONTROL register (Address 0x11A). The filter calibration time takes 100 µs. The IF bandwidth is programmed by setting the IFBW field in the RADIO_CFG_9 register (Address 0x115). The filter’s pass band is centered at an IF frequency of 200 kHz when bandwidths of 100 kHz to 200 kHz are used and centered at 300 kHz when an IF bandwidth of 300 kHz is used. DATA BITS PA RAMP 1 (256 CODES PER BIT) PA RAMP 2 (128 CODES PER BIT) PA RAMP 3 (64 CODES PER BIT) IMAGE CHANNEL REJECTION PA RAMP 4 (32 CODES PER BIT) PA RAMP 5 (16 CODES PER BIT) 09555-036 PA RAMP 6 (8 CODES PER BIT) PA RAMP 7 (4 CODES PER BIT) Figure 80. PA Ramp for Different PA_RAMP Settings The PA ramps to the level set by the PA_LEVEL or PA_LEVEL_ MCR settings. Enabling the PA ramp reduces spectral splatter and helps meet radio regulations, which limit PA transient spurious emissions. To ensure optimum performance, an adequately long PA ramp rate is required based on the data rate and the PA output power setting. The PA_RAMP setting should, therefore, be set such that Ramp Rate (Codes/Bit) < 10000 × RECEIVE CHANNEL FILTER PA_LEVEL_MCR[5 : 0] DATA_RATE[11 : 0] The ADF7023-J is capable of providing improved receiver image rejection performance by the use of a fully integrated image rejection calibration system under the control of the on-chip communications processor. To operate the calibration system, a firmware module is downloaded to the on-chip program RAM. The firmware download is supplied by Analog Devices and described in the Downloadable Firmware Modules section. To achieve the typical uncalibrated image attenuation values given in the Specifications section, it is required to use recommended default values for IMAGE_REJECT_CAL_PHASE (Address 0x118) and IMAGE_REJECT_CAL_AMPLITUDE (Address 0x119). These recommended defaults, at 915 MHz, are IMAGE_REJECT_CAL_AMPLITUDE = 0x07 and IMAGE_REJECT_CAL_PHASE = 0x16. where PA_LEVEL_MCR is related to the PA_LEVEL setting by PA_LEVEL_MCR = 4 × PA_LEVEL + 3. Rev. D | Page 69 of 104 ADF7023-J Data Sheet AUTOMATIC GAIN CONTROL (AGC) RSSI Method 1 AGC is enabled by default and keeps the receiver gain at the correct level by selecting the LNA, mixer, and filter gain settings based on the measured RSSI level. The LNA has three gain levels, the mixer has two gain levels, and the filter has three gain levels. In all, there are six AGC stages, which are defined in Table 33. Table 33. AGC Gain Modes When a valid packet is received in packet mode, the RSSI level during postamble is automatically loaded to the RSSI_READBACK register (Address 0x312) by the communications processor. The RSSI_READBACK register contains a twos complement value and can be converted to input power in dBm using the following formula: Gain Mode 1 2 3 4 5 6 LNA Gain High High Medium Low Low Low Mixer Gain High Low Low Low Low Low Filter Gain High High High High Medium Low The AGC remains at each gain stage for a time defined by the AGC_CLK_DIVIDE register (Address 0x32F). The default value of AGC_CLK_DIVIDE = 0x28 gives an AGC delay of 25 μs. When the RSSI is above AGC_HIGH_THRESHOLD (Address 0x35F), the gain is reduced. When the RSSI is below AGC_LOW_THRESHOLD (Address 0x35E), the gain is increased. The AGC can be configured to remain active while in the PHY_RX state or can be locked on preamble detection. The AGC can also be set to manual mode, in which case, the host processor must set the LNA, filter, and mixer gains by writing to the AGC_MODE register (Address 0x35D). The AGC operation is set by the AGC_LOCK_MODE setting in the RADIO_CFG_7 register (Address 0x113) and is described in Table 34. The LNA, filter, and mixer gains can be read back through the AGC_GAIN_STATUS register (Address 0x360). 2 3 To extend the linear range of RSSI measurement down to an input power of −110 dBm (see Figure 42), a cosine adjustment can be applied using the following formula: RSSI(dBm) = 8   COS   × RSSI_READBACK − 106  RSSI _ READBACK  where COS(X) is the cosine of angle X (radians). RSSI Method 2 The CMD_GET_RSSI command can be used from the PHY_ON state to read the RSSI. This RSSI measurement method uses additional low-pass filtering, resulting in a more accurate RSSI reading. The RSSI result is loaded to the RSSI_READBACK register (Address 0x312) by the communications processor. The RSSI_READBACK register contains a twos complement value and can be converted to input power in dBm using the following formula: RSSI(dBm) = RSSI_READBACK – 107 The CMD_GET_RSSI execution time is specified in Table 11. RSSI Method 3 Table 34. AGC Operation AGC_LOCK_MODE Bits in RADIO_CFG_7 Register 0 1 RSSI(dBm) = RSSI_READBACK − 107 Description AGC is free running. AGC is disabled. Gains must be set manually. AGC is held at the current gain level. AGC is locked on preamble detection. RSSI The RSSI is based on a successive compression, log amplifier architecture following the analog channel filter. The analog RSSI level is digitized by an 8-bit SAR ADC for user readback and for use by the digital AGC controller. The ADF7023-J has three RSSI measurement functions that support a wide range of applications. These functions can be used to implement carrier sense (CS) or clear channel assessment (CCA). In packet mode, the RSSI is automatically recorded in MCR memory and is available for user readback after receipt of a packet. This method supports the measurement of RSSI by the host processor at any time while in the PHY_RX state. The receiver input power can be calculated using the following procedure: 1. 2. 3. 4. 5. Table 36 details the three RSSI measurement methods. Set AGC to hold by setting the AGC_MODE register (Address 0x35D) = 0x40 (only necessary if AGC has not been locked on the preamble or sync word). Read back the AGC gain settings (AGC_GAIN_STATUS register, Address 0x360). Read the ADC_READBACK[7:0] bit values (Address 0x327 and Address 0x328; see the Analog-to-Digital Converter section). Re-enable the AGC by setting the AGC_MODE register (Address 0x35D) = 0x00 (only necessary if AGC has not already been locked on the preamble or sync word). Calculate the RSSI in dBm as follows: RSSI(dBm) =  ADC_READBACK[7:0] × 1 + Gain_Correction  − 109   7   where Gain_Correction is determined by the value of the AGC_GAIN_STATUS register (Address 0x360) as shown in Table 35. Rev. D | Page 70 of 104 Data Sheet ADF7023-J Table 35. Gain Mode Correction for 2FSK/GFSK/MSK/GMSK RSSI AGC_GAIN_STATUS (Address 0x360) 0x00 0x01 0x02 0x0A 0x12 0x16 To simplify the RSSI calculation, the following approximation can be used by the host processor: 1 ≈ 1 1 1  1 + +  7 8 8 64  GAIN_CORRECTION 44 35 26 17 10 0 Table 36. Summary of RSSI Measurement Methods RSSI Method 1 2 3 Available in Packet Mode Yes Available in Sport Mode No 2FSK/GFSK/ MSK/GMSK Yes Yes 2FSK/GFSK/ MSK/GMSK Yes Yes RSSI Type Automatic end of packet RSSI Modulation 2FSK/GFSK/ MSK/GMSK CMD_GET_RSSI command from PHY_ON RSSI via ADC and AGC readback, FSK Description Automatic RSSI measurement during reception of the postamble in packet mode. The RSSI result is available in the RSSI_READBACK register (Address 0x312). Automatic RSSI measurement from PHY_ON using CMD_GET_RSSI. The RSSI result is available in the RSSI_READBACK register (Address 0x312). RSSI measurement based on the ADC and AGC gain read backs. The host processor calculates RSSI in dBm. SPORT MODE GPIOS IF FILTER MIXER LIMITERS FREQUENCY CORRELATOR I LNA RxDATA/ CLOCK AND RxCLK DATA RECOVERY RFIO_1P RFIO_1N COMMUNICATIONS PROCESSOR POST-DEMOD FILTER Q PREAMBLE DETECT IF DISCRIM_PHASE[1:0] IFBW[1:0] (ADDRESS RADIO_CFG_9[7:6]) POST_DEMOD_BW[7:0] DATA_RATE[11:0] DISCRIM_BW[7:0] SYNC WORD DETECT PREAMBLE_MATCH = 0 AFC SYSTEM PI CONTROL RANGE 2T AVERAGING FILTER AFC LOCK MAX_AFC_RANGE[7:0] AFC_LOCK_MODE[1:0] AFC_KI[3:0] (ADDRESS RADIO_CFG_11[7:4]) AFC_KP[3:0] Figure 81. 2FSK/GFSK/MSK/GMSK Demodulation and AFC Architecture Rev. D | Page 71 of 104 09555-156 RF SYNTHESIZER (LO) ADF7023-J Data Sheet 2FSK/GFSK/MSK/GMSK DEMODULATION A correlator demodulator is used for 2FSK, GFSK, MSK, and GMSK demodulation. The quadrature outputs of the IF filter are first limited and then fed to a digital frequency correlator that performs filtering and frequency discrimination of the 2FSK/GFSK/MSK/ GMSK spectrum. Data is recovered by comparing the output levels from two correlators. The performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of additive white Gaussian noise (AWGN). This method of 2FSK/GFSK/MSK/ GMSK demodulation provides approximately 3 dB to 4 dB better sensitivity than a linear frequency discriminator. The 2FSK/GFSK/ MSK/GMSK demodulator architecture is shown in Figure 81. The ADF7023-J is configured for 2FSK/GFSK/MSK/GMSK demodulation by setting DEMOD_SCHEME = 0 in the RADIO_CFG_9 register (Address 0x115). To optimize receiver sensitivity, the correlator bandwidth and phase must be optimized for the specific deviation frequency, data rate, and maximum expected frequency error between the transmitter and receiver. The bandwidth and phase of the discriminator must be set using the DISCRIM_BW bits in the RADIO_CFG_3 register (Address 0x10F) and the DISCRIM_ PHASE[1:0] bits in the RADIO_CFG_6 register (Address 0x112). The discriminator setup is performed in three steps. Step 1: Calculate the Discriminator Bandwidth Coefficient K The Discriminator Bandwidth Coefficient K depends on the modulation index (MI), which is determined by MI = K is the discriminator coefficient. Floor[x] is a function to round down to the nearest integer. IF_Freq is the IF frequency in hertz (200 kHz or 300 kHz). FSK_Dev is the 2FSK/GFSK/MSK/GMSK frequency deviation in hertz. Freq_Error_Max is the maximum expected frequency error, in hertz, between Tx and Rx. Step 2: Calculate the DISCRIM_BW Setting The bandwidth setting of the discriminator is calculated based on the Discriminator Coefficient K and the IF frequency. The bandwidth is set using the DISCRIM_BW[7:0] setting (Address 0x10F), which is calculated according to  K × 3.25 MHz  DISCRIM_BW[7:0] = Round    IF _ Freq  Step 3: Calculate the DISCRIM_PHASE Setting The phase setting of the discriminator is calculated based on the Discriminator Coefficient K, as described in Table 37. The phase is set using the DISCRIM_PHASE[1:0] value in the RADIO_CFG_6 register (Address 0x112). Table 37. Setting the DISCRIM_PHASE[1:0] Values Based on K K Even Odd Even Odd K/2 Odd (K + 1)/2 Even Even Odd DISCRIM_PHASE[1:0] 0 1 2 3 AFC 2 × FSK _ Dev Data Rate where FSK_Dev is the 2FSK/GFSK/MSK/GMSK frequency deviation in hertz (Hz), measured from the carrier to the +1 symbol frequency (positive frequency deviation) or to the −1 symbol frequency (negative frequency deviation). Data Rate is the data rate in bits per second (bps). The ADF7023-J features an internal real-time automatic frequency control loop. In receive mode, the control loop automatically monitors the frequency error during the packet preamble sequence and adjusts the receiver synthesizer local oscillator using proportional integral (PI) control. The AFC frequency error measurement bandwidth is targeted specifically at the packet preamble sequence (dc free). AFC is supported during 2FSK/GFSK/MSK/GMSK demodulation.   IF _ Freq MI ≥ 1, AFC on: K = Floor    FSK _ Dev + Freq _ Error _ Max  AFC can be configured to lock on detection of the qualified preamble or on detection of the qualified sync word. To lock AFC on detection of the qualified preamble, set AFC_LOCK_ MODE = 3 (Address 0x116) and ensure that preamble detection is enabled in the PREAMBLE_MATCH register (Address 0x11B). AFC lock is released if the sync word is not detected immediately after the end of the preamble. In packet mode, if the qualified preamble is followed by a qualified sync word, the AFC lock is maintained for the duration of the packet. In sport mode, the AFC lock is released on transitioning back to the PHY_ON state or when a CMD_PHY_RX is issued while in the PHY_RX state.   IF _ Freq MI < 1, AFC on: K = Floor  Data Rate  + Freq _ Error _ Max 2  where: MI is the modulation index. To lock AFC on detection of the qualified sync word, set AFC_LOCK_MODE = 3 and ensure that preamble detection is disabled in the PREAMBLE_MATCH register (Address 0x11B). If this mode is selected, consideration must be given to the selection of the sync word. The sync word should be dc free and have short run lengths yet low correlation with the preamble sequence. See the The value of K is then determined by  IF _ Freq  MI ≥ 1, AFC off: K = Floor    FSK _ Dev     IF _ Freq  MI < 1, AFC off: K = Floor  Data Rate    2        Rev. D | Page 72 of 104 Data Sheet ADF7023-J sync word description in the Packet Mode section for further details. After lock on detection of the qualified sync word, the AFC lock is maintained for the duration of the packet. In sport mode, the AFC lock is released on transitioning back to the PHY_ON state or when CMD_ PHY_RX is issued while in the PHY_RX state. AFC is enabled by setting the AFC_LOCK_MODE bits in the RADIO_CFG_10 register (Address 0x116), as described in Table 38. Table 38. AFC Mode AFC_LOCK_MODE [1:0] 0 1 2 3 Mode Free running: AFC is free running. Disabled: AFC is disabled. Hold: AFC is paused. Lock: AFC locks after the preamble or sync word. The bandwidth of the AFC loop can be controlled by the AFC_KI and AFC_KP bits in the RADIO_CFG_11 register (Address 0x117). The maximum AFC pull-in range is automatically set based on the programmed IF filter bandwidth (the IFBW bits in the RADIO_CFG_9 register (Address 0x115). Table 39. Maximum AFC Pull-In Range IF Bandwidth (kHz) 100 150 200 300 Max AFC Pull-In Range (kHz) ±50 ±75 ±100 ±150 AFC and Preamble Length The AFC requires a certain number of the received preamble bits to correct the frequency error between the transmitter and the receiver. The number of preamble bits required depends on the data rate and whether the AFC is locked on detection of the qualified preamble or locked on detection of the qualified sync word. This is discussed in more detail in the Recommended Receiver Settings for 2FSK/GFSK/MSK/GMSK section. AFC Readback The frequency error between the received carrier and the receiver local oscillator can be measured when AFC is enabled. The error value can be read from the FREQUENCY_ERROR_READBACK register (Address 0x372), where each LSB equates to 1 kHz. The value is a twos complement number. The FREQUENCY_ERROR_ READBACK value is valid in the PHY_RX state after the AFC has been locked. The value is retained in the FREQUENCY_ ERROR_READBACK register after recovering a packet and transitioning back to the PHY_ON state. Post-Demodulator Filter A second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. The bandwidth of this post-demodulator filter is programmable and must be optimized for the user’s data rate and received modulation type. If the bandwidth is set too narrow, performance degrades due to inter-symbol interference (ISI). If the bandwidth is set too wide, excess noise degrades the performance of the receiver. For optimum performance, the post-demodulator filter bandwidth should be set close to 0.75 times the data rate (when using FSK/GFSK/MSK/GMSK modulation). The actual bandwidth of the post-demodulator filter is given by Post-Demodulator Filter Bandwidth (kHz) = POST_DEMOD_BW × 2 where POST_DEMOD_BW is set in the RADIO_CFG_4 register (Address 0x110). CLOCK RECOVERY An oversampled digital clock and data recovery (CDR) PLL is used to resynchronize the received bit stream to a local clock in all modulation modes. The maximum symbol rate tolerance of the CDR PLL is determined by the number of bit transitions in the transmitted bit stream. For example, during reception of a 010101 preamble, the CDR achieves a maximum data rate tolerance of ±3.0%. However, this tolerance is reduced during recovery of the remainder of the packet where symbol transitions may not be guaranteed to occur at regular intervals during the payload data. To maximize data rate tolerance of the receiver’s CDR, 8b/10b encoding or Manchester encoding should be enabled, which guarantees a maximum number of contiguous bits in the transmitted bit stream. Data whitening can also be enabled on the ADF7023-J to break up long sequences of contiguous data bit patterns. Using 2FSK/GFSK/MSK/GMSK modulation, it is also possible to tolerate uncoded payload data fields and payload data fields with long run length coding constraints if the data rate tolerance and packet length are both constrained. More details of CDR operation using uncoded packet formats are discussed in the AN-915 Application Note. The CDR PLL of the ADF7023-J is optimized for fast acquisition of the recovered symbols during preamble and typically achieves bit synchronization within five symbol transitions of preamble. RECOMMENDED RECEIVER SETTINGS FOR 2FSK/GFSK/MSK/GMSK To optimize the ADF7023-J receiver performance and to ensure the lowest possible packet error rate, it is recommended to use the following configurations: • • • • Set the recommended AGC low and high thresholds and the AGC clock divide. Set the recommended AFC Ki and Kp parameters. Use a preamble length ≥ the minimum recommended preamble length. When the AGC is configured to lock on the sync word at data rates greater than 200 kbps, it is recommended to set the sync word error tolerance to one bit. The recommended settings for AGC, AFC, preamble length, and sync word are summarized in Table 41. Rev. D | Page 73 of 104 ADF7023-J Data Sheet Recommended AGC Settings Recommended AFC Settings To optimize the receiver for robust packet error rate performance, when using minimum preamble length over the full input power range, it is recommended to overwrite the default AGC settings in the MCR memory. The recommended settings are as follows: The bandwidth of the AFC loop is controlled by the AFC_KI and AFC_KP bits in the RADIO_CFG_11 register (Address 0x117). To ensure optimum AFC accuracy while minimizing the AFC settling time (and thus the required preamble length), the AFC_KI and AFC_KP bits should be set as outlined in Table 41. • • • AGC_HIGH_THRESHOLD (Address 0x35F) = 0x78 AGC_LOW_THRESHOLD (Address 0x35E) = 0x46 AGC_CLK_DIVIDE (Address 0x32F) = 0x0F or 0x19 (depends on the data rate; see Table 41) Recommended Preamble Length Note that the accuracy of the RSSI readback is degraded with these modified settings. When AFC is locked on preamble detection, the minimum preamble length is between 40 bits and 60 bits depending on the data rate. When AFC is set to lock on sync word detection, the minimum preamble length is between 14 bits and 32 bits, depending on the data rate. When AFC and preamble detection are disabled, the minimum preamble length is dependent on the AGC settling time and the CDR acquisition time and is between 8 bits and 24 bits, depending on the data rate. The required preamble length for various data rates and receiver configurations is summarized in Table 41. MCR memory is not retained in PHY_SLEEP; therefore, to allow the use of these optimized AGC settings in low power mode applications, a static register fix can be used. An example static register fix to write to the AGC settings in MCR memory is shown in Table 40. Table 40. Example Static Register Fix for AGC Settings Recommended Sync Word Tolerance BBRAM Register 0x128 (STATIC_REG_FIX) 0x12B 0x12C Data 0x2B Description Pointer to BBRAM Address 0x12B 0x5E 0x46 0x12D 0x12E 0x5F 0x78 0x12F 0x130 0x2F 0x0F 0x131 0x00 MCR Address 0x35E Data to write to MCR Address 0x35E (sets AGC low threshold) MCR Address 0x35F Data to write to MCR Address 0x35F (sets AGC high threshold) MCR Address 0x32F Data to write to MCR Address 0x32F (sets AGC clock divide) Ends static MCR register fixes At data rates greater than 200 kbps and when the AGC is configured to lock on the sync word, it is recommended to set the sync word error tolerance to one bit (SYNC_ERROR_TOL = 1). This prevents an AGC gain change during sync word reception causing a packet loss by allowing one bit error in the received sync word. Rev. D | Page 74 of 104 Data Sheet ADF7023-J Table 41. Summary of Recommended AGC, AFC, Preamble Length, and Sync Word Error Tolerance for 2FSK/GFSK/MSK/GMSK Data Rate (kbps) 300 Frequency Deviation (kHz) 75 IF BW (kHz) 300 AFC Pull-In Range (kHz) ±150 200 150 100 50 38.4 50 37.5 25 12.5 20 200 150 100 100 100 ±100 ±75 ±50 ±50 ±50 9.6 10 100 ±50 1 10 100 ±50 Setup 1 1 2 3 1 1 1 1 1 2 3 1 1 1 1 High Threshold 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 0x78 AGC 2 Low Threshold 0x46 0x46 0x46 0x46 0x46 0x46 0x46 0x46 0x46 0x46 0x46 0x46 0x46 0x46 AFC 3 Clock Divide 0x0F 0x19 0x19 0x19 0x19 0x19 0x19 0x19 0x19 0x19 0x19 0x19 0x19 0x19 On/Off On On Off On On On On On On Off Off On Off On Ki 7 8 Kp 3 3 7 7 7 7 7 7 3 3 3 3 3 3 7 3 7 3 Minimum Preamble Length (Bits) 4 64 32 24 58 54 52 50 44 14 8 8 46 8 40 Sync Word Error Tolerance (Bits) 5 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Setup 1: AFC and AGC are configured to lock on preamble detection by setting AFC_LOCK_MODE = 3 and AGC_LOCK_MODE = 3. Setup 2: AFC and AGC are configured to lock on sync word detection by setting AFC_LOCK_MODE = 3, AGC_LOCK_MODE = 3, and PREAMBLE_MATCH = 0. Setup 3: AFC is disabled and AGC is configured to lock on sync word detection by setting AFC_LOCK_MODE = 1, AGC_LOCK_MODE = 3, and PREAMBLE_MATCH = 0. For Setup 2 and Setup 3, sync word length is 24 bits. Sync word detect length has an impact on minimum preamble length. 2 The AGC high threshold is configured by writing to the AGC_HIGH_THRESHOLD register (Address 0x35F). The AGC low threshold is configured by writing to the AGC_LOW_THRESHOLD register (Address 0x35E). The AGC clock divide is configured by writing to the AGC_CLK_DIVIDE register (Address 0x32F). Note that the accuracy of the RSSI readback is degraded with these modified AGC threshold settings. 3 The AFC is enabled or disabled by writing to the AFC_LOCK_MODE setting in register RADIO_CFG_10 (Address 0x116). The AFC Ki and Kp parameters are configured by writing to the AFC_KP and AFC_KI settings in the RADIO_CFG_11 register (Address 0x117). 4 The transmit preamble length (in bytes) is set by writing to the PREAMBLE_LEN register (Address 0x11D). 5 The sync word error tolerance (in bits) is set by writing to the SYNC_ERROR_TOL setting in the SYNC_CONTROL register (Address 0x120). 1 Rev. D | Page 75 of 104 ADF7023-J Data Sheet PERIPHERAL FEATURES ANALOG-TO-DIGITAL CONVERTER The ADF7023-J supports an integrated SAR ADC for digitization of analog signals that include the analog tem perature sensor, the analog RSSI level, and an external analog input signal (Pin 30). The conversion time is typically 1 µs. The result of the conversion can be read from the ADC_READBACK_HIGH register (Address 0x327), and the ADC_READBACK_LOW register (Address 0x328). The ADC readback is an 8-bit value. The signal source for the ADC input is selected via the ADC_CONFIG_LOW register (Address 0x359). In the PHY_RX state, the source is automatically set to the analog RSSI. The ADC is automatically enabled in PHY_RX. In other radio states, the host processor must enable the ADC by setting POWERDOWN_RX (Address 0x324) = 0x10. To perform an ADC readback, the following procedure should be completed: 1. 2. 3. Read ADC_READBACK_HIGH. This initializes an ADC readback. Read ADC_READBACK_LOW. This returns ADC_READBACK[1:0] of the ADC sample. Read ADC_READBACK_HIGH. This returns ADC_READBACK[7:2] of the ADC sample. TEMPERATURE SENSOR The integrated temperature sensor has an operating range between −40°C and +85°C. To enable readback of the temperature sensor in PHY_OFF, PHY_ON, or PHY_TX, the following registers must be set: 1. 2. 3. Set POWERDOWN_RX (Address 0x324) = 0x10 = 0x10. This enables the ADC. Set POWERDOWN_AUX (Address 0x325) = 0x02. This enables the temperature sensor. Set ADC_CONFIG_LOW (Address 0x359) = 0x08. This sets the ADC input to the temperature sensor. The temperature is determined from the ADC readback value using the following formula: Temperature (°C) = 0.9474 × (ADC_READBACK[7:0] – CalibrationValue[7:0]) + TCalibration The CalibrationValue[7:0] is determined via an ADC readback at a single known temperature, TCalibration. TEST DAC converts it to a high frequency, single-bit output using a secondorder Σ-Δ converter. The output can be viewed on the GP0 pin. This signal, when filtered appropriately, can be used to • • • • Monitor the signal at the post-demodulator filter output Measure the demodulator output SNR Construct an eye diagram of the received bit stream to measure the received signal quality Implement analog FM demodulation To enable the test DAC, the GPIO_CONFIGURE setting (Address 0x3FA) should be set to 0xC9. The TEST_DAC_GAIN setting (Address 0x3FD) should be set to 0x00. The test DAC signal at the GP0 pin can be filtered with a 3-stage, low-pass RC filter to reconstruct the demodulated signal. For more information, see the AN-852 Application Note. TRANSMIT TEST MODES There are two transmit test modes that are enabled by setting the VAR_TX_MODE parameter (Address 0x00D in packet RAM memory), as described in Table 42. VAR_TX_MODE should be set before entering the PHY_TX state. Table 42. Transmit Test Modes VAR_TX_MODE 0 1 2 3 4 to 255 Mode Default; no transmit test mode Transmit random data continuously Transmit the preamble continuously Transmit the carrier continuously Reserved SILICON REVISION READBACK The product code and silicon revision code can be read from the packet RAM memory as described in Table 43. The values of the product code and silicon revision code are valid only on power-up or wake-up from the PHY_SLEEP state because the communications processor overwrites these values on transitioning from the PHY_ON state. Table 43. Product Code and Silicon Revision Code Packet RAM Location 0x001 0x002 0x003 0x004 The test DAC allows the output of the post-demodulator filter to be viewed externally. It takes the 16-bit filter output and Rev. D | Page 76 of 104 Description Product code, most significant byte = 0x70 Product code, least significant byte = 0x23 Silicon revision code, most significant byte Silicon revision code least significant byte Data Sheet ADF7023-J APPLICATIONS INFORMATION APPLICATION CIRCUIT 25 VDD GP4 ADF7023-J 24 CS MISO 20 IRQ_GP3 IRQ 19 GP2 18 GP1 GP0 SCLK 21 MISO 17 09555-158 The interface, when using packet mode, between the ADF7023-J and the host processor is shown in Figure 82. In packet mode, all communication between the host processor and the ADF7023-J occurs on the SPI interface and the IRQ_GP3 pin. The interface between the ADF7023-J and the host processor in sport mode is shown in Figure 83. In sport mode, the transmit and receive data interface consists of the GP0, GP1, and GP2 pins and a separate interrupt is available on GP4, while the SPI interface is used for memory access and issuing of commands. MOSI 22 SCLK HOST PROCESSOR INTERFACE GPIO 23 MOSI CONTROLLER A typical application circuit for the ADF7023-J is shown in Figure 84. All external components required for operation of the device, excluding supply decoupling capacitors, are shown. This example circuit uses a combined single-ended PA and LNA match. Further details on matching topologies and different host processor interfaces are given in the Host Processor Interface section and the PA/LNA Matching section. Figure 82. Processor Interface in Packet Mode 25 VDD GP4 IRQ MOSI SCLK MISO IRQ_GP3 GP2 GP1 GP0 24 GPIO 23 MOSI 22 SCLK 21 MISO 20 IRQ 19 18 TxRxCLK 17 TxDATA RxDATA 09555-159 CS CONTROLLER ADF7023-J MOSI SCLK MISO IRQ_GP3 CREGDIG1 26MHz XTAL Figure 84. Typical ADF7023-J Application Circuit Diagram Rev. D | Page 77 of 104 22 21 20 GPIO MOSI SCLK MISO IRQ 19 18 17 09555-039 DGUARD GP0 23 16 15 XOSC26N GP1 24 CONTROLLER 26 25 GP4 CREGDIG2 27 XOSC32KP_GP5_ATB1 XOSC32KN_ATB2 29 28 30 VDDBAT1 CS GP2 14 VDDBAT2 NC VDD GND PAD 9 8 RFO2 XOSC26P 7 ADF7023-J CWAKEUP VDD RFIO_1N 13 6 CREGSYNTH 5 32kHz XTAL (OPTIONAL) RFIO_1P CREGRF2 12 4 RBIAS VCOGUARD HARMONIC FILTER CREGRF1 11 3 ANTENNA CONNECTION ADCIN_ATB3 32 2 CREGVCO 1 10 PA/LNA MATCH ADCVREF 31 ATB4 VDD Figure 83. Processor Interface in Sport Mode ADF7023-J Data Sheet Separate Single-Ended PA/LNA Match The ADF7023-J has a differential LNA and both a single-ended PA and differential PA. This flexibility allows numerous possibilities in interfacing the ADF7023-J to the antenna. Combined Single-Ended PA and LNA Match The combined single-ended PA and LNA match allows the transmit and receive paths to be combined without the use of an external transmit/receive switch. The matching network design is shown in Figure 86. The differential LNA match is a five-element discrete balun giving a single-ended input. The single-ended PA output is a three-element match consisting of the choke inductor to the CREGRF2 regulated supply and an inductor and capacitor series. The LNA and PA paths are combined, and a seventh-order harmonic filter provides attenuation of the transmit harmonics. In a combined match, the off impedances of the PA and LNA must be considered. This can lead to a small loss in transmit power and degradation in receiver sensitivity in comparison with a separate single-ended PA and LNA match. However, with optimum matching, the typical loss in transmit power is