9.5 Ω RON, 16-Channel, Differential 8-Channel,
±15 V/+12 V/±5 V iCMOS Multiplexers
ADG1406/ADG1407
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
9.5 Ω on resistance at 25°C
Up to 300 mA of continuous current
Fully specified at ±15 V/+12 V/±5 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
28-lead TSSOP and 32-lead, 5 mm × 5 mm LFCSP
ADG1406
S1
D
S16
APPLICATIONS
Medical equipment
Audio and video routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
A0 A1 A2 A3 EN
07419-001
1-OF-16
DECODER
Figure 1.
ADG1407
S1A
DA
S8A
S1B
DB
S8B
A0 A1 A2 EN
07419-002
1-OF-8
DECODER
Figure 2.
GENERAL DESCRIPTION
The ADG1406 and ADG1407 are monolithic iCMOS® analog
multiplexers comprising 16 single channels and eight differential
channels, respectively. The ADG1406 switches one of 16 inputs
to a common output, as determined by the 4-bit binary address
lines (A0, A1, A2, and A3). The ADG1407 switches one of eight
differential inputs to a common differential output, as determined
by the 3-bit binary address lines (A0, A1, and A2). An EN input
on both devices enables or disables the device. When disabled,
all channels switch off. When on, each channel conducts equally
well in both directions and has an input signal range that extends
to the supplies.
The industrial CMOS (iCMOS) modular manufacturing
process combines high voltage complementary metal-oxide
semiconductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
Rev. C
of high voltage devices has been able to achieve. Unlike analog
ICs using conventional CMOS processes, iCMOS components
can tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.
The ultralow on resistance and on-resistance flatness of these
switches make them ideal solutions for data acquisition and gain
switching applications where low distortion is critical. iCMOS
construction ensures ultralow power dissipation, making the
devices ideally suited for portable and battery-powered instruments.
Table 1. Related Devices
Device No.
ADG1206/ADG1207
Description
Low capacitance, low charge injection,
and low leakage 8-/16-channel ±15 V
multiplexers
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ADG1406/ADG1407
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................8
Applications ....................................................................................... 1
Thermal Resistance .......................................................................8
General Description ......................................................................... 1
ESD Caution...................................................................................8
Functional Block Diagrams ............................................................. 1
Pin Configurations and Function Descriptions ............................9
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 13
Specifications..................................................................................... 3
Terminology .................................................................................... 17
±15 V Dual Supply ....................................................................... 3
Test Circuits ..................................................................................... 18
12 V Single Supply ........................................................................ 4
Outline Dimensions ....................................................................... 20
±5 V Dual Supply ......................................................................... 6
Ordering Guide .......................................................................... 20
Continuous Current per Channel .............................................. 7
REVISION HISTORY
6/2016—Rev. B to Rev. C
Changes to Analog Inputs Parameter, Table 7 .............................. 8
Added Digital Inputs Parameter, Table 7 ...................................... 8
4/2016—Rev. A to Rev. B
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Changed LFCSP_VQ to LFCSP ................................... Throughout
Changes to Figure 4 and Table 9 ..................................................... 9
Changes to Figure 6 and Table 10 ................................................. 11
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
3/2009—Rev. 0 to Rev. A
Change to IDD Parameter, Table 2 ................................................... 4
Change to IDD Parameter, Table 3 ................................................... 5
Changes to Figure 16 ...................................................................... 14
8/2008—Revision 0: Initial Version
Rev. C | Page 2 of 20
Data Sheet
ADG1406/ADG1407
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted.1
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match Between
Channels (ΔRON)
On-Resistance Flatness (RFLAT(ON))
+25°C
−40°C to
+85°C
VSS to VDD
9.5
11.5
0.55
14
16
1
1.6
1.5
1.7
1.9
2.15
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.01
±1
Drain Off Leakage, ID (Off )
±0.25
±0.01
±0.5
±0.05
±0.5
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
−40°C to
+125°C1
2.3
Break-Before-Make Time Delay, tBBM
tOFF (EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise
(THD + N)
−3 dB Bandwidth
ADG1406
ADG1407
Insertion Loss
CS (Off )
CD (Off )
ADG1406
ADG1407
Ω max
Ω typ
VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V,
IS = −10 mA; see Figure 27
VDD = +13.5 V, VSS = −13.5 V , VS = ±10 V,
IS = −10 mA
VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V,
IS = −10 mA
Ω max
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD = ∓10 V; see Figure 28
±4
nA max
nA typ
VS = ±10 V, VD = ∓10 V; see Figure 28
±3
±20
VS = VD = ±10 V; see Figure 29
±3
±20
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
2.0
0.8
±0.002
3
105
160
40
200
225
10
tON (EN)
V
Ω typ
Ω max
Ω typ
Test Conditions/Comments
nA typ
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
Unit
83
110
98
120
10
−73
−70
0.07
140
155
145
165
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ
60
110
0.6
8
MHz typ
MHz typ
dB typ
pF typ
90
45
pF typ
pF typ
Rev. C | Page 3 of 20
RL = 100 Ω, CL = 35 pF
VS = 10 V, see Figure 30
RL = 100 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 31
RL = 100 Ω, CL = 35 pF
VS = 10 V; see Figure 32
RL = 100 Ω, CL = 35 pF
VS = 10 V; see Figure 32
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz; see
Figure 37
RL = 50 Ω, CL = 5 pF; see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 36
f = 1 MHz
f = 1 MHz
ADG1406/ADG1407
Data Sheet
Parameter
CD, CS (On)
ADG1406
ADG1407
POWER REQUIREMENTS
IDD
+25°C
−40°C to
+85°C
−40°C to
+125°C1
pF typ
pF typ
0.002
μA typ
μA max
μA typ
μA max
μA typ
μA max
V min/max
280
475
ISS
0.002
1
±4.5/±16.5
VDD/VSS
1
2
Test Conditions/Comments
f = 1 MHz
115
70
1
IDD
Unit
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V, 5 V or VDD
Temperature range for B version is −40°C to +125°C.
Guaranteed by design, not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match Between
Channels (ΔRON)
On-Resistance Flatness (RFLAT(ON))
+25°C
−40°C to +85°C
−40°C to +125°C1
Unit
0 to VDD
V
Ω typ
18
21.5
0.55
26
1.2
1.6
28.5
1.8
5
6
6.9
7.3
±0.01
±0.25
±0.01
±1
Drain Off Leakage, ID (Off )
±0.5
±0.01
±0.5
±3
±20
±3
±20
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.8
±0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
Break-Before-Make Time Delay, tBBM
4
170
250
75
310
350
30
Rev. C | Page 4 of 20
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,
IS = −10 mA
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,
IS = −10 mA
Ω max
nA typ
±4
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,
IS = −10 mA; see Figure 27
Ω max
Ω typ
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID, IS (On)
Ω max
Ω typ
Test Conditions/Comments
nA max
nA typ
VDD = 10.8 V
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 28
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 28
nA max
nA typ
nA max
VS = VD = 1 V or 10 V; see Figure 29
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
ns typ
ns max
ns typ
ns min
RL = 100 Ω, CL = 35 pF
VS = 8 V; see Figure 29
RL = 100 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 31
Data Sheet
Parameter
tON (EN)
tOFF (EN)
Charge Injection
ADG1406/ADG1407
+25°C
145
205
112
150
−40°C to +85°C
−40°C to +125°C1
250
285
175
200
10
Off Isolation
−73
dB typ
Channel-to-Channel Crosstalk
−70
dB typ
−3 dB Bandwidth
ADG1406
ADG1407
Insertion Loss
35
70
0.6
MHz typ
MHz typ
dB typ
12
pF typ
145
72
pF typ
pF typ
166
93
pF typ
pF typ
0.002
μA typ
μA max
μA typ
μA max
V min/max
CS (Off )
CD (Off )
ADG1406
ADG1407
CD, CS (On)
ADG1406
ADG1407
POWER REQUIREMENTS
IDD
150
VDD
2
Test Conditions/Comments
RL = 100 Ω, CL = 35 pF
VS = 8 V; see Figure 31
RL = 100 Ω, CL = 35 pF
VS = 8 V; see Figure 31
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 35
RL = 50 Ω, CL = 5 pF; see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 36
f = 1 MHz
f = 1 MHz
f = 1 MHz
1
IDD
1
Unit
ns typ
ns max
ns typ
ns max
pC typ
475
5/16.5
Temperature range for B version: −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. C | Page 5 of 20
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
VSS = 0 V, GND = 0 V
ADG1406/ADG1407
Data Sheet
±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match Between
Channels (ΔRON)
On-Resistance Flatness (RFLAT(ON))
+25°C
−40°C to
+85°C
VSS to VDD
21
25
0.6
29
1.3
5.2
1.7
6.4
7.3
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.01
±0.25
±0.01
±1
Drain Off Leakage, ID (Off )
±0.5
±0.01
±0.5
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
−40°C to
+125°C1
32
1.9
7.6
Break-Before-Make Time Delay, tBBM
tOFF (EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion, THD + N
−3 dB Bandwidth
ADG1406
ADG1407
Insertion Loss
CS (Off )
CD (Off )
ADG1406
ADG1407
CD, CS (On)
ADG1406
ADG1407
Ω max
Ω typ
Ω max
Ω typ
VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5 V,
IS = −10 mA; see Figure 27
VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5V,
IS = −10 mA
VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5 V,
IS = −10 mA
Ω max
VDD = +5.5 V, VSS = −5.5 V
VS = ±4.5 V, VD = ∓4.5 V; see Figure 28
±4
nA max
nA typ
VS = ±4.5 V, VD = ∓4.5 V; see Figure 28
±3
±20
VS = VD = ±4.5 V; see Figure 29
±3
±20
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
2.0
0.8
±0.002
3.5
260
435
90
510
565
30
tON (EN)
V
Ω typ
Test Conditions/Comments
nA typ
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
Unit
230
335
205
290
10
–73
–70
0.18
400
445
340
370
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ
40
80
1.15
10
MHz typ
MHz typ
dB typ
pF typ
123
62
pF typ
pF typ
148
88
pF typ
pF typ
RL = 100 Ω, CL = 35 pF
VS = 5 V; see Figure 30
RL = 100 Ω, CL = 35 pF
VS1 = VS2 = 5 V; see Figure 31
RL = 100 Ω, CL = 35 pF
VS = 5 V; see Figure 32
RL = 100 Ω, CL = 35 pF
VS = 5 V; see Figure 32
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz; see
Figure 37
RL = 50 Ω, CL = 5 pF; see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 36
f = 1 MHz
f = 1 MHz
f = 1 MHz
Rev. C | Page 6 of 20
Data Sheet
Parameter
POWER REQUIREMENTS
IDD
ADG1406/ADG1407
+25°C
−40°C to
+85°C
−40°C to
+125°C1
0.002
1
ISS
0.002
1
±4.5/±16.5
VDD/VSS
1
2
Unit
μA typ
μA max
μA typ
μA max
V min/max
Test Conditions/Comments
VDD = +5.5 V, VSS = −5.5 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V, 5 V, or VDD
Temperature range for B version: −40°C to +125°C.
Guaranteed by design, not subject to production test.
CONTINUOUS CURRENT PER CHANNEL
Table 5. Continuous Current per Channel (ADG1406)
Parameter
CONTINUOUS CURRENT PER CHANNEL1
15 V Dual Supply
28-Lead TSSOP
32-Lead LFCSP
12 V Single Supply
28-Lead TSSOP
32-Lead LFCSP
5 V Dual Supply
28-Lead TSSOP
32-Lead LFCSP
1
25°C
85°C
125°C
Unit
180
300
100
150
50
60
mA max
mA max
150
260
90
130
50
55
mA max
mA max
140
245
85
130
45
55
mA max
mA max
25°C
85°C
125°C
Unit
135
235
85
125
45
55
mA max
mA max
110
190
70
110
40
50
mA max
mA max
105
180
65
100
40
50
mA max
mA max
Test Conditions/Comments
VDD = +13.5 V, VSS = −13.5 V
VDD = 10.8 V, VSS = 0 V
VDD = +4.5 V, VSS = −4.5 V
Guaranteed by design, not subject to production test.
Table 6. Continuous Current per Channel (ADG1407)
Parameter
CONTINUOUS CURRENT PER CHANNEL1
15 V Dual Supply
28-Lead TSSOP
32-Lead LFCSP
12 V Single Supply
28-Lead TSSOP
32-Lead LFCSP
5 V Dual Supply
28-Lead TSSOP
32-Lead LFCSP
1
Test Conditions/Comments
VDD = +13.5 V, VSS = −13.5 V
VDD = 10.8 V, VSS = 0 V
VDD = +4.5 V, VSS = −4.5 V
Guaranteed by design, not subject to production test.
Rev. C | Page 7 of 20
ADG1406/ADG1407
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 7.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Continuous Current, Sx or Dx Pins
Peak Current, Sx or Dx Pins
(Pulsed at 1 ms, 10% Duty
Cycle Maximum)
28-Lead TSSOP
32-Lead LFCSP
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
Reflow Soldering, Pb-Free
Peak Temperature
Time at Peak Temperature
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Table 5 and Table 6
specifications + 15%
Table 8. Thermal Resistance
Package Type
28-Lead TSSOP
32-Lead LFCSP
ESD CAUTION
300 mA
550 mA
−40°C to +125°C
−65°C to +150°C
150°C
260 (+0/−5)°C
10 sec to 40 sec
Overvoltages at the Ax, EN, Sx, or Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating may be applied at any
one time.
Rev. C | Page 8 of 20
θJA
97.9
27.27
θJC
14
Unit
°C/W
°C/W
Data Sheet
ADG1406/ADG1407
28 D
2
27 VSS
NC
3
26 S8
S16
4
25 S7
S15
5
24 S6
S14
6
S13
7
S12
8
S11
9
20 S2
S10 10
19 S1
S9 11
18 EN
GND 12
17 A0
NC 13
16 A1
A3 14
15 A2
22 S4
NC = NO CONNECT
S8
S7
S6
S5
S4
S3
S2
S1
9
10
11
12
13
14
15
16
21 S3
ADG1406
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
GND
A3
A2
NC
NC
A1
A0
EN
TOP VIEW
(Not to Scale)
23 S5
1
2
3
4
5
6
7
8
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. THE EXPOSED PAD MUST BE TIED TO
THE SUBSTRATE, VSS.
07419-003
ADG1406
S16
S15
S14
S13
S12
S11
S10
S9
07419-004
1
NC
32
31
30
29
28
27
26
25
VDD
NC
VDD
NC
D
NC
NC
NC
VSS
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADG1406 LFCSP Pin Configuration
Figure 3. ADG1406 TSSOP Pin Configuration
Table 9. ADG1406 Pin Function Descriptions
TSSOP
1
2, 3, 13
4
5
6
7
8
9
10
11
12
14
15
16
17
18
Pin No.
LFCSP
31
12, 13, 26, 27,
28, 30, 32
1
2
3
4
5
6
7
8
9
10
11
14
15
16
Mnemonic
VDD
NC
Description
Most Positive Power Supply Potential.
No Connect.
S16
S15
S14
S13
S12
S11
S10
S9
GND
A3
A2
A1
A0
EN
Source Terminal 16. This pin can be an input or an output.
Source Terminal 15. This pin can be an input or an output.
Source Terminal 14. This pin can be an input or an output.
Source Terminal 13. This pin can be an input or an output.
Source Terminal 12. This pin can be an input or an output.
Source Terminal 11. This pin can be an input or an output.
Source Terminal 10. This pin can be an input or an output.
Source Terminal 9. This pin can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are
turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be
connected to ground.
Drain Terminal. This pin can be an input or an output.
Exposed Pad. The exposed pad must be tied to the substrate, VSS.
19
20
21
22
23
24
25
26
27
17
18
19
20
21
22
23
24
25
S1
S2
S3
S4
S5
S6
S7
S8
VSS
28
Not applicable
29
0
D
EPAD
Rev. C | Page 9 of 20
ADG1406/ADG1407
Data Sheet
Table 10. ADG1406 Truth Table
A3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. C | Page 10 of 20
On Switch
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADG1406/ADG1407
27 VSS
NC 3
26 S8A
4
25 S7A
S7B 5
24 S6A
S6B 6
23 S5A
22 S4A
21 S3A
S3B 9
20 S2A
S2B 10
19 S1A
S1B 11
18 EN
GND 12
17 A0
NC 13
16 A1
NC 14
15 A2
NC = NO CONNECT
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
9
10
11
12
13
14
15
16
TOP VIEW
(Not to Scale)
S4B 8
ADG1407
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
GND
A2
NC
NC
NC
A1
A0
EN
ADG1407
S5B 7
1
2
3
4
5
6
7
8
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. THE EXPOSED PAD MUST BE TIED TO
THE SUBSTRATE, VSS.
07419-036
S8B
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
07419-037
28 DA
DB 2
32
31
30
29
28
27
26
25
VDD 1
NC
DB
NC
VDD
NC
DA
NC
VSS
Data Sheet
Figure 6. ADG1407 LFCSP Pin Configuration
Figure 5. ADG1407 TSSOP Pin Configuration
Table 11. ADG1407 Pin Function Descriptions
TSSOP
1
2
3, 13, 14
4
5
6
7
8
9
10
11
12
15
16
17
18
Pin No.
LFCSP
29
31
11, 12, 13, 26,
28, 30, 32
1
2
3
4
5
6
7
8
9
10
14
15
16
Mnemonic
VDD
DB
NC
Description
Most Positive Power Supply Potential.
Drain Terminal B. This pin can be an input or an output.
No Connect.
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
A2
A1
A0
EN
Source Terminal 8B. This pin can be an input or an output.
Source Terminal 7B. This pin can be an input or an output.
Source Terminal 6B. This pin can be an input or an output.
Source Terminal 5B. This pin can be an input or an output.
Source Terminal 4B. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
Source Terminal 2B. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are
turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
Source Terminal 1A. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Source Terminal 3A. This pin can be an input or an output.
Source Terminal 4A. This pin can be an input or an output.
Source Terminal 5A. This pin can be an input or an output.
Source Terminal 6A. This pin can be an input or an output.
Source Terminal 7A. This pin can be an input or an output.
Source Terminal 8A. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be
connected to ground.
Drain Terminal A. This pin can be an input or an output.
Exposed Pad. The exposed pad must be tied to the substrate, VSS.
19
20
21
22
23
24
25
26
27
17
18
19
20
21
22
23
24
25
S1A
S2A
S3A
S4A
S5A
S6A
S7A
S8A
VSS
28
Not applicable
27
0
DA
EPAD
Rev. C | Page 11 of 20
ADG1406/ADG1407
Data Sheet
Table 12. ADG1407 Truth Table
A2
X
0
0
0
0
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
On Switch Pair
None
1
2
3
4
5
6
7
8
Rev. C | Page 12 of 20
Data Sheet
ADG1406/ADG1407
TYPICAL PERFORMANCE CHARACTERISTICS
16
18
VDD = +10V
VSS = –10V
14
VDD = +13.5V
VSS = –13.5V
15
ON RESISTANCE (Ω)
VDD = +12V
VSS = –12V
10
8
6
VDD = +16.5V
VSS = –16.5V
VDD = +15V
VSS = –15V
4
12
TA = +125°C
TA = +85°C
9
TA = +25°C
6
TA = –40°C
3
TA = 25°C
IS = –10mA
VDD = +15V
VSS = –15V
0
–16.5 –13.5 –10.5 –7.5 –4.5
–1.5
4.5
1.5
7.5
0
–15
10.5 13.5 16.5
–10
07419-009
2
07419-006
ON RESISTANCE (Ω)
12
–5
0
VS, VD (V)
Figure 7. On Resistance as a Function of VD (VS), Dual Supply
30
25
VDD = +4.5V
VSS = –4.5V
VDD = +5.0V
VSS = –5.0V
20
15
VDD = +5.5V
VSS = –5.5V
10
VDD = +7V
VSS = –7V
0
–7
TA = 25°C
IS = –10mA
–5
–3
–1
1
TA = +85°C
15
TA = +25°C
10
TA = –40°C
5
07419-007
5
TA = +125°C
20
3
VDD = +5V
VSS = –5V
0
–5
7
5
–4
–3
07419-010
25
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
15
VDD = +3.V
VSS = –3.V
30
–2
–1
VS, VD (V)
0
1
2
3
4
5
VS, VD (V)
Figure 11. On Resistance as a Function of VD (VS)
for Different Temperatures, 5 V Dual Supply
Figure 8. On Resistance as a Function of VD (Vs), Dual Supply
25
40
VDD = +5V
VSS = 0V
30
20
20
VDD = +10.8V
VSS = 0V
15
ON RESISTANCE (Ω)
VDD = +8V
VSS = 0V
25
VDD = +12V
VSS = 0V
10
VDD = +15V
VSS = 0V
TA = 25°C
IS = –10mA
0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0 13.5
TA = +85°C
TA = +25°C
10
TA = –40°C
5
VDD = +13.2V
VSS = 0V
VDD = +12V
VSS = 0V
07419-008
5
TA = +125°C
15
0
15.0
0
2
07419-011
35
ON RESISTANCE (Ω)
10
Figure 10. On Resistance as a Function of VD (VS)
for Different Temperatures, 15 V Dual Supply
35
0
5
VS, VD (V)
4
6
8
10
VS, VD (V)
VS, VD (V)
Figure 12. On Resistance as a Function of VD (VS)
for Different Temperatures, 12 V Single Supply
Figure 9. On Resistance as a Function of VD (VS), Single Supply
Rev. C | Page 13 of 20
12
ADG1406/ADG1407
Data Sheet
1.0
14
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
0.4
0.2
0
–0.2
IS (OFF) +–
ID (OFF) +–
IS (OFF) –+
ID (OFF) –+
ID, IS (ON) ++
ID, IS (ON) – –
–0.4
–0.6
–0.8
07419-012
–1.0
–1.2
–1.4
0
10
20
30
VDD = +12V
VSS = 0V
VBIAS = +1V/+10V
12
LEAKAGE CURRENT (nA)
LEAKAGE CURRENT (nA)
0.6
40
50
60
70
10
8
IS (OFF) +–
ID (OFF) +–
IS (OFF) –+
ID (OFF) –+
ID, IS (ON) ++
ID, IS (ON) ––
6
4
2
0
07419-015
0.8
–2
–4
80
20
0
40
TEMPERATURE (°C)
Figure 13. Leakage Current as a Function of Temperature (up to 85°C),
15 V Dual Supply
4
120
2
IDD (µA)
100
0
IS (OFF) +–
ID (OFF) +–
IS (OFF) –+
ID (OFF) –+
ID, IS (ON) ++
ID, IS (ON) – –
–4
–6
0
20
80
VDD = +15V
VSS = –15V
60
VDD = +12V
VSS = 0V
40
20
40
60
80
100
0
120
07419-016
–2
07419-013
LEAKAGE CURRENT (nA)
120
TA = 25°C
IDD PER LOGIC INPUT
140
–8
VDD = +5V
VSS = –5V
0
1.5
3.0
TEMPERATURE (°C)
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
LOGIC LEVEL (Ax, EN) (V)
Figure 17. IDD vs. Logic Level
Figure 14. Leakage Current as a Function of Temperature,
15 V Dual Supply
7
100
TA = 25°C
VDD = +5V
VSS = –5V
VBIAS = +4.5V/–4.5V
IS (OFF) +–
ID (OFF) +–
IS (OFF) –+
ID (OFF) –+
ID, IS (ON) ++
ID, IS (ON) ––
4
3
2
1
0
–1
–2
0
20
40
60
80
100
40
VDD = +5V
VSS = –5V
20
0
VDD = +12V
VSS = 0V
–20
–40
–60
07419-014
–3
VDD = +15V
VSS = –15V
60
–80
–15
120
07419-017
5
80
CHARGE INJECTION (pC)
6
LEAKAGE CURRENT (nA)
100
160
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
6
–4
80
Figure 16. Leakage Current as a Function of Temperature,
12 V Single Supply
8
–10
60
TEMPERATURE (°C)
–10
–5
0
5
10
VS (V)
TEMPERATURE (°C)
Figure 18. Charge Injection vs. Source Voltage
Figure 15. Leakage Current as a Function of Temperature,
5 V Dual Supply
Rev. C | Page 14 of 20
15
Data Sheet
ADG1406/ADG1407
350
0
300
VDD = +5V
VSS = +5V
VDD = +12V
VSS = 0V
150
100
VDD = +15V
VSS = –15V
0
–40
–20
0
20
40
60
80
100
–80
ADJACENT SWITCHES
(S1A TO S1B)
–100
07419-018
50
–60
–120
1k
120
10k
100k
1M
10M
FREQUENCY (Hz)
TEMPERATURE (°C)
1G
Figure 22. ADG1407 Crosstalk vs. Frequency
Figure 19. Transition Time vs. Temperature
0
0
–20
100M
07419-021
200
ADJACENT CHANNELS
(S1A TO S2A)
–40
CROSSTALK (dB)
TIME (ns)
250
VDD = +15V
VSS = –15V
TA = 25°C
–20
VDD = +15V
VSS = –15V
TA = 25°C
–0.5
–60
–80
–100
–2.0
–2.5
–3.0
VDD = +15V
VSS = –15V
TA = 25°C
–3.5
10k
100k
1M
10M
FREQUENCY (Hz)
100M
1G
07419-019
–120
1k
–1.5
–4.0
100
100M
VS = 20V p-p
0.12
0.10
–70
–90
0.08
VS = 15V p-p
0.06
–110
0.04
–130
0.02
10k
100k
1M
10M
FREQUENCY (Hz)
100M
1G
VDD = +15V
VSS = –15V
TA = 25°C
RL = 100Ω
0
VS = 10V p-p
07419-023
THD + N (%)
–50
–150
1k
10M
0.14
VDD = +15V
VSS = –15V
TA = 25°C
07419-020
CROSSTALK (dB)
–30
10k
100k
1M
FREQUENCY (Hz)
Figure 23. ADG1406 On Response vs. Frequency
Figure 20. Off Isolation vs. Frequency
–10
1k
0
2
4
6
8
10
12
14
16
18
FREQUENCY (kHz)
Figure 24. THD + N vs. Frequency, 15 V Dual Supply
Figure 21. ADG1406 Crosstalk vs. Frequency
Rev. C | Page 15 of 20
20
07419-022
INSERTION LOSS (dB)
OFF ISOLATION (dB)
–1.0
–40
ADG1406/ADG1407
Data Sheet
0
1.2
–20
VS = 10V p-p
VDD = +5V
VSS = –5V
TA = 25°C
RL = 110Ω
ACPSRR (dB)
–40
0.6
0.4
VS = 5V p-p
0.2
VS = 2.5V p-p
0
0
2
4
6
8
10
12
14
16
18
NO DECOUPLING
CAPACITORS
–60
–80
DECOUPLING
CAPACITORS
ON SUPPLIES
–100
07419-024
THD + N (%)
0.8
–120
100
20
FREQUENCY (kHz)
Figure 25. THD + N vs. Frequency, 5 V Dual Supply
1k
10k
100k
FREQUENCY (Hz)
Figure 26. ACPSRR vs. Frequency
Rev. C | Page 16 of 20
1M
10M
07419-025
1.0
VDD = +15V
VSS = –15V
TA = 25°C
V p-p = 0.63V
Data Sheet
ADG1406/ADG1407
TERMINOLOGY
tBBM
Off time measured between the 80% points of the switches
when switching from one address state to another.
RON
Ohmic resistance between the D and S terminals.
ΔRON
Difference between the RON of any two channels.
VINL
Maximum input voltage for Logic 0.
RFLAT(ON)
Flatness is defined as the difference between the maximum
and minimum value of on resistance as measured.
VINH
Minimum input voltage for Logic 1.
IS (Off)
Source leakage current when the switch is off.
IINL, IINH
Input current of the digital input.
ID (Off)
Drain leakage current when the switch is off.
IDD
Positive supply current.
ID, IS (On)
Channel leakage current when the switch is on.
ISS
Negative supply current.
VD, VS
Analog voltage on Terminal D and Terminal S.
Off Isolation
A measure of unwanted signal coupling through an off channel.
CS (Off)
Channel input capacitance for the off condition.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
CD (Off)
Channel output capacitance for the off condition.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
CD, CS (On)
On switch capacitance.
On Response
The frequency response of the on switch.
CIN
Digital input capacitance.
Total Harmonic Distortion Plus Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and the switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and the switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
AC Power Supply Rejection Ratio (ACPSRR)
Measures the ability of a device to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude
of signal on the output to the amplitude of the modulation is
the ACPSRR.
Rev. C | Page 17 of 20
ADG1406/ADG1407
Data Sheet
TEST CIRCUITS
V
A
IDS
ID (ON)
ID (OFF)
A
S
NC
VD
3V
50%
50%
D
A
VD
NC = NO CONNECT
Figure 28. Off Leakage
Figure 27. On Resistance
ADDRESS
DRIVE (VIN)
D
VS
07419-125
VS
S
Figure 29. On Leakage
tr < 20ns
tf < 20ns
VDD
VSS
VDD
VSS
A0
0V
VIN
tTRANSITION
S1
A1
50Ω
VS1
S2 TO S15
A2
A3
tTRANSITION
VS16
S16
ADG14061
90%
2.4V
OUTPUT
OUTPUT
D
EN
GND
300Ω
35pF
07419-028
90%
1SIMILAR CONNECTION FOR ADG1407.
Figure 30. Address to Output Switching Times, tTRANSITION
3V
ADDRESS
DRIVE (VIN)
VDD
VSS
VDD
VSS
A0
VIN
0V
S1
A1
50Ω
VS
S2 TO S15
A2
A3
S16
80%
ADG14061
80%
OUTPUT
2.4V
OUTPUT
D
EN
GND
300Ω
35pF
07419-029
tBBM
1SIMILAR CONNECTION FOR ADG1407.
Figure 31. Break-Before-Make Delay, tBBM
3V
ENABLE
DRIVE (VIN)
50%
VDD
VSS
VDD
VSS
A0
50%
S1
A1
A2
0V
VS
S2 TO S16
A3
tOFF (EN)
0.9VOUT
OUTPUT
ADG14061
0.9VOUT
VIN
50Ω
OUTPUT
D
EN
GND
300Ω
1SIMILAR CONNECTION FOR ADG1407.
Figure 32. Enable Delay, tON (EN), tOFF (EN)
Rev. C | Page 18 of 20
35pF
07419-030
tON (EN)
07419-027
D
07419-026
IS (OFF)
S
Data Sheet
ADG1406/ADG1407
3V
VDD
VSS
VDD
A0
VSS
A1
A2
VIN
A3
ADG14061
VOUT
∆VOUT
S
D
EN
VS
QINJ = CL × ∆VOUT
GND
VIN
CL
1nF
VOUT
07419-031
RS
1SIMILAR CONNECTION FOR ADG1407.
Figure 33. Charge Injection
VDD
VDD
VSS
VDD
NETWORK
ANALYZER
NETWORK
ANALYZER
VSS
S
VSS
0.1µF
0.1µF
0.1µF
0.1µF
VOUT
50Ω
50Ω
VDD
VSS
S1
RL
50Ω
D
VS
R
50Ω
S2
D
OFF ISOLATION = 20 log
VS
VOUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 34. Off Isolation
VDD
GND
VOUT
VS
07419-034
GND
VOUT
07419-032
RL
50Ω
Figure 36. Channel-to-Channel Crosstalk
VSS
0.1µF
0.1µF
VDD
VDD
NETWORK
ANALYZER
VSS
VSS
0.1µF
0.1µF
AUDIO PRECISION
50Ω
VDD
VS
GND
IN
VOUT
VOUT WITHOUT SWITCH
RL
10kΩ
07419-033
GND
VOUT WITH SWITCH
VS
V p-p
D
VIN
INSERTION LOSS = 20 log
RS
S
D
RL
50Ω
VSS
Figure 37. THD + N
Figure 35. Bandwidth
Rev. C | Page 19 of 20
VOUT
07419-035
S
ADG1406/ADG1407
Data Sheet
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
1
6.40 BSC
14
PIN 1
0.65
BSC
0.15
0.05
0.30
0.19
COPLANARITY
0.10
1.20 MAX
SEATING
PLANE
8°
0°
0.20
0.09
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 38. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
0.30
0.25
0.18
32
25
0.50
BSC
1
24
TOP VIEW
0.80
0.75
0.70
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
0.50
0.40
0.30
PIN 1
INDICATOR
9
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
112408-A
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 39. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADG1406BRUZ
ADG1406BRUZ-REEL7
ADG1406BCPZ-REEL7
ADG1407BRUZ
ADG1407BRUZ-REEL7
ADG1407BCPZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Description
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07419-0-6/16(C)
Rev. C | Page 20 of 20
Package Option
RU-28
RU-28
CP-32-7
RU-28
RU-28
CP-32-7
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